CN103491375B - JPEG compression system based on bin DCT algorithm - Google Patents
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Abstract
The invention discloses a kind of, and the JPEG compression system emphasis based on binDCT improves in terms of compression algorithm, and the algorithm used is emerging bin DCT algorithm.In this algorithm, all coefficients are binary system and all multiplication are replaced as displacement and add operation, therefore can more quickly be realized simply and by hardware and software.The complexity of DCT conversions is reduced by binary system DCT algorithms, opposite traditional algorithm simultaneously, the present invention improves the compression ratio of image to sacrifice certain picture quality as cost, thus can extensively using in the various radio multimedia sensor network systems such as similar no the end of a thread monitoring.
Description
Technical field
The present invention relates to a kind of image compression systems, and in particular to a kind of low overhead, high compression towards wireless sense network
Rate and JPEG compression system based on bin DCT algorithm.
Background technology
From the 1960s, with the continuous improvement of electronic technology and computer technology and universal, using number side
Method carries out image procossing (Digital Image Processing) and enters the high-speed developing period.The digitized processing of image indicates so that image letter
It number can transmit in high quality, and convenient for retrieval, analysis, processing and the storage of image.But the expression of digital picture needs greatly
The data space of amount, thus data compression coding must be carried out.
By basic research in more than 30 years, image compression encoding research was initially entered newly from the 90's of late 1980s
Period.On the one hand practical research is entered, theoretical research is on the other hand continued deeper into.
Several marks that the research of practical aspect concentrates on International Organization for standardization and International Telecommunication Union ITU joints are worked out
In standard, practical development has effectively been pushed.In 1988 formed draft, 1990 by ITU-TH.261 suggest, be
Image Compression Coding Technology moves towards practical essential step, it is the knot product of 40 years achievements in research of image compression encoding.Into
The standard of a series of images International compression coding is proposed after the nineties in succession.The mixed coding technology that these suggestions generally use
It is current most practical high efficiency encoding method, has obtained extensive popularization and application.The development trend of Image Compression is：It calculates
Method is more complicated, and compression ratio higher, the compression ratio of JPEG is in l:The compression ratio of 20 or so, JPEG2000 will be l:200 or higher,
MPEG compression standards also have been subjected to several generations development, and from MPEG-1 to MPEG-2, MPEG-4 till now, compression algorithm is increasingly
Complexity, operand is increasing, and compression ratio is also higher and higher.
Wireless multimedia sensor network (WMSN) is grown up on the basis of traditional wireless sensor networks (WSN)
The novel sensor network with the multimedia messages perceptional function such as audio, video, image.In radio multimedia sensor network
In, gather around that there are one the JPEG IP kernels of efficient processing video flowing are particularly significant.
In the environment of wireless multi-hop, unpressed original video stream needs great bandwidth.It is therefore apparent that for more
Media sensor network needs effective lossless compressiong.Traditional wireless and wired video coding technique that is applied to is base
Rate is generated in reducing bit using statistical method by source encoder.To reach this purpose, encoder passes through frame internal pressure
Contracting technology reduces the redundancy in a frame, while also having using inter-frame compression techniques (also referred to as predictive coding or estimation)
Reduce the redundancy between continuously shaking.
These aspects are mainly concentrated on to the research of jpeg coder in the world：Compression algorithm is improved, restructural core
Piece and IP kernel weight framework.Dynamic reconfigurable permission selectively substitutes certain logical blocks at runtime, to improve FPGA's
Area utilization.Method about restructural chip.It is generally based on mixed hardware/software architecture.To wherein computation-intensive
Application component be mapped in specific hardware-core.The distribution FPGA resource of these kernels on the same stage.And it is remaining by soft
Part is realized.More areas are reduced in a manner of sacrificing a small amount of performance by this method.Have again is exactly by changing IP kernel
Framework realize that the encoder of low overhead, such as QihuiZhang mention a kind of new framework mode, two-dimensional dct is calculated into mould
Block allows two one-dimensional continuous transformation processions to decompose using the part of difference, and in-between result memory parallel with one changes
Position, can reach higher running frequency, and realize by additional SIPO, PISO and register bank.
But the research hotspot of current JPEG is optimized processor speed and obtains the image of high quality.It is such design and
The low overhead and image high compression rate of wireless sense network require to run counter to, and these methods have higher complexity, realize compared with
For complexity.
Invention content
Present invention aims at provide a kind of JPEG pressures based on bin DCT algorithm for deficiency of the prior art
The problems such as compression system, which solve the little compressible of current image compression system, high expense and high complexities.
In order to solve the problems, such as it is in the prior art these, technical solution provided by the invention is：
A kind of JPEG compression system based on bin DCT algorithm, the JPEG compression system include binDCT modules,
Zigzag modules, quantization modules, coding module and controller module, in system work process, binDCT modules according to
8 × 8 data blocks of input are carried out binDCT transformation, and output data are sent into Zigzag modules by bin DCT algorithm；
Zigzag units rearrange the matrix after the transformation of input according to the sequence of Zigzag, then by output data
It send to quantization modules；
Output data is multiplied by the matrix reciprocal of quantization matrix by quantization modules, is entered data into coding mould after completing quantization
Block；
Quantization modules output data is split as DC component and AC compounent by coding module, to DC component with exchange point
Amount uses different coding modes, is respectively completed differential encoding and variable-length encoding and moisture in the soil coding；Control module is responsible for generating institute
The logic control signal and timing control signal for having module, finally export the data of coding.
For above-mentioned technical proposal, inventor also has further optimal enforcement scheme.
As an optimization, binDCT modules use binDCT matrixes when carrying out discrete cosine transform to image data,
Be displacement and add operation by all multiplication operational transformations of dct transform, binDCT modules by every one group of eight conducts of data,
After advanced every trade transformation, then into ranks variation, after completing one-dimensional transform, then two-dimensional transform is carried out, is finally completed binDCT transformation.
As an optimization, Zigzag modules use two ram, and using ping-pong operation, the processing of ping-pong operation is mainly handle
It is assigned to whens input traffic is by input data selecting unit etc. in data buffer zone zigram0 and zigram1.
Further, then Zigzag modules are selected first by the data flow cache of input to zigram0 by input data
It selects, switches over, and by the data flow cache of input to zigram1, at the same time, also pass through the data of zigram0 defeated
The selection for going out data selection unit is sent to quantization modules and is handled；It is selected again by input data in the third period later
At the same time the data of zigram1, are passed through the data flow cache of input to zigram0 by the switching again of unit again
The switching of output data selection unit is sent to quantization modules and is handled；So cycle, in cycles.
As an optimization, the quantizer of quantization modules constantly generates address signal, and quantization parameter is read from quantization parameter table,
Quantization parameter table includes two quantization parameter tables of the quantization parameter table and carrier chrominance signal UV of storing luminance signal Y, is in quantization
What is stored in number table is the inverse of corresponding quantization step, and quantization modules are directly by the quantization parameter phase of binDCT coefficients and reading
Multiply.
As an optimization, data are split as DC components and AC components by coding module；Wherein DC values use the side of differential encoding
Formula, the AC data after quantization will appear a large amount of continuous zero, can with Run- Length Coding (RLE), a large amount of zero to AC data
To be indicated with fewer data, the bit number used is reduced, VLC codings then are carried out to AC data, according to the big of VLI codes
Small carry out Huffman encoding, and AC components carry out VLC codings, according to the size of the VLC codes of AC coefficients and run length from Hough
Corresponding Huffman code is checked in graceful code table
Controller module is to input 8 entire codings of register control by user as an optimization, is set by user defeated
Enter the MCU formats of image and the corresponding quantization table of quantity, each component and Huffman table and generates coding and start and stop letter
Number etc., sequential and logic control are carried out to entire cataloged procedure.
Scheme in compared with the existing technology, it is an advantage of the invention that：
JPEG compression system emphasis based on binDCT described in the invention improves in terms of compression algorithm, the calculation of use
Method is emerging bin DCT algorithm.In this algorithm, all coefficients are that binary system and all multiplication are replaced as shifting and add
Method operates, therefore can more quickly be realized simply and by hardware and software.DCT is reduced by binary system DCT algorithms to turn
The complexity changed, while opposite traditional algorithm, the present invention improve the compression of image to sacrifice certain picture quality as cost
Rate, thus can extensively using in the various radio multimedia sensor network systems such as similar no the end of a thread monitoring.
Description of the drawings
The invention will be further described with reference to the accompanying drawings and embodiments：
Fig. 1 is the general structure schematic diagram of the JPEG compression system of the embodiment of the present invention；
Fig. 2 is the binDCT matrixes in the embodiment of the present invention；
Fig. 3 is the binDCT module frame charts in the embodiment of the present invention；
Fig. 4 is the picture element matrix input sequence in the embodiment of the present invention；
Fig. 5 is the Zigzag module frame charts in the embodiment of the present invention；
Fig. 6 is the quantization modules block diagram in the embodiment of the present invention；
Fig. 7 is the coding module block diagram in the embodiment of the present invention；
Fig. 8 is the huff module status machine frame figures in the embodiment of the present invention；
Fig. 9 is the pack module status machine frame figures in the embodiment of the present invention；
Figure 10 is the controller module block diagram in the embodiment of the present invention.
Specific implementation mode
Said program is described further below in conjunction with specific embodiment.It should be understood that these embodiments are for illustrating
The present invention and be not limited to limit the scope of the invention.The implementation condition used in embodiment can be done according to the condition of specific producer
Further adjustment, the implementation condition being not specified is usually the condition in routine experiment.
Embodiment：
Present embodiment describes a kind of JPEG compression system based on bin DCT algorithm, overall structure is as shown in Figure 1, institute
It includes binDCT modules, Zigzag modules, quantization modules, coding module and controller module to state JPEG compression system, in system
In the course of work,
BinDCT modules carry out binDCT transformation according to bin DCT algorithm, by 8 × 8 data blocks of input, and will export number
According to feeding Zigzag modules；
Zigzag units rearrange the matrix after the transformation of input according to the sequence of Zigzag, then by output data
It send to quantization modules；
Output data is multiplied by the matrix reciprocal of quantization matrix by quantization modules, is entered data into coding mould after completing quantization
Block；
Quantization modules output data is split as DC component and AC compounent by coding module, to DC component with exchange point
Amount uses different coding modes, is respectively completed differential encoding and variable-length encoding and moisture in the soil coding；Control module is responsible for generating institute
The logic control signal and timing control signal for having module, finally export the data of coding.
As described above, entire JPEG compression system is divided into two parts, one is compressed encoding part, and one is control unit
Point.The input data of compressed encoding part is initial data to be encoded, by binDCT modules, Zigzag modules, quantization mould
Block, coding module, finally obtain final data；The input of control section is that address and control input, and is primarily to facilitate configuration
The register of JPEGIP cores, controls image encoding process, and control section is last to obtain output data.
BinDCT moulds kernel variable in the block, binDCT matrixes are as shown in Figure 2.By to matrix observation it can be found that
BinDCT matrixes have the feature of symmetry.One kind of value is replaced using coefficient C0-C11, matrix can be turned
It changes.According to the algorithm of binDCT, entire binDCT transformation only needs to may be implemented by addition and displacement, by entire binDCT
The structure of module is as shown in Figure 3.
BinDCT modules include 7 modules.Wherein module, responsible generate control signal to dctctrl modules in order to control,
Tri- modules of mulh, selecth, sumh carry out one-dimensional horizontal binDCT to data and convert, mulv, selectv, sumv tri-
Module carries out One-dimensional Vertical binDCT transformation to data.Zigram0 and zigram1 is the plug-in ram of zigzag modules.
Dctram is the plug-in ram of dct modules.Mulv and mulh modules are responsible for
Number is multiplied.Due to using complement arithmetic, by simply shifting and addition, by all coefficients with input
Pixel value is multiplied.128 are subtracted to input pixel first.So that between the ranging from -128-128 of input pixel, for even letter
Number.Input is positive number, and after subtracting 128, data may be negative, therefore need to convert negative while subtracting 128
For complement code.Simultaneously input pixel input be eight, in order to improve operational precision, need to data carry out Bits Expanding, last two
After the completion of dimension transformation, then clip extension bits.
Introduced cases pixel is inputted by 8 × 8 matrix one by one.The sequence of input is inputted by row
, as shown in figure 4, input sequence is X00, X01 ... X07 ... X70 ... X77.
Selcth and the function of selcth are that mulh is multiplied with the mulv result obtained is arranged according to the sequence of matrix
Row.Sumh with sumv modules are responsible for the result that each column is multiplied and add symbol, then carry out summation operation.Dctctrl modules are responsible for production
The control signal of raw selcth, selctv, sumh and sumv module, while the address signal of dctram is generated, complete row transformation
As a result transposition.The main input signals of dctctrl modules are clock signal clk, synchronous initial signal strt.It is inputted by row
, each clock inputs a pixel.Dctctrl has been completed at the same time the transposition to row transformation.4 three countings are respectively adopted
Device realizes address conversion.Wherein ahh and ahl constitutes memh signals, and avh and avl constitute memv signals, the two letters
Number it is the address input and output signal of dctram respectively.Since memh signals are different with memv signal-counts method, write
Enter address and read the difference of address, completes the transposition of matrix.
The input of Zigzag modules is the output data of binDCT modules.Present invention employs two ram, are grasped using table tennis
Make.It is assigned to data buffer zone whens the processing of ping-pong operation is mainly input traffic by input data selecting unit etc.
In zigram0 and zigram1.First then the data flow cache of input to zigram0 is selected by input data, into
Row switching, and by the data flow cache of input to zigram1, at the same time, the data of zigram0 are also passed through into output data
The selection of selecting unit is sent to quantization modules and is handled.And then pass through input data selecting unit in the third period
Switch again, by the data flow cache of input to zigram0, at the same time, the data of zigram1 is passed through into output again
The switching of data selection unit is sent to quantization modules and is handled.So cycle, in cycles.Zigzag modules are divided into three
Part, two zigram and control signal generator module zigzag.Its visible Fig. 5 of block diagram.
Since the output data of binDCT modules is not Y, but the transposition of Y, therefore the first step is to utilize Zigzag
Module carries out transposition to Y.It realizes that transposition is very simple, input data is counted using a counter x, due to data
Input is inputted by row.It only needs to overturn the Gao Sanwei of x and third position, then into row storage data, you can to obtain Y
Transposition.Second step generates read signal with Zigzag modules according to the sequence of Zigzag.By carrying out zigzag sequences to image
Afterwards, high fdrequency component and low frequency component are detached.Quantization matrix defined in matrix divided by Joint Photographic Experts Group be can be obtained into quantization knot
Fruit.
But in hardware circuit, multiplication is easier to realize than division, and the hardware circuit expended is less.Therefore multiplication is used
Instead of division the matrix reciprocal of quantization matrix is acquired to replace the operation of quantization.
Since after asking down, coefficient is less, therefore stored after the coefficient of the coefficient matrix of storage is amplified 2n times.By this
Divide operations are converted to multiplication operation by mode.Since the different components of image correspond to different quantization matrixes, therefore in JPEGIP
Cure two quantization tables in core, is quantified using different quantization tables for different components.Since coefficient is exaggerated,
The value of quantization table has deposited two values, and one is amplified number, and one is the n for amplifying 2n times.The block diagram of quantization modules is visible
Fig. 6.F1 and f2 representative functions in figure.In total there are two function in Fig. 6, f1 major functions are according to control signal, in advance accordingly
Quantization tabular value, will quantization tabular value detach, be separated into quantization table value of magnification and shift value sh.By the defeated of zigzag modules
Go out and quantify tabular value to be input in mul modules, two numbers are multiplied, completes quantization operation.The value muli inputs that will be obtained
Into f2, shifting function is carried out according to the value of sh, right-shift operation obtains original value ym.Again by ym input states machine 1, by this number
It is sent to output after carrying out floor operation, finally obtains the value after quantization.
In coding module, DC components and AC components for data use different coding modes.First to DC components into
Then row differential encoding carries out variable-length encoding to result, while carrying out variable-length encoding to AC components, finally carry out Huffman volume
Code.It is finally completed the coding of all data, it is enc that data, which are packaged output,.Wherein Huffman encoding, it is static Hough to use
Required tabular value is solidificated in IP kernel by graceful table.All relevant modules of coding are placed in a total module by we.
Due to the processing of JPEG compression be handled according to 8 × 8 pieces one by one, then input the last one process block when
It waits, it is the last one block to need a signal prompt, this signal is last signals.And different components correspond to different Houghs
Graceful table, it is therefore desirable to a marker current color component.Visible Fig. 7 of block diagram of coding module.
Component after quantization, which inputs to, becomes module, and len modules carry out differential encoding to DC components therein.len
Module completes the Run- Length Coding to the differential encoding and AC data of DC data.Huff modules complete to the difference values of DC coefficients into
Row VLI codings carry out VLC codings to the value of AC coefficients, and according to the size of DC coefficient VLI codes, are looked into from Huffman code tables
Corresponding Huffman codes are obtained, are checked in from Huffman code tables accordingly according to the size of the VLC codes of AC coefficients and run length
Huffman codes.Due to from huff module output valve indefinite lengths, it is therefore desirable to which pack modules are packaged.Finally compiled to allow
Data fit Joint Photographic Experts Group after code needs to add flag bit to data, this function is completed by aflag modules.Store modules
The data generated in caching cataloged procedure are mainly responsible for, data is given to aflag modules and handles.
Len modules are mainly to complete the differential encoding of DC coefficients, and calculate the ZRL in data, and carried out to AC elongated
Coding.In len modules, an asynchronous FIFO is devised, to buffering encoded data.
The major function of huff modules is to calculate the address of Huffman tabular value.Generate ZRL and EOB simultaneously.Whenever the company of generation
Continue 16 0 coefficients then one ZRL of output.Higher compression ratio in order to obtain, all ZRL codes be dropped with one it is single
EOB replaces.Single clock coding is carried out for each data, and ZRL codes are pushed into a very shallow FIFO, if module is with 0
Value termination, then refresh and replaced by EOB codes.The Huffman value extracted from Huffman table passes to pack modules and is packaged.
When carrying out Huffman encoding, need especially to be handled according to special circumstances, for example, coding it is last or
When person needs to be inserted into reboot flag position.Therefore a state machine is designed in inside modules to be simulated.The block diagram of state machine
It can be seen that Fig. 8.
6 kinds of states are devised in total, are waits, normal, padr, padf, restrt and flsh respectively.Wherein
Waits states are wait state, restart in module synchronization and either asynchronous restart or be always this when clear signal is effective
A state.When the FIFO of len modules is not empty, it is meant that when huff modules have data to be handled, enter
Normal states.When i.e. restart signals are effective when initial register design is to be inserted into restart, enter
Padr states are ready for insertion into reboot flag position.After padr states, it is inserted into reboot flag position, enters normal states after the completion.?
In normal states, if handled a last process block, if finally encoding obtained data less than 32, need
To be filled into line position, meet the condition of byte-aligned, if therefore final_sig be 1 when, into padf states.Padf shapes
After the completion of state, EOB flag bits are required supplementation with, into flsh states.
Pack modules be mainly complete by after coding Huffman code value (hcode) and the DC that is calculated of len modules with
Value (fvalue) after AC variable-length encodings is packaged, and is packaged into 32 data and is exported.Pack moulds state machine in the block
Main purpose is to discriminate between reboot flag position and is inserted into situation.The visible Fig. 9 of state machine diagram.
It will be seen from figure 9 that tetra- states of a total of idle, restrt, flushc and flush1.This state machine be in order to
It is inserted into what the position filling that restart flag bits and image end up was serviced.If asynchronously or synchronously resetting or clear signal are effective
When, it is idle states.When idle states, if flush=1, that is, when needing to carry out end filling, enter
Flush1 states.According to the size of corresponding remaining data, 0xf of corresponding size is supplemented, until supplying 32.Flush1 states
After, into flushc states, carry out continuous f fillings.In idle states, restrt is entered if restart=1
State.It is inserted into 32 additional data.After insertion, if flush=1 and dout_vldi=1, enter flushc states；
If flush=1 and dout_vldi=0, enter flush1 states；If flush=0 and dout_vldi=1, enter
Idle states indicate that the insertion of reatart flag bits finishes, into normal encoding.
The function of aflag modules is mainly that the flag bit of 32 data and it that coding obtains is read from memory module, together
When outputting encoded data.By its flag bit state, aflag modules decide whether be by the Data expansion for being 0xff
0xff00.Only carried out when 0xff this bit is not flag bit.
Store modules include 4bit depth, the FIFO of 36bit width.Include the data and 4bit of 4 bytes in each FIFO
Mark bit byte.Since the enc data finally generated are 8 data, therefore 32 of coding generation are cached with this FIFO
Data.Congestion can not be generated with reading-white-writing data.
Controller module reads data from register configuration input by user, converts it to corresponding timing control letter
Number and logic control signal.Visible Figure 10 of block diagram of control module.In Figure 10, input signal is that din is deposit input by user
Device configuration data, eover signals come from coding module.Eover signals are generated when encoding the when of completing.It is deposited first from input
Corresponding logic control signal output is extracted in device.Obtain corresponding registers signal r1-r7 and control register group.It generates simultaneously
The postpones signal col2 and module control signal nextcomp of current Color component signals col1 and it is represented and is inputted new face
Colour cell part.Then by the corresponding Huffman table of color component selection, Huffman table control signal colh is obtained.Last basis
Colh signals and register configuration signal behavior accordingly centered on current Huffman table hti module input.Secondly, it generates
The control signal ncol of current color number of components.This signal is obtained into color component quantity colsel by inquiring register.
Again, the counter mcucnt and mc of mcu are changed into kernel enabling signal go and kernel stop signal stp.State is negative in figure
Duty generates the state of control module.A total of 7 states of this state machine.Respectively idle state ectrl_ewait, start to encode
State ectrl_estart, first DCT encoding states ectrl_edctw1, second DCT encoding states ectrl_edctw2,
The coding of second DCT encoding state delaying states ectrl_nx3w, normal encoding state ectrl_enc and the last one MCU
State ectrl_ende.
If go signals are effective, i.e., kernel enabling signal, which effectively enters, starts encoding state.If en signals are effective, en signals
Come from coding module, when variable-length encoding FIFO non-emptys and it is less than when it is effective.Into first DCT encoding state.When
En=1 and nx0=1 then enter second DCT encoding state.Enter ectrl_enx3w when en=1 and nx0=1 again
State.When en=1 and nx3=1, into encoding state.When finali signals are effective, into the last one
MCU encoding states.
The foregoing examples are merely illustrative of the technical concept and features of the invention, its object is to allow the person skilled in the art to be
It cans understand the content of the present invention and implement it accordingly, it is not intended to limit the scope of the present invention.It is all smart according to the present invention
The equivalent transformation or modification that refreshing essence is done, should be covered by the protection scope of the present invention.
Claims (7)
1. a kind of JPEG compression system based on bin DCT algorithm, which is characterized in that the JPEG compression system includes binDCT
Module, Zigzag modules, quantization modules, coding module and controller module, in system work process,
BinDCT modules carry out binDCT transformation according to binDCT algorithms, by 8 × 8 data blocks of input, and by output data
It is sent into Zigzag modules；
Zigzag modules rearrange the matrix after the transformation of input according to the sequence of Zigzag, then send output data
To quantization modules；
Output data is multiplied by the matrix reciprocal of quantization matrix by quantization modules, is entered data into coding module after completing quantization；
Quantization modules output data is split as DC component and AC compounent by coding module, is adopted to DC component and AC compounent
With different coding modes, it is respectively completed differential encoding and variable-length encoding and moisture in the soil coding；
Control module is responsible for generating the logic control signal and timing control signal of all modules, finally carries out the data of coding
Output；
The coding module is simulated when carrying out Huffman encoding by built-in state machine, is carried out to special circumstances special
Other places are managed, and the state machine includes 6 kinds of states, is waits, normal, padr, padf, restrt and flsh respectively,
Middle waits states are wait state, module synchronization restart it is either asynchronous restart or when clear signal is effective, always
For waits states；When huff modules have data to be handled, into normal states；When initial register design is slotting
When entering to restart, i.e., when restart signals are effective, into padr states, it is ready for insertion into reboot flag position restrt；padr
After state, it is inserted into reboot flag position restrt, enters normal states after the completion；In normal states, if having located
When managing a last process block, if finally encoding obtained data less than 32, needs to fill into line position, meet byte-aligned
Condition, into padf states；After the completion of padf states, EOB flag bits are required supplementation with, into flsh states.
2. according to the JPEG compressibilities based on binDCT algorithms described in claim 1, which is characterized in that binDCT
Module uses binDCT matrixes when carrying out discrete cosine transform to image data, all multiplication that DCT is converted
Operational transformation is displacement and add operation, and binDCT modules are by every one group of eight conducts of data, after advanced every trade transformation, then into
Ranks change, and after completing one-dimensional transform, then carry out two-dimensional transform, are finally completed binDCT transformation.
3. according to the JPEG compressibilities based on binDCT algorithms described in claim 1, which is characterized in that Zigzag
Module uses two ram, and using ping-pong operation, input traffic is mainly passed through input data by the processing of ping-pong operation
It is assigned to whens selecting unit etc. in data buffer zone zigram0 and zigram1.
4. according to the JPEG compressibilities based on binDCT algorithms described in claim 3, which is characterized in that Zigzag
Module by the data flow cache of input to zigram0, is then selected by input data first, is switched over, and by input
Data flow cache is to zigram1, at the same time, the selection that the data of zigram0 are also passed through output data selection unit
, it is sent to quantization modules and is handled；It, will be defeated later again in the third period by the switching again of input data selecting unit
The data flow cache entered is to zigram0, at the same time, the data of zigram1 is passed through output data selection unit again
Switching, be sent to quantization modules and handled；So cycle, in cycles.
5. according to the JPEG compressibilities based on binDCT algorithms described in claim 1, which is characterized in that quantization mould
The quantizer of block constantly generates address signal, and quantization parameter is read from quantization parameter table, and quantization parameter table includes storage brightness
The quantization parameter table of signal Y and two quantization parameter tables of carrier chrominance signal UV, what is stored in quantization parameter table is corresponding amount
Change the inverse of step-length, binDCT coefficients are directly multiplied by quantization modules with the quantization parameter of reading.
6. according to the JPEG compression system based on bin DCT algorithm described in claim 1, which is characterized in that coding module will
Data are split as DC components and AC components；VLI codings are carried out using differential encoding laggard row to DC components, to AC
Component Run- Length Coding（RLE）VLC codings are carried out afterwards, and Huffman encoding is carried out according to the size of DC component VLI codes, according to
The size and run length of the VLC codes of AC components check in corresponding Huffman code from Huffman code table.
7. the JPEG compression system according to claim 1 based on binDCT algorithms, which is characterized in that controller module
To be encoded by the way that 8 registers controls of user's input are entire, by the MCU formats and quantity of user's setting input picture, each
The corresponding quantization table of component and Huffman table and generation coding start and stop signals etc., sequential is carried out to entire cataloged procedure
And logic control.
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