CN1206951A - Duplication controller and fault recovery method - Google Patents

Duplication controller and fault recovery method Download PDF

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Publication number
CN1206951A
CN1206951A CN98105673A CN98105673A CN1206951A CN 1206951 A CN1206951 A CN 1206951A CN 98105673 A CN98105673 A CN 98105673A CN 98105673 A CN98105673 A CN 98105673A CN 1206951 A CN1206951 A CN 1206951A
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data
computing module
holding wire
output
circuit
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CN98105673A
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CN1089203C (en
Inventor
岛村光太郎
守田雄一朗
高桥宜孝
堀田多加志
佐藤博康
上田茂太
阪东明
铃木宏和
坂本幸治
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/182—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits based on mutual exchange of the output between redundant processing components
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B9/00—Safety arrangements
    • G05B9/02—Safety arrangements electric
    • G05B9/03—Safety arrangements electric with multiple-channel loop, i.e. redundant control systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
    • G06F11/184—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components where the redundant components implement processing functionality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/187—Voting techniques
    • G06F11/188—Voting techniques where exact match is not required
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99951—File or database maintenance
    • Y10S707/99952—Coherency, e.g. same view to multiple users
    • Y10S707/99953—Recoverability

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Hardware Redundancy (AREA)

Abstract

A replicated controller and a fault recovery method therefor which can restore a faulty system to a normal state without interrupting operation of an equipment, even in an equipment controller performing processing with short operating periods. In a fault recovery method for a replicated controller, control data is divided into a plurality of blocks on the basis of dependency of the blocks, and a plurality of blocks are transferred in a sequential order of superiority of the dependency from the normally operating system to the faulty system in a period over a plurality of operating periods. By this, even in an equipment controller performing processing at a short operating period, the system, in which failure is caused, can be restored into normal state without interrupting operation of the equipment.

Description

Copy controller and fault recovery method thereof
The present invention relates generally to copy controller and fault recovery method thereof.The copy controller and the fault recovery method thereof that need not when more particularly, the present invention relates in copy controller, break down to interrupt the operation of controlled target device and can recover fault.
The controller of the equipment of control such as power converter needs high reliability, because the influence of fault is more great for controlled bigger target device.Thereby at the controller that is used for controlling large-scale equipment, so that being provided in a plurality of systems, a plurality of controllers of equal value each other taked a kind of method that improves the reliability of control by copy controller, make both to have made in a system of controller and break down, can carry out control by using from the normal output of all the other system's middle controllers.
As a kind of fault recovery method when in traditional copy controller, breaking down, in each system of copy controller, provide the transport zone of storage for the necessary control data of fault recovery.When in a system, breaking down, data in the transport zone are transferred to the system that breaks down in the idling cycle that normal system is handled, output by normal system keeps the control to equipment, and the system that breaks down after the transfer of having finished data is restarted.Like this, just can under the situation of the operation of not interrupting controlled target device, revert to normal condition to failure system, thereby provide high reliability for controller.
Yet, when the fault recovery method that is used for copy controller when tradition is used to carry out the controller of equipment of processing in the short operation cycle, can not in the free time in the operation cycle, shift all data.If the data in the transport zone will shift by a plurality of operation cycles, then during the data of transport zone are transferred to a plurality of operation cycles of failure system, failure system can not be transferred to, thereby data all in the transport zone and the Data Matching in the normal system can not be made by the normal system data updated.For that reason, the data in transport zone must be forbidden the renewal of the data in the normal system when failure system shifts, so that can not continue control appliance.
So an object of the present invention is to provide a kind of copy controller and fault recovery method thereof, it is to carry out in the device controller of handling with the short operation cycle that this controller and method had both made, and also need not the operation of interrupting device and can recovering failure system is normal condition.
To achieve these goals, at the fault recovery method that is used for copy controller according to the present invention, the block-based correlation of control data is divided into a plurality of, and a plurality of were shifted to failure system by the system of the priority of correlation order from normal running in the time in a plurality of operation cycles.Like this, both made and carried out in the device controller of handling with the short operation cycle, the system that breaks down also can be resumed the operation that need not interrupting device for normal condition.
In said method, in failure system, to carry out normal process and reach after the given time cycle, control data is transferred to failure system from the system of normal running.Like this, the data that can not be resumed in an operation cycle can finally be resumed and be normal data.
On the other hand, no matter whether fault detect exists, per operation cycle exchanges one of a plurality of between system, so when existing the numerical value that has high reliability when inconsistent to be used in the next operation cycle by identification between the numerical value in each system.Like this, software configuration can be simplified.And both made that occur in the normal method can not detected fault, also can proceed normal handling.
In copy controller according to the present invention, transport zone has a plurality of zones and is used to store and is divided into a plurality of data according to the correlation between the piece, make to be stored in data in a plurality of in a plurality of operation cycles, transfer to failure system from the system of normal running by the priority order of correlation.Like this, both made in the device controller of carry out handling by the short operation cycle, the system that breaks down also can revert to normal system and need not the operation of interrupting device.
Fig. 1 is the block diagram of configuration of first embodiment of the expression control device that is used for power converter according to the present invention.
Fig. 2 is the flow chart that expression is used for selecting the algorithm of one of data of being received by computing module.
Fig. 3 is the block diagram of the concrete configuration of expression AD module 121 shown in Figure 1.
Fig. 4 is the block diagram of the concrete configuration of expression computing module 131 shown in Figure 1.
Fig. 5 is the block diagram of the concrete configuration of expression transfering controling circuit 312 shown in Figure 4.
Fig. 6 is the view that the data on the expression memory 412 shown in Figure 5 are arranged.
Fig. 7 is the block diagram of the concrete configuration of expression synchronization control circuit 318 shown in Figure 4.
Fig. 8 is the sequential chart of the operation of expression synchronization control circuit 318 shown in Figure 4.
Fig. 9 is the block diagram of the concrete configuration of expression output control circuit 324 shown in Figure 4.
Figure 10 is the block diagram that selects the concrete configuration of two voting machines 104 in the expression shown in Figure 1 three.
Figure 11 is the flow chart of the processing of computing module during normal running of the control device of electric power converter shown in Figure 1.
Figure 12 is the flow chart of data flow in the computing shown in the presentation graphs 11B.
Figure 13 is the schematic diagram of the processing in the expression PWM controlled step shown in Figure 12.
Figure 14 is the diagram of an example of the concrete processing of the expression phase-detection that is used for obtaining phase theta shown in Figure 13.
Figure 15 is the diagram of an example of the expression electric power shown in Figure 12 concrete processing that detects step.
Figure 16 is the diagram of an example of the concrete processing of expression voltage control step shown in Figure 12.
Figure 17 is the diagram of an example of the concrete processing of PWM controlled step among expression Figure 12.
Figure 18 is the diagram of an example of the concrete processing of PWM controlled step shown in expression Figure 12.
Figure 19 is the content of computing shown in expression Figure 12 and the diagram of the relation between the influence that fault reaches.
Figure 20 is the diagram of expression first embodiment of performed processing method when detecting fault in the computing module 131 at the control device of the electric power converter shown in Fig. 1.
Figure 21 is a diagram of representing each processing shown in Figure 20 in detail.
Figure 22 is the diagram of expression second embodiment of performed processing method when detecting fault in the computing module 131 at the control device of the electric power converter shown in Fig. 1.
Figure 23 is a diagram of representing each processing shown in Figure 22 in detail.
Figure 24 is the flow chart that the recursive data shown in expression Figure 23 is selected the handling process in the step.
Figure 25 is the block diagram of second embodiment of the concrete configuration of computing module 131 shown in the presentation graphs 1.
Figure 26 is the block diagram of the concrete configuration of transfer blade 1802 shown in expression Figure 25.
Figure 27 is the block diagram of the concrete configuration of operation board 1804 shown in expression Figure 25.
Figure 28 is the diagram of the data flow in operation board 1804 shown in expression Figure 25 and 1806 the processing.
Figure 29 is the diagram of arranging that expression is stored in the data among the RAM 316 of operation board shown in Figure 25 1804 and 1806.
Figure 30 be expression when the computing module 131 of the control device of electric power converter shown in Figure 1 ' in the diagram of an example of performed processing method when detecting fault, wherein the configuration shown in Figure 25 be used for computing module 131 '.
Figure 31 is a diagram of representing the processing shown in Figure 30 in detail.
Figure 32 is the block diagram of configuration of second embodiment of the expression control device that is used for power converter according to the present invention.
Figure 33 is the block diagram of the concrete configuration of computing module 2531 shown in expression Figure 32.
Figure 34 is the block diagram of the concrete configuration of synchronization control module 2618 shown in expression Figure 33.
Figure 35 is the sequential chart of the operation of synchronization control circuit 2618 shown in expression Figure 33.
Figure 36 is the diagram of expression embodiment of performed processing method when detecting fault in the computing module at the control device of the electric power converter shown in Figure 33.
Hereinafter with reference to accompanying drawing the preferred embodiments of the present invention are discussed.
Fig. 1 is the block diagram of first embodiment of the electric power converter controller that is suitable for of expression the present invention.
Among Fig. 1, vicinity at the electric power converter 102 that carries out the conversion between alternating electromotive force and the direct current power, power supply to electric power converter 102 input dc power power is housed, and is used to current value and the current value of magnitude of voltage and transition detection and the transducer 111 to 11n that magnitude of voltage is the low power signal of telecommunication in the electrical system that detects electric power converter 102 and be connected to electric power converter 102.The output of transducer 111 to 11n is connected to by holding wire 141 to 14n respectively and is used for the input port that converting analogue signals is the AD module 121 to 123 of digital signal.The input port of each AD module 121 to 123 is connected to the output port of computing module 131 to 133, the conversion timing that these computing modules are specified from the analog signal to the digital signal each AD module 121 to 123.The output port of each AD module 121 to 123 is connected to the input port of computing module 131 to 133 by each holding wire 151 to 153.The input/output end port of computing module 131 to 133 interconnects to 176 by holding wire 161 to 166 and 171.The output port of computing module 131 to 133 is connected to the input port that selects two voting machines 104 in three, and this voting machine has the sort of signal of the same signal of greater number in a plurality of input signals by each holding wire 181 to 183 outputs.The output port that selects two voting machines 104 in three is connected to the switch terminals of each switching device that forms current converter 102 by holding wire 106.
The operation of the embodiment of electric power converter controller shown in below will illustrating.
At electric power converter 102 be connected in the electrical system of electric power converter 102, current value and magnitude of voltage to the power supply of electric power converter 102 supply capabilities are detected by transducer 111 to 11n, are converted to the low power signal of telecommunication and are input to AD module 121 to 123 by holding wire 141 to 14n by transducer 111 to 11n.After the analog signal of conversion input was digital signal, each AD module 121 to 123 shifted each computing module 131 to 133 by each holding wire 151 to 153.Conversion in the AD module 121 to 123 from the analog signal to the digital signal is adapted to by the timing of computing module 131 to 133 by each holding wire 191 to 193 appointments.
Computing module 131 transmits synchronizing signal by holding wire 171 and 76 respectively to each computing module 132 and 133, and receives synchronizing signal by holding wire 175 and 173 from computing module 132 and 133.Based on reaching by holding wire 175 and 173 synchronizing signals that receive by holding wire 171 and 176 synchronizing signals that transmit, computing module 131 produces the enabling signal that is used for the conversion operations of AD module 121, and transmits the operation start signal that is produced by holding wire 191 to AD module 121.On the other hand, computing module 131 receives data and transmits the data that received from AD module 121 by holding wire 161 and 166 respectively to computing module 132 and 133 from AD module 121 by holding wire 151, and meanwhile respectively by holding wire 165 and 163 process computing modules 132 and 133 data that receive from AD module 122 and 123.When all three AD modules 121,122 and 123 are received data, computing module 131 algorithm according to the rules decision making see whether have among three AD modules 121,122 and 123 one of any such as open circuit, nonvolatil fault such as short circuit takes place, it is undesired that wherein remarkable different data are judged as, the AD module that never breaks down is selected data, produces to be used for controlling the pulse width modulation controlled pulse of electric power converter 102 operations and to select two voting machines 104 to transmit this control impuls in three by holding wire 181. Other computing module 132 and 133 is carried out and computing module 131 identical operations.That is, computing module 131,132 and 133 uses from the data of identical AD module and carries out same arithmetic operation.Thereby computing module 131,132 and 133 should produce same control impuls.If the control impuls that is produced by each computing module then can be decision making and at certain computing module fault take place through more inconsistent.
Fig. 2 is that expression is used for the flow chart that the AD module that never breaks down is selected the algorithm of data among AD module 121,122 and 123.Hereinafter with reference to shown in the selection operation of flowchart text computing module 131.
Computing module 131 initial setting up indication AD module 121 is in the parameter e1 of fault and the parameter e2 (step S1) that indication AD module 122 is in fault.
Then, all data of receiving from computing module 131 of verification see whether undesired situation occurs.Owing in the AD transformation result, include error, so do not break down from inconsistent always not being illustrated in the AD module of the data of two AD modules.Thereby whether the detection of improper situation is by the data from two AD modules being compared and according to dropping within the predetermined number range from the difference between the data of two AD modules carrying out.If do not fall in the predetermined number range, then make the abnormal judgement of one of two data from the difference between the data of two modules A D.Otherwise when falling in the predetermined number range from the difference between the data of two modules A D, two data of then can decisioing making all are normal.In order to carry out this decision, computing module 131 at first receives data to be determined (step S2), calculates poor from the data of AD module 121 and 122 and the judgement (step S3) of going on business and whether falling into the predetermined value scope.
When surpassing predetermined numerical value and being made in the judgement that one of AD module breaks down from the data of AD module 121 with from the difference of the data of AD module 122, then making improper situation based on the difference between the data, to appear at AD module 121 still be 122 judgement (step S4).
When surpass from the difference between the data of AD module 121 and 123 the predetermined value scope and thereby when being made in the judgement that one of two modules break down, judge that then fault occurs in AD module 121.Indicate then at AD module 121 out of order parameter e1 and be set to one (1) (step S5).
When break down in one of two AD modules 121 and 122 from the difference indication between the data of AD module 121 and 122 and from the difference between the data of AD module 121 and 123 fall into the predetermined value scope and thereby when being made in the judgement that two modules do not break down, judge that then fault occurs in AD module 122.Indicate then at AD module 122 out of order parameter e2 and be set to one (1) (step S6).
When falling into normal range (NR), make the judgement that two AD modules 121 and 122 are in normal condition from the difference between the data of AD module 121 and 122.At this moment parameter e1 and e2 are constant.
When all data have been finished improper detection (step S7), select according to 131 pairs of data of computing module as a result of improper detection.At first make verification and see whether parameter e1 is in (1) (step S8).If parameter e1 is 1, then carries out verification and see whether parameter e2 is in one (1) (step S9).
When two parameter e1 and e2 were one (1), then computing module 131 was selected data (step S10) from AD module 123.When parameter e1 is one (1) and parameter e2 when being zero (0), then computing module 131 is selected data (step S11) from AD module 122.On the other hand, when parameter e1 was zero (0), then computing module 131 was selected data (step S12) from AD module 121.
Computing module 131 uses selected data to produce the operation that the pulse code modulated control impuls is controlled electric power converter 102, and selects two voting machines 104 to transmit these control impuls in three by holding wire 181.
Select two voting machines 104 to receive the control impuls that is used for electric power converter 102 in three, be used for selecting control impuls by the majority of input control impuls to carry out selecting in three two voting from three computing modules 131 to 133 by holding wire 181 to 183.Then, selecteed control impuls is sent to the switch terminals of each switching device of electric power converter 102.Both made and broken down, and also can select correct control impuls and be sent to electric power converter 102, thereby can carry out normal handling continuously to obtain high reliability at one of any computing module.
Fig. 3 is the block diagram of concrete structure of AD module 121 of the electric power converter controller of presentation graphs 1.Here, for the purpose of simplifying the description, an example that uses four transducers is shown.
AD module 121 has and is used for AD plate 202 that converting analogue signals is a digital signal and 204 and the transfer blade 206 of the transfer of the numerical data of control transformation.Holding wire 141 and 142 is connected to the input port of AD plate 202, and data/address bus 212 is connected to its output port.On the other hand, holding wire 143 and 144 is connected to the input port of the AD plate 204 of control signal 214 inputs, and its output port is connected to data/address bus 212.Holding wire 191 and data/address bus 212 are connected to the input port of the transfer blade of control signal 214 inputs, and holding wire 151 is connected to its output port with output control signal 214.
The operation of AD module 121 below will be discussed.
AD plate 202 is used to start the order of AD conversion by control signal 214 responses from transfer blade 206, so that carry out the conversion of analog to digital for the signals that pass through holding wire 141 and 142 receptions from transducer 111 and 112.On the other hand, AD plate 202 is by the order that be used to read state of control signal 214 responses from transfer blade 206, so that export the signal that carries out state of indication self AD conversion operations to data/address bus 121.On the other hand, when by control signal 214 when transfer blade 206 is received the order that is used for sense data, the numerical data that AD transfer blade 202 has been changed to data/address bus 212 outputs.The operation of AD plate 204 is identical with the operation of AD plate 202.
Transfer blade 206 transmits the order that start ADs conversion so that export control signal 214 to AD plate 202 and 204 by holding wire 191 operation response commencing signals.Next, by control signal 214, transfer blade 206 transmits and is used to read the order of AD plate 202 and 204 states so that receive the signal of indication AD plate 202 and 204 states by data/address bus 212.When the signal indication AD of indicating status plate 202 and 204 was in the AD conversion, then reading up to AD of repeat mode converted.When the AD conversion had all been finished among both at AD plate 202 and 204, transfer blade 206 transmitted control signals and sends the order that is used for sense data so that receive data by data/address bus 212 to AD plate 202 and 204.In case receive all data corresponding to four transducers, then transfer blade 206 is exported the data of receiving to holding wire 151.
The AD module 122 and 123 of the power converter controller of Fig. 1 is similar to the formation of AD module 121 so that carry out same operation.
Fig. 4 is the block diagram of the concrete configuration of the computing module 131 shown in the presentation graphs 1.
In the figure, holding wire 163 is connected to and is used to change the input port that serial data is the serial input circuit 302 of parallel data.An output port of serial input circuit 302 is connected to the input port of transfering controling circuit 312 by holding wire 332, and transfering controling circuit 312 is used for the data in an internal storage temporary transient storage input signal and output storage when reading request.Holding wire 161 is connected to and is used to change the output port that parallel data is the serial output circuit 304 of serial data.The input port of serial output circuit 304 is connected to the output port of transfering controling circuit 312 by holding wire 334.Holding wire 151 is connected to the input port of serial input circuit 306, and the output port of serial input circuit 306 is connected to the input port of transfering controling circuit 312 by holding wire 336.Holding wire 166 is connected to the output port of serial input circuit 308, and the input port of serial output circuit 308 is connected to the output port of transfering controling circuit 312 by holding wire 338.Holding wire 165 is connected to the input port of serial input circuit 310, and the output port of input circuit 310 is connected to the input port of transfering controling circuit by holding wire 340.And then the input and output port of transfering controling circuit 312 is also connected to bus 342.
Except transfering controling circuit 312, being connected to also being useful on of bus 342 monitors in central processing unit (CPU) 320, read-only memory (ROM) 314, the random-access memory (ram) 316 and the data on the bus 342, and be used for detecting input and output port, and be used for electric power converter 102 is produced and the input and output port of the output control circuit 324 of output control pulse such as the fault monitoring circuit that opens circuit 322 of fault such as the noise on the bus 342 and bus.The output port of fault monitoring circuit 322 also is connected to the input port of CPU 320 by holding wire 346.The input port of output control circuit 324 also is connected to the output port that is used for AD module 121 is produced the synchronization control circuit 318 of operation start signal by holding wire 344.The output port of synchronization control circuit is connected to holding wire 181.And then the output port of synchronization control circuit is also connected to holding wire 191,171,176 and 344, and its input port is also connected to holding wire 173 and 175.
The operation of computing module 131 below will be described.
When serial input circuit 302,306 and 310 receives serial data from holding wire 163,151 and 165, they are converted to parallel data with the serial data of receiving, and export parallel datas by holding wire 332,336 and 340 to transfering controling circuit 312 respectively.
When serial output circuit 304 and 308 received parallel data from transfering controling circuit 312 by holding wire 334 and 338, the parallel data that their conversions are received was a serial data, and to holding wire 161 and 166 these serial datas of output.
When transfering controling circuit 312 received parallel data from serial input circuit 302,306 and 310 by holding wire 332,336 and 340, it is temporary transient this parallel data of storage in an internal storage.
And then when transfering controling circuit 312 was read request by bus 342 receptions from the data of CPU 320, it exported the data that are stored in the memory by 342 to CPU 320.And then when transfering controling circuit received data from CPU 320 by bus 342, it stored these data in internal storage.
In addition, after the data that serial input circuit 306 or CPU 320 receive, it is by holding wire 334 and 338 data to serial output circuit 304 and 308 output storages in the temporary transient storage of transfering controling circuit.
CPU 320 passes through transfering controling circuit 312 in the data of predetermined cycle reception from three AD modules 121,122 and 123, through bus 342, produce the data that are used to control electric power converter 102 by the data of selecting normal AD module, and transmit the data that produce to output control circuit 324 by bus 342.And then when needs during to other computing modules 132 and 133 transferring datas, CPU shifts the data that need by bus 342 to transfering controling circuit 312.
Data on fault monitoring circuit 322 monitor bus 342, and when detecting fault, export initializing signals to CPU 320 by holding wire 346.The detection of fault is to be undertaken by signal of using to bus supply such as the such error checking of parity check and the improper property that detects data.Can use a kind of method, wherein have a program to be used for the check sum of ROM 314, the read/write verification of RAM 316 etc., and when detecting mistake, mistake occur by bus 342 notice fault monitoring circuits.
Synchronization control circuit 318 receives and transmits synchronizing signal to it from computing module 132 and 133 by holding wire 171,175 and 176,173 respectively, produces the operation start signal that is used for the AD conversion and to holding wire 191 these signals of output.Simultaneously, synchronization control circuit is counted elapsed time after the operation start signal becomes logic level 1, and exports these count values to output control circuit 324 by holding wire 344.
Based on reaching the temporal information that receives from synchronization control circuit by holding wire 344 from the control data that CPU 320 receives by bus 342, output control circuit 324 produces the control impuls that is used for circuit converter 102, and to holding wire 181 these control impuls of output.
Computing module 132 and 133 has the configuration identical with computing module 131 and operates by identical mode.
Fig. 5 is the block diagram of the concrete configuration of the transfering controling circuit 312 shown in the presentation graphs 4.
Among Fig. 5, holding wire 332,336 and 340 is connected respectively to the input port of buffer 402,406 and 410.Buffer 402,406 and 410 output port are connected to bus 422.Buffer 404 and 408 input port are connected to bus 422, and the output port of buffer 404 and 408 is connected respectively to holding wire 334 and 338.The input port of buffer 416, the input/output end port of the output port of buffer 418 and memory 412 also is connected to bus 422.The input port of the output port of buffer 416 and buffer 418 is connected to bus 342.The input/output end port that control circuit 414 is used for reading and transmit the data that are stored in memory 412 is connected to each input/output end port of buffer 402,404,406,408,410,416 and 418.
The operation of control circuit 312 below will be described.
When buffer 402,406 and 410 received data by holding wire 332,336 and 340, they were to the write request of control circuit 414 outputs for memory 412.When buffer when control circuit 414 receives the signal of indication " ready ", they to bus 422 outputs by holding wire 332,336 and 340 data that receive.The data that buffer 402,406 and 410 outputs to bus 422 are received and are stored in the memory by memory 412.
When buffer 404 and 408 when control circuit 414 receives data and gets request, they are respectively to holding wire 334 and 338 outputs.The data that buffer 404 and 408 is obtained are from the data of memory 412 to bus 422 outputs.
When memory 412 when control circuit 414 receives the data sense commands, it is to bus 422 output data designated.And then, when memory when control circuit 414 receives the data write orders, it obtains data from bus 422, and stores this data in the unit of appointment.
When buffer 416 received the data sense command by bus 342, it read request to control circuit 414 dateouts.When buffer was received the signal of indication " ready ", it obtained the data of memory 412 to bus 422 outputs, and to bus 342 these data of output.
When buffer 418 when bus 342 is received the data write order, it obtains the data that appear on the bus 342, and to the write request of control circuit 414 outputs to memory.And then when buffer when control circuit 414 is received the signal of indication " ready ", the data that it is obtained from bus 342 to bus 422 outputs.The data that buffer 418 outputs to bus 422 are placed into memory 412 and are stored in the memory.
Fig. 6 is the diagram that data are arranged on the expression memory shown in Figure 5.Memory 412 is divided into four zones, data of promptly receiving 1 to 3 and transmission data 1.
In data 1 that are used for receiving and 3 zone, respectively with data from buffer 402 and 410.The data that write are read out under the request of reading from buffer 416.
In the zone of the data 2 that are used for receiving, with data from buffer 406.Finished write in, data output to buffer 404 and 408.And then data are read out from buffer 416 when reading request.
In the zone of the data 1 that are used for transmitting, with data from buffer 418.Finished write in, data output to buffer 404 and 408.
Fig. 7 is the block diagram of the concrete configuration of expression synchronization control circuit 318 shown in Figure 4.
Among Fig. 7, holding wire 173 is connected to the input of buffer 616.The output of buffer 616 is connected to an input of each AND gate circuit 608 and 612 by holding wire 646.Holding wire 175 is connected to the input of buffer 622.The output of buffer 622 is connected to another input of AND gate circuit 612 and an input of AND gate circuit 610 by holding wire 644.AND gate circuit 608 and each another input of 610 are connected to the output of delay circuit (DL circuit), and this delay circuit is used to the signal that postpones to receive and the signal by holding wire 642 output delaies.And then AND gate circuit 608,610 and 612 output are connected to each input of the OR gate circuits 606 of three inputs.The output of OR gate circuit 606 is connected to the reset terminal of counter 604 and the input of buffer 602 by holding wire 632.The output of buffer 602 is connected to holding wire 191.The output that is used for the count value of counter 604 is connected to holding wire 344, and it is used to export the carry end of counting termination signal is connected to buffer 618,620 and DL circuit 614 by holding wire 640 each input.The output of buffer 618,620 is connected respectively to holding wire 171 and 176.
The operation of synchronization control circuit 318 below will be described.
Counter 604 increases its count value one by one by each preset time, and to holding wire 344 its count values of output.And then when counter was received operation start signal from OR circuit 606 by holding wire 632, it removes its count value was 0.When count value becomes when equaling predetermined value, counter is fixed its count value, and to holding wire 640 output counting termination signals.
Receive counting during termination signal by holding wire 640 from counter 604 when DL circuit 614, its delay counter termination signal reaches the scheduled time, and then to the signal of holding wire 642 output delaies.By between other computing modules 132 and 133, shifting the counter required time of termination signal, make DL circuit 614 be adapted to postpone the counting termination signal of computing module 131.
Buffer 616 and 622 passes through holding wire 173 and 175 from computing module 133 and 132 count pick up termination signals, and respectively to holding wire 646 and 644 outputs.Buffer 618 and 620 passes through holding wire 640 from counter 604 count pick up termination signals, and respectively to holding wire 171 and 176 outputs.
Three AND circuit 608,610 and 612 and OR circuit 606 select two voting machine in forming one three.Promptly, if numerical value more than two holding wires 642,644 and 646, perhaps be in logic level 1 more than two numerical value from the counting termination signal of three computing modules 131,132 and 133, then voting machine is to the signal of holding wire 632 output indication logic levels 1, otherwise it is to the signal of holding wire 632 output indication logic levels 0.From three, select the signal of the indication logic level 1 of two voting machines output to be input to AD module 121 by buffer 602 and holding wire 191.
Fig. 8 is the sequential chart of the operation of synchronization control circuit 318 shown in the presentation graphs 4.
In the counter of each computing module 131 to 133, count value is pursued one-plus-one by cycle regular hour, and termination signal is counted in output when count value reaches predetermined value.Because it is different for each module that count value adds this certain time cycle of one by it, thus the output timing of counting termination signal with each module difference.In the present embodiment, suppose at first to export, and export at last from the output of the counting termination signal of computing module 132 from the output of the counting termination signal of computing module 131.When the counting termination signal of any two computing modules transferred logic level 1 to, the synchronization control circuit of each computing module made that the logic level that shifts enabling signal is 1.Thereby, in this example, when the counting termination signal of computing module 132 becomes logic level 1, the transfer enabling signal of all AD modules 121 to 123 is transferred to logic level 1, can be digital signal with identical timing converting analogue signals like this, just in all AD modules 121 to 123.When the counting termination signal, when promptly shifting enabling signal and becoming logic level 1, because the counter of each computing module is reset, the counting termination signal also just transfers logic level 0 to.In this example, before becoming logic level 1, its counting termination signal, is maintained logic level 0 in all time so it counts termination signal because the counter of computing module 132 is reset.
Fig. 9 is the block diagram of concrete structure of the output control circuit 324 of the computing module 131 shown in the presentation graphs 4.
Among Fig. 9, holding wire 344 is connected to one of input of comparator 804, and another input is connected to the output port of register 802 by holding wire 812.The output of comparator 804 is connected to the triggering signal input of latch cicuit 809 by holding wire 816, and the output of latch cicuit 806 is connected to the input of buffer 808 by holding wire 818.The input of register 802 is connected to bus 342, and the output of buffer 808 is connected to holding wire 181.
The operation of output control circuit 324 below will be described.
Register 802 receives by bus 342 and storage is used for the data of electric power converter control from CPU 320, and passes through holding wire 812 and 814 respectively to comparator 804 and latch cicuit 806 outputs.The data that are used for circuit converter control are included in the signal controlling cycle and are used for the relative time information with respect to fiducial time of the rising or the step-down operation of control impuls, and the judgement control impuls is selected as the information of logic level 0 or logic level 1 when through the relative time of the operation that is used to specify.
Comparator is to comparing from synchronization control circuit 318 count value of receiving and the relative time information of receiving from register by holding wire 812 by holding wire 344, if wherein both are consistent each other, then make the output level of holding wire 816 become logic level 1, and inconsistent, then make the output level of holding wire 816 become logic level 0.
When the output level of the holding wire 816 of comparator 804 transferred logic level 1 to, latch cicuit 806 was according to the output level that regularly changes holding wire 818.Like this output level of Bian Huaing be equal to from register 802 signal supplied level by holding wire 814.
Buffer 808 provides the output signal of latch cicuit 806 to holding wire 181.
Like this, the control impuls that is used to control the switching manipulation of electric power converter 102 is set to the signal level pointed to by CPU 320 in the CPU320 predetermined timing.
Figure 10 is the block diagram of the concrete structure of the majority decision circuit in the electric power converter controller 104 shown in the presentation graphs 1.
Among Figure 10, holding wire 181,182 and 183 is connected respectively to the input of buffer 902,904 and 906.The output of buffer 902 is connected respectively to one of input of AND gate circuit 908 and 912 by holding wire 922.The output of buffer 904 is connected respectively to one of another input of AND gate circuit 908 and input of AND door 910.The output of buffer 906 is respectively AND gate circuit 910 and 912 another inputs.AND gate circuit 908,910 and 912 output are connected respectively to the input of three input OR gate circuits 914, and the output of OR gate circuit 914 is connected to holding wire 106.
Below, with the operation of explanation majority decision circuit 104.
Buffer 902,904 and 906 receives control impuls respectively by holding wire 181,182 and 183, and provides the control impuls of receiving respectively to holding wire 922,924 and 926.
Majority decision circuit by combination AND circuit 908,910 and 912 and OR circuit 914 set up.When 2 on holding wire 922,924 and 926 or more control signal have logic level 1, determined the control impuls on the holding wire 106 also to be logic level 1, and when 2 or more control signal have logic level 0, determined that the control impuls on the holding wire 106 also is logic level 0.
Figure 11 represents the handling process of normal running in the computing module 131,132 and 133 of electric power converter controller shown in Figure 1.
Figure 11 a is the handling process in computing module 131,132 and 133.Computing module 131,132 and 133 repeats same operation in cycle regular hour.Computing module 131,132 and 133 is handled cycle k at each, and k+1, k+2 etc. carry out and handle＜0 〉.The startup that is used for the arithmetic operation carried out periodically at each computing module 131,132 and 133 regularly is synchronized, and beginning from the exchange mutually between them of the initial data of supplying with of AD module in each operation cycle.
Figure 11 b is expression signal processing flow chart of handling process in the signal operation module in the cycle.At first, the data that provide from the AD module when the operation cycle begins are provided mutually for computing module and another computing module in step S11, and then, select active data at step S12, and utilize the data of selecting to carry out computing at step S13 then.Finished after the computing, computing module is changed to the data of idle state to wait for that the back will be shifted.
Figure 12 is the flow chart that predetermined data is handled in the computing step shown in the presentation graphs 11B (step S13).This computing step (S13) is made up of four treatment steps: phase-detection step (step S21), power detection step (step S22), voltage detecting step (step S23) and PWM controlled step (step S24).In following explanation to each treatment step, the letter character that has subscript " k " is represented its numerical value at calculated variable of k operation cycle, and the letter character that has subscript " k-1 " represents that its numerical value is at calculated variable of k-1 operation cycle.
As shown in figure 13, the purpose of phase-detection treatment step (step S21) is in order to carry out such processing, promptly wherein changes profile from the time of magnitude of voltage V in the data of AD module and approached and calculate the phase place q of each time cycle in a single sine curve.
Figure 14 is the example for the detailed process of calculating phase place q phase-detection processing shown in Figure 13.Among Figure 14, the process among the row No.1 is to make time t increase an operation cycle.Process among the row No.2 to 5 is to handle the input data in cycle to variable V (I) storage n in the past, and wherein I is any natural number.Process among the row No.7 to 22 is to be used to calculate the sinusoidal amplitude that is approached.In the process of No.9, suppose that amplitude V0 is the amplitude in the first pre-treatment cycle, obtain the summation d0 of the difference between sine curve and the input data.In the process of No.11, suppose amplitude V0 be amplitude in the first pre-treatment cycle and increment DV and, obtain the summation dp of the difference between sine curve and the input data.In the process of No.13, suppose that amplitude V0 is the poor of amplitude in the first pre-treatment cycle and increment DV, obtain the summation dm of the difference between sine curve and the input data.Be expert at process among the No.15 to 22 obtains summation d0, dp, and the minimum value of dm, and determine that its corresponding amplitude V0 is last numerical value.
The process of row 24 to 25 is used for estimating that sine curve that Figure 13 is approached passes the time t0 of vertical axis (time shaft).These processes are equal to those processes for the capable No.9 to 22 that obtains amplitude V0
The process of row No.27 to 28 is used to estimate the sinusoidal period T of being approached.These processes are equal to those processes for the capable No.9 to 22 that obtains amplitude V0.
The process of row 30 to 34 is used for deducting 2p so that indication surpasses 2p at computing module phase place q indexed variable tv is set from phase place q when phase place q surpasses 2p.
Process among the row No.35 is used to obtain phase place q.
As mentioned above, phase-detection is handled and is only relied on input data and internal data, but does not rely on power detection, the result of voltage control and PWM controlled step.
Figure 15 is an example of the detailed process of power detection step (step S22) shown in Figure 12.Among Figure 15, P represents to have the power composition of the phase place that is equal to voltage V, and Q represents from the phase component of voltage V skew 90 degree.
From Figure 15 obviously as seen, power detection step (step S22) only relies on the data of input, result and internal data that phase-detection step (step S21) is handled, but do not rely on the result of voltage control step (step S23) and PWM controlled step (step S24).
Figure 16 is an example of the detailed process of voltage control step (step S23) shown in Figure 12.Among Figure 16, OP represents to have the voltage composition of the output voltage expected value OV of the phase place that is equal to voltage V, and OQ is the voltage composition that has from the expection voltage OV of the output voltage of the phase places of voltage V skew 90 degree.Calculating for output voltage composition OP and OQ just just is activated when the marker tv that indicates phase place q to surpass 2p transfers 1 to.The correction value that obtains as the product of the difference between gain gp and power P and its desired value PI is added output voltage composition OP to.The correction value that obtains as the product of the difference between gain gq and power Q and its desired value QI is added output voltage composition OQ to.As the sum of products of the cosine of the product of the sine of output voltage composition OP and phase place q and output voltage OQ and phase place q and calculate the output voltage values OV of expection.
As mentioned above, voltage control step (step S23) only relies on the data of input, phase-detection step (step S21), and power detection step (step S22) and internal data, but do not rely on the result of PWM controlled step.
Figure 17 is the schematic diagram of the processing of expression PWM controlled step (step S24).In PWM controlled step (step S24), compare between the desired value OV to standard triangular wave and output voltage, and dispose PWM then like this and control, make that when desired value OV surpasses triangular wave control impuls can conducting, and when triangular wave during above desired value OV control impuls can turn-off.
Figure 18 is an example of the detailed process in the PWM controlled step (step S24).
Among Figure 18, row 1 and 2 process are used for making the variable f increment of phase place of indication triangular wave.Variable f handles phase place place at each to be increased one by one, and 0 and 2m-1 between change, wherein m is that the magnitude of voltage of hypothesis triangular wave is to be normalized value under 1 the situation in 1 cycle of handling from-VM to the time that VM changes.The magnitude of voltage that this means triangular wave 0 and m between increase to VM from-VM, and magnitude of voltage reduces from VM to-VM between m and 2m.
Process among the row No.3 to 12 is used to obtain the current magnitude of voltage of triangular wave and the change direction S of control impuls.Since when variable f during less than phase place m control impuls change to OFF from ON, so the direction S of variation is set to 0.On the other hand, because control impuls changes to ON from OFF when variable f surpasses phase place m, so the direction S that changes is set to 1.
Process in the row 13 to 18 is used to obtain the crosspoint between triangular wave and the output voltage expected value OV.Each other under the situation of intersecting in next single processing cycle of current time, the intersection time is set to C at the expected value OV of triangular wave and output voltage.Numerical value C defines by the count value that relative time is converted to counter 604, and the count value of counter 604 changes to CM from 0 in single processing cycle.Each other in single processing cycle under the Uncrossed situation, numerical value C is set to greater than maximum CM, changes to prevent control impuls at the expected value OV of triangular wave and output voltage.
As mentioned above, PWM controlled step (step S24) depends on the input data, the result of phase-detection step (step S21), power detection step (step S22) and voltage control step (step S23), and internal data.
As mentioned above, each treatment step in the electric power converter controller is from upstream to the downstream and can be decomposed corresponding to data dependence relation.
Figure 19 is a diagram of representing the fail result of computing concrete among Figure 12 and correspondence thereof.
Figure 19 A is illustrated in fault and occurs in the fail result under the impaired situation of internal data V (n-1) in cycle (k-1) and the phase-detection step (step S21).
In the processing for cycle (k), it is invalid that V (n) result of calculation that depends on numerical value V (n-1) becomes, but numerical value V (n-1) reverts to effectively.In addition, in the processing for cycle (k+1), V (n) result of calculation becomes effectively.
As implied above, it is invalid that internal data V (1) was unfortunately become to V (n), as long as the input data guarantee that then they just can revert to effectively for effective.Can in subsequent processes, revert to effective internal data V (1) such as once becoming invalid and be called as the onrecurrent data to the such data of V (n).
Figure 19 B is illustrated in and breaks down in the cycle (k-1) and be used for fail result under the impaired situation of voltage-controlled internal data OP.
In processing, because the numerical value of internal data OP depends on self, so its numerical value remains effectively for cycle (k).This keeps in cycle (k+1) processing afterwards similarly.
Like this, because internal data OP depends on they self, so if in a single day they transfer invalid data to, they can not be resumed to effectively again.In case thisly become data invalid and that can not be resumed and be called as recursive data.Have only recursive data just can when any fault takes place, transfer to failure system from normal system.Can be understood that, be used for storing the memory area of recursive data and being used for storing onrecurrent memory of data zone by defining respectively, and can carry out the processing that is used for shifting specially recursive data effectively.
Figure 19 C is illustrated in and breaks down in the cycle (k-1) and be used for fail result under the impaired situation of dateout P of power detection.
Result of calculation for all data P, OP and V in the processing of cycle (k) when invalid depends on data P.This situation keeps in cycle (k+1) processing afterwards similarly.
Like this, in case that the result of power detection becomes is invalid, it is invalid that voltage-controlled result also becomes.Thereby, just need when the data in any fault of generation and the effective system are transferred to null system, in upstream process, to shift in advance internal data.
Figure 20 is expression when the diagram of first embodiment of performed processing method during detection failure in the computing module 131 of the control device of electric power converter shown in Fig. 1.
At operation cycle (k+2), computing module 131 detects fault, makes CPU 320 produce reset signal, the register constant in control control circuit, RAM 316 and memory 412, and start-up control circuit and the operation of each element initialization.Initialization except in, at first undertaken whether having detected similar fault in the verification of hardware fault and the verification predetermined period of time in the past by self-check program.If the hardware fault of detecting has perhaps detected similar fault in the predetermined period of time in the past, then determine to recover this fault, and stop initialization process.Otherwise, begin to carry out aforesaid initialization process such as hardware such as registers.
At operation cycle (k+3), because computing module 131 is to be in during the initialization process, so can not between this computing module and other computing modules, carry out the AD exchanges data.Thereby computing module 132 and 133 is selected and is handled from except the normal data from two data the data of computing module 131.
In the operation cycle (k+4) and (k+5), because finished initialization process, so carry out normal process (handle＜0 〉).By the processing during two cycles, the onrecurrent data in the internal data obtain effective numerical value.Yet recursive data remains invalid, and dateout also be retained as invalid.
At operation cycle (k+6), computing module 131 request computing modules 132 begin the transfer (processing＜i 〉) of recursive data in normal process.
At operation cycle (k+7), in normal process, computing module 131 shifts the recursive data (processing＜t1 〉, processing＜r1 〉) of relevant phase-detection step (step S21) shown in Figure 12 to computing module 131 from computing module 132.
At operation cycle (k+8), in normal process, computing module 131 shifts the recursive data (processing＜t2 〉, processing＜r2 〉) of relevant phase-detection step (step S22) shown in Figure 12 to computing module 131 from computing module 132.Because computing module 131 carries out this processing by using from computing module 132 in the recursive data of the relevant phase-detection step (step S21) of operation cycle (k+7) reception, so all results of phase-detection step (step S21) become effective numerical value.
At operation cycle (k+9), in normal process, computing module 131 shifts the recursive data (processing＜t3 〉, processing＜r3 〉) of relevant voltage control step (step S23) shown in Figure 12 to computing module 131 from computing module 132.Because computing module 131 carries out this processing in the operation cycle (k+7) with the relevant phase-detection step (step S21) of (k+8) reception and the recursive data of power detection step (step S22) respectively by using from computing module 132, so all results of phase-detection step (step S21) and power detection step (step S22) become effective numerical value.
At operation cycle (k+10), in normal process, computing module 131 shifts the recursive data (processing＜t4 〉, processing＜r4 〉) of relevant PWM controlled step (step S24) shown in Figure 12 to computing module 131 from computing module 132.Because computing module 131 carries out this processing in operation cycle (k+7), (k+8) and the recursive data of relevant phase-detection step (step S21), power detection step (step S22) and voltage control step (step S23) that (k+9) receives respectively by using from computing module 132, so all results of phase-detection step (step S21), power detection step (step S22) and voltage detecting step (step S23) become effective numerical value.
In the operation cycle (k+11) and afterwards, computing module is carried out normal process (handle＜0 〉).Because computing module 131 carries out this processing in operation cycle (k+7), (k+8), (k+9) and the recursive data of relevant phase-detection step (step S21), power detection step (step S22), voltage control step (step S23) and PWM controlled step (step S24) that (k+10) receives respectively by using from computing module 132, so all results of phase-detection step (step S21), power detection step (step S22), voltage detecting step (step S23) and PWM controlled step (step S24) become effective numerical value.
During the operation cycle (k+2) arrived (k+10), computing module 131 output valid data were because the dateout of computing module 132 and 133 is selected two voting machine 104 selections in three, so can normal running electric power converter 102.
So like this, can be reversed to effective numerical value at processing onrecurrent data V (i) during carrying out continuously during the operation cycle (k+2).Yet it can not always carry out inverse transform an operation cycle, and must a maximum n operation cycle in order to be reversed to effective numerical value.So as shown in figure 20, before the transfer of recursive data began, computing module 131 must be carried out repeatedly (being secondary) normal running＜0 in the situation of example shown in Figure 20 〉.
Figure 21 A, 21B and 21C are the diagrams of the processing shown in Figure 20 of expression in detail.
Figure 21 A is illustrated in the content of processing of operation cycle (k+6) computing module 131 of Figure 20.Though the contents processing of normal condition shown in the content of handling and Figure 11 B is (exchanges data step S11 much at one, data are selected step S12, calculation process step S13 and idle step S14 are identical), but different with it is in normal condition, wherein is provided with the step (S12) of output recursive data transfer request after finishing calculation process step S13.
Figure 21 B is illustrated in the content of processing of operation cycle (k+6) computing module 131 of Figure 20.Though the contents processing of normal condition shown in the content of handling and Figure 11 B also much at one, different with it is in normal condition, wherein is provided with the step (S212) that transmits recursive data after finishing calculation process step S13.
Figure 21 C is illustrated in the content of processing of operation cycle (k+6) computing module 131 of Figure 20.Though the contents processing of normal condition shown in the content of handling and Figure 11 B also much at one, different with it is in normal condition, wherein is provided with the step (S213) that receives recursive data after finishing calculation process step S13.
Figure 22 is the diagram of expression second embodiment of performed processing method when detecting fault in the computing module 131 at electric power converter controller shown in Figure 1.The characteristics of this embodiment are that not only when fault takes place, and when carrying out normal process, order is carried out the exchange of the recursive data in each treatment step shown in Figure 12 among three computing modules.
At operation cycle (k), all computing modules are normally carried out processing (processing＜c2 〉).And then computing module is finished the recursive data among the exchange power detection step S22 during cycle free time of handling, and the verification consistency.If detect inconsistently, then select to have the numerical value of high reliability and proceed to handle according to described process after a while.
Though the processing in the processing in operation cycle (k+1) and operation cycle (k) is carried out by similar mode, be that with the processing difference in operation cycle (k) recursive data is the recursive data among the voltage control step S23.
At operation cycle (k+2), computing module 131 detection failure allow CPU 320 to produce reset signal, and the register constant in control control circuit 414, RAM 316 and memory 412, the initialization process of start-up control circuit and each element.Computing module 131 can not be carried out the exchanges data between this computing module and other computing modules.Thereby computing module 132 and 133 is for two recursive data verification consistency of removing from the recursive data of computing module 131.
Because at operation cycle (k+3), computing module 131 is in during the initialization process, it can not carry out the exchanges data between this computing module and other computing modules.Thereby computing module 132 and 133 is selected and is handled from the normal data of removing from two data outside the computing module 131.The consistency of recursive data is by the same way as verification.
At operation cycle (k+4), carry out the processing identical (＜c2 〉), so and the consistency of recursive data among the verification power detection step S22 with the processing in operation cycle (k).Thereby, in computing module 131, also select from computing module 132 and 133 recursive data that shift.Recursive data among the power detection step S22 becomes effective numerical value.
Processing in the operation cycle (k+5) is also identical with the processing in operation cycle (k+4).Thereby the recursive data among the voltage control step S23 becomes effective numerical value.Though the recursive data in power detection step S22 once obtained valid data in the operation cycle (k+4), but depend on the recursive data among the power detection step S22 of numerical value of the recursive data among the phase-detection step S21, after the processing of complete operation cycle (k+5), become invalid data, because the recursive data among the phase-detection step S21 of computing module 131 is not in effective numerical value.
Processing in the operation cycle (k+6) is also identical with the processing in operation cycle (k+5).Thereby though the recursive data among the PWM controlled step S24 becomes effective numerical value, the recursive data after finishing processing among the voltage control step S23 becomes invalid data.
Processing in the operation cycle (k+7) is also identical with the processing in operation cycle (k+5).Thereby though the recursive data among the phase-detection step S21 becomes effective numerical value, the recursive data after finishing processing among the PWM controlled step S24 becomes invalid data.
Processing in the operation cycle (k+8) is also identical with the processing in operation cycle (k+5).And then, both made finish handle after recursive data in phase-detection step S21 still remain valid because it only depends on input data and internal data among the phase-detection step S21.
Processing in the operation cycle (k+9) is also identical with the processing in operation cycle (k+8).Thereby the recursive data among the voltage control step S23 becomes effective numerical value, and the recursive data among recursive data in phase-detection step S21 and the power detection step S22 also remains effective numerical value.
Processing in the operation cycle (k+10) is also identical with the processing in operation cycle (k+8).Thereby the recursive data among the PWM controlled step S24 becomes effective numerical value, and the recursive data that reaches among the voltage control step S23 among the recursive data in phase-detection step S21, the power detection step S22 also remains effective numerical value.
In the operation cycle (k+11) and afterwards, carry out normal process.Among recursive data among the phase-detection step S21, the power detection step S22, the result of voltage control step S23 and PWM controlled step becomes effective numerical value.
By be provided with when computing module have with it be the processing just often carried out be equal to fault the time performed processing, can simplify the structure of software.Thereby its effect is the fault reduction of software.And then, because also be in normal condition, carry out the consistency desired result of recursive data,, also can normally handle by the data of selecting to have high reliability so both made the sort of fault that appearance can not find by normal method thereby the inconsistency that recursive data occurs.
Figure 23 is a diagram of representing each processing shown in Figure 22 (＜c1〉to＜c4 〉) in detail.The content of handling basically with processing＜0 shown in Figure 11 B content identical, institute's difference is, is provided with recursive data exchange step (step S231) and recursive data selection step (S232) afterwards in calculation process (S13).
Figure 24 is the flow chart that recursive data is selected the handling process in the step (S232) shown in expression Figure 23.Select the operation of step hereinafter with reference to this flowchart text recursive data.
At first, the variable e of indication error code is initialized to 0 (step S241).
Then, the recursive data D1 of computing module 131 and the recursive data D2 of computing module 132 are compared (step S242) each other.If both are unequal, then add 1 (step S243) to variable e.
Then, the recursive data D1 of computing module 131 and the recursive data D3 of computing module 133 are compared (step S244) each other.If both are unequal, then add 2 (step S245) to variable e.
Then, the recursive data D2 of computing module 132 and the recursive data D3 of computing module 133 are compared (step S246) each other.If both are unequal, then add 4 (step S247) to variable e.
The numerical value of verification variable e (step S248) then.
If the numerical value of variable e is 0, then all recursive data D1, D2 and D3 are normal, thereby any recursive data is selectable.Suppose the recursive data D1 selected (step S249) of computing module 131.
If the numerical value of variable e is 3, then the recursive data D1 of computing module 131 is abnormal, and the recursive data D2 of computing module 132 and 133 and D3 are normal.Under this situation, the recursive data D3 of the recursive data D2 of computing module 132 and computing module 133 is selectable.Suppose the recursive data D2 selected (step S250) of computing module 132.
If the numerical value of variable e is 5, then the recursive data D2 of computing module 132 is abnormal, and the recursive data D1 of computing module 131 and 133 and D3 are normal.Under this situation, the recursive data D3 of the recursive data D1 of computing module 131 and computing module 133 is selectable.Suppose the recursive data D1 selected (step S251) of computing module 131.
If the numerical value of variable e is 6, then the recursive data D3 of computing module 133 is abnormal, and the recursive data D1 of computing module 131 and 132 and D2 are normal.Under this situation, the recursive data D2 of the recursive data D1 of computing module 131 and computing module 132 is selectable.Suppose the recursive data D1 selected (step S252) of computing module 131.
If the numerical value of variable e is 7, then the recursive data of plural computing module is abnormal.Owing under this situation, can not determine which computing module is normal, so select the recursive data D of three computing modules 131,132 and 133 1, D 2And D 3Mean value (step S253).
The numerical value of variable e is that 1,2 or 4 situation can not take place in principle.
Figure 25 is the block diagram of second embodiment of expression computing module 131 concrete configurations shown in Figure 1.The characteristics of present embodiment have been a plurality of operation boards.
Computing module 131 ' comprise a transfer blade 1802 and two operation boards 1804,1806 of being used for transfer signal, each is used to carry out arithmetic operation.
Holding wire 163,151,165,173,175 and bus 1812 be connected to the input port of transfer blade.Operation board 1804 and 1806 input/output end port are connected to bus 1812.
Below will illustrate computing module 131 ' operation.
Transfer blade 1802 by holding wire 171,176 to computing module 132 ', 133 ' (each has and computing module 131 ' identical configuration) transmit synchronizing signals, and by holding wire 175,173 respectively from computing module 132 ', 133 ' receive synchronizing signal.Computing module 131 ' reach by the enabling signal of 171, the 176 synchronizing signals generations that transmit to AD module 121 based on the synchronizing signal of passing through holding wire 175,173 receptions, and export these enabling signals to holding wire 191.And then, computing module 131 ' receive data from AD module 121 by holding wire 151, and by holding wire 161,166 to computing module 132 ', 133 ' transmit the data that receive from AD module 121.In addition, it by holding wire 165,163 from AD module 122,123 through computing modules 132 ', 133 ' receive data.When all data of receiving from three AD modules 121 to 123, according to the generation of the fault in three AD modules of algorithm verification shown in Figure 2.Data from the AD module that does not wherein break down are selected, and selecteed data are sent to operation board 1804 and 1806 by bus 1812.And then transfer blade receives control data from computing module 1804, produces the control impuls that is used for power converter 102, and to holding wire 181 these control impuls of output.
Operation board 1804 and 1806 receives data by bus 1812 from transfer blade 1802, and carries out arithmetic operation, receives the also intermediate object program of transfer operation by bus 1812.
Figure 26 is the block diagram of the concrete configuration of the transfer blade 1802 shown in expression Figure 25.The configuration of transfer blade 1802 is almost identical with the configuration of computing module 131 shown in Figure 4.Yet the difference in the configuration is to be provided with reception and transmission that bus interface 1904 is used for the signal between intermediary and the level and smooth bus 342 and 1812.
When interface 1904 receives data write signal from CPU 320 by bus 342, the write request that it receives to bus 1812 outputs.When bus interface when bus 1812 receives the signal of indication " ready ", it is to bus 1812 output write datas.When bus interface 1904 when CPU 320 receives data and reads request signal, the read request that it is received to bus 1812 outputs.When the signal received from bus 1812 indication " ready ", it obtains data from bus 1812, and to the obtained data of bus 342 outputs.
Figure 27 is the block diagram of the concrete configuration of operation board 1804 among expression Figure 25.The configuration of operation board 1804 is subclass of the configuration of transfer blade shown in Figure 26 1802.With transfer blade 1802 different being, do not install serial input circuit 302,306,310, serial output circuit 304,308, transfering controling circuit 312, synchronization control circuit 318, and output control circuit 324.Other assemblies are identical with transfer blade 1802.
The configuration of the operation board 1806 shown in Figure 25 is also identical with operation board 1804.
Figure 28 is the diagram of the data flow in the processing of expression operation board 1804 shown in Figure 25 and 1806.Operation board 1804 and 1806 entire process are divided into five parts, promptly handle 1 to handling 5.Operation board 1804 is carried out and is handled 1,3 and 5, and operation board 1806 is carried out processing 2 and 4.These handle 1 to 5 corresponding to the phase-detection shown in Figure 12, power detection, voltage control, processing such as PWM control.
Handle 1 and only depend on input data and internal data, and do not rely on the result of processing 2 to 5.
Handle 2 and only depend on input data and internal data, and do not rely on the result of processing 1,3,4,5.
Handle 3 and only depend on the input data, handle 1,3 result and internal data, and do not rely on the result of processing 4,5.
Handle 4 and only depend on the input data, handle 1,3 result and internal data, and do not rely on the result of processing 3,5.
Handle 5 and depend on the input data, handle 1,2,3,4, result and internal data.
Figure 29 is the diagram of arranging of the data of storage among the RAM 316 of expression operation board 1804 shown in Figure 25 and 1806.
The data of RAM 316 are classified as the input data, onrecurrent data and recursive data, and be arranged in four zones that separate: input is a region R 1, onrecurrent data area R2, recursive data region R 31 is to R35 and free space R4.Like this, by arranging recursive data, then can understand the transfer that to carry out recursive data between operation board 1804 and 1806 transfer blades 1802 effectively in certain zone.
Figure 30 be expression when the computing module 131 of the control device of power converter shown in Figure 1 ' in the diagram of one example of performed processing method when detecting fault, wherein the configuration shown in Figure 25 be applicable to computing module 131 '.Processing mode shown in Figure 30 almost is similar to the processing mode shown in Figure 22, and difference only is, is increased to for five processed in units cycles for the appearance of recursive data consistency desired result from four processed in units cycles.
Figure 31 is the diagram of the processing shown in Figure 30 of expression in detail.
Operation board 1804 and 1806 starts its processing receive the input data from transfer blade 1802 after, and the time started in the processing cycle of operation board is after the time started in the processing cycle of transfer blade 1802.
After having finished processing 1, operation board 1804 is to operation board 1806 transfer processing results.After having finished processing 2 and 4, operation board 1806 is to operation board 1804 transfer processing results.
Transfer blade 1802 exchange and filtering recursive data.This processing is startup after the processing that stop to produce the target recursive data, regularly submits to the type of target recursive data in the startup of signal processing this processing in the cycle.
Handle sequence and be decomposed and be assigned in as shown in Figure 31 three independent plates, can understand, both made for sequentially carrying out other and handled expection and need the long time cycle, but whole processing can be carried out in certain processing cycle fully.
Figure 32 is that expression is used for the block diagram according to the configuration of control device second embodiment of power converter of the present invention.As for the difference of this embodiment and first embodiment shown in Figure 1, AD module and computing module are divided in triplicate individually among first embodiment, otherwise AD module and computing module are divided into individually in duplicate in the present embodiment.The power converter control device has two AD modules 2521 and 2522 and two computing modules 2531 and 2532.In order to set up dual structure, computing module 2531 is connected to by holding wire 2508 and selects circuit 2504, is used for to the information of selecting circuit 2504 to provide judgement whether to break down at computing module itself.Other characteristics in the configuration are almost identical with characteristics in the power converter control device of first embodiment, and institute's difference is, because the less number that is connected lead of AD module and computing module number is less.
In the power converter control device in the present embodiment, the fault message of selecting circuit 2504 to receive from the computing module 2531 of holding wire 2508, if and in computing module 2531, do not have fault, the output that provides at holding wire 2581 from computing module 2531 then is provided and is outputed to holding wire 2506.Otherwise,, the output that provides at holding wire 2582 from computing module 2532 then is provided and is outputed to holding wire 2506 if in computing module 2531, fault is arranged.
Figure 33 is the block diagram of the concrete configuration of expression computing module 2531 shown in Figure 32.
Among Figure 33, holding wire 2551 and 2562 is connected to and is used to change serial input circuit 2606 that serial data is a parallel data and 2610 input port, serial input circuit 2606 and 2610 output port are connected to the input port of transfering controling circuit 2612 by holding wire 2636 and 2649, this transfering controling circuit temporarily stores the input signal that carries on holding wire 2636 and 2640 into internal storage, and response data is read the data that request output is stored.Holding wire 2561 is connected to and is used to change the output port that parallel data is the serial output circuit 2608 of serial data, and the input port of serial output circuit 2608 is connected to the output port of transfering controling circuit 2612 by holding wire 2638.The input/output end port of transfering controling circuit 2612 also is connected to bus 2642.
What be connected to bus 2642 except transfering controling circuit 2612 is central processing unit (CPU) 2620, read-only memory (ROM) 2614, random access storage device (RAM) 2616, be used for the data on the monitor bus 2642 and detect such as the fault monitoring circuit 2622 of the disconnection of bus 2642 and noise and be used to produce and export each input/output end port for the output control circuit 2624 of the control impuls of power converter 2502 usefulness.Output port is connected to the input port of CPU 262 and is also connected to holding wire 2508 by holding wire 2646.The input port of output control circuit 2624 is connected to the output port of the synchronization control circuit 2618 that is used to produce the operation start signal that uses for AD module 2521 by holding wire 2644, and the output port of output control circuit 2624 is connected to holding wire 2581.Output port is also connected to holding wire 2591 and 2571, and its input port is connected to holding wire 2572.
The operation of computing module 2531 below is discussed.
When serial input circuit 2606 and 2610 receives respectively serial data from holding wire 2551 and 2562, then their serial datas of receiving of conversion are parallel data, and by holding wire 2636 and 2640 respectively to transfering controling circuit 2612 these parallel datas of output.
When serial output circuit 2608 received parallel data from transfering controling circuit 2612 by holding wire 2638, then the parallel data received of its conversion was a serial data and to holding wire 2561 these serial datas of output.
When transfering controling circuit 2612 received parallel data from serial input circuit 2606 and 2610 by holding wire 2636 and 2640, then it temporarily stored this parallel data in the internal storage into.When transfering controling circuit 2612 was read request by bus 2642 receptions from the data of CPU 2620, then it exported the data that are stored in the memory by bus 2642 to CPU 2620.In addition, when transfering controling circuit receives data from CPU 2620 by bus 2642, its data of receiving to inner memory stores then.Temporarily to inner memory stores after the data that serial input circuit 2606 or CPU 2620 receive, transfering controling circuit is by the data of holding wire 2638 to the 2608 output storages of serial output circuit.
CPU 2620 receives the data that are derived from two AD modules 2521 and 2522 from transfering controling circuit 2612 by bus 2642 in the fixing cycle, by selecting data from effective AD module to produce data, and provide the data that produced to output control circuit 2624 by bus 2642 for power controlling transducer 2502 usefulness.If desired to another computing module 2532 transferring datas, then CPU 2620 shifts data necessary by bus 2642 to transfering controling circuit 2612.
The data that fault monitoring circuit 2611 is observed on the bus 2642, and when detecting any fault, export initializing signals to CPU 2620 by holding wire 2646.As for fault detection method, then the signal by the parity check bit that error checking on being used for bus 2642 is provided detects invalid data.Can also allow CPU 2620 to carry out the read/write verification that checking routines are used for check sum and the RAM2616 of ROM 2614, and if detect any mistake, then by bus 2642 to fault monitoring circuit 2622 reporting errors states.The information that fault monitoring circuit 222 is exported enabling signals and whether had fault to holding wire 2508.
Synchronization control circuit 2618 by holding wire 2571 and 2572 with computing module 2532 exchange synchronizing signals, produce for the operation start signal of AD conversion and to holding wire 2591 and export these signals.Simultaneously, synchronization control circuit becomes logic level 1 to time counting from the operation start signal, and sends count value by holding wire 2644 to output control circuit 2624.
Based on temporal information of receiving from synchronization control circuit 2618 by holding wire 2644 and the control data of receiving from CPU 2620 by bus 2642, the control impuls that output control circuit 2624 produces for power converter 2502 usefulness, and pass through holding wire 2581 to selecting circuit 2504 these control impuls of output.
The computing module 2532 of power converter control device shown in Figure 32 also is to dispose and operate by computing module 2531 similar modes.
Figure 34 is the block diagram of expression synchronization control circuit 2618 concrete configurations shown in Figure 33.
Among Figure 34, holding wire 2572 is connected to the input of buffer 2712, and the output of buffer 2712 is connected to one of input of comparator 2706 by holding wire 2728.Another input of comparator 2706 is connected to the output of the delay circuit (DL circuit) 2708 of the received signal that delay is provided by holding wire 2724.The count value output of counter 2704 is connected to holding wire 2644, and provides the carry end of counting termination signal to be connected to the input of DL circuit 2708 and buffer 2702 and 2710 by holding wire 2722.Buffer 2702 and each output of 2710 are connected respectively to holding wire 2591 and 2571.
The below operation of explanation synchronization control circuit 2618.
Counter 2704 every fixed time periods make its count value increase by 1, and to holding wire 2644 these count values of output.When count value and the corrected value of receiving from comparator 2706 by holding wire 2724 and when reaching predetermined numerical value, operation start signal and reset count value that counter 2704 outputs are used for the AD conversion are 0.
When DL circuit 2708 by holding wire 2722 when counter 2704 is received the operation start signal, it by fixed time period postpone the operation start signal and to holding wire 2726 outputs be delayed signal.DL circuit 2798 is used for the operation start signal that uses for computing module 2531 with computing module 2532 swap operation enabling signal required time cycle delays.
Buffer 2702 and 2710 receives the operation start signal by holding wire 2722 from counter 2704, and passes through holding wire 2591 and 2571 output function enabling signals respectively to AD module 2521 and computing module 2532.
Buffer 2712 receives the operation start signal by holding wire 2572 from computing module 2532, and sends this signal of receiving to comparator 2706 by holding wire 2728.
Comparator 2706 receives the enabling signals of changing for AD by holding wire 2726 and 2728 at computing module 2531 and 2532, and based on the correction numerical value of the calculating of the time difference between these operation start signals, and export this to counter 2704 by holding wire 2724 and proofread and correct numerical value for counter 2704 usefulness.
Figure 35 is the sequential chart of the operation of synchronization control circuit 2618 shown in expression Figure 33.
Each computing module 2531 and 2532 counter 2704 are pressed fixed time period increases count value one, and when count value and proofread and correct numerical value export this operation start signal when reaching predetermined value.In this example, the counter of supposing computing module 2531 is than the counter of computing module 2532 increment in the shorter cycle.
Change startup regularly at an AD, owing to have identical timing with the operation start signal of exporting from computing module 2532 from the operation start signal of computing module 2531 outputs, so correction numerical value is 0.Change startup regularly at the 2nd AD, owing to early output of operation start signal of exporting from computing module 2532 from the operation start signal ratio of computing module 2531 outputs.Thereby, be negative owing to supply the correction numerical value of computing module 2531 usefulness, so operation start regularly is delayed to the startup timing of expection; Because the correction numerical value for computing module 2532 usefulness is positive, so the startup of operation start timing ratio expection regularly early.So, have much at one timing from the operation start signal of computing module 2531 output with from the operation start signal of computing module 2532 outputs.
Figure 36 be expression shown in Figure 33 when detecting fault in the computing module 2531 at the control device of power converter the diagram of the embodiment of performed processing method.
Present embodiment is a situation of saving computing module 133 among the embodiment shown in Figure 20.Because power transfer is by using from the signal controlling of computing module 2532 outputs when computing module 2531 output invalid datas, so be appreciated that, as as shown in 20 the embodiment, needn't suspend power converter just can be so that computing module 2531 reverts to normal mode of operation similarly.
In the present embodiment, because the output of computing module 2531 and 2532 selects to depend on the fault detection capability of computing module 2531, so its weakness is, the output signal of mistake may output to power converter when non-detectable fault takes place, but its advantage is, the quantity of system component can be reduced to almost 2/3 of power converter control device shown in Figure 1.
To the example of power converter control device some embodiment of the present invention has been described though consulted and used the present invention, obviously the present invention is applicable to the control device of other types.
As above described in detail, in the multiplexed control device that the present invention is suitable for, can understand, if any fault takes place, then by control data is transferred under the such control of the system that detects fault from the system of normal running, fault detection system can revert to normal mode of operation and device is suspended.

Claims (4)

1. fault recovery method that is used for copy controller, this duplicates is for carrying out identical processing is used for controlled equipment with output control signal in the predetermined cycle in a plurality of systems, wherein when in one of a plurality of systems of described copy controller, detecting fault, it is normal condition to recover failure system that control data is transferred to failure system from the system of normal running, said method comprising the steps of:
Based on described correlation described control data is divided into a plurality of; And
By the priority of correlation order, by a plurality of operation cycles from the system of described normal running to described failure system, shift described a plurality of.
2. the fault recovery method described in claim 1 is wherein carried out after period demand of normal process in described failure system, and control data is transferred to described failure system from the system of described normal running.
3. the fault recovery method described in claim 1, no matter wherein whether fault detect exists, exchanged between described system in one of a plurality of of each operation cycles, so when existing between the numerical value of each system when inconsistent, the numerical value with high reliability is used for the next operation cycle by identification.
4. copy controller, it comprises:
A plurality of controllers, it duplicates is for carry out same treatment in the predetermined cycle in a plurality of systems, so that to controlled equipment output control signal;
Select circuit, this circuit is used for to described equipment output at the numerical value of selecting to have high reliability from the output of described a plurality of controllers;
Each described controller has storage and is used for when the transport zone that out of order controller is reverted to the necessary data of normal condition when one of a plurality of controllers break down; And
Described transport zone has a plurality of zones, be used to rely on the correlation storage between described to be divided into a plurality of data, so in the one-period in a plurality of operation cycles, the data that are stored in described a plurality of are transferred to described failure system by the priority of correlation from the system of normal running.
CN98105673A 1997-03-19 1998-03-18 Duplication controller and fault recovery method Expired - Fee Related CN1089203C (en)

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US6038683A (en) 2000-03-14
JPH10271834A (en) 1998-10-09
CN1089203C (en) 2002-08-14
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EP0866389A3 (en) 1999-10-20
KR100548831B1 (en) 2006-06-21

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