CN1205788A

CN1205788A - Method for setting operating mode of an integrated circuit and integrated circuit

Info

Publication number: CN1205788A
Application number: CN 96199214
Authority: CN
Inventors: D·林德维斯特
Original assignee: Telefonaktiebolaget LM Ericsson AB
Current assignee: Telefonaktiebolaget LM Ericsson AB
Priority date: 1995-12-21
Filing date: 1996-12-13
Publication date: 1999-01-20

Abstract

An integrated circuit (IC) which can function in a number of different operating modes is set to a setting mode by a control signal (SR1) on the control signal input (R). The circuit (IC) includes a signal sequence generator (PG) which in the setting mode generates setting signal sequences (SA0-SA3) on four of the address connections (A0-A3) of the circuit (IC). An operating mode is selected by coupling one of the address connections (A3) with a setting signal input (M) on a signal sequence detector (PD) in the circuit (IC). The signal sequence detector (PD) interprets the setting signal sequence (SA3) from the signal sequence generator (PG) and sets control outputs (PO1, PO2, SO1, SO2) on the signal sequence detector (PD) to different combinations of 'low' and 'high' signal levels respectively in dependence on the sequence (SM1) received in the detector (PD), whereafter the circuit (IC) switches to an operating mode in which the address conductors (A0-A3) forward signals in accordance with the operating mode.

Description

Be used to be provided with the method and the integrated circuit of the operator scheme of integrated circuit

Invention field

The present invention relates to be used to be provided with the method and apparatus of the operator scheme of an integrated circuit, this integrated circuit is carried out different functions according to selected operator scheme.

Background technology is described

The integrated circuit that can carry out difference in functionality becomes more and more common, and the equipment that contains integrated circuit therein needs compact and effective usually with respect to current drain.Can run into such demand when joining the parts of this equipment in the integrated circuit.The function that joins in the integrated circuit is many more, and circuit is just big more.In addition, adopt one and identical circuit in different application, wherein this identical circuit is carried out difference in functionality, and this is normally useful.For sort circuit can be worked, just need and to be set to different operator schemes by circuit.

For sort circuit being arranged to each operator scheme, early stage solution comprises some circuit installation signalization inputs of special employing, the setting of these input control circuits.For example use a switch, by with a low or high signal level, for example signal ground or operating voltage are added to respectively in these inputs, and a signal level just is added in these inputs.Added signal level is at a predetermined instant.Normally when starting, read in circuit and be understood that a kind of operator scheme.

In the development of said method, the result of generation is, can use these signal links as signalization input back in normal running at signal link, and these signal links are coupled to aforesaid signal level by ohmic medium.This just makes these signal links can be used in the normal running after setting up procedure finishes, and needn't emit risk of short-circuits.

The problem of this solution is only to be used to be provided with special many signal links and many lead-in wires that are connected of function.It is very limited to can be used in the space that holds electron device in present equipment, and this just means that the quantity of the connection lead-in wire that circuit needs is big more, and the needs that then satisfy compact devices just become difficult more.

Signalization input for ohmic load, another problem that exists in the reality is, under the situation that the pattern setting up procedure finishes, when this circuit receives on described signal or sends signal, electric current will flow through described resistance, consequently increase power consumption, this will cause, for example, can not satisfy the needs of facility compact, especially when the situation of equipment during by a space consuming powered battery.

US Patent specification No.4,902,917 provide a kind of method of avoiding the problems referred to above at least in part, and in this patent, an integrated circuit is provided with its operator scheme by a signal that sends at least two different signalizations to a signalization input end.Described different signalization obtains from the clock signal output terminal on this integrated circuit.Deliver to the clock signal of this signalization input end, for example selected by the output selection of adopting a multi-way switch.

A shortcoming of this solution is that after operator scheme was provided with, the described signal output of tranmitting data register signal can not be used with any signal except that clock signal.

Summary of the invention

The problem relevant with known solution be, utilizes signal output part to send burst to signalization input end and the setting operation pattern, and burst does not wherein change after this operator scheme is set.Therefore, people will rely on the normal function that described signal is exported when circuit is arranged to an operator scheme.

The method according to this invention also is coupled this line and signalization input by one of them line of selecting the circuit signal line.Circuit keeps the pattern of setting then, is provided with in the pattern at this that normal running of circuit is interrupted and send the prearranged signal sequence on selected signal link.According to the described burst that receives on this signalization input end, this burst is understood that a request that circuit is set to a kind of operator scheme.This signal link is got back to normal running then, perhaps as output, perhaps as input.

The device that constitutes according to the present invention comprises can be with an integrated circuit of at least two kinds of mutual different operator scheme work.This circuit comprises at least one signalization input end and at least two other signal links.This signal link can be optional kind: input, output or input-output combination.One of these signals utilize the line by its transmission signalization to be connected to a signalization input end.

Method of the present invention is included in this signalization input end and is connected to one of described signal link select operating mode later on, and described signal link is represented selected operator scheme.This circuit switches to one pattern is set then, and each in wherein a plurality of signal links sends a predetermined signalization sequence, and this sequence is unique for each selectable operator scheme.

When the reception of the signalization sequence on the signalization input end finishes, circuit is provided with mode switch to selected operator scheme from this, wherein, described signal link switches to the normal running with output signal and/or input signal according to selected operator scheme.

Therefore, one object of the present invention is achieved, that is, can utilize the dedicated connection of minimum number and circuit is set to an operator scheme under the situation that does not have unnecessary current drain.

By an advantage provided by the invention is that many signal links of circuit are provided with the period of only using a weak point in the pattern at circuit.When the setting up procedure of circuit finished, these lines turned back to its normal manipulation mode as signal output or signal input, therefore the quantity of the signal link in the circuit can be minimized.

Below with reference to accompanying drawings, describe the present invention in detail in conjunction with most preferred embodiment.

The accompanying drawing summary

Fig. 1 a is the block scheme according to an integrated circuit that can be adjusted to different operation modes of the first embodiment of the present invention.

Fig. 1 b is the table of the different circuit connections of explanation.

Fig. 1 c has illustrated circuit connection and from the burst of circuit connection.

Fig. 1 d is the process flow diagram of an explanation the inventive method.

Fig. 2 a is the block scheme of an explanation integrated circuit that can be adjusted to different operation modes according to a second embodiment of the present invention.

Fig. 2 b is the table of the different circuit connections of explanation.

Fig. 2 c has illustrated that circuit engages and from the burst of circuit connection.

Fig. 2 d is the process flow diagram of an explanation the inventive method.

The detailed description of most preferred embodiment

Fig. 1 a has illustrated an integrated circuit (IC), and this integrated circuit constitutes such as a part that is included in control circuit in the not shown big system etc.This circuit is installed on the circuit board with other integrated circuit usually.To describe the different lines and the element of this integrated circuit (IC) below in detail.

This integrated circuit (IC) comprises a computer unit CPU.One reading writing memory RAM, a read only memory ROM, a burst detecting device PD, a burst generator PG, a scaling unit PS and a plurality of lines between these elements.

This computing unit CPU calculates and controls and delivers to and transmit from the information of other circuit component or unit.This read-only memory ROM contains the information that can be read by this computing unit CPU but can not rewrite.The information that this reading writing memory RAM contain can be read and rewrite by this computing unit CPU.Memory cell RAM, ROM have control input end SI1 and SI2 respectively, and SI1 is used for detecting the PD reception from burst with SI2 and has the control signal of two different signal levels-" low " and " height " level.One " height " signal level on the control of read-only memory ROM input SI1 allows by data bus DB and from reading of data wherein.Correspondingly, one " height " signal level on the control input SI2 of reading writing memory RAM allows by data bus DB the RAM memory to be read and write.

By data bus DB transmission, this bus DB is made of eight single data lead D0-D7 information between memory unit RAM, ROM and computing unit CPU.Address bus AB with ten six roots of sensation address wire A0-A15 transmits binary address to memory cell RAM, ROM, so that information can read or write by data bus DB from computing unit CPU from the stored position of memory cell ROM, RAM.

Scaling unit PS is connected to computing unit CPU.Burst generator PG and burst detecting device PD, and this scaling unit PS is as transmitting or send a clock signal SC1 to these unit.Clock signal SC1 need be used for the work of synchronous all circuit and can have different frequencies, and this frequency is by the information decision that receives on the first control input end PI1 of scaling unit and its second control input end PI2 from signal sequential detector PD.In a kind of mode similar to storage circuit ROM, RAM, it is " height " or " low " that control input end PI1, PI2 detect two different signal levels respectively.If control input end PI1 receives " height " signal level and control input end PI2 receives one " low " signal level, then scaling unit PS sends the clock signal SC1 with first frequency f1.On the other hand, be " height " if having " low " signal level and the signal level on the PI2 of control input end at the signal on the PI1 of control input end, then scaling unit PS sends the clock signal SC1 with second frequency f2.Clock signal SC1 is produced in scaling unit PS by clock signal SC0, and this clock signal SC0 is sent to this IC circuit on clock signal input C.

Burst generator PG is connected to four address wires or the line A0-A3 of address bus AB, so-called first four-address lead A0-A3.These address wires have the function that sends prearranged signals sequence SA0-SA3 on address wire A0-A3 separately.This will IC circuit be in by control signal SR1 start pattern is set the time take place, this pattern will be described in detail in the back.The prearranged signals sequence is shown in the limited period DT of Fig. 1 C one and sends, and by being stored in the very first time monitor unit TU1 Be Controlled.Burst SA0-SA3 is stored among the first memory cell SU1 of burst generator PG.

Burst detecting device PD is used for receiving a control signal sequence SM1 and explaining this burst from burst generator PG by line X during IC circuit is in circuit pattern is set.Line X will explain with reference to method of the present invention in instructions in further detail.By four control signal output ends PO1, PO2, SO1, SO2, burst detecting device PD sends control signals to other unit in the circuit according to this explanation.The first control signal output ends PO1 and the second control signal output ends PO2 are connected respectively to the first control input end PI1 and the second control input end PI2 of scaling unit.The third and fourth control signal output ends SO1 and SO2 are connected respectively to the control input end SI1 of read-only memory ROM and the control input end SI2 of reading writing memory RAM.

Clock signal input terminal C is connected to scaling unit PS, and scaling unit PS forms internal clock signal SC1 according to the external timing signal SC0 of input.Internal clock signal SC1 is sent to other unit of IC circuit from scaling unit PS.Signal input end R is connected to computing unit CPU, burst generator PG and burst detecting device PD.Make IC circuit enter the aforesaid control signal SR1 that pattern is set and send to these unit by signal input end R.Signalization input end M is connected to burst detecting device PD and burst SM1 sends to input end M from burst generator PG.The address wire A0-A15 of address bus AB also comprises the installation circuit connection lines.Binary address on address wire A0-A15 partly sends to these integrated circuit units and partly sends to external unit.One specific function is carried out by aforesaid first four-address lead A0-A3: be connected to computing unit CPU and memory cell RAM, the ROM except the same with remaining address wire A4-A15, as previously mentioned, this first four-address lead is also connected to burst generator PG.In pattern was set, burst generator PG sent signalization sequence SA0-SA3 to burst detecting device PD on these first four-address leads A0-A3.The burst that receives in burst detecting device PD will depend on that address wire A0-A3 that is connected to circuit signalization input M.

Data bus DB and data conductor D0-D7 thereof are also included within the aerial lug on the IC circuit.Information transmits in (not shown) between the circuit unit and between the circuit external unit by these lines D0-D7.

Fig. 1 b has illustrated the method that starts different modes of circuit operation.For example, be binary-level 1011 when burst generator PD makes its control output end PO1, PO2, SO1, SO2, when perhaps being expressed as " height ", " low ", " height ", " height ", start first operator scheme with aforesaid signal level.IC circuit can be operated in one of them of four kinds of different modes, and in first operator scheme, clock signal SC1 has first frequency f1, and computing unit CPU can communicate by letter with memory cell ROM, RAM with address bus AB by data bus DB.In second operator scheme, clock signal SC1 has identical first frequency f1, but reading writing memory RAM is free of attachment to data bus DB and address bus AB, this means that the memory cell of communicating by letter with computing unit CPU has only read-only memory ROM.The 3rd operator scheme is defined as, and clock signal SC1 has second frequency f2, and computing unit CPU the two is communicated by letter with memory cell ROM, RAM can resembling in first operator scheme.In the 4th operator scheme, clock signal SC1 has second frequency f2, and as in second operator scheme, reading writing memory RAM is free of attachment to data bus DB and address bus AB.

Above-mentioned each operator scheme uniquely corresponding to the signalization sequence SA0-SA3 among the first memory cell SU1 that is stored in burst generator PG, when control signal SR1 is received on signal input end R, IC circuit enters the pattern of setting and burst generator PG sends corresponding burst SA0-SA3 on address wire A0-A3.These signalizations SA0-SA3 is received on burst detecting device PD, according to one among the sequence SA0-SA3 that has received, determine that among control output end SO1, SO2, PO1, the PO2 which should be set to signal level 0, which should be set to signal level 1.When control input PI1, the PI2 of input SI1, SI2 of the control on memory cell ROM, the RAM and scaling unit PS detect these signal levels, think that then IC circuit is set to a kind of operator scheme.

Now with reference to accompanying drawing 1a-c, in conjunction with the declarative description of the 4th operator scheme method of the present invention.

Clock signal SC1 is shown among Fig. 1 c with control signal SR1.One clock cycle was an elapsed time between two time marks, for example from T2 to T3.Be shown in that the signal level S of ordinate represents

level

0 and 1 among the figure, before moment T1 and constantly the dotted portion presentation address bus line A0-A3 transmission arbitrary signal of these signals after the T4.Therefore, IC circuit is being in normal manipulation mode before the moment T1 and after moment T4.Therefore, the aforementioned time interval that is designated as DT in Fig. 1 c and 1d is the time interval that IC circuit is in the pattern of setting therein.

Method of the present invention comprises following method step:

-user selects IC circuit to enter the 4th operator scheme in aforementioned four kinds of operator schemes.

-between signalization input M and address bus line A3, set up line X.This line X can be the form at the overlap joint line between described line A3, M on the circuit board that IC circuit is mounted thereon.

-make IC circuit enter the pattern of setting by the SR1 that transmits control signal via control signal input R end to IC circuit.According to Fig. 1 c, a moment from 0 to the 1 switch level S of control signal SR1 between T0 and T1.This variation of signal level is detected in IC circuit, and the normal manipulation mode of IC circuit is interrupted when beginning clock period T1-T2, and IC circuit enters the pattern of setting.

-burst SA0-SA3 sends from burst generator PG on address bus line A0-A3.These bursts promptly transmit among clock period T1-T2, the T2-T3 shown in Fig. 1 c, the T3-T4 at time interval DT.Owing to set up line X between address wire A3 and signalization input end M, therefore, the signalization sequence SM1 that arrives signalization input end M will be the burst as burst SA3 that sends from address wire A3.Be provided with pattern the DT in period of process controlled by the very first time monitor unit TU1 of burst generator PG.When the closing time that arrival one is stored among the very first time monitor unit TU1, this very first time monitor unit TU1 interrupts the transmission from the burst SA0-SA3 of burst generator PG, represents with the clock periodicity of clock signal SC1 this closing time.

-burst detecting device PD received signal sequence SM1, SM1 is sent to signalization input end M by selected address wire A3 and line X from burst generator PG.The burst SM1 that is received is stored among the second memory cell SU2.After pattern was set, the burst SM1 in the second memory cell SU2 can be used to determine according to following explanation which operator scheme will be IC circuit will enter.

-according to the table of Fig. 1 b, signalization sequence SM1 explained in burst detecting device PD, and its control output end PO1, PO2, SO1, SO2 are set to binary-level 0101 (" end ", " height ", " low ", " height ").Therefore, the control of read-only memory ROM input SI1 will be set to level " height " and cause described memory to be connected to address bus AB and data bus DB.The control input end SI2 of reading writing memory RAM will be set to level " low " and cause described ram memory to be free of attachment to bus AB, DB.Scaling unit PS is difference received signal level " low " and " height " on signal input PI1 and PI2.This will cause scaling unit PS to send the clock signal SC1 with second frequency f2.Then interrupt the reception of signalization SM1 among burst detecting device PDs when having arrived the closing time in being stored in the second time monitoring unit TU2, represents with the clock periodicity of clock signal SC1 this closing time.Have this closing time and the identical duration of closing time that is stored in very first time monitor unit TU1.

The end that-operator scheme is provided with.When in IC circuit, having received signalization SM1 behind the clock period T3-T4 by signalization input M, the then setting of end operation pattern.This will realize according to the order from time monitoring unit TU1 and TU2.IC circuit is returned to the transmission binary address from mode switch to the four operator schemes and address wire A0-A3 are set immediately, and circuit units all in the 4th operator scheme are according to this specific operation mode work.

Fig. 1 d has illustrated fundamental method step of the present invention.Process flow diagram is used for reading with following description:

-at first step 101, the user selects IC circuit to enter the 4th operator scheme;

-in second step 102, address wire A3 is connected to signalization input M.

-at third step 103, import R by the SR1 that transmits control signal to the control signal of IC circuit and make IC circuit enter the pattern of setting.

-in the 4th step 104, signalization sequence SA3 sends to burst detecting device PD via signalization input M from burst generator PG.

-in the 5th step 105, explain the signalization sequence SM1 that in burst detecting device PD, receives.

-in the 6th step 106, the control output end SO1 of burst detecting device PD, SO2, PO1, PO2 are set to " low ", " height ", " low ", " height " respectively, these signals also are sent to memory cell RAM immediately, the control input end SI1 of ROM, control input end PI1, the PI2 of SI2 and scaling unit PS.

-in the 7th step 107, selected operator scheme finishes this process owing to IC circuit switches to, and in selected operator scheme, address wire A0-A3 uses according to this operator scheme.

Noted earlier is that the address wire A3 that selects utilizes line X to be directly connected to signalization input end M.But possible is, this connects and can enough other methods realize, for example, utilizes multi-way switch, and it can make different address wire A0-A3 be connected with signalization input end M according to simple a switching.

Fig. 2 a, 2b, 2c, 2d have illustrated another embodiment according to integrated circuit (IC) 2 of the present invention.Be similar to the IC circuit in the previous examples, IC circuit 2 comprises a computing unit CPU, reading writing memory RAM, a read-only memory ROM, a burst detecting device PD2, a burst generator PG, a scaling unit PS and a plurality of lines between these elements.Therefore, IC circuit 2 comprises all unit and the line that IC circuit comprised of Fig. 1 c.But IC circuit 2 also has two signalization input end M1, M2 in addition.Be similar to top description, signal input part M1, M2 are connected to four control output end PO1, PO2 with oneself, the burst detecting device PD2 of SO1, SO2.Burst detecting device PD2 is used for via line X1, and X2 receives the burst SM1 from burst generator PG, SM2, and described sequence will be stored among the memory cell SU2 and be explained.The burst SM1 control that receives on signal input part M1 is added to the control output end PO1 that is connected with scaling unit PS, the signal level on the PO2.The burst SM2 that receives on signal input part M2 control is added to respectively the control output end SO1 that is connected with reading writing memory RAM with read-only memory ROM, the signal level on the SO2.

The same with the example of front, IC circuit 2 can be set to different operator schemes.Be similar to previous embodiment, these operator schemes are combinations of the different frequency of the memory cell ROM, the RAM that connect and clock signal SC1.The table of Fig. 2 b has illustrated the example with eight different operation modes.It is identical with previous embodiment to be numbered 1 to 4 operator scheme, is new and be numbered 5 to 8 operator scheme to this example.From the table of Fig. 2 b, as seen, be exactly control output end PO1, the PO2 that its value is different from previous embodiment, thereby make scaling unit PS produce clock signal SC1 with two other different frequency f3, f4.

Be similar to previous embodiment, each operator scheme is corresponding to the unique signalization sequence SA0-SA3 among the first memory cell SU1 that is stored in burst generator PG.Second embodiment also shows operator scheme how to represent other under the situation that does not increase the signal link number, by set up a line X2 between signalization input M2 and signal ground GND, a burst that is made of constant signal level " low " can be sent to burst detecting device PD2.In corresponding method, a burst that only is made of signal level " height " can transmit from a line of the power Vcc of IC circuit 2.These are shown among Fig. 2 c with other burst SA0-SA3 by the burst that the constant signal level constitutes.

Eight different operator schemes have only been enumerated in the present embodiment.Utilize two signalization input end M1, M2, four signal link A0-A3 and two constant level GND, Vcc can represent some patterns that are provided with, according to the line x1 that is used between the signal link A0-A3, x2, signal level GND, Vcc and signalization input end M1, the combination of M2 can be represented 32 kinds of operator schemes at most.

When control signal SR1 was received on signal input end R, IC circuit 2 switched to the pattern of setting, and burst generator PG sends burst SA0-SA3 on corresponding address wire A0-A3.Signalization SA0-SA3, constant signal level " low " and " height " from signal ground GND and power Vcc is received in burst detecting device PD2 respectively.According to the burst that on each signalization input end M1, M2, has received, among burst detecting device PD2 specified control output terminal SO1, SO2, PO1, the PO2 which should be set to signal level " low ", and which should be set to signal level " height ".

Second inventive method comprises following method step:

-user selects to enter the 5th operator scheme with commutation circuit IC2.

-between signalization input end M1 and address bus line A0, set up line X1.This line can have the form of the overlap joint line on this circuit board, and these IC circuit 2 (not shown) are being installed between described line A0, M1 on this circuit board.

-between signalization input end M2 and operating voltage line Vcc, set up line X2.This line can be in the form of the overlap joint line on this circuit board these IC circuit 2 (not shown) to be installed between described line Vcc, M2 on this circuit board.

-make IC circuit 2 be set to the pattern of setting by the SR1 that transmits control signal via signal input end R to IC circuit 2.According to Fig. 2 c, the moment from " low " to " height " level switch level S of control signal SR1 between T0 and T1.This variation of signal level is detected in IC circuit 2, and the normal mode of IC circuit 2 is interrupted when the clock period, T1-T2 began, and described circuit switches to the pattern of setting.

-burst SA0-SA3 sends from burst generator PG on address bus line A0-A3.These bursts promptly transmit among clock period T1-T2, the T2-T3 shown in Fig. 2 c, the T3-T4 at time interval DT.Owing to set up line X1 between address wire A0 and signalization input end M1, the signalization sequence SM1 that therefore arrives signalization input end M1 will be the burst as burst SA0 that sends from address wire A0.The time cycle DT that pattern is set is controlled by the very first time monitor unit TU1 of burst generator PG.When arrive one be stored among the very first time monitor unit TU1 closing time the time, this very first time monitor unit TU1 interrupts the transmission from the burst SA0-SA3 of burst generator PG, represents with the clock periodicity of clock signal SC1 this closing time.

-in pattern is set, importing M1 to signalization via selected address wire A0 and line X1, burst detecting device PD2 is received from the burst SM1 that burst generator PG sends.What also receive is the constant signal level of being represented by burst SM2 0 to second signalization input M2.Burst SM1, the SM2 that is received is stored among the second storage unit SU2.After making circuit enter the pattern of setting, burst SM1, the SM2 in the second memory cell SU2 can be used to determine that according to following explanation IC circuit 2 is with the operator scheme that is set to.

-according to the table of Fig. 2 b, explain signalization sequence SM1, SM2, and revise control output end PO1, PO2, SO1, SO2 are corresponding signal levels " low ", " low ", " height ", " height ".This makes the control input SI1 of read-only memory ROM be set to level " height " and cause described read-only memory ROM to be connected to address bus AB and data bus DB.The control input end SI2 of reading writing memory RAM also is set to level " height " and also causes reading writing memory RAM to be connected to bus AB, DB.Scaling unit PS imports PI1 at signal, the last received signal level " low " and " low " respectively of PI2.This will cause scaling unit PS to send the clock signal SC1 with the 3rd frequency f 3.Then interrupt signalization sequence SM1 among burst detecting device PD2s when arriving the closing time in being stored in the second time monitoring unit TU2, and the reception of SM2 is represented with the clock periodicity of clock signal SC1 this closing time.Have this closing time and the identical duration of closing time that is stored in very first time monitor unit TU1.

The end that-operator scheme is provided with.When in IC circuit 2, having received signalization SM1, SM2 behind the clock period T3-T4 by signalization input end M1, M2, the then setting of end operation pattern.This will realize according to the order from time monitoring unit TU1 and TU2.IC circuit 2 is immediately from being provided with mode switch to the five operator schemes, and wherein all unit of IC circuit 2 are according to described operator scheme work, and address wire A0-A3 is returned to the transmission binary address.

Fig. 2 d has illustrated fundamental method step of the present invention.Process flow diagram is used for reading with following description.

-at first step 201, the user selects to make IC circuit be suitable for the 5th operator scheme.

-in second step 202, address wire A0 is connected to the first signalization input end M1, and the second signalization input end M2 is connected to operating voltage line Vcc.

-at third step 203, import R to the control signal of IC circuit 2 by the SR1 that transmits control signal, make IC circuit 2 enter the pattern of setting.

-in the 4th step 204, signalization sequence SA0 sends to burst detecting device PD2 via signalization input end M1 from burst generator PG.The second signalization sequence SM2 is constant signal level 1 and sends to second signalization input M2 from operating voltage line Vcc.

-in the 5th step 205, explain the signalization sequence SM1, the SM2 that in burst detecting device PD2, receive.

-in the 6th step 206, the control output end SO1 of burst detecting device PD2, SO2, PO1, PO2 are set to " low ", " low ", " height ", " height " respectively, and these signal levels also are sent to control input end SI1, the SI2 of memory cell RAM, ROM and control input end PI1, the PI2 of scaling unit PS immediately.

-in the 7th step 207, this method switches to selected operator scheme along with IC circuit 2 and finishes, and wherein, address wire A0-A3 uses according to described operator scheme.

In the description in front, directly by line X1, X2, the address wire A0 of selection are connected to signalization input M1 and operating voltage Vcc are added to the second signalization input end M2.But, it should be understood that these connect enough other methods of energy and realize that for example, utilize one or two multi-way switch, described multi-way switch can easily make each address wire A0-A3 and signalization input end M1, M2 connects.What it is also to be understood that is, one or same address wire A0-A3 can be connected to two signalization input end M1, M2.

In two aforesaid examples, the address wire A0-A3 of address bus AB is used to the signal output of signalization sequence SA0-SA3.Its accurately reason be that address wire A0-A3 is signal output in normal running.But adopting the normal running at circuit is that the line of exporting is not the sin qua non as output.Possible in addition solution is, signal input (not shown) wherein also can be used for interim as the signal output in the pattern being set and transmitting signalization sequence SA0-SA3 with this.But, when using this solution, need to consider to be connected to the external unit of these inputs.Need the notice external circuit to stop to guarantee that to integrated circuit (IC) 2 transmission signals and employing measure external circuit will not be configured to signal SA0-SA3 and damage.

The combination that will also be appreciated that signal input, signal output and two-way I/O also is possible as the signal output that is provided with in the pattern.

Claims

One kind with integrated circuit (IC IC2) is set to one of them method of at least two kinds of predetermined independent manipulation modes, and wherein this circuit (IC) comprises at least two signal links (A0-A3);

-signalization input end (M), it is set to predictive mode of operation by described sequence (SM1) indication according to the prearranged signals sequence (SM1) that receives with circuit (IC), and wherein this circuit (IC) also comprises

-signal input end (R), it is set to one according to the control signal (SR1) that receives with circuit (IC) pattern is set, at this different prearranged signals sequence (SA0-SA3) of every signal link (A0-A3) transmission in pattern is set, and wherein, this method comprises following method step:

One of them of the described operator scheme of-selection;

-one of them of described signal link (A0-A3) is connected to described signalization input end (M), wherein, send a burst (SA3) at described this signal link (A3) that is provided with in the pattern, when when this signalization input end (M) is gone up reception, this burst is indicated selected operator scheme;

-be received in the control signal (SR1) on the described signal input end (R), so that this circuit (IC) is set to the described pattern that is provided with, and described burst (SA3) is received on described signalization input end (M); And

-this circuit (IC) is set to operator scheme by this burst (SA3) indication, wherein every signal link (A0-A3) is according to selected operator scheme work.
One kind with integrated circuit (IC IC2) is set to the method for predetermined one of them of at least two kinds of different operation modes, and wherein this circuit (IC2) comprises at least two signal links (A0-A3); At least two signalization input end (M1, M2), they are according at least one the prearranged signals sequence (SM1 that receives, SM2) circuit (IC2) is set to described predictive mode of operation by described sequence (SM1) indication, wherein this circuit (IC2) also comprises a signal input end (R), it is set to one according to the control signal (SR1) that receives with circuit (IC2) pattern is set, at this different prearranged signals sequence (SA0-SA3) of every signal link (A0-A3) transmission in pattern is set, and wherein, this method comprises following method step:

One of them of the described operator scheme of-selection;

-at least one described signal link (A0-A3) is connected at least one described signalization input end (M1, M2), wherein, transmit a burst (SA0) at the described signal link described in the pattern (A0) that is provided with, this burst is indicated selected operator scheme according to the reception at least one described signalization input end (M1);

-be received in the control signal (SR1) on the described signal input end (R), so that this circuit (IC2) is set to the described pattern that is provided with, and described burst (SA0) is received at least one described signalization input end (M1); And

-this circuit (IC2) is set to operator scheme by this burst (SA0) indication, wherein every signal link (A0-A3) is according to selected operator scheme work.
3. method according to claim 2, wherein the outside source of circuit (IC2) (GND, Vcc) be connected at least one described signalization input end (M1, M2).
4. according to one of them the method for claim 1-3, wherein, when in its operator scheme, (IC IC2) has the signal output part (A0-A3) that is used for described signal link (A0-A3) to described integrated circuit.
5. according to one of them the method for claim 1-3, wherein, when in its operator scheme, (IC IC2) has the signal input part (A0-A3) that is used for described signal link (A0-A3) to described integrated circuit.
6. according to one of them the method for claim 1-3, wherein, when in its operator scheme, described integrated circuit (IC, IC2) have at least one signal output part (A0-A1) and at least one signal input part (A2-A3), described output terminal and input end are used for described signal link (A0-A3).
7. according to one of them the method for claim 1-3, wherein, when in its operator scheme, (IC IC2) has the two-way signaling input/signal output part (A0-A3) that is used for described signal link (A0-A3) to described integrated circuit.
8. according to one of them the method for claim 1-3, wherein, when in its operator scheme, this integrated circuit (IC, IC2) have address wire (A0-A3) on address bus (AB), described address wire (A0-A3) is used for described signal link (A0-A3).
9. according to one of them the method for claim 1-3, wherein, when in its operator scheme, this integrated circuit (IC, IC2) have data conductor (D0-D3) on data bus (DB), described data conductor (D0-D3) is used for described signal link (A0-A3).
10. according to one of them the method for claim 1-3, wherein, when in its operator scheme, this integrated circuit (IC, IC2) have at least one in the address wire (A0) on the address bus (AB) and at least one data conductor (D0) on data bus (DB), described address wire (A0) and described data conductor (D0) are used for described signal link (A0-A3).
11. an integrated circuit comprises

-at least one burst generator (PG), it comprises at least two signal links (A0-A3), wherein this burst generator (PG) sends signalization sequence (SA0-SA3) by this signal link (A0-A3);

-at least one burst detecting device (PD), it comprises signalization input end (M) and at least two control output end (PO1, PO2, SO1, SO2), wherein this burst detecting device (PD) is provided with each control output end (PO1, PO2 according to the signalization sequence (SM1) that receives, SO1 SO2) is one of them of two signal levels;

-a line (X) between signal link one of them (A3) and this signalization input (M); And

(TU1, TU2), wherein, (TU1 TU2) comprises the device that is used for interrupting by described burst generator (PG) transmission of signalization sequence (SA0-SA3) in described time monitoring unit in-at least one time monitoring unit.
12. an integrated circuit (IC2) comprising:

-at least one burst generator (PG), it comprises at least two signal links (A0-A3), wherein this burst generator (PG) sends signalization sequence (SA0-SA3) by this signal link (A0-A3);

-at least one burst detecting device (PD2), it comprises at least two signalization input (M1, M2) and at least two control outputs (PO1, PO2, SO1, SO2), wherein (SM1 SM2) is provided with each control module (PO1, PO2 to this burst detecting device (PD2) according to the signalization sequence that receives, SO1 SO2) is one of them of two signal levels;

-at least two lines (X1, X2), wherein said line (X1) remains on the connection between at least one described signal link (A0) and at least one the described signalization input (M1); And

(TU1, TU2), this time monitoring unit comprises the device that is used for interrupting by described burst generator (PG) transmission of signalization sequence (SA0-SA3) in-at least one time monitoring unit.
13. integrated circuit according to claim 13 (IC2), wherein the circuit outside source (GND, Vcc) be connected at least one described signalization input end (M1, M2).
14. (IC, IC2), wherein said signal link (A0-A3) is signal output according to one of any integrated circuit of claim 11-13
15. (IC, IC2), wherein said signal link (A0-A3) is the signal input according to one of any integrated circuit of claim 11-13.
(IC, IC2), wherein said signal link (A0-A3) comprises at least one signal output and the input of at least one signal 16. according to one of any integrated circuit of claim 11-13.
17. (IC, IC2), wherein said signal link (A0-A3) comprises at least one two-way signaling output/signal input according to one of any integrated circuit of claim 11-13.
(IC, IC2), wherein (IC IC2) comprises an address bus (AB) to this circuit, and therein, described signal link (A0-A3) comprises the described address bus of part (AB) 18. according to one of any integrated circuit of claim 11-13.
(IC, IC2), wherein (IC IC2) comprises a data bus (DB) to this circuit, and therein, the part of described signal link (A0-A3) composition data bus (DB) 19. according to one of any integrated circuit of claim 11-13.
20. one of any integrated circuit (IC according to claim 11-13, IC2), this circuit (IC wherein, IC2) comprise an address bus (AB) and a data bus (DB), and wherein, described signal link (A0-A3) comprises at least one in the address wire (A0) on this address bus (AB) and at least one data conductor (D0) on this data bus (DB).