CN1203483A - Phase-locked loop circuit - Google Patents
Phase-locked loop circuit Download PDFInfo
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- CN1203483A CN1203483A CN98108872A CN98108872A CN1203483A CN 1203483 A CN1203483 A CN 1203483A CN 98108872 A CN98108872 A CN 98108872A CN 98108872 A CN98108872 A CN 98108872A CN 1203483 A CN1203483 A CN 1203483A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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Abstract
The invention provides a phase-locked loop (PLL) circuit, wherein, the outputs of a reference signal source (1) and voltage-controlled oscillator (VCO) circuit (3) are frequency-divided by frequency divider circuits (2,4), respectively. A phase comparator circuit (5) is provided for outputting an error signal indicative of a phase difference between these signals, if any. A window generator circuit (9) is connected for outputting a window signal. A low-pass filter (LPF) circuit (7) is charged up in responding to receipt of both the output signal of the charge pump circuit (6) and the boost voltage so that the control voltage may rapidly increase in potential at a target value without rising up to any excess values. Whereby, undershoot and overshoot may be eliminated or at least greatly suppressed thus enabling achievement of high-speed frequency transition with increased reliability.
Description
The present invention relates to a kind of phase-locked loop circuit (PLL).
Current, in the PLL circuit of the PLL frequency synthesizer in can be used for mobile communication system or similar system, carried out some in order to shorten the trial of locking time in startup and channel switch process.
A kind of known circuit is shown in Figure 12 (a) in the prior art, wherein provide two low pass filters of different time constant (LPF) 123 and 124 as the LPF that is called as " loop filter ", it averages by the production of operation to charge pump circuit 121, so as to producing control voltage, be used to control the frequency of voltage-controlled oscillator (VCO) circuit 122.By during frequency translation, use the LPF 123 of a unique short period constant, and after locking, it is transformed into remaining LPF 124 than large time constant, this circuit is used to shorten the time interval that makes loop stability required.In addition, label 125 is represented reference signal source; Label 126 and 127 is represented frequency divider circuit, is used for frequency division is carried out in the output of this reference signal source 125 and VCO 122 respectively; Label 128 is represented phase comparator circuit.
The circuit of another kind of prior art is shown in Figure 12 (b), and it is designed to by the LPF 129 that utilizes variable time constant, reduces the time constant in the frequency translation process.
Also known another kind of prior art, it provides two to provide the mutually different charge pump circuit of ability of charge carrier to loop filter, though thisly be configured in not explanation herein.This is configured, make when the output frequency of VCO when being also referred to as the target frequency of " locking frequency ", a charge pump circuit with high electric charge deliverability is realized from the filling and the release of the carrier of loop filter circuit turnover, thereby make VCO export quick approach locking frequency or near by frequency, and after this, make another charge pump work, thereby carry out the accurate adjustment of frequency values with less electric charge deliverability.
Figure 12 (c) represents another kind of prior art, comprising divider circuit 130,131, remove outside the frequency divider 126,127, provide these divider circuits to be used to control the comparison frequency value that will compare at comparator 128, also comprise control circuit 132, be used to control the frequency dividing ratio of frequency dividing circuit, wherein when frequency translation begins, the comparison frequency value temporarily is higher than frequency values nominal or standard, thereby shorten locking time, by means of being locked under the standard frequency, realize the channel switch operation simultaneously.Notice that herein label 23 represents LPF.
Yet the shortcoming of changing the scheme of above-mentioned loop filter circuit or charge pump circuit is to be difficult to correctly determine conversion timing.For this reason, the progression that is used to produce the circuit of the signal that is used to change increases, and meanwhile, brings the danger that produces frequency fluctuation owing to the noise in the transfer process.In addition, the circuit requirement that is designed to change between loop filter circuit uses two dissimilar loop filter circuits, and this makes its circuit area not increase with needing.The prior art that utilization is changed between charge pump circuit, electric charge deliverability enhanced charge pump circuit may be own just to noise-sensitive, thereby the bad behavior of the loop filter that exerts an influence in pll system.
The prior art that is designed to temporary transient increase comparison frequency when frequency translation begins need be used extra frequency divider 130,131, is used to increase comparison frequency.Another problem relevant with this prior art be, when the comparison frequency of bringing into use in transfer is converted into standard frequency so that instantaneous when carrying out channel switch, pll system may be interfered.
Therefore, the objective of the invention is to, a kind of phase-locked loop (PLL) circuit that can overcome the problems of the prior art is provided.
Another object of the present invention is, the PLL circuit that provides a kind of realization fast frequency with reliability of increase to shift.
For achieving the above object, the invention provides a kind of specific phase-locked loop (PLL) circuit, wherein use one or several to be different from the control circuit of charge pump circuit, wherein control circuit is connected for providing boost voltage to the capacity cell in the LPF integrating circuit, so that response produces output control voltage as the phase difference of the output of phase comparator circuit, so as to realizing at a high speed and more stable frequency translation.
The PLL circuit comprises the reference signal source that is used to produce reference frequency signal, first divider circuit, be used for the reference frequency signal as the output of reference signal source is carried out frequency division, voltage-controlled pierce circuit, the signal that is used for the confirmable frequency of the with good grounds control voltage of output device, second divider circuit, be used for the output signal of voltage-controlled pierce circuit is carried out frequency division, phase comparator circuit, it is the phase place of the output signal separately of first and second divider circuits relatively, so as to exporting the error signal of its pulsewidth corresponding to the phase difference that detects, charge pump (charge pump) circuit, it responds as the error signal of the output of phase comparator circuit and is driven, low pass filter (LPF), it has integrating circuit, and be used for the output of mean charge pump circuit, thereby export a average signal as control voltage, and control circuit, it monitors error signal, and response is more than or equal to the appearance of the phase error of a predetermined value, provides suitable booster tension corresponding to final phase difference to the capacity cell in the integrating circuit of LPF.
Wherein, control circuit preferably so is provided with, and when making pulsewidth when error signal more than or equal to predetermined value, control circuit produces has the approaching booster tension that is used to make the control magnitude of voltage that voltage-controlled oscillator circuit vibrates under target frequency.
Control circuit also preferably is set for and produces for the peak pulse duration of the error signal window signal of use, and when the pulsewidth of relatively representing error signal of this pulse width signal and error signal during more than or equal to a predetermined value, according to predetermined level data are set and produce booster tension, so that booster tension is set near control magnitude of voltage or near the enough values the control magnitude of voltage, so that voltage-controlled oscillator circuit is vibrated under target frequency.
Control circuit also preferably includes memory or " memory " circuit, be used for therein that memory level is provided with data and certain is provided with data, the frequency dividing ratio of first divider circuit and/or second divider circuit for example is so that provide the ability that these two frequency dividing ratios is set and booster tension is set.
In addition, the PLL circuit that comprises the reference signal source that is used to produce reference frequency signal preferably can also be provided, first divider circuit, be used for the reference frequency signal as the output of reference signal source is carried out frequency division, voltage-controlled oscillator circuit, be used to export signal with the characteristic frequency that can determine according to control voltage, second divider circuit, be used for the output signal of voltage-controlled oscillator circuit is carried out frequency division, phase comparator circuit, be used for comparing mutually the phase place of first and second divider circuits output signal separately, so as to exporting the error signal of its pulsewidth corresponding to detected phase difference, charge pump circuit, it responds as the error signal of the output of phase comparator circuit and is driven, LPF, it has integrating circuit, and the output that can operate charge pump circuit averages, export average signal then as control voltage, and control circuit, it monitors error signal, and at phase difference in the time interval greater than a predetermined value, capacity cell to the integrating circuit of LPF provides booster tension, and after stopping to provide booster tension,, also no longer provide booster tension even phase difference surpasses predetermined value once more.
A major advantage of the present invention is, can carry out high speed and reliable frequency translation.
Specifically, utilize to be designed to be provided with frequency according to target and the PLL circuit of different booster tension, and the generation of response given reference phase difference and utilize this booster tension, can on the whole frequency band of PLL circuit, quicken the transfer of expected frequence.This makes the design of PLL circuit make amendment according to any possible variation of the standard of use therein VCO circuit easily again, thereby reduces cost.
Another advantage of the present invention is, use booster tension by being limited in a moment, can eliminate or undesirable hyperharmonic less stress phenomenon suppress to take place at least greatly, and needn't carry out too thin or too accurate booster tension setting, thereby make it possible to realize the PLL circuit that fast frequency shifts with the cost realization that reduces greatly.
Fig. 1 is the structure chart of phase-locked loop (PLL) circuit according to first embodiment of the invention.
Fig. 2 is used for the structure of major part of the circuit of key diagram 1.
Fig. 3 is the sequential chart of operation that is used for the circuit of key diagram 1.
The operation of Fig. 4 key diagram 1 circuit.
The operation of Fig. 5 key diagram 1 circuit.
Fig. 6 is the structure chart of phase-locked loop (PLL) circuit according to second embodiment of the invention.
Fig. 7 is used for the structure of major part of the circuit of key diagram 6.
Fig. 8 is used for the structure of major part of the circuit of key diagram 6.
Fig. 9 is used for the structure of major part of the circuit of key diagram 6.
Figure 10 is the sequential chart of operation that is used for the circuit of key diagram 6.
The modification of the major part of Figure 11 key diagram 6.
The structure of the PLL circuit of Figure 12 (a)-(c) explanation prior art.
The following describes phase-locked loop (PLL) circuit according to first embodiment of the invention.Fig. 1 is the structure principle chart of explanation first embodiment of the invention.In the drawings, label 1 is represented reference signal source, and its generation is also sent the signal that can be used as benchmark.Label 2 is represented divider circuit, and it is used for the output signal of reference signal source 1 is carried out frequency division.Label 3 representative voltage control generator (VCO) circuit, it is used to export the signal with the frequency that can determine according to the value of the control voltage that is provided for control end by operation.Label 4 representatives are used for the output signal of VCO3 is carried out the divider circuit of frequency division.Label 5 is phase comparator circuit, and it can be operated and be used for mutually relatively the output signal A and the B of divider circuit 2,4, thereby at U, the output of D end has the error signal corresponding to the pulsewidth of detected phase difference.More particularly, when signal A phase lead signal B, then in the error signal of U end output corresponding to this final phase difference; On the contrary, when the former the phase lag latter, then from the corresponding error signal of D end output.Label 6 is charge pump circuits, it comprises P-channel metal-oxide-semiconductor (PMOS) transistor and N-channel MOS (NMOS) transistor of interconnected in series, be connected in together between unshowned herein power end VDD of their drain electrode (5V) and the VSS (0V), and its drain electrode connects together at the connected node that can be used as output, the U end of response phase comparator circuit 5 and each output signal of D end, the grid of described PMOS transistor and nmos pass transistor is driven conducting and ends.
Label 7 is represented low pass filter (LPF) circuit, and it is used for the output signal of mean charge pump 6 by operation, thereby exports final average signal as control voltage.Fig. 2 shows a kind of circuit structure of reality.It mainly comprises two-stage integration circuit 71,72.First order integrator 71 can be made of resistance R 1-R4 and capacitor C 1, makes the output of charge pump 6 be provided for an end CH of resistance R 1, makes the booster tension that the following describes offer an end BS of resistance R 2 simultaneously.Second level integrator 72 comprises resistance R 5 and the capacitor C 2 of control voltage is provided at its output OUT.
Label 8 is represented the window generator circuit, its output window signal, and its pulsewidth is the center with the trailing edge as the signal B of the input of phase comparator 5.More particularly, the generation of window signal is carried out waveform shaping by the M signal to the frequency divider stage of frequency divider 4 and is realized.Notice that herein when the pulsewidth of the window signal of output is center when limiting its mid point with the trailing edge of signal B, the window signal generator can selectively design by this way, make its output with the trailing edge of signal A window signal as its center.
Label 9 representatives promote generator circuit, its response window signal and error signal U, the reception of D, be not in error signal under the situation within the pulsewidth of window signal, be used for producing the lifting signal, in the time of within error signal is in the window signal pulsewidth, then stop to produce the lifting signal.In other words, making the state of its output is that high impedance interrupts.Wherein, this circuit is designed to basis from U, and the error signal of D end produces " H " and " L " status signal.
Label 10 is level generator circuit, its response is as the lifting signal of the output that promotes generator 9, being used to export its magnitude of voltage can be provided with the booster tension that data are determined according to level, and data are set described level and the frequency division data are set in advance, and is used for changing or revising frequency of oscillation.More particularly, produce a specific voltage as booster tension, its magnitude of voltage is near being applicable to the control voltage that VCO 3 is arranged on vibration under the target frequency.
Label 11 is oscillation control circuits, is used for forcing VCO 3 selectively vibration under a frequency of a plurality of different target frequencies; For this reason, control circuit has memory cell, wherein store the frequency division data and data are set about the level of certain frequency, be used for that response frequency changes order or from the instruction of unshowned control section (for example using the control module of the electronic equipment of present embodiment), frequency division data according to the reaction target frequency, to frequency divider 2,4 output frequency division signalizations, so as to changing or revise the value of these frequency dividing ratios, simultaneously data are set to level generator 9 output level signalizations according to level, thereby, force it to determine the value of booster tension.
Operation below with reference to sequential chart explanation present embodiment shown in Figure 3.
Fig. 3 represents the frequency of oscillation transfering state of VCO 3, signal A wherein, and B is the signal by the output signal frequency division gained of reference signal source 1 and VCO 11, it is respectively a frequency divider 2,4 output signal, the phase place of signal B lags behind than signal A, shown in " A " and " B " among Fig. 3.Phase comparator 5 is operated, and is used for these signals of comparison A, B, the error signal U of output shown in Fig. 3 " U ".Response error signal U, charge pump 6 is operated, and is used for the capacity cell C1 to LPF 7, the C2 charging.Window generator 8 is to promoting generator 9 output window signal W, and it is with the trailing edge of the signal B center as its pulsewidth, shown in " W " among Fig. 3.Because this moment, error signal U dropped on the outside of the pulsewidth of window signal W, produce the lifting signal so promote generator 9 response error signal U.Receive promote signal after, level generator 10 its output produce and send its magnitude of voltage near be used for making VCO 3 with the booster tension of the control voltage of target frequency vibration shown in Fig. 3 " BS ".For example, the hypothetical target frequency is f1 as shown in Figure 4, then is produced as to produce the booster tension of its required magnitude of voltage of this frequency near control magnitude of voltage V1.Then, the BS that this booster tension is offered LPF shown in Figure 37 holds, and so as in first order integrating circuit 71, removes outside the output of the charge pump 6 that is provided for the CH end, also capacitor C 1 is charged, thereby the magnitude of voltage of control voltage is increased fast by booster tension.This increase of the frequency of oscillation of VCO 3 can make signal A, and the phase difference between the B reduces; When error signal dropped within the pulsewidth of window signal, booster tension was interrupted, and the BS end becomes high impedance.After this, control voltage increases owing to being charged separately and may be continued by charge pump 6, reaches the suitable control magnitude of voltage that is used to produce target frequency at last; At this moment, the PLL circuit of present embodiment is just locked.In the curve of Fig. 5 label be the curve shows of " a " when using booster tension frequency to time relation, this relation when label does not use booster tension for the curve shows of " b ".By curve " a " as seen, because PLL is locked after forcing the quick increase of its frequency near the booster tension of target frequency f1 by use by means of charge pump 6, so its locking is more very fast than the situation " b " of not using booster tension.Under situation " a ", be locked in t0 realization constantly, and under situation " b ", then realize at t1.
Should note, when the phase place of signal B is ahead of signal A but error signal D when not dropping within the pulsewidth of window signal W, produce the booster tension of " L " level, make the level generator 10 that receives this signal be used as this booster tension the voltage of power end VSS, so as to frequency is descended fast, make the phase place of above-mentioned signal B lag behind signal A, be called as leading operation thereby allow to carry out.
By as seen above-mentioned, described embodiment is provided with specially, make when frequency translation begins by removing outside the output that utilizes charge pump 6, also utilize booster tension and increase control voltage fast, and after this only use charge pump 6 to increase more accurately and control voltage.Thereby, just can obtain to be enough to obtain the magnitude of voltage of the expection of target frequency with speed that increases and precision, this can make the PLL circuit of present embodiment lock apace again.Should be noted that herein when target frequency is f1,, then may make the too big situation of charge volume of capacitor C 1, thereby VCO 3 is worked being higher than under the too high frequency f x of frequency f 1 if the value of booster tension is set to VDD.Therefore, shown in Fig. 5 " c ", attempt to compensate the overshoot or the feasible increase too much of the less stress confession required time of convergence of aforesaid state, thereby can not the shortening time.In view of this, described embodiment is so constructed, and makes booster tension be set near the value that is close to the selection that produces the required control magnitude of voltage of target frequency, just thinks just to utilize when error signal surpasses predetermined pulsewidth this booster tension simultaneously.In addition, have only when needed, comparison window signal and error signal also use booster tension can suppress to take place the hyperharmonic less stress separately.
The value that shall also be noted that booster tension in the present embodiment is set to be close to and produces target frequency and certain value of required control voltage, rather than and control the identical value of magnitude of voltage itself accurately; According to the structure of the characteristic (for example response characteristic) of VCO 3 and used LPF, and time constant, the value of booster tension can change, thereby by each frequency under taking one thing with another, can be arranged on an approaching value.This booster tension is provided with simultaneously and carries out according to the setting of relevant frequency division data.In general, the data of using in the PLL circuit when frequency translation can comprise 3 kinds: be used for divider circuit and with respect to the frequency division of reference signal source data be set, be used for divider circuit and data be set with respect to the frequency division of VCO, and function setting data, for every kind of frequency, these data are set in advance, and are stored in the storage area of control circuit, be used to control PLL and operate (memory cell in the oscillating controller 11 is not shown in the present embodiment).In addition, each divider circuit with respect to reference signal source and the setting and the function setting of frequency dividing ratio once carried out, particularly, by the frequency (being the frequency of signal A in the present embodiment) that is provided with respect to the frequency dividing ratio of reference signal source by each divider circuit, in case its under initial situation by initial setting up after, just no longer change.On the contrary, when frequency shift, all to carry out of the setting of each divider circuit with respect to the frequency dividing ratio of VCO.For this reason, described embodiment is set for and removes storage and be used for being provided with outside the data bit with respect to the frequency dividing ratio of VCO 3 frequency dividers 4, storage therein is used for being provided with the particular data position of booster tension, when frequency shift, it is read, and, carry out the setting of level generator 7 simultaneously according to the setting of frequency divider 4.In this way, present embodiment can be provided with best booster tension for each frequency, thereby almost can shorten locking time in the whole frequency band of VCO 3.In addition, during the process of design PLL circuit,, just can adapt to any possible change of the standard of use therein VCO circuit by revising the value of setting in advance of booster tension simply, the standard that reduces the part outside the VCO simultaneously changes, and this makes again and reduces cost.
Should also be noted that, though first embodiment is so arranged, make and booster tension is set by level generator 10, but the present invention is not limited to this, but can revise, for example, booster tension is fixed as a predetermined value, perhaps uses the condition of this booster tension in addition by additional some restriction conduct.The following describes the PLL circuit of the second embodiment of the present invention that makes in this way.
The structure of present embodiment at first is described with reference to Fig. 6.In the accompanying drawings, with Fig. 1 in the identical parts or the element that use represent with identical label.In Fig. 6, label 12 is represented phase comparator circuit, and label 13 is represented charge pump circuit.The practical structures of phase comparator 12 and charge pump 13 as shown in Figure 7.Phase comparator 12 is combined by this way by a plurality of NAND doors and inverter, make it at its terminal FR, FV received signal " A " and " B ": when the phase place of signal A was ahead of signal B, phase comparator was in the error signal of " u " end output corresponding to this phase difference; Otherwise, when the phase place of signal A lags behind signal B, then in the corresponding error signal of " d " end output.Charge pump 13 comprises PMOS transistor and nmos pass transistor, and they are connected in series between the VSS mutually at power end VDD, and its drain electrode connects together at common node, and common node links to each other with output OUT 1 again.The response of these PMOS and nmos pass transistor respectively can conducting from the error signal of " u " end of phase comparator 5 and " d " end or is ended, so as to providing power supply to the low pass filter that the following describes (LPF).Attention is in Fig. 7, and the R end is a reset terminal, and the reset signal that it is used to import the oscillation control circuit (not shown) resets phase comparator 12 and charge pump circuit 13.Label 14 is represented LPF, and it can be made of two-stage integrating circuit 141,142 as shown in Figure 8.First order integrator 141 is made of resistance r1-r4 and electric capacity c1, and the output of charge pump 13 is supplied to " ch " end of resistance r1, is supplied to " bs " end of resistance r2 from the booster tension of the lifting circuit that the following describes.Second level integrator 142 is made of resistance r5 and electric capacity c2, produces control voltage at output OUT 2.Label 15 representative of Fig. 6 promotes circuit, its structure as shown in Figure 9, comprising D flip-flop circuit df1-df4, NAND door na1-na5, NOR door no1, inverter i1-i4, nmos pass transistor N1, and PMOS transistor P1.Promote the input receive window signal of circuit 15 at inverter i1, simultaneously at d1, from the u of phase comparator 12, the error signal of d end is not so that at the output voltage of output OUT 3 generations corresponding to each signal for d2 termination contracture.
The following describes the operation of present embodiment.
Figure 10 is the sequential chart that is used to illustrate the operation of present embodiment, represents with identical label with the similar signal of Fig. 3 in it.Suppose that the PLL circuit that makes present embodiment operates at the moment of Figure 10 t0.Note at this moment carving, after response reset signal R makes the whole PLL circuit reset of present embodiment, operate and to begin.Thereby D flip-flop df1-df4 is maintained at reset mode, and the output of NOR door is in " H " level, and PMOS transistor P1 and nmos pass transistor N2 end, and output OUT 3 is a high impedance, and LPF 14 receives only the output from charge pump 13.
The phase place of supposing the moment signal B after the operation beginning lags behind signal A, and at moment t1, the error signal of gained " u " may rise to " H " level.Then, produce window signal W at moment t2.D flip-flop df1 receives this signal at its clock end CP1 by inverter i1 and NAND door na1, pin signal " H " then from the u end, this signal at data terminal d1 to be received with the synchronous mode of the trailing edge of window signal W, so as to output signal is raise for " H " level, shown in " Q1 " among Figure 10.Signal Q1 arrives PMOS transistor P1 through NAND door na4, makes this transistor turns.Thereby the OUT3 end may be made gained voltage be added on the bs end of LPF 14 as booster tension by drop-down towards power end VDD side.The control magnitude of voltage of noting being used to producing the VCO 3 of target frequency herein is set to the magnitude of voltage of power end VDD.Should also be noted that the control magnitude of voltage that is lower than this value if desired, can be by the relevant bleeder circuit output that is used for the output of output OUT 3 is converted to the suitable voltage value.An example is, bleeder circuit 16 shown in Figure 11 is provided, by two divider resistance r6, the series circuit of r7 is connected to power end VSS to output OUT 3, the common node that makes these two resistance simultaneously is as output, and its output is provided for the bs end by the transmission door " tr " relevant with it.In addition, among Figure 11 and Fig. 8, similar elements is used identical symbolic representation among Fig. 9.Preferably this circuit constitutes by this way, makes in the operation shown in fig. 10, is in moment of high impedance at output OUT 3, and it is closed and force bs to hold a side to be in high-impedance state to send door tr.
Return Fig. 8, electric capacity c1 also is raised voltage charging by the error signal charging from charge pump 13, makes booster tension near the required control magnitude of voltage of target frequency (being the magnitude of voltage of power end VDD herein).Thereby, signal A, the phase difference between the B reduces, and makes error signal u drop within the pulsewidth of window signal W; At this moment, promptly at moment t3, the current potential of window signal W was attempted to raise before the current potential of the error signal u that is in " H " level increases, and made D flip-flop df1 operate, thereby read " L " state of d1 end, made signal Q1 drop to " L " level.This makes PMOS transistor P1 end, and output OUT 3 is in high-impedance state, thereby makes LPF 14 receive only the output of charge pump 13.Because this voltage drop of signal Q1, D flip-flop df3 are locked in " H " level signal (current potential of this signal is pulled to power vd D) that its data terminal d3 receives, thereby produce the output signal Q3 of " H " level.Correspondingly, NOR door no1 is fixed on " L " level with the current potential of its output signal.Therefore, even window signal u within the pulsewidth of window signal W took place not drop on afterwards,, promote circuit 15 and also make output OUT 3 remain on high-impedance state owing to do not produce output voltage.In other words, present embodiment is provided with specially, only makes after the operation beginning moment at once utilize booster tension.This method is used to eliminate owing to excessively using from producing a certain booster tension that begins to produce just over the error signal of window signal pulsewidth the hyperharmonic less stress takes place, and this suppresses the overcharge of electric capacity c1 again.More particularly, when the value of this booster tension is fixed on a magnitude of voltage by LPF 14, with carrying out in first embodiment thin or accurate booster tension setting compare, the hyperharmonic less stress may take place easily, for avoiding this problem, second embodiment uses " one is used constantly " method, and its restriction is only used booster tension to a moment.In other words, present embodiment has been avoided carrying out thin booster tension setting or adjusting, thereby has reduced the complexity of circuit structure, and reduces product cost.
The PLL circuit that should be noted that mode of operation supposition present embodiment described herein is restarted after moment t4, and the phase place of putative signal B is ahead of signal A.In this case, at the d of phase comparator 12 end error signal d may appear.The D flip-flop df2 that receives this error signal d in its d2 termination also receives signal corresponding to the anti-phase form of window signal W at clock end CP2, and at the state of this data terminal of time locking d2 of its trailing edge, makes output signal Q2 become high potential.At this moment, another D flip-flop df4 receives output signal Q2 in its clock termination, and at the state of the trailing edge locking data end d4 of this signal.Thereby, when error signal d is not within the pulsewidth of window signal W, nmos pass transistor N1 conducting, the potential drop that makes output OUT 3 is to " L " level.Thereby the current potential of the bs of LPF 14 end is pulled to power end VSS, compares quick minimizing so as to the value that makes control voltage with the situation of the output that receives only charge pump 13.When error signal d was within the pulsewidth of window signal W, output OUT 3 was in high-impedance state, even in this case, when output OUT 3 was in " L " level that presents high-impedance state, after this this end also kept high impedance status.
Though booster tension is used in above explanation supposition when the operation of PLL circuit begins, sort circuit can improve, and makes that working as VCO 3 is changed frequency and the D flip-flop df3 that resets, and also uses booster tension during df4.
From the above description obviously as seen, second embodiment can use this booster tension to simplify the setting of booster tension value by restriction, simultaneously to be similar to the mode of above-mentioned first embodiment, provides the ability that keeps the high speed lock operation.
Claims (5)
1 one kinds of phase-locked loop circuits comprise:
Be used to produce the reference signal source of reference frequency signal;
First divider circuit is used for the described reference frequency signal as the output of described reference signal source is carried out frequency division;
Voltage-controlled pierce circuit is used to export the signal that has corresponding to the frequency of a control voltage;
Second divider circuit is used for the described output signal of described voltage-controlled pierce circuit is carried out frequency division;
Phase comparator circuit is used for the phase place of the output signal separately of more described first and second divider circuits, if when having phase difference therebetween, then so as to exporting the error signal of its pulsewidth corresponding to therebetween phase difference;
Charge pump circuit, it responds as the error signal of described phase comparator circuit output and is driven;
Low-pass filter circuit with integrating circuit is used for the output of average described charge pump circuit, thereby exports an average signal as described control voltage; And
Control circuit is used to monitor error signal, and response is more than or equal to the appearance of the phase error of a predetermined value, provides booster tension corresponding to described phase difference to the capacity cell in the integrating circuit of described low-pass filter circuit.
2 phase-locked loop circuits as claimed in claim 1, wherein said control circuit is when the pulsewidth of described error signal during more than or equal to described predetermined value, produces the booster tension that has near the described control magnitude of voltage that is used to make described voltage-controlled oscillator circuit to vibrate under target frequency.
3 phase-locked loop circuits as claimed in claim 1, wherein said control circuit is used to produce the window signal that the peak pulse duration for described error signal uses, and when the pulsewidth of described error signal is more than or equal to described predetermined value between the comparable period of described window signal and described error signal, according to default level data are set and produce described booster tension, so that described booster tension is set near on certain value of described control magnitude of voltage, so that described voltage-controlled oscillator circuit is vibrated under described target frequency.
4 phase-locked loop circuits as claimed in claim 3, wherein said control circuit comprises memory circuitry, be used for storing the data that described level is provided with data and comprises the frequency dividing ratio of described first divider circuit and/or described second divider circuit therein, described frequency dividing ratio be set simultaneously so that described booster tension is set.
5 one kinds of phase-locked loop circuits comprise:
Be used to produce the reference signal source of reference frequency signal;
First divider circuit is used for the described reference frequency signal as the output of described reference signal source is carried out frequency division;
Voltage-controlled pierce circuit is used to export the signal that has corresponding to the frequency of a control voltage;
Second divider circuit is used for the described output signal of described voltage-controlled pierce circuit is carried out frequency division;
Phase comparator circuit is used for the phase place of the output signal separately of more described first and second divider circuits, if when having phase difference therebetween, then so as to exporting the error signal of its pulsewidth corresponding to therebetween phase difference;
Charge pump circuit, it responds as the error signal of the output of described phase comparator circuit and is driven;
Low-pass filter circuit with integrating circuit is used for the output of average described charge pump circuit, thereby exports an average signal as described control voltage; And
Control circuit, be used to monitor described error signal, in the time of outside described phase difference is in a particular value, provide booster tension to the capacity cell in the described integrating circuit of described low-pass filter circuit, and after stopping to apply booster tension, even when described phase difference surpasses described particular value once more, stop to apply described booster tension.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06269197A JP3313998B2 (en) | 1997-03-17 | 1997-03-17 | Phase locked loop |
| JP62691/97 | 1997-03-17 | ||
| JP62691/1997 | 1997-03-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1203483A true CN1203483A (en) | 1998-12-30 |
| CN1111955C CN1111955C (en) | 2003-06-18 |
Family
ID=13207576
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN98108872A Expired - Fee Related CN1111955C (en) | 1997-03-17 | 1998-03-17 | Phase-locked loop circuit |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5903197A (en) |
| JP (1) | JP3313998B2 (en) |
| KR (1) | KR100265453B1 (en) |
| CN (1) | CN1111955C (en) |
| TW (1) | TW407400B (en) |
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| WO2009076838A1 (en) * | 2007-12-14 | 2009-06-25 | Huawei Technologies Co., Ltd. | Control data process method and device |
| CN100563109C (en) * | 2004-02-27 | 2009-11-25 | 三洋电机株式会社 | The PLL circuit |
| CN101615906B (en) * | 2008-10-28 | 2012-10-03 | 东莞理工学院 | Clock-synchronization digital phase-locking method and device |
| WO2015081564A1 (en) * | 2013-12-06 | 2015-06-11 | 海能达通信股份有限公司 | Frequency synthesis method of fast locking based on phase-locked loop frequency and circuit thereof |
| CN109964396A (en) * | 2016-10-03 | 2019-07-02 | 德州仪器公司 | Transient affair detector circuit and method |
| CN114422043A (en) * | 2022-03-28 | 2022-04-29 | 成都嘉纳海威科技有限责任公司 | Reliability test device and method |
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| US6154508A (en) * | 1998-03-23 | 2000-11-28 | Vlsi Technology, Inc. | Method and system for rapidly achieving synchronization between digital communications systems |
| JP3447617B2 (en) * | 1999-06-04 | 2003-09-16 | エヌイーシーマイクロシステム株式会社 | Digital variable frequency oscillator |
| US7242229B1 (en) | 2001-05-06 | 2007-07-10 | Altera Corporation | Phase locked loop (PLL) and delay locked loop (DLL) counter and delay element programming in user mode |
| US6992517B2 (en) * | 2003-08-11 | 2006-01-31 | Atmel Corporation | Self-limiting pulse width modulation regulator |
| JP4469758B2 (en) * | 2005-07-04 | 2010-05-26 | パナソニック株式会社 | Audio processing device |
| US7501803B1 (en) * | 2005-09-22 | 2009-03-10 | Cypress Semiconductor Corporation | Synchronized boost signal apparatus and method |
| US7268632B2 (en) * | 2005-09-30 | 2007-09-11 | International Business Machines Corporation | Structure and method for providing gate leakage isolation locally within analog circuits |
| KR100800143B1 (en) * | 2006-04-11 | 2008-02-01 | 주식회사 하이닉스반도체 | Phase locked loop and phase locked method |
| JP4104634B2 (en) * | 2006-05-23 | 2008-06-18 | シャープ株式会社 | Semiconductor device |
| KR100934222B1 (en) * | 2007-08-29 | 2009-12-29 | 한국전자통신연구원 | High Resolution Capacitive-Time Conversion Circuit |
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| US9906227B2 (en) * | 2015-08-13 | 2018-02-27 | Maxlinear, Inc. | Method and system for a sampled loop filter in a phase locked loop (PLL) |
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| CN114172511B (en) * | 2021-12-13 | 2024-06-18 | 四川九洲电器集团有限责任公司 | Frequency preset control method and device based on FPGA, medium and electronic equipment |
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| JPS6010458B2 (en) * | 1979-08-23 | 1985-03-18 | 富士通株式会社 | Phase locked loop circuit |
| US4543540A (en) * | 1983-04-25 | 1985-09-24 | Honeywell Inc. | Phase locked loop with limited phase correction when in locked condition |
| US4562411A (en) * | 1983-12-29 | 1985-12-31 | Rca Corporation | Prepositioning circuit for phase lock loop |
| IL71718A (en) * | 1984-05-01 | 1990-01-18 | Tadiran Ltd | Millimeter wave frequency synthesizer |
| EP0840456A3 (en) * | 1990-10-22 | 1999-08-25 | NEC Corporation | PLL frequency synthesizer capable of changing an output frequency at a high speed |
-
1997
- 1997-03-17 JP JP06269197A patent/JP3313998B2/en not_active Expired - Lifetime
-
1998
- 1998-03-10 TW TW087103491A patent/TW407400B/en not_active IP Right Cessation
- 1998-03-12 US US09/041,466 patent/US5903197A/en not_active Expired - Lifetime
- 1998-03-17 KR KR1019980008930A patent/KR100265453B1/en not_active IP Right Cessation
- 1998-03-17 CN CN98108872A patent/CN1111955C/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100563109C (en) * | 2004-02-27 | 2009-11-25 | 三洋电机株式会社 | The PLL circuit |
| US8031015B2 (en) | 2004-02-27 | 2011-10-04 | Sanyo Electric Co., Ltd. | Phase-locked loop circuit |
| WO2009076838A1 (en) * | 2007-12-14 | 2009-06-25 | Huawei Technologies Co., Ltd. | Control data process method and device |
| CN101615906B (en) * | 2008-10-28 | 2012-10-03 | 东莞理工学院 | Clock-synchronization digital phase-locking method and device |
| WO2015081564A1 (en) * | 2013-12-06 | 2015-06-11 | 海能达通信股份有限公司 | Frequency synthesis method of fast locking based on phase-locked loop frequency and circuit thereof |
| CN109964396A (en) * | 2016-10-03 | 2019-07-02 | 德州仪器公司 | Transient affair detector circuit and method |
| CN109964396B (en) * | 2016-10-03 | 2021-12-10 | 德州仪器公司 | Transient event detector circuit and method |
| CN114422043A (en) * | 2022-03-28 | 2022-04-29 | 成都嘉纳海威科技有限责任公司 | Reliability test device and method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980080333A (en) | 1998-11-25 |
| KR100265453B1 (en) | 2000-09-15 |
| JPH10256906A (en) | 1998-09-25 |
| US5903197A (en) | 1999-05-11 |
| CN1111955C (en) | 2003-06-18 |
| JP3313998B2 (en) | 2002-08-12 |
| TW407400B (en) | 2000-10-01 |
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