CN1192490C - Method of sampling, downconverting, and digitizing bandpass signal using digital predictive coder - Google Patents

Abstract

A simple down converting A/D converter utilizing predictive coding principles. By placing the sampler inside the predictive loop, the predictive loop filter can be implemented using DSP techniques, thus eliminating the complexities introduced by use of discrete-time analog circuitry. Then, by re-mapping the output of the predictive loop filter into the analog domain using a D/A converter, the predictive filter output signal is subtracted from the input analog signal to generate the prediction error signal. Therefore, through directly sampling the prediction error signal and converting the output of the predictive loop filter into analog representation using a low-cost multiple bit D/A, the use of discrete-time analog circuitry is eliminated and the complexity of the converter design is greatly reduced.

Description

With digital predictive device to bandpass signal sampling, down coversion and method for digitizing

It the present invention relates to the use of the field of Digital Signal Processing design wireless receiver.

Here is reference for the present invention:

[1] F.de Jager, " Δ modulation -- the method for carrying out PCM transmission using element number " PhilipsRes.Repts., vol.7, pp.442-466；1952.

[2] H.S.MeDonald, " pulse code modulation and ADPCM encoder " 1970 U.S. Patent No. 3,526,855 (nineteen sixty-eight application).

[3] R.Steele, Δ modulating system, New York；Wiley, 1957.

[4] H.Inose, Y.Yasude and J.Murakami, " telemetry system coded modulation -- delta sigma modulation " IRE Trans.Space Elect.Telemetry, vol.SET-8, pp.204-209, Sept.1962.

[5] S.K.Tewksbury and R.W.Hallock, " the noise-shaping encoder of 1 rank of over-sampling linear prediction and N > ", Sys., vol.CAS-25, pp.436-447,1978 years July of IEEE Trans.Circuits.

[6] Sys., vol.41, no.6, pp.402-405,1994 years June of D.B Ribner, " multi-stage bandpass delta sigma modulator " IEEE.Trans.Circuits.

[7] A.M.Thurston, " ∑ of digital radio-Δ frequency (IF) A-D converter " GECJoumal of Research Incorporating Marconi Review and Plessey ResearchReview, vol.12, no.2, pp.76-85,1995.

[8] N.van Bavel et al., " analog/digital interface of cellular phone " IEEE CustomIntegrated Circuits Conference, pp.16.5.1-16.5.4,1994.

It is had many advantages in the work of radio frequency (RF) receiver using Digital Signal Processing (DSP) technology.However, the utilization of these advantages is largely dependent on the ability that signal from analog amount is effectively transformed into digital quantity.

In traditional radio frequency (RF) receiver, utilize analog circuit, by one or more conversions to intermediate frequency (IF), the signal being received is downconverted as same phase (I) and orthogonal (Q) base band ingredient, is then transformed into numeric field in the analog to digital A/D converter of fundamental frequency using a pair of of pulse code modulator (PCM) type work.There are a variety of decayed sources when using this design scheme, they limit the performance being able to achieve.Separating capacity of the receiver between the signal component higher than intermediate frequency and lower than intermediate frequency will be all reduced for signal mixing is become any phase error in the local oscillator of I and Q base band ingredient.For example, 40 decibels of discrimination for obtaining (I-Q) requires the orthorhombic phase potential difference of these local oscillators within 0.5 °, including all drifts as caused by aging, temperature and manufacturing tolerance.This phase accuracy preferably must be held in a pair of of analog channel from beginning to end, and including A/D conversion function.It is similar to its, the amplitude-frequency response of two analog channels, including any gain mismatch between two A/D converters, it is necessary to be matched well, to keep the difference of (I-Q) of receiver.Furthermore in order to obtain 40 decibels of discrimination, the matching of the amplitude-frequency response in two channels is higher than 0.1 decibel and is necessary.This tolerance is possible, and can be more than this tolerance by using routine debugging；However, being often able to obtain such tolerance in a pair of of digital channel, therefore the digitized function directly to IF channel can be provided, to completely avoid these equilibrium problems.

IF/ analog circuit is not needed using the design scheme that traditional PCM type multidigit A/D converter carries out direct A/D conversion to the IF signal being received.Although a large amount of high speed digital switches are arranged beside sensitive RF circuit can cause to interfere, it is generally recognised that its potential advantage has been more than the difficult point in new design.Carrying out another question caused by digitized processing for IF signal is to need to carry out high-speed a/d conversion, it is a kind of together in the higher linear hybrid of the prime of receiver needs the problem of.Traditional is mostly that A/D converter has the quality that, it can obtained signal bandwidth is equal to the half of sample frequency, less than the surplus in view of anti-mixed filtering.The bandwidth of converter and the product (or dynamic range) of resolution ratio are used to measure the performance of converter, and it generally will reflect in the difficulty of design described device and the price in its market.Because common IF signal is narrowband compared with its carrier frequency, so, the optimal encoding scheme for a very special problem cannot be represented using broadband multi-digit converter.Certain can realize the greatly simplification of A/D converter processing by making it work in a subsampled fashion, carrier frequency being made to be higher than sample frequency.However, the bandwidth for reaching design object in this way and the channel filtering before dynamic range needs reinforcement conversion, to prevent other channels due to obscuring the increase for entering passband and leading to cost and power consumption.

Although being conventionally based on baseband signal, particularly audio signal and working, but its attractive characteristic (see the reference of front) is shown according to the A/D converter of prediction and interpolation coding (such as, Δ conversion and ∑-Δ are converted) design.Firstly, they are a kind of over-sampling coding techniques, i.e., by the precise quantification of time, rather than the precise quantification of level realizes the precision of coding.Therefore, for given sample frequency, compared with pulse code modulation (PCM) technology of standard, available bandwidth is substantially reduced, and designs the considerations of reflecting this compromise in demand by being suitable for simplifying for low tolerance element.In general, analog filtering required for this converter is therefore fairly simple.

The second advantage of this type of coding is their intrinsic linear characteristics.Multi-digit converter is highly susceptible to the influence of component tolerances, and the Nonlinear Mapping between analog- and digital- domain to be avoided to be difficult.A kind of very effective method that eliminating this influence is pulsed using high level additional high, it will effectively remove non-linear dependencies from input signal, and by it is described influence to reduce become a kind of faint noise source.This technology can be used to eliminate the non-linear effects in encoder, but, finally limit its performance is pcm encoder, and this itself can generate highly relevant distortion, this include evenly spaced radio channel application in be also likely to be difficult.

Many authors have advocated the encoder (that is, ∑-Δ converter) that interpolated value type is used in conversion of the analog quantity in high-frequency I F to digital quantity, as most latter two author in reference described above.Although the advantages of these technologies by these authors describe it is clear that still one, which is conceived to, reduces cost, and overcome the challenge on many implement to be still necessary to for the designer of target to reduce power consumption.Most outstanding in these challenges is such a fact, although these technologies finally generate oversampled signals position (1-bit) digital representation of IF signal, but the signal must be simulated into continuous time expression from it first and be converted into the expression of analog discrete time, before being mapped to numeric field (quantify or digitize), the signal will be handled by fine discrete-time analogues circuit.Moreover, the advantages of realizing the high dynamic range as provided by these technologies and low quantizing noise needs to be implemented the encoding loop of high-order, this will greatly increase complexity.

The present invention realizes simple down coversion A/D converter using predictive coding principle.By the way that sampler is arranged in predictive loop, prediction loop filter can be realized using DSP technology, therefore, eliminate complexity caused by due to using discrete-time analogues circuit.Then, the output for predicting loop filter is mapped by analog domain by using D/A converter again, subtracts predictive filter output signal from input analog signals to generate predictive error signal.Therefore, by directly sample to predictive error signal and the output for predicting loop filter being converted into analog quantity using cheap multidigit D/A converter, the present invention avoids the complexity for using discrete-time analogues circuit and greatly reducing converter design.

DSP technology is mainly used in the operation of predictive loop, can use flexibility provided by these technologies in this way matched the characteristics of adapting to digital forecast loop with input signal.Higher dynamic range and lower quantizing noise performance are achieved with using low order and relatively simple predictive loop in this way.

The present invention generates the signal for controlling the variable gain amplifier being arranged in front of predictive loop input terminal by the numeral output using the loop, further expands the dynamic range of digital predictive device.

In addition, the converter provides the zero offset Digital Signal Processing element of the estimated value of the offset as caused by various circuits, the direct current greatly enhanced (DC) offset behavior by being packed into.By the estimated value of this offset by number in a manner of in conjunction with the output phase of predictive filter, introduce the estimated value of the offset in the input terminal of sampler.

The present invention is mainly different from prior art described in the reference enumerated in one section of prior art at four aspects.First, sampler is arranged inside predictive loop to allow to realize predictive filter using DSP technology, therefore, reduces the complexity of entire converter, the flexibility reprogramed for the characteristic of predictive filter is increased, the dynamic range of converter and noiseproof feature are improved.Second, enable the work of predictive coding device to make predictive loop by signal down coversion in subharmonic mode, and further reduced the complexity of the Digital Logic for realizing predicted figure filter.Third controls the dynamic range that the gain level being applied in input signal makes it possible to further increase converter using the output signal of predictive loop.4th, zero offset device in fitting machine eliminates the offset as caused by the defect of circuit, significantly improves the DC offset behavior of analog-digital conversion process.

Fig. 1 is the block diagram of down coversion digitizer of the present invention.

Fig. 2 is the more detailed block diagram of sampler in Fig. 1.

Fig. 3 is the general structure chart of predictive filter in Fig. 1.

Fig. 4 illustrates the z- plan view of the typical filter stage of Fig. 3, and every level-one in the predictive filter element is realized in the form of second order filter.

Fig. 5 is the improved curve graph illustrated by the way that the order of predictive filter is increased to two dynamic ranges and detection bandwidth obtained from one.

Fig. 6 is the block diagram of automatic growth control (AGC) loop.

The preferred plan of the digital quadrature mixer of Fig. 7 explanatory diagram 1.

Fig. 8 is the block diagram of zero offset device loop.

Fig. 9 is the block diagram for illustrating specific implementation of the invention.

Figure 10 is the integrated circuit curve graph obtained for indicating dynamic range measurement result in the case where the effect of no automatic gain control loop by the exemplary embodiment of Fig. 9.

In the design of most of receiver, the signal for being received and modulating is down-converted to intermediate frequency (IF), and be filtered to it and select desired signal, removes undesired adjacent signals and the channel of induced noise and interference.In modern receiver, the IF after down coversion must further be down-converted to base band and be digitized, and then, be handled by digital demodulator.Directly to IF signal sampling and processing is obtained take after IF signal required for multiple technologies problem caused by high disposal process handling capacity pushed the demand handled baseband signal.

Advanced technology has been had already appeared on bandpass sampling recently.They propose the concept directly to IF signal sampling.These technologies are realized usually using analog circuit is transformed into numeric field for IF signal, since this trend will encounter the difficulty in several designs, to overcome these difficulties, then will lead to and implement costly.

The present invention introduces a kind of new design scheme for analog-digital converter, it can sample modulation carrier wave (IF) signal, and down-convert to base band.Down coversion digitizer included by the present invention realizes following three processes:

1. modulation IF signal is converted into digital representation (that is, digitlization).

2. modulation IF signal to be down-converted to the digital representation of baseband inphase and quadrature component.

3. a pair processed modulation IF signal amplitude carries out automatically controlling, to expand the dynamic range of digitized processing, quantizing noise is minimized.

Fig. 1 is the block diagram of down coversion digitizer of the invention, it includes following elements:

1. digital control variable gain amplifier (200), the amplifier modulates the amplitude of IF input signal (100) according to control signal adjustment caused by gain control logic (300).

2. gain control logic element (300), the output signal (410) of predictive filter is converted into control signal (310) by it, and the control signal is used to be arranged the yield value of variable gain amplifier (200).

3. analog quantity adding element (500), it is generated error signal (510) by the way that the output signal of amplifier output signal (210) the digital addition element (1200) to be combined after being converted into analog representation using digital quantity analog quantity converter (DAC) (700).

4. sampling element (800), error signal (510) is converted into digital representation (810) by it.

5. predicted figure filter (400), it utilizes the predicted value obscured (aliased) component (810) and constitute the digital representation of modulation IF input signal (100) of sampled error signal (810).

6. zero offset device element (600), the element is calculated due to operating generated deviant, and is supplied to a kind of digital addition element (1200) revise signal.

7. digital addition element (1200), the inverted signal (inverse) of offset correction signal (610) is added by the element with the output (410) of predictive filter, in order to provide DAC input signal (1210).

Digital analog converter 8. (DAC) element (700), the numeral output (1210) of digital addition element (1200) is converted to analog representation (710) by it.

9. digital quadrature mixer (900), the output (410) of predictive filter is mixed down baseband inphase (I) (910) and orthogonal (Q) (920) digital component by it.

10. being respectively same phase (I) (910) and two rate attenuation filters (1000 that orthogonal (Q) (920) baseband output signal provides, 1100), they are used to: (a) filter should not alias components；(b) sampling rate is reduced to suitable with the bandwidth of modulated signal.

Entire down coversion digital quantizer has analog quantity part, digital quantity part and mixed signal part.In the present invention, analog quantity part is minimized as far as possible, makes it possible to maximally utilise the flexibility of Digital Signal Processing.The analog quantity part of down coversion digital quantizer includes variable gain amplifier (200) and analog quantity addition node (500) in Fig. 1.Feedback DAC (700) and sampler (800) are mixed signal elements, and function is conversion of the signal from digital quantity to analog quantity to be carried out in feedback channel, and the conversion of signal from analog amount to digital quantity is carried out in feedforward path.All other element in down coversion digital quantizer is all realized using digital hardware, and carrys out work with oversampling clock rate (50).

The work of down coversion digital quantizer of the invention can carry out optimal description by the work of three loops, each circuit includes a part in mentioned-above element.Firstly, predictive loop includes adder (500), sampler (800), predictive filter (400), digital addition element (1200), and feedback DAC (700).Second, zero offset device loop includes zero offset element (600), digital addition element (1200), DAC (700), analog addition element (500) and sampler (800).Finally, automatic gain control loop includes automatic growth control logic AGC (300), variable gain amplifier (200), analog addition element (500), sampler (800) and predictive filter (400).

Down coversion digital quantizer output signal (1010 and 1110) is that the same phase (I) of modulation and the long number of orthogonal (Q) base band component indicate respectively.These output signals are generally sent to the digital demodulation part of receiver, for detecting and taking out modulation intelligence.

The basic element of down coversion digital quantizer of the invention is the characteristic of predictive loop.The loop generates the prediction (710) for input signal (100).When adder (500) subtracts the predicted value, generate predictive error signal (510).Under steady operation mode, predictive loop will be so that predictive error signal (510) be minimum.When the process is completed, the output of predictive filter (400) is the digital representation of analog-modulated input signal (100).In frequency by the modulation carrier wave after making the maximum frequency response of predictive filter be in sampler (800) sampling, obtain the smallest loop error signal.According to this principle, sampler (800) plays a key role in the work of down coversion digital quantizer.

Since the work of down coversion digital quantizer is that basis makes the smallest principle of predictive error signal at steady state, so this error signal is usually closer to zero.Due to nonideal operation, certain offset will be generated.These deviate the normal value that error signal will be made to deviate its zero point.The predetermined estimated value generated for these offsets of zero offset device loop, and these offsets are eliminated from error signal.

Analog input signal is successfully critically depend on the dynamic range of down coversion digital quantizer to the conversion of digital quantity.It works since down coversion digital quantizer is based upon the principle of the digital forecast value of feedback channel signal (410) generation input signal (100), so this predicted value is suitable for the optimum value for generating a kind of measurement, AGC amplifier (200) setting is arrived suitable yield value by the measurement.The purpose of AGC loop is that the amplitude for modulating carrier wave (100) is maintained on the level within the dynamic range of predictive loop.Sampling element (800)

Since down coversion digital quantizer of the invention is worked based on the principle sampled to the smallest predictive loop error signal, so this error signal is indicated to be sufficient with one, therefore, the sampler can be realized with 1 cheap analog-digital converter (ADC), as shown in Fig. 2, the ADC includes limiting amplifier (840) and " D " trigger (850).In general, of the invention any one special application can enough multi-byte samples devices realize.However, due to can inexpensively realize down coversion digital quantizer, so being used as the basis that most preferred embodiment illustrates to the explanation for the down coversion digital quantizer for using 1 sampler below.

Within the scope of the invention, loop error signal is converted into digital representation from analog quantity by sampling element.As such sampling processing as a result, the sampled output signal (810) includes the alias components of loop error signal (510).Prediction circuit of the invention is indicated using the minimum alias components of modulation carrier wave (100) with fa.The frequency fc of IF carrier wave (100) is modulated, the relationship between the frequency fs and alias components fa of sampling clock (50) is:

Fc=[m+n] fs (1)

With

Alias components

Fa=nfs

Here m indicates integer, and n is decimal, and $-\frac{1}{2}\≤n\≤\frac{1}{2}.$ When $n=\±\frac{1}{4}$ When, the complexity of predictive filter (400) and digital quadrature mixer (900) will be greatly reduced.

Limiting amplifier (840) generates bistable state continuous time signal (841), and " D " trigger converts the signal at clock cycle edge as digital sampled signal.

In sampler design as shown in Figure 2,1 ADC (830) is by high-gain amplifier (840) Lai Shixian, when the amplitude of error signal (510) is greater than the half of the amplitude of the least significant bit (LSB) of feedback DAC (700), the amplifier carries out clipping." D " trigger (850) samples the output of high-gain amplifier (841) in clock edge.The trigger has input threshold value, so that when the output (841) of amplifier is higher than the half of its voltage range, trigger is considered Digital Logic " 1 ", when amplifier output (841) is lower than the half of voltage range, trigger is considered Digital Logic " 0 ".

According to the gain bandwidth characteristic for the semiconductor technology for being used to realize 1 ADC, it may be necessary to add track and hold circuit before the limiting amplifier (840) of Fig. 2.When with sample frequency fs work, track and hold circuit effectively provides the alias components of lower frequency fa to limiting amplifier, and frequency fa is within the gain bandwidth range for realizing the semiconductor technology of limiting amplifier (840).The designer of 1 ADC needs to trade off analysis, so as to according to the centre frequency of IF, sample clock frequency (fs), and for realizing that the gain bandwidth characteristic of the semiconductor technology of 1 ADC determines the requirement of track and hold circuit.

Predictive filter element (400)

In the operation of the present invention, predictive filter (400) plays a key role.Error signal (510) is converted into sampling digital representation from the analog representation of its continuous time using 1 sampler (800) by predictive filter, and the predictive filter element of loop is realized using Digital Signal Processing.The predicted value of modulated medium frequency IF (100) when predictive filtering element predetermined generation next sampling period.In the present invention, by be arranged predictive filter (400) pole make its on frequency domain with through oversampler (800) sampling after the centre frequency of alias components (fa) of modulated medium frequency IF (100) it is consistent.The effective predicted value key request of modulated medium frequency IF (210) for generating next sampling period is that modulation bandwidth (W) will be slightly lower than clock rate (fs), and the clock frequency is again related with carrier frequency according to the following formula:

W < < fc=[m+n] fs (2)

Wherein m is integer, and n is decimal, and $-\frac{1}{2}\&le;n\&le;\frac{1}{2}.$ As previously mentioned, working as $n=\&PlusMinus;\frac{1}{4}$ When, the complexity of predictive filter (400) and digital quadrature mixer (900) will be greatly reduced.

Although the operation of down coversion digital quantizer of the invention is all centre frequency fc that is effective, selecting m >=2 sample clock frequency (50) that must be chosen select will to be made to be lower than IF for any integer value m.Such selection will be greatly simplified the design of down coversion digital quantizer, and the IF signal for enabling it to compare possible IF signal frequency higher frequency in other situations is digitized.This design has the advantages that following, i.e., the numerical portion of down coversion digital quantizer works at lower clock frequency fc while keeping higher IF centre frequency fc.Lower clock frequency fs (50) causes the digital hardware of down coversion digital quantizer to have lower power consumption and less expensive cost and simpler.Higher IFfc reduces the cost and complexity of the RF component before down coversion digital quantizer.Enable system designer by the way that whole cost to be minimized in the numerical value for reaching most cheap radio design, while by sample frequency selection in the numerical value for reaching most cheap digital hardware design the selection of IF centre frequency in this way.

The general structure of predictive filter element (400) is as shown in figure 3, the structure of the predictive filter element is the series connection of some filters, and the Z plane transmission function of these filters is respectively by A_k(z) it indicates, k=0 to K-1, K represent the order of predictive filter.Pass through gain factor a before the output that summation generates predictive filter_kThe output of every level-one is weighted.Filter stage as shown in Figure 3, every level-one of predictive filter are realized by second order filter, and the complex pole of second order filter is located on z-plane as shown in Figure 4.

Adjust the coefficient (b of filter₁)_kThe angle between positive real axis and pole radius will be changed.It is determined that resonance frequency (the f of filter stage₀)_k.Adjust the coefficient (b of filter₂)_kThe radial distance of pole pair relevant to z-plane origin will be changed.It will determine 3 dB bandwidth (BW of filter_3db)_k.These relationships are determined by following equations (3):

The Q value of k-th filtering stage is determined by following expression formula:

$Q_k=\&lsqb;\frac{{\mathrm{<figure-callout\; id="0"\; label="f"\; filenames="C9811529300341.png,C9811529300351.png"\; state="\{\{state\}\}">f</figure-callout>}}_0}{{\mathrm{BW}}_{3\mathrm{db}}}{\&rsqb;}_k,k=\mathrm{0,1},\&CenterDot;\&CenterDot;\&CenterDot;k-1$

$r_k=\sqrt{\frac{\sin (\mathrm{\&pi;}\&lsqb;1-\frac{1}{{2Q}_k}\&rsqb;)-1}{\cos (\mathrm{\&pi;}\&lsqb;1-\frac{1}{{2Q}_k}\&rsqb;)}}---\left(3\right)$

${\mathrm{\&theta;}}_k=2\mathrm{\&pi;}\frac{{\left(f_0\right)}_k}{f_s}$

(b₁)_k=-2r_kcos(θ_k)

(b₂)_k=r_k

The position of pole determines the frequency response of predictive filter (400).The maximum frequency response of predictive filter grade is located at the modulation IF (f after sampling₀) centre frequency on or in its vicinity.The exact position of pole is determined by the characteristic of signal of interest.

It, can be the selection of poles on the position for realizing optimum performance because being to realize predictive filter element (400) using Digital Signal Processing.Such pole location may is that for analog quantity it is impossible, because to will lead to filter unstable for the component variation caused by temperature, technique, aging etc..In addition, digitized filter can reprogram the response of filter by changing the coefficient of filter, in this way, the characteristic of predictive filter is allowed to match with input signal (100).

The major advantage that can be realized through the invention first is that, predictive filter (400) is realized by digital filter.Different from the design of analog filter, the filter will not make its performance change due to technique, temperature and aging.In addition, can reprogram to the response of predictive filter, it is made to match with modulated medium frequency IF (100).Within the scope of the invention, the following parameter of general pre- geodesic structure as shown in Figure 3 can be reprogramd:

The series of K=filter

a_kThe weighted gain of=every level-one filter

(f₀)_kThe centre frequency of=every level-one filter

(BW_3dbThe bandwidth of)=every level-one filter

It can change the frequency response of predictive loop of the invention by reprograming to these parameters.By realizing relationship described in equation (2), using the external algorithm for obtaining these setting values, according to the setting for initializing or dynamically carrying out these parameter values.

Quantizing noise is added in the digital representation of signal by the analog-digital converter in traditional broadband, Nyquist (Nyquist) bandwidth of the entire signal after the sampling from 0Hz to fs/2 of the cover signal.On the other hand, digital forecast loop of the invention has the advantages that for quantizing noise to be limited in intrinsic in narrower bandwidth.The bandwidth of this noise is more much narrower than Nyquist (Nyquist) bandwidth.Reduction of this digital processing after predictive loop in terms of broadband noise alleviates the design limitation to Digital Signal Processing element thereafter.In the early stages during dynamic frequency response adjustment, the characteristic of narrow-band noise right remain.

The feature of dynamic frequency response adjustment of the invention is all useful for many occasions.For example, calculation method described in equation (3) can be used to dynamically adjust the coefficient (b1) of predictive filter by the instantaneous carrier frequency for tracking modulation IF (100) using external algorithm_k(b2)_k, so as to as due to Doppler effect, frequency shift caused by transmitter receiver oscillator drift etc. makes the centre frequency (f of predictive filter grade₀)_kTrack carrier frequency.This allow down coversion digital quantizer keep modulated medium frequency IF (100) digital representation high signal-to-quantizing noise ratio.

Another application of dynamic frequency response adjustment feature of the invention is, it can be used to reduce the distortion as caused by the interference signal of cellular telephone system due under the occasion of multi-channel receiver.In the presence of interference, external algorithm can adjust the parameter of predictive filter, make it that interference signal be better anticipated, and delete these signals by subsequent digital filtering in this way, not need to carry out shaping to main signal.By comparing the signal power of the adjacent output at different levels of the predictive filter structure (400), this external algorithm can be derived that the measurement of the interference of adjacent channel.When this compares expression adjacent channel, there are the coefficient (b that the algorithm that when strong jamming, then can use equation (3) dynamically adjusts predictive filter₁)_k(b₂)_k, to increase the effective bandwidth (BW of predictive filter_3db)_k.The effective bandwidth for increasing predictive filter prevents the adverse effect that may cause by adjacent channel strong jamming, such as slope overload and intermodulation effect.Therefore, utilize the ability of the dynamic frequency response adjustment of predicted figure filter, down coversion digital quantity converter of the invention it is predetermined can the abnormal growth to adjacent channel interference dynamically react, while when interference keeps higher dynamic range when within specified level.

Another advantage of digital predictive filter (400) is word length extension function.In other words, the input sample (810) of predictive filter can be made of 1 quantized signal, and the output (410) of predictive filter can be multidigit.Sampler can be realized by 1 sampler, therefore the present invention reduces manufacturing cost by simplifying sampling element, and does not reduce its performance.In addition, the word length extension function of predictive filter (400) increases the accuracy of digital representation (410).

The dynamic range of signal is determined by the digit of digital representation in digital information processing system.It is every to increase by 1 dynamic range that provide about 6 decibels.Predictive filter (400) generates word length and extends function, leads to the high dynamic range of signal digital representation (410).Determined by the digit of the feedback signal (410) for being input to (700) DAC from the predictive filter to dynamic range portion of the invention.The determination of the digit is according to following factor: (1) feeding back the implementation cost of DAC (700)；(2) requirement of dynamic range；And the complexity of (3) predictive filter (400).

Fig. 5 illustrates the improvement of obtained dynamic range and detection bandwidth by the way that the order of predictive filter is increased to 2 from 1.This improvement is obtained by the shaping of the power spectral density to quantization error signal (810).These figures show the power spectral densities that when additive white Gaussian noise (AWGN) that the input when predictive loop includes the least significant bit LSB (Δ) that its root-mean-square valve (rms) is equal to feedback DAC (700), sampler is exported.The power spectrum chart is shown: lower for the broader frequency range, the level of the quantizing noise that sample bandwidth when using second-order prediction filter.The predictive filter of higher order can make loop eliminate more noises from main bandwidth, therefore a trench is generated on quantization error signal frequency spectrum.Second-order prediction filter will generate a bigger trench.The size and shape of trench determines that loop reduces the degree of sampled signal quantizing noise near centre frequency fa.It is a kind of instruction, indicates predictive filter is how to estimate signal on next sampling period.

Predictive filter element (400) completes two functions in loop.The estimated value of first its next sampling period input signal (100) of generation.Secondly, predictive filter element (400) filters quantizing noise, while increasing the word length of signal (410) digital representation.The noise bandwidth for reducing output signal is exactly second function of predictive filter.Traditional analog-digital converter injects quantizing noise (σ_e ²), power are as follows:

${\mathrm{\&sigma;}}_e^2=\frac{{\mathrm{\&Delta;}}^2}{12}---\left(4\right)$

It will be sampled and be exported in the thermal noise of the input terminal of traditional ADC.The signal (810) that down coversion digital quantizer passes through after making sampling generates its output signal by the predictive filter (400), and predictive filter (400) is a kind of narrow band filter for being suitable for main signal.Therefore, the noise component(s) outside the frequency band containing desired signal will greatly be decayed in predictive filter.(out-of-band additional filterings are provided by rate attenuation filter (1000,1100)).Since predictive filter increases the word length of the signal after sampling, so reducing the amplitude of signal least significant bit, and the power of quantizing noise is reduced (from equation 4).In addition, the pole by accurately selecting predictive filter, can further reduce entire predictive loop heat input noise and modulated signal bandwidth to the quantizing noise outside near field.The pole of this noise shaping characteristic requirements predictive filter is located at the inside of z-plane unit circle.

Analog-digital converter generally exchanges detection bandwidth for dynamic range.The dynamic range of down coversion digital quantizer of the invention is determined that the width of trench is equal to signal bandwidth on the point by the depth of trench on certain point.The order of increase predictive filter (400) will deepen and widen simultaneously the trench of the frequency spectrum of noise signals of quantization.Therefore, the performance of second-order prediction filter is better than single order predictive filter significantly.Deeper trench provided by second-order prediction filter can be realized bigger dynamic range.Trench is wider, then the bandwidth for the signal of being indicated is wider, and precision is higher.

Since the output (410) of predictive filter of the invention has high dynamic range, so DAC (700) must support identical dynamic range.Quick and wide dynamic range DAC implements much more cost effective compared with traditional analog-digital converter of same size and identical speed.In fact, the present invention using simple and cheap high dynamic range DACs as high dynamic range, wide detection bandwidth analog-digital converter in element.

In view of the chip size of hardware, for the scheme compared with other over-samplings, had the advantages that using digital forecast filter (400) and multidigit DAC (700) multiple.For example, typical oversampling analog-to-digital converter realizes the add-minus function of filtering and signal using conversion capacitor.These schemes need to realize conversion capacitor using sizable chip area.On the contrary, realizing DAC (700) of the invention only needs the sub-fraction of chip area used in comparable over-sampled converter conversion capacitance structure.In addition, digital pre- geodesic structure can be realized with the transistor of minimum feature size, to realize that the Digital Logical Circuits of predictive filter (400) only accounts for the chip area of very little.

Frequency (fa) by selecting sample modulation carrier wave, which is equal to fs/4, can further reduce cost of the invention.Centre frequency (the f for selecting predictive filter at different levels₀)_kEqual to fa=fs/4, by generating small yield value in predictive filter, the circuit can be greatly simplified.It is illustrated in this circuit embodiments that will be given below.

Digital analog converter (DAC) (700)

The summing signal (1210) of the digital representation of predictive filter output (410) and zero migration revise signal (610) are converted into analog representation (710) by the element.The selection of the digit of DAC (700) will be enough to ensure that quantizing noise of the quantizing noise as caused by DAC (700) lower than the predictive filter (400) before the DAC and prediction noise.

Digital addition element (1200)

Zero migration revise signal is added by digital addition element with the output (410) of predictive filter, provides the input signal (1210) of DAC.

Analog addition element (500)

The analog representation (710) of prediction signal is added by analog addition element with the IF signal (210) for being amplified, modulating, and is generated error signal (510).Total delay around predictive loop is maintained at two clock cycle.When combining with the selection of fa=fs/4, the effect of this delay will lead to feedback signal (710) sign-inverted.This makes it possible to by the way that signal (710) is simply realized negative-feedback with input signal (210) the phase Calais of analog addition node (500).

Automatic growth control logic circuit (300)

The general requirement of receiver dynamic range is more much bigger by analog-digital converter dynamic range obtained than individually.Two factors to work determine the dynamic range of received signals.First, the fast variation amount containing modulation intelligence.This component of dynamic range is referred to as instantaneous dynamic range.Second, the slow component as caused by external factor, the component is not loaded with useful information relevant to modulation intelligence.Receiver must have enough dynamic ranges to support the two components.The dynamic range as provided by predictive loop of the present invention can make a reservation for the entire dynamic range equal to or more than received signals.It however, can be realized more cost effective scheme using the following fact, i.e., include the dynamic range portion of received signal slow component, component useful information not relevant to modulation.The component can be removed using the automatic gain control loop (AGC) before predictive loop.Since the output (410) of predictive filter is the digital forecast value to the modulation carrier wave (100) for reaching down coversion digitizer input terminal, so this signal is the ideal signal for controlling AGC.

The purpose of AGC loop is that the amplitude for modulating IF (100) is maintained within predictive loop dynamic range.The block diagram of AGC loop is as shown in Figure 6.AGC loop includes AGC control logic circuit (300), variable gain amplifier (200), analog addition element (500), sampling element (800) and predictive filter (400).AGC control logic circuit (300) includes power detector (320), addition node (330), AGC loop booster element (340), AGC loop filter (350) and gain control encoder (360).Power detector (320) provides the estimation of the power of predictive filter output (410).AGC loop works to any monotonic function for the signal level for including power or amplitude.

Compared with external AGC provided by the output (321) of power detector and set value calculation device (370), generate AGC gain adjustment signal (331).AGC set value calculation device (370) adjusts the level (210) of AGC output.The AGC setting value of the gain of AGC control logic circuit (300) setting AGC (200), the signal level for making amplifier output (210) and AGC set value calculation device (370) matches.The input of AGC control logic circuit (300) is the output of predictive filter output (410) and AGC set value calculation device (370).AGC loop booster element (340) amplifies AGC gain adjustment signal (331).The gain of AGC loop booster element (340) determines loop settling time.

AGC loop filter (350) is filtered amplified gain adjustment signal.It reacts since AGC loop is predetermined to the signal component changed slowly in Dynamic Signal, so AGC loop filter (350) is by averagely being reduced the rate that power detector exports (320) to the output valve.Loop filter output (341) is converted into format appropriate, to control variable gain amplifier (200) by encoder (310).Variable gain amplifier (200)

Variable gain amplifier (200) receives on signal (100) as the variation of AGC control logic output (310) is added in gain.Variable gain amplifier (200) has enough controllable gains to remove the slowly varying component received in signal (100) dynamic range completely.

Zero offset device (600)

Due to the offset of inside and outside generation, the reduced performance of all analog-digital converters can be made, digital output signal is caused to deviate ideal value.It will lead to these offsets by technique, temperature and aging, and by the caused component variation of obscuring that undesirable simulation couples the sampling clock harmonic wave being added in input signal.Detection is carried out to these offsets and deletion is difficult.

The advantages of down coversion digital quantizer of the invention is that have integrated zero offset element (600), it automatically and dynamically can detect and delete the offset that may be unfavorable for analog-to-digital conversion.Traditional analog-digital converter can not dynamically delete the influence of offset error.General analog-digital converter needs manual correction or needs the correcting mode of converters offline during correction.These correction forms are non-dynamic, and are easy to be influenced by temperature and aging, and eventually lead to the reduction of performance due to deviating.

The zero offset element (600) of down coversion digital quantizer determines the compensation during operation, therefore does not need manually adjusting for offline mode.In analog-digital conversion process, zero offset device is continuously estimated the size of offset and is removed.

The block diagram of zero offset device loop is as shown in Figure 8.Zero offset device loop includes zero offset element (600), digital addition element (1200), DAC (700), analog quantity adding element (500) and sampler (800).

Because the operation of predictive loop is so that error signal (510) is zero, in case of no offset, the output average value of sampler (800) should be zero.If there is offset, the average value of sampler output is proportional to the offset.Sampler is exported and is equalized by zero offset device (600), to determine offset correction signal (610).Zero offset loop filter (620) calculates the average value of sampler output (800).Then the deviant of estimation is amplified using digital amplifier (630), and is added with the output of predictive filter and generates feedback signal (1210).

Digital quadrature mixer (DQM) (900)

The function of DQM (900) is that the output for the predictive filter (400) that will have a centre frequency fa down-converts to baseband inphase (I) and orthogonal (Q) component.Conventionally, the signal that it is fa multiplied by centre frequency with sin (fa) and cos (fa) that this down coversion to base band, which is needed, to generate (I) and (Q) component respectively.In the present invention, since fa is selected to be equal to fs/4, so the value in the sin (fa) and cos (fa) of the period calculating of clock fs is simply (0,1,0, -1) in a cycle of fa.In this way, the present invention selects fa=fs/4 to simplify DQM element (900) significantly.As shown in fig. 7, DQM is a kind of simple circuit, the output sample of predictive filter is alternately transmitted to same phase (I) (910) or orthogonal (Q) (920) output end by it.Then output end I and output end Q by alternately reverse phase, to generate last same phase (I) and orthogonal (Q) output sample.

Rate attenuation filter (1000,1100)

Two kinds of functions are completed in rate attenuation filter (1000) and (1100): same to phase (I) and orthogonal (Q) component are filtered and are sampled.Rate attenuation filter is predetermined to eliminate the frequency multiplication item (2*fa) as caused by DQM (900).In addition, rate attenuation filter filters the input signal, to prevent from obscuring caused by being reduced as sampling rate.The filtering of rate attenuation filter is more much bigger than preventing from obscuring required filtering.It designs these digital filters and is to pass through main signal damply, and the unwanted signal other than main signal frequency band is attenuated.This decaying makes down coversion digital quantizer generate the sampled signal for being lower than input signal noise band.

Realize that sampling rate decaying is the processing speed in order to reduce digital signal.The circuit of each rate attenuation filter (1000 and 1100) is identical.Since they are all digital, so the same phase (I) (1010) of the output signal of down coversion digital quantizer and orthogonal (Q) (1110) component will not be lost due to gain and phase imbalance with analog circuit.

Embodiment

Implement and verify down coversion digital quantizer of the invention in the form of a part of radio receiver.Semiconductor technology for this design is CMOS, 0.6 micron, 2-poly, 3-metal.Entire circuit combines on mixed signal CMOS integrated circuit with other functions, and is proved to meet the design requirement of radio receiver work.The details of the circuit arrangement is as shown in Figure 9.

In implementation example as shown in Figure 9, the centre frequency of modulated medium frequency IF is fc=82.8MHz, and two edge-band widths are 30kHz.For this special design, sampling rate (fs) is selected as 14.4MHz.This leads to the spectrum inversion fa on 3.6MHz.It corresponds to the parameter in following equations 1.

$\mathrm{fc}=82.8\mathrm{Mhz}=\&lsqb;m+n\&rsqb;\mathrm{fc}=\&lsqb;6-\frac{1}{4}\&rsqb;*14.4\mathrm{Mhz}$

$\mathrm{fa}=-3.6\mathrm{Mhz}=-\frac{1}{4}*14.4\mathrm{Mhz}$

Negative sign indicates spectrum inversion.

In gain bandwidth characteristic, the frequency of IF and when being designed comprehensive analysis of sample clock frequency to selected semiconductor technology, track and hold circuit needed for determining sampler.As shown in figure 9, sampler (2800) be by track and hold circuit, be followed by limiter and ' D ' trigger in the form of realize.Using track and hold circuit is because limiter does not have enough gain bandwidths that limiter is made to establish bistable state level on next sampling period on fc=82.8MHz.Track and hold circuit generates the aliased frequency that frequency is fa, and the aliased frequency can be activated in bistable state value by limiter, and be converted into number format by ' D ' trigger.

The coefficient of predictive filter structure as shown in Figure 9 are as follows:

a₁=a₂=1

(b₁)₁=(b₁)₂=0

(b₂)₁=(b₂)₂=1

In this scheme, the delay that the analog representation of (2710) is exported from error signal (2510) to predictive filter around predictive loop is two clock cycle.As a result, DAC output (2710) is added by adder (2500) with modulation carrier wave (2100), rather than subtract each other.

According to the analysis for dynamic range needed for entire down coversion digital quantizer, DAC (2700) is designed to 9 DAC.It is 250 millivolts that 9 DAC (2700), which have maximum peak-peak output voltage,.DAC (700) has sufficiently small settling time, to guarantee that error signal (2510) is established in the exact transition time of an ADC (2800).

The form of the output (2610) of zero offset element numerically is added with the output of predictive filter.Then DAC is exported and is added with the IF (2210) for being modeled amplification, modulation.The comprehensive output of predictive filter and zero offset device is converted into analog representation using 9 DAC.By the way that zero-signal to be added with the analog representation (2710) of prediction signal with the IF (2210) for being amplified, modulating, the adding element generates error signal (2510).

AGC control logic (2300) predetermined control casacade multi-amplifier (2200).The maximum value for the overall gain realized by the casacade multi-amplifier of variable gain is 71 decibels, and minimum value is -1 decibel.Every level-one of casacade multi-amplifier is all numerically controlled, and there are two specified yield values for tool.The nominal gain value of every first stage amplifier is selected by 1 in digital control logic circuit output (2310).The gain stage of variable gain amplifier is controlled according to lower relation of plane:

Gain stage type

Number ' 1 '

Number ' 0 '

It is conventional	7.0 decibel	- 3.0 decibels
			It is intermediate	4.0 decibel	0 decibel
Fine 3	0 decibel	- 2.0 decibels
			Fine
2	0 decibel	- 1.0 decibels
			Fine
1	0 decibel	- 0.5 decibel
			Fine
0	0 decibel	- 0.25 decibel

The realization of DQM is as shown in Figure 8.Rate attenuation filter is realized in the form of three comb filter are cascade.The output of rate attenuation is selected to 160ksps.After rate attenuation, it is 10 that each sampled value, which is truncated,.

The measurement for the dynamic range realized by the integrated circuit of implementation example shown in Fig. 9 is as shown in Figure 10, the not influence of AGC loop here.As shown in the figure, down coversion digital quantizer provides the dynamic range greater than 52 decibels.This is equivalent to double 8 base band analog-digital converters while carrying out the dynamic range that the down coversion with noise attentuation function from IF to base band can be provided.This dynamic range expansion has been more than 124 decibels by the design of AGC loop.

Although having disclosed and describing highly preferred embodiment of the present invention, however, it should be apparent that those skilled in the art can carry out various changes to the present invention in form and content, this is also without departing from the scope of the invention without departing from spirit of the invention.

Claims (29)

1. a kind of down coversion digital quantizer includes:

The variable gain amplifier coupled with modulation carrier wave, the latter includes the automatic gain control loop for controlling the variable-gain amplifier gain；

With the double sampling predictive loop of the output coupling of the variable gain amplifier；

The digital quadrature mixer coupled with the sampling predictive loop；And

With the rate attenuation filter of each output coupling of the digital quadrature mixer.

2. down coversion digital quantizer according to claim 1, it is characterised in that: the double sampling predictive loop includes the sampler in the re prediction loop.

3. down coversion digital quantizer according to claim 2, it is characterized by: the double sampling predictive loop includes the predictive filter with the sampler output coupling, the output of the predictive filter is coupled with digital analog converter, the output of the digital analog converter, input of the result as the sampler are subtracted from the output of the variable gain amplifier.

4. down coversion digital quantizer according to claim 3, it is characterised in that: the automatic gain control loop provides automatic gaining controling signal using the output of the predictive filter for the variable gain amplifier.

5. down coversion digital quantizer according to claim 3, it is characterised in that: the output of the predictive filter is the numeric word more than the digit of output of its digit than the sampler.

6. down coversion digital quantizer according to claim 5, it is characterised in that: the sampler is 1 sampler.

7. down coversion digital quantizer according to claim 3, it is characterised in that further include zero offset device, the zero offset device responds the output of the sampler and offset correction signal is coupled to the input terminal of the sampler.

8. down coversion digital quantizer according to claim 7, it is characterized by: the zero offset device responds the offset of the output of the sampler and provides numeral output, and the output that the zero offset device is exported with the predictive filter is combined before being coupled to digital analog converter, the input digit of the digital analog converter is enough to ensure that quantizing noise of the quantizing noise introduced by digital analog converter lower than the predictive filter and predicts noise.

9. down coversion digital quantizer according to claim 3, it is characterised in that: the total delay around the predictive loop is two sampling clock cycles, and sampling rate is 4 times of the minimum alias components frequency of the modulation carrier wave.

10. down coversion digital quantizer according to claim 9, it is characterized by: by alternately by the signal be transported to each channel and alternately be transported to each channel the signal it is reversed, the digital quadrature mixer is by it with the input signal of sampling rate input multiplied by sequence 0,1,0, -1 and 1,0, -1,0.

11. down coversion digital quantizer according to claim 10, it is characterised in that: the predetermined frequency multiplication item for eliminating the minimum aliasing signal generated in the digital quadrature mixer of the rate attenuation filter.

12. down coversion digital quantizer according to claim 3, it is characterised in that: the sampler is 1 sampler.

13. down coversion digital quantizer according to claim 12, it is characterised in that: 1 sampler includes limiter and trigger.

14. down coversion digital quantizer according to claim 12, it is characterised in that: the working frequency of the sampler is fs, centre frequency fc of the frequency fs lower than modulation carrier wave.

15. down coversion digital quantizer according to claim 12, it is characterised in that: the working frequency of the sampler is to modulate the centre frequency fc of carrier wave.

16. down coversion digital quantizer according to claim 12, it is characterised in that: the working frequency of the sampler is 4 times of the centre frequency of modulation carrier wave.

17. down coversion digital quantizer according to claim 3, it is characterised in that: the working frequency of the sampler is fs, centre frequency fc of the frequency fs lower than modulation carrier wave.

18. a kind of down coversion and method for digitizing, it is characterised in that the following steps are included:

Sampler, predictive filter, digital analog converter and adding element are provided, the sampler samples the analog quantity of input, and provide the Digital output for responding the input, the predictive filter receives the Digital output of the sampler, the output of the predictive filter is converted into analog quantity by digital analog converter, and carries out negative-feedback by analog addition element；

Carrier wave will be modulated and be coupled to the analog addition element that its centre frequency is fc；

The sampler works according to the sampler clock frequency lower than frequency fc.

19. down coversion according to claim 18 and digitizing solution, it is characterised in that: the output of the predictive filter be its digit than sampler output digit more than multi-bit word.

20. down coversion according to claim 19 and digitizing solution, it is characterised in that: the sampler is 1 sampler.

21. down coversion according to claim 18 and digitizing solution, it is characterised in that: the predictive filter uses digital processing technology.

22. method according to claim 21, it is characterised in that: the predictive filter be it is programmable, allow to and the modulation carrier frequency of carrier wave, the sample frequency of sampler and modulate the bandwidth of carrier wave and match.

23. method according to claim 21, it is characterised in that: the predictive filter be in the initial state it is programmable, allow to and the modulation carrier frequency of carrier wave, the sample frequency of sampler and modulate the bandwidth of carrier wave and match.

24. method according to claim 21, it is characterised in that: the predictive filter be it is programmable, so that it is matched with the modulation carrier wave for being supplied to adding element.

25. method according to claim 21, it is characterised in that: the predictive filter can be reprogramed dynamically, and the characteristic of itself and the variation for the modulation carrier wave for being supplied to adding element is made to match.

26. method according to claim 21, it is characterised in that: the series of the filter of the predictive filter, the weighted gain of every level-one, the centre frequency of each filter and each filter stage bandwidth be programmable.

27. method according to claim 26, it is characterised in that: the predictive filter be it is programmable, can respond as Doppler effect, transmitter receiver oscillator drift and it is described modulation carrier characteristics variation caused by carrier frequency variation.

28. method according to claim 21, it is characterised in that: the series of the predictive filter is programmable.

29. method according to claim 21, it is characterized by: described the step of modulation carrier wave is coupled to analog addition element, includes the steps that required modulation carrier wave and at least one neighbouring modulation carrier wave being coupled to analog addition node, and the pole of the predictive filter at different levels be it is programmable, so as to consistent with modulation channels and the adjacent modulation frequency of carrier wave.

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