CN118646434A

CN118646434A - Compact radio frequency receiving and transmitting change-over switch based on CMOS

Info

Publication number: CN118646434A
Application number: CN202410798365.7A
Authority: CN
Inventors: 张然; 隋芳媛
Original assignee: China National Aero Technology Import and Export Corp CATIC; CETC 10 Research Institute
Current assignee: China National Aero Technology Import and Export Corp CATIC; CETC 10 Research Institute
Priority date: 2024-06-20
Filing date: 2024-06-20
Publication date: 2024-09-13

Abstract

The invention discloses a compact radio frequency receiving and transmitting change-over switch based on CMOS, which comprises: a voltage source V1 and a radio frequency receiving and transmitting switching circuit; the radio frequency receiving and transmitting switching circuit comprises: the antenna port pin1, the transmitting channel port pin2 and the receiving channel port pin3 are provided with a first n-order lumped inductance-capacitance equivalent network between the antenna port pin1 and the transmitting channel port pin2, and a switch formed by an NMOS tube NM1 is arranged at the transmitting channel port pin2 and connected to GND in parallel; a second n-order lumped inductance-capacitance equivalent network is arranged between the antenna port pin1 and the receiving channel port pin3, and a switch formed by a PMOS tube PM1 is arranged at the receiving channel port pin3 and connected to GND in parallel; and the ground level of the radio frequency receiving and transmitting switching circuit is GND, and the power supply voltage is the power supply end VDD. The invention reduces the chip area of the switch, reduces the insertion loss introduced when the radio frequency signal passes through the receiving and transmitting change-over switch, and improves the linearity performance of the switch in the transmitting mode.

Description

Compact radio frequency receiving and transmitting change-over switch based on CMOS

Technical Field

The invention belongs to the field of CMOS radio frequency integrated circuit design, and particularly relates to a compact radio frequency receiving and transmitting change-over switch based on CMOS.

Background

For a time division duplex radio frequency communication system, a receiving and transmitting change-over switch is a key device for realizing the switching of receiving and transmitting functions of the radio frequency system. As shown in fig. 1, the transceiver switch is a three-port device, and is composed of a transmitting branch switch and a receiving branch switch, where pin1 is an antenna port, pin2 is a transmitting path port, and pin3 is a receiving path port. In normal operation, one of the transmitting branch switch and the receiving branch switch is in an on state, and the other switch is in an off state. When the radio frequency communication system works in a transmitting mode, the transmitting branch switch is turned on, and the receiving branch switch is turned off, so that signals of the transmitting channel can be transmitted to an antenna end through the turned-on transmitting branch switch, and meanwhile, the turned-off receiving branch can prevent the signals from entering the receiving channel. When the radio frequency communication system works in a receiving mode, the receiving branch switch is turned on, and the transmitting branch switch is turned off, so that signals received by the antenna can be transmitted to the receiving channel through the turned-on receiving branch switch, and meanwhile, the turned-off transmitting branch can prevent the signals from entering the transmitting channel.

In order to improve energy efficiency and reduce interference, a communication system generally needs to use a low-loss and high-isolation transceiver switch. In the following analysis, the port impedances of pin1, pin2, pin3 were all defaulted to the standard 50 ohms. Specifically, in the reception mode: since the receiving path side is more important for low noise and suppression performance for the transmit leakage signal, it is required to achieve as low insertion loss as possible between pin1 and pin3, and as high isolation as possible between pin1 and pin2, and good port standing wave performance is required for pin1 and pin 3. In the transmit mode: since the high linearity and high output power are more important on the transmit path side, this requires as high linearity and low insertion loss as possible between pin1 and pin2, and good port standing wave performance for pin1 and pin 2.

The radio frequency receiving and transmitting change-over switch designed by adopting the low-cost CMOS process can improve the system integration level, reduce the volume of a communication system and reduce the production cost. Based on the CMOS process, there is a transceiver switch adopting a transmission line-parallel switch type structure. As shown in fig. 2, pin1 and pin2 are separated by a 1/4 lambda transmission line T1, the characteristic impedance of the transmission line T1 is 50 ohms, a switch formed by an NMOS tube NM1 is added at pin2 and connected in parallel to GND, the drain electrode of NM1 is connected to pin2, the source electrode of NM1 is connected to ground, and the gate electrode of NM1 is controlled by the level of node a; the pin1 and the pin3 are separated by a 1/4 lambda transmission line T2, the characteristic impedance of the transmission line T2 is 50 ohms, a switch formed by an NMOS tube NM2 is added at the pin3 and connected to GND in parallel, the drain electrode of the NM2 is connected with the pin3, the source electrode of the NM2 is connected with the ground, and the grid electrode of the NM2 is controlled by the level of a node B; ground level=gnd of the circuit, supply voltage=vdd. In the following analysis, the port impedances of pin1, pin2, pin3 were all defaulted to the standard 50 ohms. In the receive mode: the level=vdd of the node a, NM1 works in a deep linear region, the switch formed by the node a is in an on state, the on resistance of the NM1 is close to 0 ohm, and the impedance seen from the pin1 to the pin2 is enabled to be towards infinity through the impedance transformation function of the 1/4 lambda transmission line T1, so that the radio frequency signal is prevented from flowing into the transmission line T1 from the pin 1; level=gnd of node B, NM2 operating in the cut-off region, the switch it constitutes being in the off state; the radio frequency signal may be transmitted from pin1 to pin3 via transmission line T2. In the transmit mode: the level=vdd of the node B, NM2 works in the deep linear region, the switch formed by the node B is in an on state, the on resistance of the NM2 is close to 0 ohm, and then the impedance seen from pin1 to pin3 is theoretically towards infinity through the impedance transformation function of the 1/4 lambda transmission line T2, so that the radio frequency signal is prevented from flowing into the transmission line T2 from pin 1; level=gnd of node a, NM1 is operating in the cut-off region, the switch it constitutes being in the off state; the radio frequency signal may be transmitted from pin2 to pin1 via transmission line T1.

The problems with the above solution are:

1) The 1/4 lambda transmission line based on the CMOS technology is long, resulting in high loss and large occupied area.

2) In the emission mode, the NMOS tube NM1 should always work in the cut-off region, but due to the parasitic capacitance between the drain electrode of NM1 and the grid electrode of NM1, when the emission signal is increased to a certain extent, the transient voltage generated by the leakage of the emission signal to the grid electrode can cause the NM1 working region to be converted into a linear region, so that the on-resistance of NM1 is converted from high resistance to low resistance; with further increase of the transmit signal, the transmit signal at pin2 will have an increasing proportion of branches through NM1 to GND, resulting in a phenomenon of gain compression of the transmit signal, which limits the high linearity performance of the transmit path.

3) In the transmitting mode, although the threshold of the gate voltage capable of converting the NM1 operating region into the linear region can be improved by adding a static level switching port to the drain and the source of the NM1, so as to relieve the gain compression phenomenon occurring when the transmitting signal is increased, and improve the linearity performance of the switch in the transmitting mode, in order to ensure the normal operation of the NM2, it is also necessary to add a blocking capacitor in series in the signal path in the transmitting branch, which brings additional loss and increases the chip area.

Disclosure of Invention

The invention aims at: in order to overcome the problems in the prior art, the invention discloses a compact radio frequency receiving and transmitting change-over switch based on CMOS. The chip area of the switch is reduced, the insertion loss of the radio frequency signal when passing through the receiving and transmitting change-over switch is reduced, and the linearity performance of the switch in the transmitting mode is improved.

The aim of the invention is achieved by the following technical scheme:

a CMOS-based compact radio frequency transreceiving switcher, the compact radio frequency transreceiving switcher comprising: a voltage source V1 and a radio frequency receiving and transmitting switching circuit;

the negative electrode of the voltage source V1 is connected with the ground end GND, and the positive electrode of the voltage source V1 is connected with the power end VDD;

The radio frequency receiving and transmitting switching circuit comprises: an antenna port pin1, a transmit path port pin2, a receive path port pin3,

A first n-order lumped inductance-capacitance equivalent network is arranged between the antenna port pin1 and the transmitting channel port pin2, a switch formed by an NMOS tube NM1 is arranged at the transmitting channel port pin2 and connected to GND in parallel through a capacitor C1, wherein the drain electrode of the NMOS tube NM1 is connected with the transmitting channel port pin2, the source electrode of the NMOS tube NM1 is connected with the ground through the capacitor C1, and the grid electrode of the NMOS tube NM1 is controlled by the level of a node A;

A second n-order lumped inductance-capacitance equivalent network is arranged between the antenna port pin1 and the receiving channel port pin3, a switch formed by a PMOS tube PM1 is arranged at the receiving channel port pin3 and connected to GND in parallel through a capacitor C6, the drain electrode of the PMOS tube PM1 is connected with the receiving channel port pin3, the drain electrode of the PMOS tube PM1 is connected with the ground through the capacitor C6, and the grid electrode of the PMOS tube PM1 is controlled by the level of a node B;

and the ground level of the radio frequency receiving and transmitting switching circuit is GND, and the power supply voltage is the power supply end VDD.

According to a preferred embodiment, the source of the NMOS transistor NM1 and the drain of the PMOS transistor PM1 are respectively provided with a static level switching port D and a static level switching port E.

According to a preferred embodiment, the first n-order lumped inductance-capacitance equivalent network and the second n-order lumped inductance-capacitance equivalent network are 3-order lumped inductance-capacitance equivalent networks. Wherein, the unit inductance value of the 3-order lumped inductance-capacitance equivalent network is L ₀, and the unit capacitance value is C ₀.

According to a preferred embodiment, the antenna port pin1 is connected to the center tap of the inductor L2 and one end of the capacitor Cp2, and the inductance value of the inductor L2 is 2L ₀;

One end of the capacitor Cp2 is connected with GND, the other end of the capacitor Cp2 is connected with the central tap end of the inductor L2 and the antenna port pin1, the capacitance value of the capacitor Cp2 is parasitic capacitance from a port pad of the antenna port pin1 to GND, and the capacitor value is a unit capacitance value C ₀.

According to a preferred embodiment, the first n-order lumped inductance-capacitance equivalent network comprises a capacitance Cp1, a capacitance C2, a capacitance C3 and an inductance L1, and a capacitance Cp2 and an inductance L2 which are common to the second n-order lumped inductance-capacitance equivalent network;

one end of the capacitor C3 is connected with GND, and the other end of the capacitor C is connected with the inductor L2 and the inductor L1;

One end of the capacitor C2 is connected with GND, and the other end of the capacitor C is connected with the central tap end of the inductor L1;

one end of the capacitor Cp1 is connected with GND, and the other end is connected with the drain electrode of the NMOS tube NM1 and the transmitting channel port pin 2.

According to a preferred embodiment, the capacitance value of the capacitor Cp1 is the sum of the parasitic capacitance from the port pad of the transmit path port pin2 to GND and the parasitic capacitance from the drain of the NMOS transistor NM1 to GND, and is C ₀/2;

The inductance value of the inductor L1 is 2L ₀; the capacitance value of the capacitor C2 is a unit capacitance value C ₀/2; the capacitance value of the capacitor C3 is C ₀/2.

According to a preferred embodiment, the second n-order lumped inductance-capacitance equivalent network comprises a capacitance Cp3, a capacitance C4, a capacitance C5 and an inductance L3, and a capacitance Cp2 and an inductance L2 which are common to the first n-order lumped inductance-capacitance equivalent network;

one end of the capacitor C4 is connected with GND, and the other end of the capacitor C is connected with the inductor L2 and the inductor L3;

one end of the capacitor C5 is connected with GND, and the other end of the capacitor C is connected with the central tap end of the inductor L3;

One end of the capacitor Cp3 is connected with GND, and the other end is connected with the source electrode of the PMOS tube PM1 and the receiving channel port pin 3.

According to a preferred embodiment, the capacitance value of the capacitor Cp3 is the sum of the parasitic capacitance from the port pad of the receiving channel port pin3 to GND and the parasitic capacitance from the source of the PMOS tube PM1 to GND, and is C ₀/2;

The inductance value of the inductor L3 is 2L ₀; the capacitance value of the capacitor C4 is C ₀/2; the capacitance value of the capacitor C5 is C ₀/2.

According to a preferred embodiment, the radio frequency transceiver switching circuit further comprises: capacitor C1, capacitor C6, resistor R1, resistor R2, resistor R3;

One end of the capacitor C1 is connected with GND, and the other end of the capacitor C is connected with the source electrode and R2 of the NMOS tube NM1 and used for blocking a direct current path between the source electrode of the NMOS tube NM1 and the GND and providing an alternating current path for radio frequency signals between the source electrode of the NMOS tube NM1 and the GND;

One end of the capacitor C6 is connected with the GND, and the other end of the capacitor C is connected with the drain electrode and the R3 of the PMOS tube PM1 and used for blocking a direct current path between the drain electrode of the PMOS tube PM1 and the GND and providing an alternating current path for radio frequency signals between the drain electrode of the PMOS tube PM1 and the GND;

one end of the resistor R1 is connected with the inductor L1, the inductor L2 and the capacitor C3, and the other end of the resistor R1 is connected with the node C and is used for preventing the radio frequency signal from being shunted to the point C, and simultaneously, a direct current level is provided for the drain electrode of the NMOS tube NM1 and the source electrode of the PMOS tube PM1 through the point C;

one end of the resistor R2 is connected with the node D, and the other end of the resistor R2 is connected with the source electrode of the NMOS tube NM1 and the blocking capacitor C1, and is used for preventing a radio frequency signal from being shunted from the drain electrode of the NMOS tube NM1 to a point D, and simultaneously providing a direct current level for the source electrode of the NMOS tube NM1 through the point D;

One end of the resistor R3 is connected with the node E, and the other end of the resistor R3 is connected with the drain electrode of the PMOS tube PM1 and the blocking capacitor C6 and is used for preventing a radio frequency signal from being shunted from the drain electrode of the PMOS tube PM1 to the point E and providing a direct current level for the drain electrode of the PMOS tube PM1 through the point E.

The foregoing inventive concepts and various further alternatives thereof may be freely combined to form multiple concepts, all of which are contemplated and claimed herein. Various combinations will be apparent to those skilled in the art from a review of the present disclosure, and are not intended to be exhaustive or all of the present disclosure.

The invention has the beneficial effects that: the invention improves the transceiving switch structure of the transmission line-parallel switch type structure based on the CMOS process, reduces the chip area of the switch, reduces the insertion loss introduced when the radio frequency signal passes through the transceiving switch, and improves the linearity performance of the switch in the transmitting mode.

The method specifically comprises the following steps: the invention adopts an n-order lumped inductance-capacitance equivalent network composed of the tapped inductance and the capacitance to replace a 1/4 lambda transmission line to reduce the insertion loss, and compared with the common inductance, the tapped inductance can further save the chip area; the NMOS tube NM2 of the receiving branch is replaced by a PMOS tube PM1, static level switching ports are added to the drain electrodes and the source electrodes of the NM1 and the PM1, and in a transmitting mode, the grid voltage threshold value capable of enabling the NM1 working area to be converted into a linear area is improved, so that the gain compression phenomenon occurring when a transmitting signal is increased is relieved, the linearity performance of a switch in the transmitting mode is improved, meanwhile, PM1 can work normally after the level is switched, extra loss caused by introducing a series-connection blocking capacitor in a signal path is avoided, and extra chip area is occupied.

Drawings

FIG. 1 is a schematic diagram of a transceiver switch in a radio frequency communication system;

FIG. 2 is a schematic diagram of a transmit-receive switch using a transmission line-parallel switch configuration;

FIG. 3 is a schematic diagram of a relationship between a 1/4 lambda transmission line and an n-tap inductor-capacitor equivalent network;

Fig. 4 is a schematic structural diagram of a compact CMOS-based rf transreceiving switch of the present invention.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

In the description of the present invention, it should be noted that, directions or positional relationships indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., are directions or positional relationships based on those shown in the drawings, or are directions or positional relationships conventionally put in use of the inventive product, are merely for convenience of describing the present invention and simplifying the description, and are not indicative or implying that the apparatus or element to be referred to must have a specific direction, be constructed and operated in a specific direction, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.

Furthermore, the terms "horizontal," "vertical," "overhang," and the like do not denote a requirement that the component be absolutely horizontal or overhang, but rather may be slightly inclined. As "horizontal" merely means that its direction is more horizontal than "vertical", and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.

In the description of the present invention, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

In addition, in the present invention, if a specific structure, connection relationship, position relationship, power source relationship, etc. are not specifically written, the structure, connection relationship, position relationship, power source relationship, etc. related to the present invention can be known by those skilled in the art without any creative effort.

Example 1

Referring to fig. 3, 3-order lumped inductance-capacitance equivalent network composed of tapped inductance and capacitance is adopted in the transmitting branch switching circuit and the receiving branch switching circuit to replace a 1/4 lambda transmission line; in practical application, an odd-order high-order lumped inductance-capacitance equivalent network such as 5-order can be adopted. The relationship between the 1/4λ transmission line and the unit inductance value L ₀ and the unit capacitance value C ₀ of the n-order lumped inductance-capacitance equivalent network is determined by the following relationship:

Wherein T _D is the transmission delay of the 1/4λ transmission line, f ₀ is the characteristic frequency of the 1/4λ transmission line, and Z ₀ is the characteristic impedance of the 1/4λ transmission line.

Referring to fig. 4, the invention discloses a compact radio frequency transceiver switch based on CMOS, comprising: the voltage source and the radio frequency receiving and transmitting switching circuit. The negative pole of the voltage source V1 is connected with the ground end GND, and the positive pole of the voltage source V1 is connected with the power end VDD.

The radio frequency receiving and transmitting switching circuit comprises:

And a receiving channel signal port pin3 connected with one end of the PM1 source and one end of the L3.

The source is connected with pin3, the grid is connected with node B, and the drain is connected with PMOS tube PM1 that R3 one end and blocking capacitor C6 one end link to each other.

And one end of the resistor R3 is connected with the node E, and the other end of the resistor R3 is connected with the PM1 drain electrode and the blocking capacitor C6, and the resistor R3 is used for preventing the radio frequency signal from being shunted from the PM1 drain electrode to the point E and simultaneously providing a direct current level for the PM1 drain electrode through the point E.

And the blocking capacitor C6 with one end connected with the GND and the other end connected with the PM1 drain electrode and the R3 is used for blocking the direct current path between the PM1 drain electrode and the GND and simultaneously providing an alternating current path for radio frequency signals between the PM1 drain electrode and the GND.

And a capacitor Cp3 having one end connected to GND and the other end connected to the PM1 source and pin3, where the capacitor Cp3 is not an independent device, but is a sum of a parasitic capacitance from the pin3 port pad to GND and a parasitic capacitance from the PM1 source to GND, and on the premise of determining the port pad size, the size of the PMOS tube PM1 is reasonably selected so that the Cp3 capacitance=1/2×unit capacitance C ₀.

One end is connected with pin3 and PM1 source, and the other end is connected with C4 one end and L2 one end, and center tap end is with the inductance L3 that takes a tap that C5 one end links to each other, and L3 inductance=2 unit inductance L ₀.

And a capacitor C4 having one end connected to GND and the other end connected to L2 and the inductor L3, the capacitor C4 having a capacitance value=1/2×unit capacitance value C ₀.

And one end of the capacitor C5 is connected with the GND, and the other end of the capacitor C5 is connected with the L3 central tap end, and the capacitance value of the capacitor C5 is=1/2 x unit capacitance value C ₀.

One end is connected with one end of L3 and one end of C4, and the other end is connected with L1, resistance R1 and C3, and inductance L2 that center tap end and pin1 link to each other, L2 inductance value = 2 unit inductance value L ₀.

And a capacitor Cp2 having one end connected to GND and the other end connected to the L2 center tap and pin1, the capacitor Cp2 being not an independent device but a parasitic capacitance from the pin1 port pad to GND, the Cp2 capacitance value=the unit capacitance value C ₀.

And a transmitting channel signal port pin2 connected with the drain electrode of the NM1 and one end of the L1.

The drain electrode is connected with one ends of pin2 and L1, the grid electrode is connected with the node A, and the source electrode is connected with the NMOS tube NM1 with R2 and the blocking capacitor C1.

And one end of the resistor R2 is connected with the node D, and the other end of the resistor R2 is connected with the NM1 source electrode and the blocking capacitor C1, and the resistor R2 is used for preventing the radio frequency signal from being shunted from the NM1 drain electrode to the point D and providing a direct current level for the NM1 source electrode through the point D.

And the blocking capacitor C1 with one end connected with the GND and the other end connected with the NM1 source electrode and the resistor R2 is used for blocking the direct current path between the NM1 source electrode and the GND and simultaneously providing an alternating current path for radio frequency signals between the NM1 source electrode and the GND.

And a capacitor Cp1 having one end connected to GND and the other end connected to the drain of NM1, where the capacitor Cp1 is not an independent device, but is a sum of a parasitic capacitance from the pin2 port pad to GND and a parasitic capacitance from the NM1 drain to GND, and on the premise of determining the size of the port pad, the size of the NMOS transistor NM1 is reasonably selected so that the Cp1 capacitance value=1/2×unit capacitance value C ₀.

One end is connected with pin2 and NM1 drain electrode, and the other end links to each other with resistance R1, inductance L2 and electric capacity C3, and center tap end and the inductance L1 that takes tap that C2 links to each other, and L1 inductance=2 unit inductance L ₀.

And a capacitor C2 with one end connected to GND and the other end connected to the L1 center tap, wherein the capacitance value of C2=1/2×unit capacitance value C ₀.

And a capacitor C3 having one end connected to GND and the other end connected to the inductor L1, the inductor L2, and the resistor R1, wherein the capacitance C3 is equal to or less than 1/2 of the unit capacitance C ₀.

One end is connected with the inductor L1, the inductor L2 and the capacitor C3, and the other end is connected with the resistor R1 connected with the node C, so that the resistor R1 is used for preventing the radio frequency signal from being shunted to the point C and providing a direct current level for the drain electrode of the M1 through the point C.

And an antenna signal port pin1 connected with the L2 center tap end.

Based on the circuit structure, the working mechanism of the radio frequency receiving and transmitting change-over switch is as follows:

In the following analysis, the blocking capacitors C1 and C6 have larger values, and are equivalent to short circuit for radio frequency; the port impedances of pin1, pin2, pin3 are all defaults to standard 50 ohms.

In the receive mode: the level of the node A=VDD, the level of the node C=GND, the level of the node D=GND, the NM1 works in a deep linear region, a switch formed by the node A is in an on state, the on resistance of the M1 is close to 0 ohm, and the impedance of the third-order lumped inductance-capacitance network which is equivalent to a 1/4 lambda transmission line and is formed by Cp1, L1, C2, C3, L2 and Cp2 is transformed by the impedance of the third-order lumped inductance-capacitance network which is equivalent to the 1/4 lambda transmission line, so that the impedance seen from the pin1 to the pin2 tends to infinity, and the radio frequency signal is prevented from flowing from the pin1 to the pin2; level of node b=vdd, level of node e=gnd, PM1 operates in the off-region, and the switch it constitutes is in the off-state; the radio frequency signal can be transmitted from pin1 to pin3 via an equivalent 1/4 lambda transmission line consisting of Cp2, L2, C4, L3, C5, cp 3.

In the transmit mode: the level of the node B=GND, the level of the node C=VDD, the level of the node E=VDD, the PM1 works in a deep linear region, a switch formed by the node E is in an on state, the on resistance of the PM1 is close to 0 ohm, and the impedance of the third-order lumped inductance-capacitance network which is equivalent to a 1/4 lambda transmission line and is formed by Cp2, L2, C4, L3, C5 and Cp3 is transformed by the impedance of the third-order lumped inductance-capacitance network, so that the impedance seen from the pin1 to the pin3 is theoretically towards infinity, and the radio frequency signal is prevented from flowing from the pin1 to the pin3; level=gnd of node a, level=vdd of node D, NM1 operates in the cut-off region, and the switch it constitutes is in the off state; the radio frequency signal may be transmitted from pin2 to pin1 via an equivalent 1/4 lambda transmission line consisting of Cp1, L1, C2, C3, L2, cp 2.

The invention adopts an n-order lumped inductance-capacitance equivalent network composed of the tapped inductance and the capacitance to replace a 1/4 lambda transmission line to reduce the insertion loss, and compared with the common inductance, the tapped inductance can further save the chip area;

The NMOS tube NM2 of the receiving branch is replaced by a PMOS tube PM1, static level switching ports are added to the drain electrodes and the source electrodes of the NM1 and the PM1, and in a transmitting mode, the grid voltage threshold value capable of enabling the NM1 working area to be converted into a linear area is improved, so that the gain compression phenomenon occurring when a transmitting signal is increased is relieved, the linearity performance of a switch in the transmitting mode is improved, meanwhile, PM1 can work normally after the level is switched, extra loss caused by introducing a series-connection blocking capacitor in a signal path is avoided, and extra chip area is occupied.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims

1. A CMOS-based compact radio frequency transreceiving switcher, the compact radio frequency transreceiving switcher comprising: a voltage source V1 and a radio frequency receiving and transmitting switching circuit;

the radio frequency receiving and transmitting switching circuit comprises: an antenna port pin1, a transmitting channel port pin2 and a receiving channel port pin3;

A second n-order lumped inductance-capacitance equivalent network is arranged between the antenna port pin1 and the receiving channel port pin3, a switch formed by a PMOS tube PM1 is arranged at the receiving channel port pin3 and connected to GND in parallel through a capacitor C1, the drain electrode of the PMOS tube PM1 is connected with the receiving channel port pin3, the drain electrode of the PMOS tube PM1 is connected with the ground through the capacitor C1, and the grid electrode of the PMOS tube PM1 is controlled by the level of a node B;

2. The compact radio frequency transceiver switch as claimed in claim 1, wherein a source of the NMOS tube NM1 and a drain of the PMOS tube PM1 are respectively provided with a static level switching port D and a static level switching port E.

3. The compact rf transreceiving switch of claim 1, wherein the first and second n-th order lumped inductor-capacitor equivalent networks are 3-th order lumped inductor-capacitor equivalent networks;

wherein, the unit inductance value of the 3-order lumped inductance-capacitance equivalent network is L ₀, and the unit capacitance value is C ₀.

4. A compact radio frequency transceiver switch as claimed in claim 3, wherein the antenna port pin1 is connected to a center tap of the inductor L2 and one end of the capacitor Cp2, and the inductance value of the inductor L2 is 2L ₀;

5. The compact radio frequency fransmit/receive switch of claim 4, wherein the first n-stage lumped inductor-capacitor equivalent network comprises a capacitor Cp1, a capacitor C2, a capacitor C3, and an inductor L1, and a capacitor Cp2 and an inductor L2 in common with a second n-stage lumped inductor-capacitor equivalent network;

6. The compact radio frequency transceiver switch as claimed in claim 5, wherein the capacitance value of said capacitor Cp1 is the sum of the parasitic capacitance from the port pad of the transmit path port pin2 to GND and the parasitic capacitance from the drain of the NMOS transistor NM1 to GND, and is C ₀/2;

The inductance value of the inductor L1 is 2L ₀; the capacitance value of the capacitor C2 is C ₀/2; the capacitance value of the capacitor C3 is C ₀/2.

7. The compact radio frequency fransmit/receive switch of claim 4, wherein the second n-stage lumped inductor-capacitor equivalent network comprises a capacitor Cp3, a capacitor C4, a capacitor C5, and an inductor L3;

8. The switch of claim 7, wherein the capacitance of the capacitor Cp3 is a sum of a parasitic capacitance from a port pad of the receiving channel port pin3 to GND and a parasitic capacitance from a source of the PMOS tube PM1 to GND, and is C ₀/2;

9. The compact radio frequency fransmit/receive switching switch of claim 1, wherein the radio frequency fransmit/receive switching circuit further comprises: capacitor C1, capacitor C6, resistor R1, resistor R2, resistor R3;