CN118629994A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN118629994A CN118629994A CN202411110514.2A CN202411110514A CN118629994A CN 118629994 A CN118629994 A CN 118629994A CN 202411110514 A CN202411110514 A CN 202411110514A CN 118629994 A CN118629994 A CN 118629994A
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a semiconductor structure and a manufacturing method thereof, and belongs to the technical field of semiconductors. The semiconductor structure includes: a substrate comprising a dense region and a sparse region; the first dielectric layer is arranged on the substrate; the first metal layer is arranged in the first dielectric layer, and the surfaces of the first dielectric layer and the first metal layer on the sparse area are lower than the surfaces of the first dielectric layer and the first metal layer on the dense area; the second dielectric layer is arranged on the first dielectric layer and the first metal layer, and the surface of the second dielectric layer on the sparse area is lower than the surface of the second dielectric layer on the dense area; the sacrificial nitride layer is arranged on the second dielectric layer of the sparse zone, and the surface of the sacrificial nitride layer is flush with the surface of the second dielectric layer on the dense zone; and the second metal layer is arranged in the second dielectric layer and the sacrificial nitride layer, and the surfaces of the second metal layer on the sparse area and the dense area are flush. The semiconductor structure and the manufacturing method thereof provided by the invention can improve the yield and the performance of the integrated circuit.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor structure and a manufacturing method thereof.
Background
With the continued development of integrated circuits, the feature sizes (Critical Dimension, CD) of semiconductor devices have decreased and the integration of integrated circuits has increased. In an integrated circuit, a plurality of semiconductor devices of different types are included, the densities of the different semiconductor devices are different, and the different semiconductor devices are connected through a metal wiring layer. When the metal layers are formed, as the density degree of the metal layers on the semiconductor devices is different, in the process of forming the first metal layer, the load effect of the chemical mechanical polishing (CHEMICAL MECHANICAL Polish, CMP) process at different positions of the density degree causes that the surfaces of the first metal layer are not on the same plane, thereby causing disconnection among the metal layers of partial areas when the subsequent metal layers are formed, and further affecting the yield and the performance of the integrated circuit.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a manufacturing method thereof, and the semiconductor structure and the manufacturing method thereof can meet the requirements of isolation and connection between metal layers in different areas, avoid circuit breaking caused by incomplete opening, thereby improving the yield and performance of an integrated circuit and not increasing the cost additionally.
In order to solve the above technical problems, the present invention provides a semiconductor structure, comprising:
A substrate comprising a dense region and a sparse region;
The first dielectric layer is arranged on the substrate;
The first metal layer is arranged in the first dielectric layer, and the surfaces of the first dielectric layer and the first metal layer on the sparse area are lower than the surfaces of the first dielectric layer and the first metal layer on the dense area;
the second dielectric layer is arranged on the first dielectric layer and the first metal layer, and the surface of the second dielectric layer on the sparse area is lower than the surface of the second dielectric layer on the dense area;
the sacrificial nitride layer is arranged on the second dielectric layer of the sparse region, and the surface of the sacrificial nitride layer is flush with the surface of the second dielectric layer on the dense region; and
And the second metal layer is arranged in the second dielectric layer and the sacrificial nitride layer, and the surfaces of the second metal layer on the sparse area and the dense area are flush.
In an embodiment of the present invention, a plurality of semiconductor devices are disposed in the substrate, and the semiconductor devices have a density in the dense region that is greater than a density in the sparse region.
In one embodiment of the present invention, the first metal layer is connected to the semiconductor device.
In an embodiment of the present invention, the second metal layer on the dense area is disposed at an interval from the first metal layer, and the second metal layer on the sparse area is disposed in connection with the first metal layer through a connection structure.
In an embodiment of the present invention, a capping layer is disposed between the first dielectric layer and the substrate, and between the first dielectric layer and the second dielectric layer.
The invention also provides a manufacturing method of the semiconductor structure, which comprises the following steps:
providing a substrate, wherein the substrate comprises a dense region and a sparse region;
Forming a first dielectric layer on the substrate;
Forming a first metal layer in the first dielectric layer, wherein the surfaces of the first dielectric layer and the first metal layer on the sparse area are lower than the surfaces of the first dielectric layer and the first metal layer on the dense area;
forming a second dielectric layer on the first dielectric layer and the first metal layer, wherein the surface of the second dielectric layer on the sparse region is lower than the surface of the second dielectric layer on the dense region;
forming a sacrificial nitride layer on the second dielectric layer of the sparse region, wherein the surface of the sacrificial nitride layer is flush with the surface of the second dielectric layer on the dense region; and
And forming a second metal layer in the second dielectric layer and the sacrificial nitride layer, wherein the surface of the second metal layer on the sparse region and the dense region is flush.
In an embodiment of the present invention, the manufacturing method further includes:
Forming a cap layer, the second dielectric layer, a sacrificial nitride layer, a sacrificial oxide layer and a hard mask layer on the first dielectric layer and the first metal layer in sequence, wherein the thickness of the sacrificial oxide layer on the dense region is larger than that of the sacrificial oxide layer on the sparse region;
Forming a first photoresist layer on the hard mask layer, wherein the first photoresist layer comprises a first opening and a plurality of second openings, the first openings are arranged on the dense region, the second openings are arranged on the sparse region, and the opening width of the second openings is smaller than that of the first openings; and
And etching the substrate by taking the first photoresist layer as a mask, forming a first groove at the first opening position, forming a second groove at the second opening position, wherein the bottom of the first groove is in the second dielectric layer, and the bottom of the second groove is in the sacrificial oxide layer.
In an embodiment of the present invention, the manufacturing method further includes:
Forming a first compensation layer in the first groove and the second groove;
etching the first compensation to the second groove to expose the sacrificial oxide layer; and
And changing etching conditions, etching the bottom of the second groove to the cap layer on the first metal layer to form an opening, and forming a residual part of the first compensation layer in the first groove.
In an embodiment of the present invention, the manufacturing method further includes:
Forming a second compensation layer in the first compensation layer and the opening;
forming a second photoresist layer on the second compensation layer, wherein the second photoresist layer comprises a plurality of third openings arranged on the dense region and a fourth opening arranged on the sparse region, the opening width of the third openings is smaller than that of the first openings, and the fourth opening exposes a plurality of open holes and the area between the open holes;
etching by taking the second photoresist layer as a mask, forming a third concave part at the third opening position, forming a fourth concave part at the fourth opening position, and etching the opening to the first metal layer;
Removing the second photoresist layer, the second compensation layer and the first compensation layer,
Depositing a second metal layer within the third recess and the fourth recess;
planarizing the second metal layer to be flush with the second metal layer within the third recess and the fourth recess.
In an embodiment of the present invention, after the second compensation layer and the first compensation layer are removed, tops of adjacent third recesses are communicated, an opening width of a top communicating portion of the third recesses is larger than an opening width of the fourth recesses, and a surface of the second metal layer on the dense region is lower than a surface on the sparse region.
In summary, the present application provides a semiconductor structure and a method for manufacturing the same, which have the unexpected technical effects of satisfying isolation and connection between metal layers in different regions, and avoiding circuit breaking caused by incomplete opening, thereby improving yield and performance of an integrated circuit. The design requirement of the metal wiring layer can be met, and meanwhile, the phenomenon that the metal layers which are required to be connected are not connected due to uneven surfaces is avoided, so that the problem of disconnection is avoided. On the basis of not increasing the photoetching program, the problem that the open holes are not etched to the first metal layer due to the steps of the sparse region can be solved, the problem of open circuit between the metal layers is solved, the manufacturing cost is not increased, and the manufacturing time is not prolonged. The uneven surface caused by the formation of the first metal layer can be leveled when the second metal layer is formed, and the subsequent metal layer or other structures can be manufactured on a flat substrate when the subsequent metal layer or other structures are formed, so that the yield of the process can be improved, and the quality of the semiconductor structure can be improved.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic view illustrating forming a first recess and a second recess in a first dielectric layer according to an embodiment of the present invention.
FIG. 2 is a schematic illustration of depositing a first metal layer in a first recess and a second recess in an embodiment of the invention.
Fig. 3 is a schematic diagram of a first metal layer planarization process according to an embodiment of the invention.
FIG. 4 is a schematic diagram of sequentially forming a second cap layer, a second dielectric layer, a sacrificial nitride layer, a sacrificial oxide layer and a hard mask layer on a first metal layer according to an embodiment of the present invention.
FIG. 5 is a schematic diagram illustrating planarization of a sacrificial oxide layer after sequentially forming a second cap layer, a second dielectric layer, a sacrificial nitride layer and a sacrificial oxide layer according to another embodiment of the present invention.
Fig. 6 is a schematic diagram of the first etching after forming the first groove and the second groove according to an embodiment of the invention.
Fig. 7 is a schematic diagram of a second etching process when forming the first groove and the second groove according to an embodiment of the invention.
FIG. 8 is a schematic diagram illustrating formation of a first compensation layer according to an embodiment of the invention.
FIG. 9 is a schematic diagram of forming openings at the bottoms of the first compensation layer and the second recess by etching according to an embodiment of the invention.
FIG. 10 is a schematic diagram illustrating the formation of a second compensation and second photoresist layer according to an embodiment of the invention.
Fig. 11 is a schematic view of forming a third recess and a fourth recess in an embodiment of the invention.
FIG. 12 is a schematic diagram of the second photoresist layer and the compensation layer removed according to an embodiment of the invention.
FIG. 13 is a schematic diagram of a second metal layer deposited according to an embodiment of the present invention.
Fig. 14 is a schematic view of a semiconductor structure after a second metal layer planarization process in an embodiment of the invention.
Description of the reference numerals:
10. A substrate; 100. a dense region; 200. a sparse region; 101. a semiconductor device; 102. a conductive plug; 11. an interlayer dielectric layer; 12. a first cap layer; 13. a first dielectric layer; 131. a first concave portion; 132. a second concave portion; 14. a first metal layer; 141. a first subsection; 142. a second subsection; 15. a second cap layer; 16. a second dielectric layer; 17. sacrificial nitride layer; 18. a sacrificial oxide layer; 19. a hard mask layer; 20. a first photoresist layer; 201. a first opening; 202. a second opening; 211. a first groove; 212. a second groove; 21. a first compensation layer; 22. a second compensation layer; 221. opening holes; 23. a second photoresist layer; 231. a third opening; 232. a fourth opening; 241. a third recess; 242. a fourth concave portion; 25. a second metal layer; 251. a third subsection; 252. a fourth division; 253. and a connection structure.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
In the description of the present specification, it should be understood that the directions or positional relationships indicated in terms such as "center", "upper", "lower", "front", "rear", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the apparatus or component referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Referring to fig. 14, the present application provides a semiconductor structure, which includes a substrate 10 and a plurality of metal layers disposed on the substrate 10, wherein the substrate 10 includes a dense region 100 and a sparse region 200, a first metal layer is disposed in a first dielectric layer 13, and when the first metal layer is formed, a surface of the first dielectric layer 13 and the first metal layer on the sparse region 200 is lower than a surface of the first dielectric layer on the dense region 100 due to a difference in pattern density. The second dielectric layer 16 and the sacrificial nitride layer 17 are disposed on the first metal layer and the first dielectric layer 13, so that the surface of the formed second metal layer is flush, the surface of the sacrificial nitride layer 17 is flush with the surface of the second dielectric layer 16 on the dense region 100, and meanwhile, connection between the metal layers on the sparse region is ensured. The semiconductor structure of the application can meet the isolation and connection between metal layers in different areas, and avoid the circuit break caused by incomplete opening, thereby improving the yield and performance of the integrated circuit. Meanwhile, the uneven surface caused by the formation of the first metal layer is leveled on the surface of the second metal layer, so that the yield of the subsequent manufacturing process is improved.
Referring to fig. 1, in an embodiment of the present invention, a substrate 10 is provided first, and the substrate 10 may be any material suitable for forming a semiconductor device, for example, a semiconductor material formed of silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer, or other III/V compounds, and the like, and further includes a stacked structure formed of these semiconductor materials, or is a silicon-on-insulator, a stacked silicon-on-insulator, a silicon-germanium-on-insulator, a germanium-on-insulator, and the like. Wherein a plurality of semiconductor devices 101 are formed on a substrate 10, and the substrate 10 includes a dense region 100 and a sparse region 200, the density of semiconductor devices 101 on the dense region 100 being greater than the density of semiconductor devices 101 on the sparse region 200. The present invention is not limited to the type of the semiconductor device 101, and the semiconductor device 101 may be, for example, one or more of a field effect Transistor (FIELD EFFECT Transistor, FET), a Metal-Oxide-semiconductor field effect Transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), a complementary Metal Oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS), an insulated gate bipolar Transistor (Insulated Gate Bipolar Transistor, IGBT), a high-speed recovery Diode (Fast Recovery Diode, FRD), a high-speed high-efficiency rectifier Diode (FIGH EFFICIENCY Diode, HED), a constant voltage Diode, a high-frequency Diode, a Light-Emitting Diode (LED), a gate-switching Thyristor (Gate Turn off Thyristor, GTO), a Light-triggered Thyristor (LIGHT TRIGGERED Thyristor, LTT), a Thyristor (Thyristor), a charge coupler (Charge Coupled Device, a CCD image sensor), a digital signal processing device (DIGITAL SIGNAL Processor, DSP), a Photo Relay (Photo Relay), or a microprocessor (microprocessor), and the like.
Referring to fig. 1, in an embodiment of the present invention, an interlayer dielectric layer 11 is disposed on a substrate 10, and a plurality of conductive plugs 102 are disposed in the interlayer dielectric layer 11, and the conductive plugs 102 are connected to a semiconductor device 101 in the substrate 10. The interlayer dielectric layer 11 is an insulating material such as silicon dioxide (SiO 2) or silicon nitride (SiN), and can isolate the semiconductor device 101 from the metal layer, prevent diffusion of metal, and protect the semiconductor device 101 from damage during preparation of the metal layer. In this embodiment, the conductive plug 102 is made of a low-resistance material such as tungsten, silver or gold, so that the resistance is small when the conductive plug 102 is connected to a metal layer prepared later, thereby improving the performance of the semiconductor structure.
Referring to fig. 1, in an embodiment of the present invention, a first capping layer 12 and a first dielectric layer 13 are formed on an interlayer dielectric layer 11. The first capping layer 12 is disposed on the interlayer dielectric layer 11, the first dielectric layer 13 is disposed on the first capping layer 12, and the first capping layer 12 is, for example, silicon carbide nitride (SiCN) or silicon nitride (sin) to prevent metal ions in the metal layer from diffusing into the interlayer dielectric layer 11, and the first capping layer 12 may be deposited by, for example, chemical Vapor Deposition (Chemical Vapor Deposition, CVD) or plasma enhanced chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition (PECVD). The first dielectric layer 13 is made of a Low dielectric constant (Low-K) material such as silicon dioxide or silicon fluoride (SiF), silicon oxycarbide (SiOC) or silicon oxyfluoride (SiOF) to improve the reliability of the semiconductor structure, and the first dielectric layer 13 may be deposited by chemical vapor deposition or Low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or the like. The thickness of the first capping layer 12 and the first dielectric layer 13, that is, the thickness of the first capping layer 12 and the first dielectric layer 13, may be selected according to the manufacturing requirements of the semiconductor structure.
Referring to fig. 1, in an embodiment of the present invention, a patterned photoresist layer (not shown) is formed on the first dielectric layer 13, the first dielectric layer 13 and the first cap layer 12 are etched until the interlayer dielectric layer 11 is etched, so as to form a recess, and then the patterned photoresist layer is removed by wet etching or ashing after the recess is formed. In this embodiment, the recess is formed by, for example, a dry etching process, and the etching gas may be, for example, one or a combination of several gases of trifluoromethane (CHF 3), difluoromethane (CH 2F2), nitrogen trifluoride (NF 3), sulfur hexafluoride (SF 6), nitrogen (N 2), or the like, or a mixture of them with oxygen (O 2). Wherein the recesses include a first recess 131 and a second recess 132, the first recess 131 being disposed on the semiconductor device 101 on the dense region 100, the second recess 132 being disposed on the semiconductor device 101 on the sparse region 200, the density of the first recess 131 being greater than the density of the second recess 132.
Referring to fig. 1 to 2, in an embodiment of the present application, after forming the recess, a first metal layer 14 is deposited on the recess and the first dielectric layer 13 until the first metal layer 14 completely fills the recess. In the present application, before depositing the first metal layer 14, a barrier layer (not shown) may be formed on the sidewalls and bottom of the first recess 131 and the second recess 132, and the barrier layer may be formed by physical vapor deposition (Physical Vapor Deposition, PVD) or the like, where the barrier layer may be at least one material with good adhesion, such as tantalum (Ta) or tantalum nitride (TaN), and the thickness of the barrier layer may be, for example, 2nm to 5nm. To enhance adhesion of the metal to the sidewalls of the first and second recesses 131 and 132 and to improve electrical performance of the semiconductor structure. The first metal layer 14 is, for example, a metal copper layer, a metal aluminum layer, or a metal tungsten layer. In the present embodiment, the first metal layer 14 is, for example, a metal copper layer, and the metal copper layer is formed by, for example, physical vapor deposition or electroplating.
Referring to fig. 2 to 3, in an embodiment of the invention, after the deposition of the first metal layer 14 is completed, a first planarization process is performed, for example, by chemical mechanical polishing, until the metal in the first recess 131 is level with the first dielectric layers 13 on both sides. The finally formed first metal layer 14 includes a first portion 141 and a second portion 142, the first portion 141 being formed in the first recess 131, and the second portion 142 being formed in the second recess 132. In the planarization process, since the polishing speed of the sparse region 200 is high, the surface of the first dielectric layer 13 and the first metal layer on the sparse region 200 is lower than the surface on the dense region 100, forming a height difference.
Referring to fig. 3 to 5, in an embodiment of the present invention, after the first metal layer is planarized, a second cap layer 15, a second dielectric layer 16, a sacrificial nitride layer 17, a sacrificial oxide layer 18 and a hard mask layer 19 are sequentially formed on the first dielectric layer 13 and the first metal layer. The material of the second cap layer 15 is, for example, silicon carbide nitride or silicon nitride, the second dielectric layer 16 is, for example, silicon dioxide or silicon fluoride, silicon oxycarbide or silicon oxyfluoride, the sacrificial nitride layer 17 is, for example, a silicon nitride layer or silicon carbide nitride, the sacrificial oxide layer 18 is, for example, a silicon oxide layer, and the hard mask layer 19 is, for example, a titanium nitride. The sacrificial nitride layer 17 and the sacrificial oxide layer 18 are used to ensure complete contact and surface leveling between the metal layers when the second metal layer and the connection structure are formed later, and the hard mask layer 19 plays a role of transferring patterns in the subsequent manufacturing process. When the second metal layer is formed, the sacrificial nitride layer and the sacrificial oxide layer can ensure that the opening is exposed to the first metal layer, the second metal layer can be leveled, and the quality of the semiconductor structure is improved.
Referring to fig. 4 to 5, in an embodiment of the present invention, the thickness and the deposition manner of the second cap layer 15, the second dielectric layer 16 and the sacrificial nitride layer 17 are not limited, and may be selected according to the preparation requirement of the semiconductor structure, and when the second cap layer 15, the second dielectric layer 16 and the sacrificial nitride layer 17 are formed, the height difference between the dense region 100 and the sparse region 200 is inherited by the formed second cap layer 15, second dielectric layer 16 and sacrificial nitride layer 17 in the sparse region 200. In one embodiment of the present invention, the sacrificial oxide layer 18 is formed by a chemical vapor deposition process using ethyl orthosilicate (TETRAETHYL ORTHOSILICATE, TEOS) and the thickness of the sacrificial oxide layer 18 on the sparse zone 200 is greater than the thickness of the sacrificial oxide layer 18 on the dense zone 100 due to the mobility of ethyl orthosilicate. In another embodiment of the present invention, when forming the sacrificial oxide layer 18, the deposition time is prolonged, the deposition thickness of the sacrificial oxide layer 18 is increased, and then planarization is performed by chemical mechanical polishing or the like, so as to planarize the surface of the sacrificial oxide layer 18. After forming the sacrificial oxide layer 18, a hard mask layer 19 is formed on the sacrificial oxide layer 18, and the thickness and deposition manner of the hard mask layer 19 are not limited in the present invention, and may be selected according to the manufacturing requirements of the semiconductor structure. After forming the hard mask layer 19, a first photoresist layer 20 is formed on the hard mask layer 19, and the first photoresist layer 20 is subjected to processes such as exposure and development, so as to form a first opening 201 and a plurality of second openings 202, wherein the first opening 201 is disposed on the dense region 100 and covers at least two first portions 141, the second opening 202 is disposed on the sparse region 200, and the opening width of the second opening 202 is smaller than the width of the second portion 142, i.e., is much smaller than the width of the first opening 201, and two second openings are disposed on a single second portion 142, for example.
Referring to fig. 4 to 7, in an embodiment of the present application, after forming the first photoresist layer 20, etching is performed in a direction of the substrate 10 using the first photoresist layer 20 as a mask, and in the present application, etching is performed in two steps, for example, to form a first recess 211 and a second recess 212, wherein the first opening 201 defines a position of the first recess 211, and the second opening 202 locates a position of the second recess 212. As shown in fig. 6, in the first etching, since the thickness of the sacrificial oxide layer 18 on the sparse region 200 is greater than the thickness of the sacrificial oxide layer 18 on the dense region 100, the second recess 212 is also located in the sacrificial oxide layer 18 when the first recess 211 is etched to the sacrificial nitride layer 17. Therefore, with the sacrificial nitride layer 17 on the dense region 100 as an etching stop layer, the second recess 212 is located in the sacrificial oxide layer 18 when the first recess 211 is etched to the sacrificial nitride layer 17. And then changing etching conditions, performing second etching, and removing the sacrificial nitride layer 17 and part of the second dielectric layer 16 exposed by the first groove 211 by adopting selective etching. Since the etching selectivity of the sacrificial nitride layer 17 and the sacrificial oxide layer 18 is relatively large, the first recess 211 stops in the second dielectric layer 16 and the second recess 212 stops in the sacrificial oxide layer 18 after the second etching is completed. In this embodiment, the recess is formed by, for example, dry etching, and after the etching is completed, the first photoresist layer 20 is removed by wet etching or ashing treatment. By forming the first opening 201 having a larger opening width, the stop positions of the first groove and the second groove can be controlled, thereby ensuring the contact of the openings formed later in the subsequent process.
Referring to fig. 7 to 8, in an embodiment of the present invention, after the first photoresist layer 20 is removed, a first compensation layer 21 is deposited on the recess and the hard mask layer 19, and the first compensation layer 21 is, for example, an organic dielectric layer (OrganicDielectric Layer, ODL) material. The first compensation layer 21 may be formed by a spin-coating process, and after the organic dielectric layer is spin-coated, the height of the first compensation layer 21 on the dense region 100 is slightly greater than the height of the first compensation layer 21 on the sparse region 200.
Referring to fig. 7 to 9, in an embodiment of the invention, after the first compensation layer 21 is formed, the first compensation layer 21 is directly etched, and during the etching process, since the first recess 211 is deeper than the second recess 212 and the thickness of the first compensation layer 21 on the dense region 100 is greater, when the first compensation layer 21 in the second recess 212 is completely removed, the remaining portion of the first compensation layer 21 in the first recess 211. In the etching process, when the sacrificial oxide layer 18 in the second groove 212 is detected, etching conditions are changed, and selective etching is adopted to remove the sacrificial oxide layer 18, the sacrificial nitride layer 17, the second dielectric layer 16 and part of the second cap layer 15 at the bottom of the second groove 212, so as to form an opening 221. In the present embodiment, the opening 221 is formed by, for example, dry etching. By forming the first compensation layer 21, the openings 221 can be etched to ensure contact between the metal layers when the photoresist layer is not provided.
Referring to fig. 9 to 10, in an embodiment of the invention, after forming the opening 221, a second compensation layer 22 is formed on the surface of the substrate 10, where the second compensation layer 22 is, for example, an organic dielectric layer material. The second compensation layer 22 may be formed by a spin-on process, and after the organic dielectric layer is spin-coated, the thickness of the second compensation layer 22 on the dense region 100 is slightly greater than the thickness of the second compensation layer 22 on the sparse region 200. A second photoresist layer 23 is formed on the second compensation layer 22, and a plurality of third openings 231 and fourth openings 232 are formed by exposing and developing the second photoresist layer 23. Wherein the third openings 231 are disposed on the dense area 100, and the third openings 231 are disposed on the first sections 141, the number of the third openings 231 is the same as the number of the first sections 141, the fourth openings 232 are disposed on the sparse area 200, and the fourth openings 232 expose the plurality of openings 221 and the area between the openings 221, i.e. the fourth openings 232 are disposed on the second sections 142 and expose all the openings 221 on the second sections 142. In the present embodiment, the opening width of the fourth opening 232 is larger than the opening width of the third opening 231.
Referring to fig. 10 to 11, in an embodiment of the application, after forming the second photoresist layer 23, etching is performed in the direction of the substrate 10 by using the second photoresist layer 23 as a mask, and the compensation layer, part of the second dielectric layer 16 and the second cap layer 15 in the opening 221 are removed to form a third recess 241 and a fourth recess 242. In the present embodiment, etching is performed by, for example, a dry etching process. During the etching process, since the opening width of the fourth opening 232 is greater than the opening width of the third opening 231, and the surface of the second compensation layer 22 on the sparse region 200 is lower than the surface of the second compensation layer 22 on the dense region 100, when the opening 221 etched into the fourth recess 242 exposes the second portion 142, the third recess 241 is etched into the second dielectric layer 16, and the etching is stopped. I.e. the bottom of the third recess 241 is at a predetermined distance from the first subsection 141, the bottom of the fourth recess 242 between the openings 221 is flush with the bottom of the third recess 241. In the present application, in the process of forming the opening 221, the fourth recess 242 and the third recess 241, only the opening position of the photolithography plate needs to be optimized, and on the basis of not increasing the photolithography process, the problem that the opening is not etched to the first metal layer due to the step of the sparse region is solved, the problem of open circuit between the metal layers is solved, the manufacturing cost is not increased, and the manufacturing time is not prolonged.
Referring to fig. 11 to 12, in an embodiment of the present invention, after the recess etching is completed, the second photoresist layer 23 is removed by ashing, and the second compensation layer 22 and the first compensation layer 21 are removed by ashing. After the second compensation layer 22 and the first compensation layer 21 are removed, the tops of the adjacent third concave portions 241 communicate, and the opening width of the top communicating portion of the third concave portion 241 is larger than the opening width of the fourth concave portion 242.
Referring to fig. 12 to 13, in an embodiment of the present application, after removing the compensation layer, the second metal layer 25 is deposited in the third recess 241 and the fourth recess 242 until the second metal layer 25 completely fills the recesses. In the present application, before depositing the second metal layer 25, a barrier layer (not shown) may be formed on the sidewalls and bottom of the third recess 241 and the fourth recess 242, and the barrier layer may be formed by physical vapor deposition, for example, where the thickness of the barrier layer is, for example, 2nm to 5nm, and the barrier layer is at least one material with good adhesion, such as tantalum or tantalum nitride. To enhance adhesion of the metal to sidewalls of the third and fourth recesses 241 and 242 and to improve electrical performance of the semiconductor structure. The second metal layer 25 is, for example, a metal copper layer, a metal aluminum layer, or a metal tungsten layer. In this embodiment, the second metal layer 25 is, for example, a metal copper layer, and the metal copper layer is formed by, for example, physical vapor deposition or electroplating. In the present embodiment, for example, the electrochemical plating method is selected to form the second metal layer 25, and since the opening width of the top communication portion of the third concave portion 241 is larger than the opening width of the fourth concave portion 242, the deposition rate of the second metal layer 25 in the fourth concave portion 242 is larger than that in the third concave portion 241, and the surface of the second metal layer 25 protrudes from the surface of the second metal layer 25 on the dense region 100 on the sparse region 200.
Referring to fig. 13 to 14, in an embodiment of the present application, after depositing the second metal layer 25, a second planarization process is performed, for example, a planarization process is performed by chemical mechanical polishing, to remove the second metal layer 25 in the top communication portion of the third recess until the metal layers in the third recess and the fourth recess are level. The finally formed second metal layer 25 comprises a third subsection 251 and a fourth subsection 252, the third subsection 251 is formed in the third concave portion, the fourth subsection 252 is formed in the fourth concave portion, and the second metal layer in the opening at the bottom of the fourth concave portion is defined as a connecting structure 253. The third part 251 is isolated from the first part 141, and the fourth part 252 and the second part 142 are connected by the connection structure 253, so that good contact between the metal layers in the sparse zone 200 can be ensured. The application can meet the isolation and connection between the metal layers in different areas so as to meet the design requirement of the metal wiring layer, and avoid the unconnected metal layers which are required to be connected in the sparse area and are caused by uneven surface, thereby avoiding the problem of disconnection and improving the yield and the performance of the integrated circuit.
Referring to fig. 13 to 14, in an embodiment of the present invention, during planarization, since the second metal layer 25 on the sparse region 200 is higher than the dense region 100, the polishing rate of the second metal layer 25 in the sparse region 200 is higher than that of the dense region 100, after polishing is stopped, the surfaces of the third portion 251 and the fourth portion 252 are level, the third portion 251 is level with the second dielectric layers 16 on both sides, and the fourth portion 252 is level with the sacrificial nitride layers 17 on both sides. The sacrificial nitride layer 17 on the sparse region 200 is flush with the second dielectric layer 16 on the dense region 100, that is, after the second planarization process, the surface of the second metal layer can be ensured to be flush, that is, the uneven surface caused by the formation of the first metal layer can be leveled when the second metal layer is formed, and the subsequent metal layer or other structures can be formed on a flat substrate, so that the process yield can be improved, and the quality of the semiconductor structure can be improved. After the second metal layer is formed, subsequent fabrication of the metal layer or other structure is performed, as will not be described herein.
In summary, the present application provides a semiconductor structure and a method for fabricating the same, which are capable of satisfying isolation and connection between metal layers in different regions, and avoiding circuit breaking due to incomplete opening, thereby improving yield and performance of an integrated circuit. The design requirement of the metal wiring layer can be met, and meanwhile, the phenomenon that the metal layers which are required to be connected are not connected due to uneven surfaces is avoided, so that the problem of disconnection is avoided. On the basis of not increasing the photoetching program, the problem that the open holes are not etched to the first metal layer due to the height difference of the sparse zone is solved, the problem of open circuit between the metal layers is solved, the manufacturing cost is not increased, and the manufacturing time is not prolonged. The uneven surface caused by the formation of the first metal layer can be leveled when the second metal layer is formed, and the subsequent metal layer or other structures can be manufactured on a flat substrate when the subsequent metal layer or other structures are formed, so that the yield of the process can be improved, and the quality of the semiconductor structure can be improved.
The above description of illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. Although specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As noted, these modifications can be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.
The above description is only a preferred embodiment of the present application and the description of the technical principle applied, and it should be understood by those skilled in the art that the scope of the present application is not limited to the specific combination of the above technical features, but also covers other technical features formed by any combination of the above technical features or the equivalent features thereof without departing from the inventive concept, for example, the technical features disclosed in the present application (but not limited to) are replaced with technical features having similar functions. Other technical features besides those described in the specification are known to those skilled in the art, and are not described herein in detail to highlight the innovative features of the present application.
Claims (10)
1. A semiconductor structure, comprising:
A substrate comprising a dense region and a sparse region;
The first dielectric layer is arranged on the substrate;
The first metal layer is arranged in the first dielectric layer, and the surfaces of the first dielectric layer and the first metal layer on the sparse area are lower than the surfaces of the first dielectric layer and the first metal layer on the dense area;
the second dielectric layer is arranged on the first dielectric layer and the first metal layer, and the surface of the second dielectric layer on the sparse area is lower than the surface of the second dielectric layer on the dense area;
the sacrificial nitride layer is arranged on the second dielectric layer of the sparse region, and the surface of the sacrificial nitride layer is flush with the surface of the second dielectric layer on the dense region; and
And the second metal layer is arranged in the second dielectric layer and the sacrificial nitride layer, and the surfaces of the second metal layer on the sparse area and the dense area are flush.
2. The semiconductor structure of claim 1, wherein a plurality of semiconductor devices are disposed within the substrate, the semiconductor devices having a density in the dense region that is greater than a density in the sparse region.
3. The semiconductor structure of claim 2, wherein the first metal layer is connected to the semiconductor device.
4. The semiconductor structure of claim 1, wherein the second metal layer on the dense region is spaced apart from the first metal layer, and the second metal layer on the sparse region is connected to the first metal layer by a connection structure.
5. The semiconductor structure of claim 1, wherein a cap layer is disposed between the first dielectric layer and the substrate, and between the first dielectric layer and the second dielectric layer.
6. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a dense region and a sparse region;
Forming a first dielectric layer on the substrate;
Forming a first metal layer in the first dielectric layer, wherein the surfaces of the first dielectric layer and the first metal layer on the sparse area are lower than the surfaces of the first dielectric layer and the first metal layer on the dense area;
forming a second dielectric layer on the first dielectric layer and the first metal layer, wherein the surface of the second dielectric layer on the sparse region is lower than the surface of the second dielectric layer on the dense region;
forming a sacrificial nitride layer on the second dielectric layer of the sparse region, wherein the surface of the sacrificial nitride layer is flush with the surface of the second dielectric layer on the dense region; and
And forming a second metal layer in the second dielectric layer and the sacrificial nitride layer, wherein the surface of the second metal layer on the sparse region and the dense region is flush.
7. The method of fabricating a semiconductor structure of claim 6, further comprising:
Forming a cap layer, the second dielectric layer, a sacrificial nitride layer, a sacrificial oxide layer and a hard mask layer on the first dielectric layer and the first metal layer in sequence, wherein the thickness of the sacrificial oxide layer on the dense region is larger than that of the sacrificial oxide layer on the sparse region;
Forming a first photoresist layer on the hard mask layer, wherein the first photoresist layer comprises a first opening and a plurality of second openings, the first openings are arranged on the dense region, the second openings are arranged on the sparse region, and the opening width of the second openings is smaller than that of the first openings; and
And etching the substrate by taking the first photoresist layer as a mask, forming a first groove at the first opening position, forming a second groove at the second opening position, wherein the bottom of the first groove is in the second dielectric layer, and the bottom of the second groove is in the sacrificial oxide layer.
8. The method of fabricating a semiconductor structure of claim 7, further comprising:
Forming a first compensation layer in the first groove and the second groove;
etching the first compensation to the second groove to expose the sacrificial oxide layer; and
And changing etching conditions, etching the bottom of the second groove to the cap layer on the first metal layer to form an opening, and forming a residual part of the first compensation layer in the first groove.
9. The method of fabricating a semiconductor structure of claim 8, further comprising:
Forming a second compensation layer in the first compensation layer and the opening;
forming a second photoresist layer on the second compensation layer, wherein the second photoresist layer comprises a plurality of third openings arranged on the dense region and a fourth opening arranged on the sparse region, the opening width of the third openings is smaller than that of the first openings, and the fourth opening exposes a plurality of open holes and the area between the open holes;
etching by taking the second photoresist layer as a mask, forming a third concave part at the third opening position, forming a fourth concave part at the fourth opening position, and etching the opening to the first metal layer;
Removing the second photoresist layer, the second compensation layer and the first compensation layer,
Depositing a second metal layer within the third recess and the fourth recess;
planarizing the second metal layer to be flush with the second metal layer within the third recess and the fourth recess.
10. The method of manufacturing a semiconductor structure according to claim 9, wherein after the second compensation layer and the first compensation layer are removed, tops of adjacent third recesses are communicated, an opening width of a top communicating portion of the third recesses is larger than an opening width of the fourth recesses, and a surface of the second metal layer on the dense region is lower than a surface on the sparse region.
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| CN115295530A (en) * | 2022-10-08 | 2022-11-04 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| WO2023070951A1 (en) * | 2021-10-25 | 2023-05-04 | 长鑫存储技术有限公司 | Semiconductor structure and forming method therefor |
| CN118073396A (en) * | 2022-11-11 | 2024-05-24 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
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| WO2023070951A1 (en) * | 2021-10-25 | 2023-05-04 | 长鑫存储技术有限公司 | Semiconductor structure and forming method therefor |
| CN115083905A (en) * | 2022-07-18 | 2022-09-20 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN115295530A (en) * | 2022-10-08 | 2022-11-04 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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