CN115954324B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN115954324B CN115954324B CN202310232109.7A CN202310232109A CN115954324B CN 115954324 B CN115954324 B CN 115954324B CN 202310232109 A CN202310232109 A CN 202310232109A CN 115954324 B CN115954324 B CN 115954324B
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Abstract
The invention discloses a semiconductor structure and a manufacturing method thereof, and belongs to the technical field of semiconductors. The semiconductor structure at least comprises: a substrate in which a plurality of semiconductor devices are disposed; at least one dielectric layer arranged on the substrate; the plurality of concave parts are arranged in the dielectric layer and connected with the semiconductor device, the side walls and the bottoms of the concave parts are provided with multi-layer blocking structures, and the number of layers of the blocking structures on the bottoms of the concave parts is smaller than that of the blocking structures on the side walls of the concave parts; and a metal layer disposed within the recess. The semiconductor structure and the manufacturing method thereof can improve the reliability and the performance of the semiconductor structure.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor structure and a manufacturing method thereof.
Background
After the feature sizes (Critical Dimension, CD) of the semiconductor devices enter the deep submicron stage, in order to achieve faster operation speeds, greater data storage capacity, and more functionality. The integration level of semiconductor devices is required to be continuously improved, and the number and density of metal layers are also continuously increased. With the continuous reduction of the line width of the metal, the increase of the resistance between the metal layers becomes more and more serious, which causes problems of resistance capacitance delay (RC delay) effect and electromigration failure of the metal interconnection, and reduces the performance of the semiconductor device.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a manufacturing method thereof, by the semiconductor structure and the manufacturing method thereof, the reliability of the semiconductor structure is improved, the resistance and capacitance delay effect and electromigration failure phenomenon are reduced, and meanwhile, the resistance of the semiconductor structure is reduced.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a semiconductor structure, which at least comprises:
a substrate in which a plurality of semiconductor devices are disposed;
at least one dielectric layer arranged on the substrate;
the plurality of concave parts are arranged in the dielectric layer and connected with the semiconductor device, the side walls and the bottoms of the concave parts are provided with multi-layer blocking structures, and the number of layers of the blocking structures on the bottoms of the concave parts is smaller than that of the blocking structures on the side walls of the concave parts; and
and a metal layer disposed in the recess.
In one embodiment of the invention, the barrier structure comprises a barrier layer disposed on the sidewalls and bottom of the recess, a buffer layer disposed on the barrier layer, and a seed layer disposed on the buffer layer.
In an embodiment of the present invention, the seed layer is a doped seed layer, and the dopant ions are at least one of manganese, magnesium, or zirconium.
In an embodiment of the invention, the barrier structure on the sidewall of the recess comprises the barrier layer, the buffer layer and the seed layer.
In an embodiment of the invention, the barrier structure on the bottom of the recess is one of the barrier layer, the combination of the barrier layer and the seed layer or the combination of the barrier layer and the buffer layer.
In an embodiment of the present invention, the buffer layer is a seed layer of the same material as the metal layer.
In an embodiment of the present invention, the buffer layer is at least one of copper oxynitride, tantalum oxynitride, titanium oxynitride, tungsten oxynitride, ruthenium oxynitride, rhodium oxynitride, titanium oxide, tungsten oxide, ruthenium oxide, or rhodium oxide.
The invention also provides a manufacturing method of the semiconductor structure, which at least comprises the following steps:
providing a substrate, and forming a plurality of semiconductor devices in the substrate;
forming at least one dielectric layer on the substrate;
forming a plurality of concave parts in the dielectric layer, wherein the concave parts are connected with the semiconductor device, the side walls and the bottoms of the concave parts are provided with multi-layer blocking structures, and the number of layers of the blocking structures on the bottoms of the concave parts is smaller than that of the blocking structures on the side walls of the concave parts; and
a metal layer is formed within the recess.
In an embodiment of the present invention, the method for manufacturing the blocking structure includes:
forming a barrier layer on the side wall and the bottom of the concave part;
forming a buffer layer on the barrier layer;
forming a seed layer on the buffer layer; and
and etching back the seed crystal layer, and removing the seed crystal layer at the bottom of the concave part.
In an embodiment of the present invention, the method for manufacturing the blocking structure includes:
forming a barrier layer on the side wall and the bottom of the concave part;
oxidizing the barrier layer with partial thickness, and forming a buffer layer on the barrier layer;
forming a seed layer on the buffer layer; and
and etching back the seed crystal layer and the buffer layer, and removing the seed crystal layer and the buffer layer at the bottom of the concave part.
In an embodiment of the present invention, the method for manufacturing the blocking structure includes:
forming a barrier layer on the side wall and the bottom of the concave part;
oxidizing the barrier layer with partial thickness, and forming a buffer layer on the barrier layer;
etching back the buffer layer, and removing the buffer layer at the bottom of the concave part; and
a seed layer is formed over the buffer layer and the barrier layer.
In summary, the present invention provides a semiconductor structure and a method for manufacturing the same, which can reduce diffusion of metal ions in a metal layer into a dielectric layer, improve the resistance-capacitance delay effect, reduce electromigration failure, and improve performance of the semiconductor structure. The overall resistance of the semiconductor structure is reduced, the electrical performance of the semiconductor structure is improved, and the reliability and the tolerance of the metal layer are increased.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a dielectric layer formed on a substrate in one embodiment.
FIG. 2 is a schematic diagram illustrating a recess formed in a dielectric layer according to an embodiment.
FIG. 3 is a schematic view of a barrier structure formed on a recess in an embodiment.
FIG. 4 is a schematic diagram of a seed layer etching the bottom of a recess in one embodiment.
FIG. 5 is a schematic diagram of a metal layer formed in an embodiment.
Fig. 6 is a schematic diagram of a semiconductor structure in an embodiment.
Fig. 7 is a schematic view of forming a barrier layer on a recess in another embodiment.
FIG. 8 is a schematic diagram of forming a buffer layer by oxidizing a portion of a barrier layer in another embodiment.
Fig. 9 is a schematic diagram of forming a seed layer on a buffer layer in another embodiment.
Fig. 10 is a schematic diagram of a seed layer and buffer layer etching the bottom of a recess in another embodiment.
FIG. 11 is a schematic view of a metal layer formed in another embodiment.
Fig. 12 is a schematic view of a semiconductor structure in another embodiment.
FIG. 13 is a schematic diagram of an etching buffer layer according to another embodiment.
Fig. 14 is a schematic view of a semiconductor structure in another embodiment.
Description of the reference numerals:
10. a substrate; 101. a semiconductor device; 102. an interconnect structure; 11. an insulating layer; 12. a first dielectric capping layer; 13. a first passivation layer; 14. a first dielectric layer; 15. a second dielectric capping layer; 16. a second passivation layer; 17. a second dielectric layer; 18. a hard mask layer; 19. a metal hard mask layer; 20. a concave portion; 201. a first opening; 202. a second opening; 21. a barrier layer; 22. a buffer layer; 23. a seed layer; 24. a metal layer; 25. a top dielectric cap layer.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present invention, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the indicated apparatus or element must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
The invention provides a semiconductor structure and a manufacturing method thereof, wherein the metal layer and the dielectric layer are well connected, the overall resistance of the metal layer is small, the resistance-capacitance delay effect is improved, meanwhile, electromigration failure (Electron Migration Fail) is reduced, and the performance of the semiconductor structure is improved. The semiconductor structure prepared by the invention can be widely applied to different types of semiconductor integrated devices, and the performance of the semiconductor device is improved.
Referring to fig. 1, in an embodiment of the present invention, a substrate 10 is provided, and the substrate 10 may be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer, or other III/V compound semiconductor materials, and the like, and also includes a stacked structure formed by these semiconductor materials, or is silicon on insulator, silicon on insulator stacked, silicon germanium on insulator, and the like.
Referring to fig. 1, in an embodiment of the present invention, a plurality of semiconductor devices 101 are disposed on a substrate 10, and the present invention is not limited to the types of semiconductor devices 101. The semiconductor device 101 is, for example, one or several of a field effect transistor (Field Effect Transistor, FET), a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a complementary Metal Oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS), an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), a high-speed recovery Diode (Fast Recovery Diode, FRD), a high-speed high-efficiency rectifying Diode (Figh Efficiency Diode, HED), a constant voltage Diode, a high-frequency Diode, a Light-Emitting Diode (LED), a gate Photo-closed Thyristor (Gate Turn off Thyristor, GTO), a Photo-triggered Thyristor (Light Triggered Thyristor, LTT), a Thyristor (Thyristor), a charge coupler (Charge Coupled Device, a CCD image sensor), a digital signal processing device (Digital Signal Processor, DSP), a Photo Relay (Photo Relay), or a microprocessor (Micro Processor), and the like, and may be specifically selected during the manufacturing process.
Referring to fig. 1, in an embodiment of the present invention, an insulating layer 11 is disposed on a substrate 10, and a plurality of interconnect structures 102 are disposed in the insulating layer 11, wherein the interconnect structures 102 are, for example, metal wires or conductive plugs, and the interconnect structures 102 are connected to a semiconductor device 101 on the substrate 10. The insulating layer 11 is an insulating material such as silicon dioxide or silicon nitride, and can isolate the semiconductor device 101 from the metal layer, prevent the semiconductor device 101 from being affected by diffusion of metal, and protect the semiconductor device 101 from damage during the preparation of the metal layer. In this embodiment, the interconnect structure 102 is made of a low-resistance conductive material such as tungsten, copper, silver or gold, so that the electrical resistance is small when the interconnect structure 102 is connected to the prepared metal layer, thereby improving the performance of the semiconductor integrated device. In other embodiments, the interconnect structure 102 is, for example, a metal electrode on the semiconductor device 101, and the insulating layer 11 is, for example, a dielectric layer, that is, the metal layer may be directly connected to the semiconductor device 101, or connected to the semiconductor device 101 through a metal wire or a conductive plug.
Referring to fig. 1, in an embodiment of the present invention, at least one dielectric layer is formed on an insulating layer 11, and in this embodiment, for example, two dielectric layers are formed for illustration. Wherein, a first dielectric cover layer 12, a first passivation layer 13 and a first dielectric layer 14 are formed on the insulating layer 11, and a second dielectric cover layer 15, a second passivation layer 16, a second dielectric layer 17, a hard mask layer 18 and a metal hard mask layer 19 are formed on the first dielectric layer 14. Wherein, the first dielectric cover layer 12 is disposed on the insulating layer 11, the first passivation layer 13 is disposed on the first dielectric cover layer 12, the first dielectric layer 14 is disposed on the first passivation layer 13, the second dielectric cover layer 15 is disposed on the first dielectric layer 14, the second passivation layer 16 is disposed on the second dielectric cover layer 15, the second dielectric layer 17 is disposed on the second passivation layer 16, the hard mask layer 18 is disposed on the second dielectric layer 17, and the metal hard mask layer 19 is disposed on the hard mask layer 18.
Please refer to fig. 1, in the present inventionIn an embodiment, the first dielectric capping layer 12 and the second dielectric capping layer 15 are, for example, silicon carbide nitride (SiCN) or silicon carbide (SiC), so as to prevent metal ions in the metal layer from diffusing into the insulating layer 11 or the first dielectric layer 14, and the first dielectric capping layer 12 and the second dielectric capping layer 15 are deposited by, for example, chemical vapor deposition (Chemical Vapor Deposition, CVD) or plasma-enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD). The first passivation layer 13 and the second passivation layer 16 are, for example, silicon dioxide (SiO) 2 ) And the like, the first passivation layer 13 and the second passivation layer 16 have high strength so as to increase the stress bearing capability of the first dielectric layer 14 or the second dielectric layer 17 in the manufacturing process and reduce the cracking condition of the first dielectric layer 14 or the second dielectric layer 17, and the first passivation layer 13 and the second passivation layer 16 are prepared by a chemical vapor deposition method, for example, by using Tetraethoxysilane (TEOS) as a raw material to deposit the first passivation layer 13. The first dielectric layer 14 and the second dielectric layer 17 are made of Low dielectric constant (Low-K) materials such as silicon fluoride (SiF), silicon oxycarbide (SiOC), or silicon oxyfluoride (SiOF) to improve reliability of the semiconductor integrated device, and the first dielectric layer 14 and the second dielectric layer 17 may be deposited by chemical vapor deposition or Low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or the like. In this embodiment, the thickness of the first dielectric layer 14 or the second dielectric layer 17 is, for example, 40nm to 55nm, and the thicknesses of the cover layer and the passivation layer may be selected according to the manufacturing requirements of the semiconductor integrated device.
Referring to fig. 1, in an embodiment of the present invention, the hard mask layer 18 is, for example, silicon oxide or silicon nitride, and the hard mask layer 18 is, for example, prepared by a low pressure chemical vapor deposition method, and in the subsequent preparation, the hard mask layer 18 is used as a protection layer for the second dielectric layer 17. The metal hard mask layer 19 is, for example, titanium, tantalum nitride, or titanium nitride, and the metal hard mask layer 19 is formed by, for example, physical vapor deposition or atomic layer deposition (Atomic Layer Deposition, ALD) to control the morphology and quality of the opening. In this embodiment, the thickness of the metal hard mask layer 19 is, for example, 5nm to 15nm, and the thickness of the hard mask layer 18 is, for example, 5nm to 10nm.
Referring to fig. 1 to 2, in an embodiment of the present invention, after forming a dielectric layer, a plurality of recesses 20 are formed in the dielectric layer. In the present embodiment, the recess 20 includes, for example, a first opening 201 and a second opening 202, the first opening 201 is provided on the interconnect structure 102, the second opening 202 is provided on the first opening 201, and the recess 20 is completed by two-step etching. Specifically, a patterned photoresist layer (not shown) is formed on the metal hard mask layer 19 to locate the first opening 201, and the first opening 201 is formed by etching, and the first opening 201 exposes the interconnect structure 102. After the first opening 201 is formed, the patterned photoresist layer is removed, and another patterned photoresist layer (not shown) is formed again to locate the second opening 202, and etching is performed to form the second opening 202, i.e. the recess 20 is formed. The second opening 202 corresponds to the center of the first opening 201, and the second opening 202 is etched to the second passivation layer 16.
Referring to fig. 2, in one embodiment of the present invention, in forming the recess 20, for example, by a dry etching process, the recess 20 is formed, and the etching gas may be, for example, trifluoromethane (CHF) 3 ) Difluoromethane (CH) 2 F 2 ) Nitrogen trifluoride (NF) 3 ) Sulfur hexafluoride (SF) 6 ) Nitrogen (N) 2 ) Or oxygen (O) 2 ) Or the like, or a combination of one or more gases. In other embodiments, the recess 20 may be formed using a combination of dry etching and wet etching processes or a wet etching process. In other embodiments, when a dielectric layer is disposed on the substrate 10, the recess may be formed by etching directly onto the interconnect structure 102 by a single etch, which may be selected according to the manufacturing process.
Referring to fig. 2 to 3, in an embodiment of the present invention, after forming the recess 20, a multi-layer barrier structure is formed on the sidewall and bottom of the recess 20 and the insulating layer 11, and the multi-layer barrier structure includes, for example, sequentially forming a barrier layer 21, a buffer layer 22 and a seed layer 23. Wherein a buffer layer 22 is provided on the barrier layer 21 and a seed layer 23 is provided on the buffer layer 22. In this embodiment, the barrier layer 21 is formed by physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition, atomic layer deposition, or the like, and the barrier layer 21 is a substance with good adhesion, such as tantalum (Ta), titanium (Ti), ruthenium (Ru), tantalum nitride (TaN), or titanium nitride (TiN), and the thickness of the barrier layer 21 is, for example, 2nm to 8nm. By providing the barrier layer 21, adhesion of the metal layer to the sidewalls of the recess 20 is enhanced, electromigration is reduced, and electrical performance of the semiconductor structure is improved. The buffer layer 22 is formed by physical vapor deposition, sputtering, or the like, for example, and the buffer layer 22 is a thin layer of the same material as the metal layer, such as a copper layer, for example, and the thickness of the buffer layer 22 is 2nm to 5nm, for example. The seed layer 23 is formed, for example, by physical vapor deposition or sputtering, and the seed layer 23 is a doped thin layer of the same material as the metal layer, for example, a doped layer of copper, wherein the doped ions are one or more of manganese, magnesium, zirconium, etc., and the thickness of the seed layer 23 is, for example, 10 nm-60 nm. By providing the doped seed layer 23, reliability and tolerance of the metal layer are enhanced.
Referring to fig. 2 to 4, in an embodiment of the invention, after forming the barrier layer 21, the buffer layer 22 and the seed layer 23, the seed layer 23 at the bottom of the first opening 201 is removed by etching back. Specifically, the seed layer 23 at the bottom of the first opening 201 is removed, for example, by in situ etching, for example, the substrate 10 is bombarded with an argon Plasma (Ar Plasma) to sputter etch the seed layer 23 at the bottom of the first opening 201, the sputtering direction being perpendicular to the substrate 10, whereby the seed layer 23 at the bottom of the first opening 201 is removed under the argon Plasma sputter etch. In the etching process, the direct current power (DC power) is 500-1000W, the alternating current bias power (AC bias) is 750-1300W, and the flow rate of argon is 1-20 sccm. By controlling the etching conditions, it is ensured that only the seed layer 23 at the bottom of the first opening 201 is removed.
Referring to fig. 4 to 5, in an embodiment of the invention, after etching the seed layer at the bottom of the first opening, a metal layer 24 is deposited in the recess 20, and the metal layer 24 is, for example, a metal copper layer, a metal aluminum layer, or a metal tungsten layer. In the present embodiment, the metal layer 24 is, for example, a metal copper layer, the metal layer 24 is formed, for example, by physical vapor deposition or electroplating, and the metal layer 24 fills the recess 20 to cover the seed layer 23. The metal layer 24 and the interconnection structure 102 are connected through the barrier layer 21 and the buffer layer 22, and the buffer layer 22 and the metal layer 24 are made of the same material, so that the resistance of the semiconductor structure can be reduced, and meanwhile, the problems of resistance-capacitance delay effect, electromigration failure and the like of the metal interconnection are reduced. A barrier layer 21, a buffer layer 22 and a seed layer 23 are provided between the metal layer 24 and the sidewall of the recess 20, and three layers of protection are provided on the sidewall of the recess 20, so that the electromigration phenomenon of the metal layer can be blocked, and the reliability and tolerance of the metal layer can be enhanced.
Referring to fig. 5 to 6, in an embodiment of the present invention, after forming the metal layer 24, a planarization process is performed, for example, a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process is performed to remove the metal layer 24, the seed layer 23, the buffer layer 22, the barrier layer 21, the metal hard mask layer 19 and the hard mask layer 18 on the second dielectric layer 17, so as to ensure that the metal layer 24 in the recess is level with the second dielectric layer 17 on both sides. A top dielectric cap layer 25 is formed over the metal layer 24 and the second dielectric layer 17, and the top dielectric cap layer 25 is formed, for example, by chemical vapor deposition or the like, the top dielectric cap layer 25 being, for example, silicon carbide nitride or silicon carbide or the like, to prevent diffusion of the metal layer into the dielectric layer during annealing. After forming the top dielectric cap layer 25, a tempering process is performed, and the tempering temperature is, for example, 400 ℃ to 450 ℃. By tempering, the interface performance of the metal layer and the dielectric covering layer can be improved, the interface bonding energy can be improved, and the electromigration failure phenomenon can be reduced.
Referring to fig. 7 to 13, another method for fabricating a semiconductor structure is provided in another embodiment of the present invention. The step of forming the concave portion 20 and the step before the concave portion 20 are the same as the above-described forming step, and will not be described here.
Referring to fig. 7, in one embodiment of the present invention, after forming the recess 20, a multi-layer barrier structure is formed on the sidewall and bottom of the recess 20 and the insulating layer 11. In this embodiment, the barrier layer 21 is formed first, for example, by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like, and the barrier layer 21 is made of a material with good adhesion, for example, tantalum, titanium, tungsten, ruthenium, copper, tantalum nitride, tungsten nitride, ruthenium nitride, rhodium nitride, or titanium nitride, and the thickness of the barrier layer 21 is, for example, 4nm to 13nm. By providing the barrier layer 21, adhesion of the metal layer to the sidewalls of the recess 20 is enhanced, electromigration is reduced, and electrical performance of the semiconductor structure is improved.
Referring to fig. 7 to 8, in an embodiment of the present invention, after forming the barrier layer 21, a portion of the barrier layer 21 is oxidized, and a buffer layer 22 is formed on the barrier layer 21. Wherein the barrier layer 21 is oxidized for 10s to 20s in an oxygen atmosphere at a temperature of 500 ℃ to 950 ℃ and a pressure of 10t to 30t, for example, to form a buffer layer 22 with a thickness of 2nm to 5nm, and the buffer layer 22 is copper oxynitride, tantalum oxynitride, titanium oxynitride, tungsten oxynitride, ruthenium oxynitride, rhodium oxynitride, titanium oxide, tungsten oxide, ruthenium oxide or rhodium oxide, or combinations thereof, for example. By providing a thicker barrier layer 21, the barrier layer 21 is then partially oxidized to form a buffer layer 22 composed of oxide, and at the same time, the thickness of the remaining barrier layer 21 is, for example, 2nm to 8nm. On the one hand, the blocking effect of the blocking layer 21 on electrons in the later metal layer is ensured, on the other hand, the self-alignment of the buffer layer 22 and the blocking layer 21 can be realized, and the buffer layer 22 composed of oxide can reduce the electron scattering of copper grains and reduce the resistance of the copper metal layer, while the buffer layer 22 composed of oxide can increase the resistance of the metal layer at the bottom of the first opening 201, the increase of the resistance is smaller than the resistance reduced by reducing the electron scattering of copper grains, namely, the resistance of the metal layer is reduced as a whole.
Referring to fig. 8 to 9, in an embodiment of the present invention, after forming the buffer layer 22, a seed layer 23 is formed on the buffer layer 22 to form a multi-layer barrier structure. The seed layer 23 is formed, for example, by physical vapor deposition or sputtering, and the seed layer 23 is a doped thin layer of the same material as the metal layer, for example, a doped layer of copper, wherein the doped ions are one or more of manganese, magnesium, zirconium, and the like, and the thickness of the seed layer 23 is, for example, 2nm to 8nm. By providing a doped seed layer 23, the reliability and tolerance of the metal layer is enhanced.
Referring to fig. 7, 9 and 10, in an embodiment of the present invention, after forming the seed layer 23, the seed layer 23 and the buffer layer 22 at the bottom of the first opening 201 are removed by etching. Specifically, the seed layer 23 and the buffer layer 22 at the bottom of the first opening 201 are removed, for example, by in-situ etching, for example, the substrate 10 is bombarded with an argon plasma to sputter etch the seed layer 23 and the buffer layer 22 at the bottom of the first opening 201, the sputtering direction being perpendicular to the substrate 10, so that the seed layer 23 and the buffer layer 22 at the bottom of the first opening 201 are removed under the argon plasma sputter etching. In the etching process, the DC power is 500-1000W, the AC bias power is 750-1300W, and the flow rate of argon is 1-20 sccm. By controlling the etching conditions, it is ensured that only the seed layer 23 and the buffer layer 22 at the bottom of the first opening 201 are removed.
Referring to fig. 10 to 11, in an embodiment of the invention, after etching the seed layer 23 and the buffer layer 22 at the bottom of the first opening, a metal layer 24 is deposited in the recess 20, and the metal layer 24 is, for example, a metal copper layer, a metal aluminum layer, or a metal tungsten layer. In the present embodiment, the metal layer 24 is, for example, a metal copper layer, the metal layer 24 is formed, for example, by physical vapor deposition or electroplating, and the metal layer 24 fills the recess 20 to cover the seed layer 23. The metal layer 24 is connected with the interconnection structure 102 through the barrier layer 21, so that the resistance of the semiconductor structure can be effectively reduced, and meanwhile, the problems of resistance-capacitance delay effect, electromigration failure and the like of the metal interconnection are reduced. The barrier layer 21, the buffer layer 22 and the seed layer 23 are arranged between the metal layer 24 and the side wall of the concave portion 20, and three layers of protection are arranged on the side wall of the concave portion 20, so that the electromigration phenomenon of the metal layer can be blocked, and the reliability and the tolerance of the metal layer are enhanced.
Referring to fig. 11 to 12, in an embodiment of the present invention, after forming the metal layer 24, a planarization process is performed, for example, a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process is performed to remove the metal layer 24, the seed layer 23, the buffer layer 22, the barrier layer 21, the metal hard mask layer 19 and the hard mask layer 18 on the second dielectric layer 17, so as to ensure that the metal layer 24 in the recess is level with the second dielectric layer 17 on both sides. A top dielectric cap layer 25 is formed over the metal layer 24 and the second dielectric layer 17, and the top dielectric cap layer 25 is formed, for example, by chemical vapor deposition or the like, the top dielectric cap layer 25 being, for example, silicon carbide nitride or silicon carbide or the like, to prevent diffusion of the metal layer into the dielectric layer during annealing. After forming the top dielectric cap layer 25, a tempering process is performed, and the tempering temperature is, for example, 400 ℃ to 450 ℃. By tempering, the interface performance of the metal layer and the dielectric covering layer can be improved, the interface bonding energy is improved, and the electromigration failure phenomenon is reduced. Meanwhile, during the tempering process, the doped ions in the seed layer 23 are accumulated at the interface between the seed layer 23 and the oxide buffer layer 22, the proportion of the added elements in the overall metal layer is reduced, the electron scattering of the copper grains is also reduced due to the presence of the oxide buffer layer 22, and the overall resistance is reduced. The additive elements are arranged outside the barrier layer, so that the copper metal layer can keep good reliability.
Referring to fig. 7, 8, 13 and 14, in another embodiment of the present invention, after forming the buffer layer 22, the buffer layer 22 at the bottom of the first opening 201 is removed by etching. Specifically, the buffer layer 22 at the bottom of the first opening 201 is removed, for example, by in-situ etching, for example, the substrate 10 is bombarded with argon plasma to sputter etch the buffer layer 22 at the bottom of the first opening 201, and the sputtering direction is perpendicular to the substrate 10, so that the buffer layer 22 at the bottom of the first opening 201 is removed under the argon plasma sputter etching. In the etching process, the DC power is 500-1000W, the AC bias power is 750-1300W, and the flow rate of argon is 1-20 sccm. The etching conditions are controlled to ensure that only the buffer layer 22 at the bottom of the first opening 201 is removed. That is, after the buffer layer 22 composed of oxide is formed, etching may be performed to remove the buffer layer 22 at the bottom of the first opening 201, so as to reduce the increase of the resistance value of the metal layer caused by the oxide buffer layer 22 at the bottom of the first opening 201, and further reduce the resistance value of the semiconductor structure. In this embodiment, after the buffer layer 22 is etched, the seed layer 23 is formed, and the seed layer 23 is formed on the barrier layer 21 at the bottom of the first opening and on the buffer layer 22 on the sidewall of the recess 20, and after the seed layer 23 is formed, the seed layer 23 is not etched back, and the deposition of the metal layer is directly performed, and the subsequent process is consistent with the above process and will not be described herein. In the formed semiconductor structure, the barrier layer 21 and the seed layer 23 are arranged between the bottom of the first opening 201 and the interconnection structure 102 in the metal layer 24, and the barrier layer 21, the buffer layer 22 and the seed layer 23 are arranged at the contact position of the metal layer 24 and other components in the rest area, so that the overall resistance value of the semiconductor structure can be reduced when the reliability of the semiconductor structure is improved.
In summary, the present invention provides a semiconductor structure and a method for fabricating the same, wherein a multi-layer barrier structure is formed in a recess when a metal layer is formed, the multi-layer barrier structure including a barrier layer, a buffer layer and a seed layer. The seed crystal layer is a doped metal layer, the buffer layer is a metal layer or an oxide layer which is the same as the metal layer, the blocking layer is a metal layer or a metal nitride layer, and then the seed crystal layer, the buffer layer or the seed crystal layer and the buffer layer at the bottom of the concave part are removed through back etching, so that the reliability and the tolerance of the semiconductor structure are improved. Meanwhile, the overall resistance of the semiconductor structure is reduced, the resistance-capacitance delay effect is improved, the electromigration problem is reduced, and the electrical performance of the semiconductor structure is improved.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (6)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate, and forming a plurality of semiconductor devices in the substrate;
forming at least one dielectric layer on the substrate;
forming a plurality of concave parts in the dielectric layer through two-step etching, wherein the concave parts comprise a first opening and a second opening, and the second opening corresponds to the center of the first opening; the concave part is connected with the semiconductor device, the side wall and the bottom of the concave part are provided with a multi-layer blocking structure, and the number of layers of the blocking structure on the bottom of the concave part is smaller than that of the blocking structure on the side wall of the concave part; and
forming a metal layer within the recess;
the barrier structure comprises a barrier layer, a buffer layer and a seed crystal layer, wherein the barrier layer is arranged on the side wall and the bottom of the concave part, the buffer layer is arranged on the barrier layer, and the seed crystal layer is arranged on the buffer layer;
the seed crystal layer is a doped seed crystal layer, and the doped ions are at least one of manganese, magnesium or zirconium;
forming the barrier structure on the bottom of the recess by back-etching the buffer layer, the seed layer, or the buffer layer and the seed layer, the barrier structure on the bottom of the recess being one of the barrier layer, the combination of the barrier layer and the seed layer, or the combination of the barrier layer and the buffer layer;
the buffer layer is formed by physical vapor deposition, sputtering or oxidizing part of the barrier layer, and is a seed layer of the same material as the metal layer, or is an oxide obtained by oxidizing part of the barrier layer.
2. The method of claim 1, wherein the barrier structure on the sidewall of the recess comprises the barrier layer, the buffer layer, and the seed layer.
3. The method of claim 1, wherein the buffer layer is at least one of copper oxynitride, tantalum oxynitride, titanium oxynitride, tungsten oxynitride, ruthenium oxynitride, rhodium oxynitride, titanium oxide, tungsten oxide, ruthenium oxide, or rhodium oxide.
4. The method of fabricating a semiconductor structure of claim 1, wherein the method of fabricating a barrier structure comprises:
forming a barrier layer on the side wall and the bottom of the concave part;
forming a buffer layer on the barrier layer;
forming a seed layer on the buffer layer; and
and etching back the seed crystal layer, and removing the seed crystal layer at the bottom of the concave part.
5. The method of fabricating a semiconductor structure of claim 1, wherein the method of fabricating a barrier structure comprises:
forming a barrier layer on the side wall and the bottom of the concave part;
oxidizing the barrier layer with partial thickness, and forming a buffer layer on the barrier layer;
forming a seed layer on the buffer layer; and
and etching back the seed crystal layer and the buffer layer, and removing the seed crystal layer and the buffer layer at the bottom of the concave part.
6. The method of fabricating a semiconductor structure of claim 1, wherein the method of fabricating a barrier structure comprises:
forming a barrier layer on the side wall and the bottom of the concave part;
oxidizing the barrier layer with partial thickness, and forming a buffer layer on the barrier layer;
etching back the buffer layer, and removing the buffer layer at the bottom of the concave part; and
a seed layer is formed over the buffer layer and the barrier layer.
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