CN118606259A - Bridging chip, multi-chip communication method and system - Google Patents

Abstract

A bridging chip, a multi-chip communication method and a system relate to the technical field of chips, and the bridging chip comprises: the system comprises a DSP core, a BUS BUS, an HIC controller, an XBAR unit, a DMA controller, a plurality of SPI interfaces, a plurality of FSI interfaces, an EMIF interface and a plurality of CANFD interfaces; the HIC controller comprises an HIC interface; the DSP core is connected with the BUS BUS through the DMA controller, and the DSP core is directly connected with the BUS BUS; the HIC controller is configured to control a plurality of peripheral frames FP; one path of SPI interface and one path of FSI interface are connected with one path of peripheral frame FP; the EMIF interface is connected to a peripheral frame FP. The bridge chip provided by the invention solves the problem that the DSP chip without the CANFD module continues to be applied, and expands various communication interfaces, so that the communication among various chips becomes simple and quick.

Description

Bridging chip, multi-chip communication method and system

Technical Field

The present invention relates to the field of chip technologies, and in particular, to a bridge chip, a multi-chip communication method and a system.

Background

Today, where technology is growing, there is a greater demand for chip performance, but the computational power and the number of communication interfaces of DSP chips are insufficient to meet the increasing demands of customers.

Especially in recent years, new energy automobiles are rising, and demands for communication speed, stability and power are greater and increasing. CANFD communication is now commonly used for communication of components of automobiles, CANFD (Controller Area Network Flexible Data-Rate) being a communication standard based on CAN (Controller Area Network) protocol, which aims to increase the data transmission Rate and capacity of the on-board network. CAN FD is extended on the basis of the traditional CAN protocol to support higher data transmission speed and larger data frame; and the CANFD module is not arranged in the design stage of the original DSP chip, so that the application of the original DSP in the field of new energy automobiles is far limited.

There are two general methods available: the first method is to improve the performance of a single DSP chip and integrate CANFD peripherals in the single chip; the second method is that a plurality of DSP chips cooperatively process things.

However, in the prior art, the method for improving the performance of a single DSP chip has the defects that the period from chip design to mass production is long, the design difficulty of performance improvement is high, the demand of an application end on the chip increases relatively rapidly, and the market is difficult to meet rapidly; in order to meet the requirement of automobile use, the problem of how to continue to apply the DSP chip without the CANFD module in the new energy automobile field is needed to be solved.

Disclosure of Invention

In order to overcome the defects in the background technology, the invention discloses a bridge chip, a multi-chip communication method and a system.

In order to achieve the aim of the invention, the invention adopts the following technical scheme:

In a first aspect, the invention discloses a bridge chip, which takes a DSP architecture as a main body and comprises a DSP core, a BUS BUS, an HIC controller, an XBAR unit, a DMA controller, SPI interfaces of a first preset number path, FSI interfaces of a second preset number path, EMIF interfaces of one path and CANFD interfaces of a third preset number path; the HIC controller comprises an HIC interface; the DSP core is connected with the BUS BUS through the DMA controller, and the DSP core is directly connected with the BUS BUS; the HIC controller is configured to control a fourth preset number of peripheral frames FP; one path of SPI interface and one path of FSI interface are connected with one path of peripheral frame FP; the EMIF interface is connected with one path of peripheral frames FP; every 4 CANDFD interfaces are connected with one path of peripheral frames FP; the HIC interface, the SPI interface, the FSI interface, the EMIF interface and the CANFD interface are all connected with the GPIO interface through XBAR units; the peripheral frames are connected with the BUS; the XBAR unit is used for mapping each peripheral GPIO to different physical positions of the bridge chip.

Specifically, a DSP core or HIC controller may act as a host to control the BUS via the BUS interface.

Specifically, the HIC controller has two GPIO port mappings, one of which is used for HIC interface communication.

Specifically, the EMIF interface and the HIC interface are parallel interfaces and are master-slave interfaces.

Specifically, the first preset number is equal to the second preset number in value and is greater than 0; the third preset number is a multiple of 4 and is greater than 0; the fourth preset number is the sum of the first preset number and the third preset number.

In a second aspect, the present invention discloses a multi-chip communication method, including the first bridge chip and the second bridge chip of the above-mentioned bridge chip types, where the first bridge chip and the second bridge chip communicate through a parallel bus interface HIC-EMIF.

Specifically, the communication between the first bridge chip and the second bridge chip through the parallel bus interface HIC-EMIF is specifically: the first bridge chip is used as a host, the second bridge chip is used as a slave, the EMIF interface of the first bridge chip is used as a host interface to actively control the HIC of the second bridge chip, the first bridge chip actively transmits a read-write command to the second bridge chip, and the second bridge chip receives command write data of the first bridge chip or read data to the first bridge chip through the HIC interface.

In a third aspect, the present invention discloses a multi-chip communication method, which includes the bridge chip, a first host DSP1 having an EMIF interface, and a second host DSP2 having an EMIF interface, where the first host DSP1 and the second host DSP2 are respectively connected to the bridge chip HIC through the EMIF interface for communication.

In a fourth aspect, the present invention discloses a multi-chip communication system comprising: the central bridge chip and the plurality of DSP chips are sealed into a sealed chip, GPIO of the selected interconnection communication interface is connected to a pin of the central bridge chip, and other GPIOs are bound to a PAD pin of the sealed chip to be used as GPIOs of the sealed chip; the central bridge chip is the bridge chip.

Specifically, the central bridge chip is a bridge chip set that a plurality of bridge chips are connected through a parallel bus interface HIC-EMIF; the plurality of DSP chips are one or more combinations of DSP chips comprising SPI, FSI, EMIF and HIC peripheral interfaces.

The bridge chip provided by the invention is in line with the traditional DSP and the advanced DSP, can normally perform high-speed stable communication, integrates a plurality of SPIs and a plurality of FSI serial interfaces, integrates a HIC interface and an EMIF parallel interface as the bridge chip, is communicated with a plurality of external DSP host computers for control, is additionally provided with a CANFD communication module, solves the problem that the DSP chip without the CANFD module in the original design stage can be continuously applied in the field of new energy automobiles, expands a plurality of communication interfaces, and ensures that the communication among a plurality of chips becomes simple and quick through the bridge chip.

In addition, the EMIF interface and the HIC interface in the bridge chip are parallel interfaces, the communication speed is multiple times of that of the serial interfaces SPI and FSI, the HIC interface and the EMIF interface are integrated in the bridge chip, and when no external host or slave bridge chip is arranged, multi-chip communication can be carried out through the characteristics of the bridge chip.

The multi-chip communication method provided by the invention can carry out multi-chip cooperative processing communication through the bridging chip, can rapidly meet the requirements of the market on the chip performance, reduces the design period and the application design period, accelerates the product investment in the market, and effectively reduces the cost.

The multi-chip communication system provided by the invention adopts modularized and standardized interfaces, so that when the integrated chip needs to be upgraded or new functions are added, the whole integrated chip can be omitted, a designer can select a proper functional module according to the needs, only the corresponding interface is replaced or upgraded in the bridging chip, and the corresponding functional chip or module is added or replaced in the integrated chip, so that the multi-chip communication system can be quickly integrated into the existing system, and the technical difficulty and cost are greatly reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a bridge chip according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a bridge chip to multi-chip connection according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of two bridge chips interconnected according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating interconnection communication between two EMIF hosts through a bridge chip according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of communication between multiple bridge chips according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a multi-chip encapsulation system according to an embodiment of the present invention.

Detailed Description

The present application will be explained in detail by the following examples, and the purpose of the present application is to protect all technical improvements within the scope of the present application, and in the description of the present application, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "front", "rear", "left", "right", etc., only correspond to the drawings of the present application, and in order to facilitate description of the present application, it is not necessary to indicate or imply that the apparatus or element referred to has a specific orientation.

Some terms related to the present embodiment are explained below:

（1）DSP

A DSP (DIGITAL SIGNAL Processor) is a digital Processor, a microprocessor specifically designed for digital signal processing tasks. They typically contain one or more Central Processing Units (CPUs) of the harvard architecture, an Arithmetic Logic Unit (ALU) dedicated to processing digital signals, a flash memory, and an interface for input/output (I/O) operations.

（2）HIC

HIC (Host Interface Controller) is a host interface controller, a hardware component that allows a computer host to communicate with external devices or networks. HIC can take many forms, depending on its design and use, but it is generally responsible for managing data transmission, signal conversion, and protocol processing to ensure efficient communication between a host and an external device.

（2）EMIF

EMIF (External Memory Interface) is an external memory interface, which is an interface that allows a microprocessor or microcontroller to communicate with external memory devices such as Dynamic Random Access Memory (DRAM), static Random Access Memory (SRAM), flash memory, etc. EMIF is commonly used in embedded systems to extend the storage capacity of the system or to provide access to mass storage.

（4）GPIO

GPIO (General Purpose Input/Output) is an interface used in electronic and computer engineering that allows a user to control electrical signals on hardware devices. GPIO interfaces are commonly used in microcontrollers, expansion cards, and other various electronic devices to read input signals or send control signals to external devices.

（5）SPI

SPI (SERIAL PERIPHERAL INTERFACE ) is a commonly used serial communication protocol for communication between microcontrollers, microprocessors and peripheral devices. The SPI interface is typically composed of four signal lines:

（6）FSI

FSI (Fast Serial Interface) is a fast serial interface for high speed data transfer between chips or devices.

（7）DMA

DMA (Direct Memory Access) the controller is a hardware component that manages all aspects of the data transfer, including the source and destination addresses of the data transfer, the amount of data transferred, and the operations after the transfer is completed. When the DMA transfer is completed, the DMA controller may notify the CPU via an interrupt. The DMA controller allows the peripheral to directly access the system memory without intervention from the CPU. In this way, DMA can significantly increase the efficiency and speed of data transfer, as it reduces the burden on the CPU, allowing the CPU to handle other tasks while data transfer is in the background.

（8）BUS

In a DSP chip, BUS refers to a data path for connecting different components inside the chip. These components may include a CPU, memory, peripheral interfaces, ALUs (arithmetic logic units), registers, and the like. The presence of a bus allows for efficient data transfer and communication between these components.

Example 1

Referring to fig. 1, the present embodiment provides a bridge chip, which takes a DSP architecture as a main body, and includes a DSP core, a BUS, an HIC controller, an XBAR unit, a DMA controller, a first preset number of SPI interfaces, a second preset number of FSI interfaces, an EMIF interface, and a third preset number of CANFD interfaces; the HIC controller comprises an HIC interface; the DSP core is connected with the BUS BUS through the DMA controller, and the DSP core is directly connected with the BUS BUS; the HIC controller is configured to control a fourth preset number of peripheral frames FP; one path of SPI interface and one path of FSI interface are connected with one path of peripheral frame FP; the EMIF interface is connected with one path of peripheral frames FP; every 4 CANDFD interfaces are connected with one path of peripheral frames FP; the HIC interface, the SPI interface, the FSI interface, the EMIF interface and the CANFD interface are all connected with the GPIO interface through XBAR units; the peripheral frames are connected with the BUS; the XBAR unit is used for mapping each peripheral GPIO to different physical positions of the bridge chip.

Specifically, the DSP core or HIC controller may act as a host to control the BUS via the BUS interface;

Specifically, the HIC controller has two GPIO port mappings, one of which is used for HIC interface communication. The other path of GPIO can be used for other functions, and the HIC controller of the embodiment can realize that the DSP bus bridges other peripheral frames through controlling the peripheral frames.

When the SPI interface and the FSI interface are used for multi-chip communication, since the peripheral devices belonging to the same Peripheral Frame (PF) in the DSP cannot be accessed by different host buses at the same time, for example, when the bridge chip core accesses the SPI of the peripheral frame 1, the SPI in the peripheral frame 2 or the peripheral frame 3 can be accessed by the DMA or HIC host at the same time. The SPI and FSI in the bridge DSP are designed to be in one peripheral frame, so that the blocking of the bus in the peripheral frame can be reduced when the FSI is used for connecting the external bridge DSP, and the host can only operate one peripheral at the same time when sending a command to one peripheral frame. The HIC of this embodiment may control peripheral frames to enable access to the SPI, FSI interface.

Specifically, the first preset number is equal to the second preset number in value and is greater than 0;

The values of the first preset number and the second preset number can be set according to actual requirements, and preferably, in this embodiment, the values of the first preset number and the second preset number are both 4.

Specifically, the third preset number is a multiple of 4 and greater than 0;

The third preset number value may be set according to actual requirements, and preferably, in this embodiment, the value of the third preset number is 8.

Specifically, the fourth preset number is the sum of the first preset number and the third preset number.

Specifically, the EMIF interface and the HIC interface are parallel interfaces and are master-slave interfaces.

Specifically, the bridge chip further includes an internal register and a memory.

The DSP is used as a digital signal processing chip, and generally 1 to a plurality of SPI interfaces are integrated for communication, and the communication speed of the SPI interfaces can reach 20MHz at the highest speed, so that the SPI interfaces can be used as communication interfaces between the bridge chip and the DSP; secondly, the current advanced DSP products not only have a slow communication interface SPI but also have a high-speed interface FSI or parallel processing interfaces HIC and EMIF with the speed reaching 100 MHz.

The bridge chip provided in this embodiment is redesigned by taking the DSP architecture as a main body, and external interfaces such as SPI, FSI, EMIF and HIC are added to be used as a communication bridge between hosts. As the bridge is used as a multi-chip sealing bridge, the sealing positions of the DSPs need to be adjusted, XBAR units are added in the chips for mapping the peripheral GPIOs to different physical positions bridging the DSP chips, so that the multi-chip sealing is convenient.

The bridge chip comprises the following characteristics:

1) An HIC controller may have two GPIO mapping options, which are designed to use a bridge chip to connect two EMIF interface integrated DSP chips through the HIC interface, and to select which EMIF DSP the bridge chip communicates with at a time through an interrupt signal. For example: the HIC controller may control peripheral frames FP1, FP2, FP3, FP4, FP5, FP6,7.

2) One path of EMIF interface of the bridge chip can be connected with a DSP of an external HIC interface in a host DSP of the bridge chip to control the writing and reading of external DSP data, and then a multi-core chip interconnection communication system can be formed by the HIC of the bridge DSP chip.

3) The SPI interface is used for interconnection of the traditional DSP chips. The external DSP chip is connected with the SPI interface in the bridge chip, and data movement among the multiple DSPs is carried out through a custom data frame format.

The embodiment provides a custom data frame format, the corresponding data of the format can be divided into three parts, the first part uses 16bit data as a read-write command, the second part uses 16bit data as a read-write starting address, and the third part starts to be read-write data.

In practical applications, the format of the data frame may be customized according to specific requirements and designs, where factors such as data integrity, transmission efficiency, error detection and correction need to be considered during design. In implementing custom data frame formats, both the sending and receiving parties must follow exactly the same protocol to ensure proper transmission of the data.

4) The FSI high-speed interface is used for interconnection of newer DSP chips, an external DSP chip is connected with the FSI interface in the bridge chip, and the data frame format is customized to carry out data movement among multiple DSPs.

5) The XBAR is used as each peripheral module or interface module PAD mapping, and the module can say that the peripheral interface is mapped to any DSP physical position. Because the bridging DSP chip is connected with a plurality of external pins and is complex when the chips are communicated, the XBAR function is changed, so that the connection of the chips is flexible. XBAR is similar to gpiomux, signals input by PAD can be selectively transmitted to all places inside the DSP, and signals inside the DSP can be transmitted to other places (all peripheral devices and the interior of the DSP can be designed by themselves).

6) The CANFD interface is used for external lan communication, receiving multi-chip external data, storing the received data in the bridge chip, and transmitting the received data to other DSP chips by the SPI, FSI, HIC, EMIF interface.

The DSP chip basically comprises a BUS, the BUS comprises a BUS interface, and the DSP core or the HIC controller can be used as a host computer to control the BUS through the BUS interface, so that data transmission and communication between various components and peripheral equipment are achieved.

Because the peripheral frames are bus branches, namely SPI and FSI belong to one bus branch, when the SPI interface and the FSI interface are used for multi-chip communication, the SPI interface and the FSI interface cannot be accessed by different host buses at the same time because the SPI interface and the FSI interface belong to the peripheral in one Peripheral Frame (PF) in the DSP, so that the buses cannot simultaneously access two or more peripheral under the same branch.

For example, when the bridge chip kernel accesses the SPI of peripheral frame 1, the SPI in peripheral frame 2 or peripheral frame 3 may be accessed by the DMA or HIC host at the same time. The SPI and FSI in the bridge chip are designed to be in one peripheral frame, so that the blocking of the bus in the peripheral frame can be reduced when the FSI is used for connecting the external bridge DSP (only one peripheral can be operated at the same time when the host sends a command to one peripheral frame).

The EMIF interface in the bridge chip is used as a parallel host interface to control the DSP of the external storage or external integrated HIC interface, when the bridge chip needs to read the DSP of the external integrated HIC interface by using the EMIF, the DSP of the external HIC interface only needs to send a read-write command through the EMIF interface, and the DSP of the external HIC interface reads and writes the external HIC interface through the received command.

The HIC interface of the bridge chip can be used as a slave of the host DSP integrated with the EMIF interface, and is communicated with the host DSP, and the HIC interface and the EMIF interface are master-slave interfaces. When HIC is connected to EMIF interface of host DSP, DSP host sends read-write command to bridge HIC interface through EMIF interface to operate internal register and memory of bridge chip.

The bridge chip provided by the embodiment is in line with the traditional DSP and the advanced DSP, can normally perform high-speed stable communication, integrates 4 SPI (serial peripheral interface) and 4 FSI (serial peripheral interface) and integrates one HIC interface and one EMIF parallel interface as the bridge chip, and is communicated with a plurality of external DSP host computers for control, and a CANFD (compact form factor digital) communication module is added in the bridge chip, so that the DSP chip without the CANFD module in the original design stage can be continuously applied in the field of new energy automobiles, various communication interfaces are expanded, and communication among various chips becomes simple and quick through the bridge chip.

As can be seen from the structure diagram shown in fig. 2, a single bridge in the bridge chip multi-chip interconnection disclosed in this embodiment can interconnect 4 SPI host DSPs (DSP 1-DSP 4), 4 FSI host DSPs (DSP 5-DSP 8), one EMIF host DSP (DSP 9), one HIC slave DSP (DSP 10) and 8 CANFD, so that not only can a plurality of inter-chip communications be realized, but also CANFD communication data can be received from the bridge.

In addition, the EMIF interface and the HIC interface in the bridge chip are parallel interfaces, the communication speed is multiple times of that of the serial interfaces SPI and FSI, the HIC interface and the EMIF interface are integrated in the bridge chip, and when no external host or slave bridge chip is arranged, multi-chip communication can be carried out through the characteristics of the bridge chip.

Example two

The embodiment provides a multi-chip communication method, which includes a first bridge chip and a second bridge chip of the bridge chip type described in the first embodiment, wherein the first bridge chip and the second bridge chip communicate through a parallel bus interface HIC-EMIF.

Specifically, the first bridge chip is used as a host, the second bridge chip is used as a slave, the EMIF interface of the first bridge chip is used as a host interface to actively control the HIC of the second bridge chip, the first bridge chip actively transmits a read-write command to the second bridge chip, and the second bridge chip receives command write data or read data of the first bridge chip to the first bridge chip through the HIC interface.

Because the bridge chip design has an HIC (host interface controller) bus and an EMIF (external memory interface), interconnection topology between the bridge chips DSP can be realized through a high-speed parallel bus. As can be seen from the above characteristics of the bridge chip, the HIC controller can use two-way interface selection, so there are various ways of interconnecting the bridge chips.

When the processing capacity of a single bridge chip is insufficient and can reach the design requirement after being expanded to two bridge chips DSP, only two bridges are needed to be connected through a parallel bus interface HIC-EMIF, so that the two bridge chips DSP are in interconnection communication, and the processing capacity of the bridge chips is improved.

Referring to fig. 3, the EMIF is used as a host interface to actively control the HIC, so that the bridge chip DSP1 is used as a host to actively send a read/write command to the bridge chip DSP2, and the DSP2 receives the command of the DSP1 to write data or read data to the DSP1 through the HIC.

Specifically, the architecture of fig. 3 may also replace the bridge chip DSP1 with another more powerful DSP that integrates the EMIF interface.

In this case, only the connected GPIO needs to be configured as EMIF and HIC functions after DSP1 and DSP2 are powered on.

Example III

In this embodiment, as a variation of the second embodiment, when a single bridge chip can not meet the requirements in application, multiple bridge chips DSP are required to cooperate in computation, and multi-chip interconnection is met through the HIC-EMIF topology structure in the bridge chip, as shown in fig. 4, the structure can utilize HIC and EMIF bridging of multiple bridge chips DSP to form a bridge chip set, thereby achieving higher processing capability and supporting data transmission between more DSPs.

Example IV

The present embodiment provides a multi-chip communication method, which includes a first host DSP1 having an EMIF interface, a second host DSP2 having an EMIF interface, and a bridge chip, where the first host DSP1 and the second host DSP2 are respectively connected to the bridge chip HIC in the first embodiment through the EMIF interface for communication.

Specifically, only one of the first host DSP1 and the second host DSP2 can communicate with the bridge chip at the same time.

Referring to fig. 5, when two hosts having EMIF interfaces need to communicate with each other, because the HIC controller in the bridge chip DSP can multiplex two HIC interfaces, the bridge chip DSP can simultaneously connect two EMIF hosts, and only the multiplexing information needs to be transmitted to the host DSP. If the host DSP1 wants to establish communication with the bridge chip DSP, it is checked whether the bridge chip is giving the host DSP2 about establishing communication, if the host DSP2 is communicating, the host DSP1 will not establish communication with the bridge chip DSP temporarily, and after the host DSP2 has completed communication with the bridge chip, the bridge chip HIC will reuse the GPIO at the host DSP1 end, so that the host DSP1 can communicate with the bridge chip DSP.

The multi-chip communication method described in the second to fourth embodiments can perform multi-chip cooperative processing communication through the bridge chip, and can rapidly meet the requirements of the market on chip performance, reduce the design period and the application design period, accelerate the product investment in the market, and effectively reduce the cost.

Example five

The present embodiment provides a multi-chip communication system including: and the central bridge chip and the plurality of DSP chips are sealed into a sealed chip, GPIO of the selected interconnection communication interface is connected to a pin of the central bridge chip, and other GPIOs are bound to a PAD pin of the sealed chip to be used as GPIOs of the sealed chip.

The central bridge chip is the bridge chip in embodiment one.

The plurality of DSP chips are one or a combination of a plurality of DSP chips comprising SPI, FSI, EMIF and HIC peripheral interfaces;

The central bridge chip is a single bridge chip or a bridge chip set with a plurality of bridge chips connected through a parallel bus interface HIC-EMIF.

In the multi-chip communication system provided in this embodiment, since the modularized and standardized interface is adopted in the design, when the integrated chip needs to be upgraded or a new function is added, the whole integrated chip does not need to be redesigned, the designer can select a proper functional module according to the needs, only the corresponding interface needs to be replaced or upgraded in the bridging chip, and the corresponding functional chip or module needs to be added or replaced in the integrated chip, so that the multi-chip communication system can be quickly integrated into the existing system, and the technical difficulty and cost are greatly reduced.

When other DSP chips communicate with the FSI interface of the bridge chip through the FSI interface, required data are transmitted, and the FSI interface of the bridge chip receives the data and then transmits the received information to other external DSPs or chips containing the CANFD interface.

Referring to fig. 6, for example, DSP1 transmits data to the bridge chip through SPI, the bridge chip core transmits the processed data to DSP2 connected to FSI of the bridge chip, and DSP2 receives the bridge chip transmission data through FSI.

Similarly, the CANFD data is also data transmitted by other chips received by the bridge chip through the CANFD interface, and the bridge chip can transfer the data to the FSI interface through DMA and then start the FSI interface to transmit to the DSP chip connected with the FSI externally.

In this embodiment, the type of the DSP chip is selected according to actual needs, and the plurality of DSP chips are one or a combination of a plurality of DSP chips including SPI, FSI, EMIF and HIC peripheral interfaces.

In the multi-chip communication system provided in this embodiment, since the bridge chip adopts the modularized and standardized interface, when the integrated chip needs to be upgraded or a new function is added, the whole integrated chip does not need to be redesigned, and a designer can select a proper functional module according to the needs, and only the corresponding interface needs to be replaced or upgraded in the bridge chip, and the corresponding functional chip or module needs to be added or replaced in the integrated chip, so that the multi-chip communication system can be quickly integrated into the existing system. This greatly reduces technical difficulties and costs.

The present description is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the specification. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart block or blocks and/or flow diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The invention has not been described in detail in the prior art, and it is apparent to those skilled in the art that the invention is not limited to the details of the above-described exemplary embodiments, but that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof; the present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and range of equivalency are intended to be embraced therein.

Claims (10)

1. The bridge chip is characterized by taking a DSP architecture as a main body and comprising a DSP core, a BUS BUS, an HIC controller, an XBAR unit, a DMA controller, SPI interfaces of a first preset number path, FSI interfaces of a second preset number path, EMIF interfaces of one path and CANFD interfaces of a third preset number path; the HIC controller comprises an HIC interface; the DSP core is connected with the BUS BUS through the DMA controller, and the DSP core is directly connected with the BUS BUS; the HIC controller is configured to control a fourth preset number of peripheral frames FP; one path of SPI interface and one path of FSI interface are connected with one path of peripheral frame FP; the EMIF interface is connected with one path of peripheral frames FP; every 4 CANDFD interfaces are connected with one path of peripheral frames FP; the HIC interface, the SPI interface, the FSI interface, the EMIF interface and the CANFD interface are all connected with the GPIO interface through XBAR units; the peripheral frames FP are connected with the BUS BUS; the XBAR unit is used for mapping each peripheral GPIO to different physical positions of the bridge chip.

2. The bridge chip of claim 1, wherein the DSP core or the HIC controller is operable as a host to control the BUS via the BUS interface.

3. The bridge chip of claim 1, wherein the HIC controller has two GPIO port maps, one of the GPIOs for HIC interface communication.

4. The bridge chip of claim 1, wherein the EMIF interface and HIC interface are parallel interfaces and are master-slave interfaces with respect to each other.

5. The bridge chip of claim 1, wherein the first predetermined number is equal to and greater than 0; the third preset number is a multiple of 4 and is greater than 0; the fourth preset number is the sum of the first preset number and the third preset number.

6. A multi-chip communication method comprising a first bridge chip and a second bridge chip of the bridge chip type according to any one of claims 1-5, the first bridge chip and the second bridge chip communicating via a parallel bus interface HIC-EMIF.

7. The method of claim 6, wherein the first bridge chip and the second bridge chip communicate via a parallel bus interface HIC-EMIF specifically: the first bridge chip is used as a host, the second bridge chip is used as a slave, the EMIF interface of the first bridge chip is used as a host interface to actively control the HIC of the second bridge chip, the first bridge chip actively transmits a read-write command to the second bridge chip, and the second bridge chip receives command write data of the first bridge chip or read data to the first bridge chip through the HIC interface.

8. A multi-chip communication method, comprising the bridge chip according to any one of claims 1-5, a first host DSP1 having an EMIF interface, and a second host DSP2 having an EMIF interface, wherein the first host DSP1 and the second host DSP2 are respectively connected to the bridge chip HIC through the EMIF interface for communication.

9. A multi-chip communication system, comprising: the central bridge chip and the plurality of DSP chips are sealed into a sealed chip, GPIO of the selected interconnection communication interface is connected to a pin of the central bridge chip, and other GPIOs are bound to a PAD pin of the sealed chip to be used as GPIOs of the sealed chip; the central bridge chip is the bridge chip of any one of claims 1-5.

10. The multi-chip communication system of claim 9, wherein the central bridge chip is a bridge chipset in which a plurality of the bridge chips are connected through a parallel bus interface HIC-EMIF; the plurality of DSP chips are one or more combinations of DSP chips comprising SPI, FSI, EMIF and HIC peripheral interfaces.