CN118571771A - Flash memory wafer bare chip testing process and method - Google Patents
Flash memory wafer bare chip testing process and method Download PDFInfo
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- CN118571771A CN118571771A CN202410724202.4A CN202410724202A CN118571771A CN 118571771 A CN118571771 A CN 118571771A CN 202410724202 A CN202410724202 A CN 202410724202A CN 118571771 A CN118571771 A CN 118571771A
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- 238000012360 testing method Methods 0.000 title claims abstract description 94
- 238000000034 method Methods 0.000 title claims abstract description 79
- 230000008569 process Effects 0.000 title claims abstract description 61
- 238000010586 diagram Methods 0.000 claims abstract description 40
- 238000004806 packaging method and process Methods 0.000 claims abstract description 31
- 238000012546 transfer Methods 0.000 claims abstract description 16
- 239000012528 membrane Substances 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 20
- 230000000007 visual effect Effects 0.000 claims description 10
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 239000002699 waste material Substances 0.000 claims description 6
- 238000003860 storage Methods 0.000 claims description 5
- 238000005538 encapsulation Methods 0.000 claims description 4
- 238000007599 discharging Methods 0.000 claims description 3
- 238000000465 moulding Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 102200128633 rs104893843 Human genes 0.000 claims description 2
- 238000012858 packaging process Methods 0.000 abstract description 12
- 239000004065 semiconductor Substances 0.000 abstract description 11
- 239000012634 fragment Substances 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 112
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000012937 correction Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 2
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 238000009960 carding Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 238000012804 iterative process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
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Abstract
The invention belongs to the technical field of flash memory semiconductors, in particular to a flash memory wafer bare chip testing process and a method, wherein the method comprises the following steps: transferring the wafer bare chip with the unfilled corner and the test point to a new film, generating a corresponding position state diagram by equipment, and leaving the wafer bare chip with the unfilled test point on the original blue film; warehousing the wafer bare chips according to the original film after the transfer of the wafer bare chips is completed, and storing the position state diagram of each wafer on the film to a file server; then testing the wafer bare chips on the membrane into grades, and generating a corresponding position state diagram for each wafer bare chip on the membrane; warehousing the wafer bare chips according to the films, and storing the position state diagram into a file server; and packaging and warehousing the blue film. The process has high automation degree, does not need to manually contact the wafer, and overcomes the problems of dirt and fragment; the film has a plurality of products with different capacities, and the equipment leads out corresponding wafer bare chips, which accords with the blue film packaging mode of the original factory; the wafer bare chip is converted between blue films, and finally, the films are transferred to a packaging process, and packaging is carried out.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a flash memory wafer bare chip testing process and method.
Background
Wafer bare chips are a general term of semiconductor component products, at present, when the wafer bare chips are sealed, the wafer bare chips on a film need to be transferred to a green disc manually or in a device mode in advance, then the green disc is sent to wafer bare chip equipment for testing, and finally the wafer bare chips are transferred to a packaging process in a green disc mode after the wafer bare chip testing is finished.
The method comprises the following specific steps: 1. removing the wafer die: manually visually observing the appearance of the wafer bare chip, taking the complete wafer bare chip from the blue film to an A-type green disc, taking the wafer bare chip with unfilled corners and complete test points from the blue film to a B-type green disc, and leaving the wafer bare chip with incomplete test points on the blue film; 2. and (5) warehousing: warehousing according to different appearances of the wafer bare chips, wherein the wafer bare chips are at least provided with two materials of A type and B type; 3. class a wafer die test: the class A green disc is tested, and after the test is finished, the class A green disc is classified into a class A-1, a class A-2, a class A-3 and a class A-4; 4. class B wafer die test: the class B green disc is tested, and after the test is finished, the class B green disc is classified into a class B-1, a class B-2, a class B-3 and a class B-4; 5. and (5) warehousing: warehousing according to different appearances and grades of the wafer bare chips, wherein the wafer bare chips are at least provided with eight materials of A-1, A-2, A-3, A-4 and B-1, B-2, B-3 and B-4; 6. and (3) packaging: adding a fixture and a clamp to the equipment, and packaging the green disc; 7. and (5) warehousing: and (5) packaging and warehousing.
However, the above process flows have the following risks:
1, a person touches a wafer bare chip to cause the wafer bare chip to be polluted;
2, people use different forces on the wafer bare chip, which can cause damage or dark crack;
3, the detected green discs have various capacities, the sizes of the capacities cannot be visually observed due to the same appearance, and the requirements on warehouse management are extremely high;
and 4, the packaging equipment is needed to be modified when the green disc is subjected to the packaging process, and extra conversion time is needed for each line turning.
After testing in the semiconductor packaging industry, conventional semiconductor wafer factories are divided into good and bad wafers, and for flash memory semiconductors, the wafer with the speed not reaching USB3.0 can be used as a USB2.0 product or a wafer with the capacity not reaching the standard due to the defect of the wafer manufacturing process, the wafer needs to be basically detected before packaging, the wafer needs to be manually taken down from a blue film to a green disc in the process, and then the green disc is subjected to the test of a machine table through a needle card and a computer, so that the packaging process can be carried out on the wafer judged to be normal in electric appliances.
The invention mainly creates a new technological process, does not need to touch the wafer manually in the whole process or switch to the green disc, reduces artificial misloss, improves the product quality, saves blue film data after film arrangement and film measurement in a server, has simple warehouse management, can directly carry out machine production by rear-section packaging equipment, does not need to additionally install the green disc tool, and reduces the waste of product switching time.
In the flash memory sealing industry, a manual wafer feeding mode is adopted, no one performs process optimization carding, and the method belongs to the most original and unique process in the semiconductor industry.
The key problems to be solved by the invention are as follows:
a) The rejection rate of the purchased wafer is reduced to be extremely low, and the difficulty in purchasing the wafer is reduced.
B) The curve overtaking in the field of flash memory semiconductors is realized by self-grinding domestic semiconductor test equipment.
C) The new process personnel are not contacted in the whole process, dirt and damage are avoided, and the product is more stable and has higher quality.
D) The process matching management mechanism is simpler and more convenient, and errors and mistakes caused by personnel are reduced.
In summary, the flash memory semiconductor package can be finally tested to have no bad waste characteristics, which is very good.
Disclosure of Invention
An object of an embodiment of the present invention is to provide a flash memory wafer die testing process, which aims to solve the problems in the background art.
The embodiment of the invention is realized in such a way that the flash memory wafer bare chip testing process comprises the following steps:
Step one, performing film transfer by using equipment: transferring the complete wafer bare chip and the wafer bare chip with unfilled corners and complete test points to a new film, orderly arranging, generating an electronic file of a corresponding position state diagram by equipment, and leaving the wafer bare chip with unfilled test points on a blue film;
step two, primary warehouse entry: warehousing the wafer bare chips according to the films, and storing the position state diagram into a file server;
step three, testing the membrane: after the test is finished, the electronic files are divided into various grades, and the grade data generate corresponding position state diagram electronic files;
fourth, secondary warehouse entry: warehousing the wafer bare chips according to the films, and storing the position state diagram into a file server;
step five, packaging blue films: the device is produced directly by using the membrane;
Step six, warehousing finished products: and (5) packaging the finished product and warehousing.
In the first step, a film transfer device is used for replacing a manual wafer die unloading process, the device has visual judgment, the material taking and unloading precision is high, and the spacing between the wafer die is controllable so as to generate a position state diagram.
In the third step, the film upper testing device is used for replacing the traditional green disc feeding testing device, and the device is provided with visual judgment and high in triaxial precision so as to generate a position state diagram.
In the fourth step, the position state diagram is used for replacing different state classification marks, so that the complexity of warehouse materials is simplified.
In the fifth step, a standard packaging process is used for replacing a refitted packaging process, so that labor waste of product conversion is reduced.
In the fifth step, the blue film is arranged on a die bonder, and the die bonder places the wafer bare chip on the blue film on a PCB board and mounts the wafer bare chip.
Preferably, the wafer bare chip and the PCB are connected through a wire bonding machine to form a circuit.
The PCB is molded by a molding machine after being connected, so that a layer of plastic shell is formed above the PCB and used for protecting the wafer bare chip and the gold thread from being damaged.
Wherein, preferably, the PCB is cut into single particle products by a cutting machine after being molded.
The flash memory wafer bare chip testing process provided by the embodiment of the invention has the following advantages:
(1) The whole process has higher automation degree, does not need to be contacted manually, and can overcome the problems of dirt and fragment;
(2) A plurality of products with different capacities exist on one membrane, and the equipment leads out the conditions of corresponding wafer bare chips and accords with the original package of the factory;
(3) The wafer bare chips are converted between blue films, the wafer bare chips are finally transferred into a packaging process by films, and the packaging line is quite convenient;
(4) Film transfer equipment: transferring a small amount of DIE on the film to a new film to enable the new film to fill all DIE; film test equipment: mainly testing the DIE state on the film, generating a corresponding database, and facilitating transfer to the next procedure; considering the balance and optimization of the yield, the new process can be used for mass production.
Drawings
FIG. 1 is a flow chart of process steps of a flash wafer die test process;
FIG. 2 is a schematic diagram showing the selection of good products at the process steps of a flash wafer die test process;
FIG. 3 is a schematic diagram of a process packaging procedure of a flash wafer die test process;
FIG. 4 is a process diagram illustrating a conventional flash wafer die test process;
FIG. 5 is a schematic diagram of a process packaging procedure of a flash wafer die test process;
FIG. 6 is a process packaging level diagram of a flash wafer die test process;
FIG. 7 is a schematic diagram of an original process comparison of a flash wafer die test process;
Description of the drawings: 10-wafer die; 20-unfilled corners; 30-test points; 40-new film; 50-incomplete wafer die of test point; 60-blue film; 70-a file server; 80-position state diagram electronic archives; 82-a second location state diagram electronic archive; 83-third location state diagram electronic archives; 91-grade a-1; 92-grade a-2; 93-grade A-3.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. As shown in fig. 1 to 5, to achieve the above object, the present invention provides the following technical solutions: as shown in fig. 1, a flow chart of a flash memory wafer die testing process according to an embodiment of the invention includes the following steps:
S10, carrying out film transfer by using equipment: as shown in fig. 2, transferring the complete wafer bare chip and the wafer bare chip with unfilled corners and perfect test points to a new film, orderly arranging, generating an electronic file of a corresponding position state diagram by equipment, and leaving the wafer bare chip with unfilled test points on a blue film;
S20, primary warehouse entry: the wafer die is binned according to film, as shown in fig. 3, position state diagram 80 to file server 70;
S30, testing the membrane: after the test is completed, the electronic files are classified into various grades, and as shown in fig. 3, grade data generate corresponding position state diagram electronic files 80;
S40, secondary warehouse entry: warehousing the wafer bare chips according to the films, and storing the position state diagram into a file server;
s50, blue film packaging: the device is produced directly by using the membrane;
s60, warehousing a finished product: and (5) packaging the finished product and warehousing.
The conventional test flow is shown in FIG. 4, and the steps are as follows
W10: transferring the complete chip and the chip with unfilled corners and intact test points to a new film, orderly arranging, and generating an electronic file of a corresponding position state diagram by the equipment
Leaving the chip with the incomplete test point on the blue film;
W20: warehousing the chip at one time according to the film, and storing the position state diagram to a file server;
W30: after the test is completed, dividing the test into various grades, and generating an electronic file of a corresponding position state diagram by grade data;
w40: secondary warehouse-in, namely, warehouse-in is carried out on the chip according to the film, and the position state diagram is stored in a file server;
W50: blue film encapsulation;
W60: and (5) warehousing finished products, namely finishing packaging and warehousing.
The flash memory wafer bare chip testing process provided by the application has higher whole-course automation degree, does not need to be contacted manually, and can overcome the problems of dirt and fragmentation; a plurality of products with different capacities exist on one membrane, and the equipment leads out the conditions of corresponding wafer bare chips and accords with the original package of the factory; the wafer bare chips are converted between the blue films, the wafer bare chips are finally transferred into a packaging process by the films, and the packaging line is quite convenient.
In one example of the invention, the blue film package is the same as industry standard packaging processes and no equipment modification is required for film wafer die packaging.
As a preferred embodiment of the present invention, the film transfer apparatus is used instead of the manual wafer die unloading process in S10.
In one example of the invention, the arrangement accuracy when the device performs film transfer: the X axis is 200 micrometers, the Y axis is 180 micrometers, the bottom of the wafer bare chip is contacted with the film, the bubble phenomenon can not exist, an optimal MAP arrangement scheme is automatically generated, the center point of a wafer array table is confirmed, the center of the film is ensured, seven people leftover materials are needed to be placed on the film, and a small amount of wafer bare chips on the film are mainly transferred to a new film, so that the new film can be filled with all wafer bare chips.
Compared with the manual wafer die feeding process, the whole process does not need to touch the wafer manually or switch to a green disc, so that artificial dispersion is reduced, the quality of products is improved, the film transfer equipment has visual judgment, the material taking and discharging precision is high, and the spacing between the wafer die is controllable so as to generate a position state diagram.
As another preferred embodiment of the present invention, a film-on-test device is used in place of the conventional green disc feeding test device in S30, and the device is provided with visual judgment to generate a position state diagram.
In one example of the invention, the on-film test equipment is suitable for 12-hour wafers, visual alignment judgment and error correction, automatic alignment card, XYZ three-axis needle card and wafer bare chip alignment test capability, basket loading, automatic positioning capability, main test of on-film wafer bare chip states and generation of a corresponding MPA database, convenient transfer to the next process, and because of the problem of insufficient precision of the traditional green disc loading test equipment, the three-axis precision can be improved by changing the on-film test equipment used in the embodiment, and the test precision can be effectively ensured.
As another preferred embodiment of the present invention, the location state diagram is used in S40 to replace the different state classification identifiers, so as to simplify the complexity of warehouse materials.
In one example of the invention, the wafer bare chip position is obtained through the position state diagram, and the blue film data after film swinging and film measurement are stored in the server, so that the efficient management of the product can be realized, and the management difficulty is greatly reduced.
As another preferred embodiment of the present invention, the standard packaging process is used instead of the retrofit packaging process in S50, so as to reduce the labor waste of product conversion.
In one example of the invention, the standard packaging technology is adopted, the back-end packaging equipment can be directly used for machine production, and a green disc manufacturing tool is not required to be additionally arranged, so that the waste of the product conversion time is reduced.
As another preferred embodiment of the present invention, the blue film is disposed on a die bonder, which places the wafer die on the blue film on a PCB board and performs mounting in S50.
In one example of the present invention, the wafer die and PCB are connected by a wire bonding machine to form a circuit, the PCB is molded by a molding machine after being wired to form a plastic shell over the PCB for protecting the wafer die and gold wires from damage, and the PCB is cut by a dicing machine after being molded to be cut into single particle products.
Wafer bare chips are a general term of semiconductor component products, at present, when the wafer bare chips are sealed, the wafer bare chips on a film need to be transferred to a green disc manually or in a device mode in advance, then the green disc is sent to wafer bare chip equipment for testing, and finally the wafer bare chips are transferred to a packaging process in a green disc mode after the wafer bare chip testing is finished.
The specific method comprises the following steps: the new and old processes are shown in fig. 7, and the new process flow is as follows:
T10 removing the wafer die: manually visually observing the appearance of the wafer bare chip, taking the complete wafer bare chip from the blue film to an A-type green disc, taking the wafer bare chip with unfilled corners and complete test points from the blue film to a B-type green disc, and leaving the wafer bare chip with incomplete test points on the blue film;
t20 is put into storage for one time: warehousing according to different appearances of the wafer bare chips, wherein the wafer bare chips are at least provided with two materials of A type and B type;
T30A class wafer die test: the class A green disc is tested, and after the test is finished, the class A green disc is classified into a class A-1, a class A-2, a class A-3 and a class A-4;
T40B wafer die test: the class B green disc is tested, and after the test is finished, the class B green disc is classified into a class B-1, a class B-2, a class B-3 and a class B-4;
t50 secondary warehouse entry: warehousing according to different appearances and grades of the wafer bare chips, wherein the wafer bare chips are at least provided with eight materials of A-1, A-2, A-3, A-4 and B-1, B-2, B-3 and B-4; as shown in FIG. 6, there are class A-191, class A-292, and class A-393;
and T60 packaging: adding a fixture and a clamp to the equipment, and packaging the green disc;
and (5) warehousing a T70 finished product: and (5) packaging the finished product to finish warehousing.
However, the above process flows have the following risks:
1, a person touches a wafer bare chip to cause the wafer bare chip to be polluted;
2, people use different forces on the wafer bare chip, which can cause damage or dark crack;
3, the detected green discs have various capacities, the sizes of the capacities cannot be visually observed due to the same appearance, and the requirements on warehouse management are extremely high;
and 4, during the working procedure, the packaging equipment is needed to be modified, and extra conversion working hours are needed to be consumed for each line conversion.
Wherein, the preferable scheme is that the technical route is as follows
A) Blue film transfer equipment:
A. Is suitable for 12 inch wafers.
B. And (5) visual material taking and discharging judgment and error correction.
C. Arrangement precision: x-axis 200 microns, Y-axis 180 microns.
D. The bottom of the chip is contacted with the film, and no bubble phenomenon exists.
E. an optimal MAP arrangement is automatically generated.
F. Confirming the center point of the film arranging table, and ensuring the center of the film arranging.
G. the arranging film needs to distinguish leftover materials for arrangement.
B) Film test equipment:
A. Is suitable for 12 inch wafers.
B. Visual alignment judgment and error correction.
C. the automatic alignment card has the alignment test capability of the XYZ triaxial card and the chip.
D. Basket material loading possesses automatic positioning ability.
E. And automatically generating a MAP database after product testing.
C) Develop matched equipment and tools and optimize new process efficiency.
The preferred scheme is that the process is not available at home and abroad, and if the related technical difficulty is overcome, the flash memory package enterprises which preferably adopt the process will be realized. The new generation of automatic processing equipment for flash memory wafer test can completely replace the prior manual DIE, can solve the problem of difficult state management during DIE measurement, and can directly transfer the whole film of the process to the next process without additional complex machine adjustment actions.
Wherein, the preferable scheme is that the construction index and implementation performance
Technical and economic index comprehensive description:
after the new process is introduced, the product line can be lifted at present, which is equivalent to an iterative process of quality lifting, and the quality is greatly improved; the technical difficulty can be overcome, and the flash memory encapsulation enterprises which adopt the process preferentially can be realized; and the research and the optimization of new generation process equipment are completed, and the annual output of flash memory chip products is increased.
The wafer test method has the advantages that the wafer test is highly automated, workers do not touch the wafer by hand any more, and products with higher quality are produced; in addition, the process is innovative and popularized to other companies in the flash memory industry, so that the wafer test is not blocked by the neck.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (10)
1. A flash memory wafer die testing process, comprising the steps of:
S10, carrying out film transfer by using equipment: transferring the complete wafer bare chip (10) and the wafer bare chip with unfilled corner (20) but the complete test point (30) to a new film (40), orderly arranging, generating an electronic file of a corresponding position state diagram by equipment, and leaving the incomplete wafer bare chip (50) of the test point on a blue film (60);
s20, primary warehouse entry: the wafer bare chips are put in storage in the form of arranged complete films, and the position state diagram is stored in a file server (70);
s30, testing the membrane: after the test is completed, the electronic files are divided into various grades, and the grade data generate corresponding position state diagram electronic files (80);
S40, secondary warehouse entry: the wafer bare chips are put in storage in the form of arranged complete films, and the position state diagram is stored in a file server (70);
s50, blue film packaging: the device is produced directly by using the membrane;
s60, warehousing a finished product: and packaging the finished product (80) to finish warehousing.
2. The process according to claim 1, wherein in S10, a film transfer device is used instead of a manual wafer die removal process, the device has visual judgment, and the precision of taking materials from an original film and placing new films is high, and the spacing between the wafer dies is controllable, so as to generate a position state diagram.
3. The process according to claim 1, wherein in S30, the die is placed on the green disc using the film-on-test device instead of manually removing the die, and then the test device is fed from the green disc, and the device has a visual judgment and high triaxial accuracy to generate the positional state diagram.
4. The process of claim 1, wherein the step S40 uses a position state diagram instead of a single green disc to test the plurality of green discs in different states, thereby simplifying the complexity of warehouse materials.
5. The flash wafer die test process of claim 1, wherein the standard encapsulation blue film process is used in S50 instead of the retrofit encapsulation green tape process, reducing labor waste for product conversion.
6. The process according to claim 1, wherein in S50, the blue film is mounted on a die bonder, and the die bonder places the wafer die on the blue film on a PCB board and mounts the wafer die thereon; the wafer bare chip and the PCB are connected through a wire bonding machine to form a circuit.
7. The process of claim 6, wherein the PCB is molded by a molding machine after being wired to form a plastic shell over the PCB for protecting the die and gold wires from damage.
8. A method for testing a flash memory wafer bare chip is characterized in that when equipment performs film transfer, the arrangement precision is as follows: the X axis is 200 microns, the Y axis is 180 microns, the bottom of the wafer bare chip is contacted with the film, the bubble phenomenon can not exist, an optimal MAP arrangement scheme is automatically generated, the center point of a wafer array table is confirmed, the center of the film is ensured, seven people leftover materials are needed to be placed on the film, and a small amount of wafer bare chips on the film are mainly transferred to a new film, so that the new film can be filled with all wafer bare chips; compared with the manual wafer die feeding process, the whole process does not need to touch the wafer manually or switch to a green disc, the film transfer equipment has visual judgment, the material taking and discharging precision is high, and the spacing between the wafer die is controllable so as to generate a position state diagram.
9. A kind of according to claim 8A method for testing a flash memory wafer die, the method is characterized in that the wafer bare chip is taken down: manually visually observing the appearance of the wafer bare chip, taking the complete wafer bare chip from the blue film to an A-type green disc, taking the wafer bare chip with unfilled corners and complete test points from the blue film to a B-type green disc, and leaving the wafer bare chip with incomplete test points on the blue film; warehousing according to different appearances of the wafer bare chips, wherein the wafer bare chips are at least provided with two materials of A type and B type; after the test is completed, the test is classified into a grade A-1, a grade A-2, a grade A-3 and a grade A-4; the class B green disc is tested, and after the test is finished, the class B green disc is classified into a class B-1, a class B-2, a class B-3 and a class B-4; the bare chip is put in storage with different appearances and grades, and at least eight materials of A-1, A-2, A-3, A-4 and B-1, B-2, B-3 and B-4 are provided.
10. The method for testing a flash memory wafer die of claim 8, comprising the steps of:
T10 removing the wafer die: manually visually observing the appearance of the wafer bare chip, taking the complete wafer bare chip from the blue film to an A-type green disc, taking the wafer bare chip with unfilled corners and complete test points from the blue film to a B-type green disc, and leaving the wafer bare chip with incomplete test points on the blue film;
t20 is put into storage for one time: warehousing according to different appearances of the wafer bare chips, wherein the wafer bare chips are at least provided with two materials of A type and B type;
T30A class wafer die test: the class A green disc is tested, and after the test is finished, the class A green disc is classified into a class A-1, a class A-2, a class A-3 and a class A-4;
T40B wafer die test: the class B green disc is tested, and after the test is finished, the class B green disc is classified into a class B-1, a class B-2, a class B-3 and a class B-4;
T50 secondary warehouse entry: warehousing according to different appearances and grades of the wafer bare chips, wherein the wafer bare chips are at least provided with eight materials of A-1, A-2, A-3, A-4 and B-1, B-2, B-3 and B-4;
and T60 packaging: adding a fixture and a clamp to the equipment, and packaging the green disc;
and (5) warehousing a T70 finished product: and (5) packaging the finished product to finish warehousing.
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