CN118550355A - Method and system for adjusting link resolution in photoelectric hybrid computing system and storage medium - Google Patents
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Abstract
The invention relates to the technical field of photoelectric hybrid computing, and particularly discloses a method and a system for adjusting link resolution in a photoelectric hybrid computing system and a storage medium. Wherein, the adjusting method comprises the following steps: s101, determining the maximum input optical signal of a photon calculation chip in a link to be tested based on the maximum value in the optical power input range of the photon calculation chip in the link to be tested; s102, providing a maximum input optical signal to a photon computing chip, so that a photocurrent I meeting preset conditions is generated on the input side of a transimpedance amplifier in a link to be tested; the preset conditions comprise: the product of the photocurrent I and the feedback resistor R f of the transimpedance amplifier is smaller than the initial reference voltage V ref of the analog-to-digital converter connected in series at the output side of the transimpedance amplifier; s103, obtaining a photocurrent I, and calculating to obtain a target voltage U according to the photocurrent I and a feedback resistor R f of the transimpedance amplifier; s104, the initial reference voltage V ref of the analog-to-digital converter is regulated to the target voltage U.
Description
Technical Field
The invention relates to the technical field of photoelectric hybrid computing, in particular to a method and a system for adjusting link resolution in a photoelectric hybrid computing system and a storage medium.
Background
With the rapid development of Artificial Intelligence (AI) algorithms, many new hardware and systems are emerging in the academic field and industry. Represented by GPU, multi-core chip, many-core chip, deep learning accelerator, neuromorphic chip, general brain-like computing chip, etc. that develop rapidly. The motivation is to provide more computing power through specialization of hardware to cope with the rapidly increasing demand for computing power by AI technology. Among them, photon computing technology is expected to provide extremely efficient AI computing power by virtue of advantages of light in terms of bandwidth, time delay, energy consumption and the like.
However, the photon computing chip realizes linear computation mainly through matrix multiplication operation, and is widely operated in an Artificial Intelligence (AI) algorithm. However, in addition to matrix calculation, nonlinear calculation is introduced into the complex neural network, and although the input and output of the neural network are not in a simple linear relationship, the fitting degree of the neural network is improved, so that the complex problem is solved more favorably. Thus, in order to exert the obvious advantages of the optical system while ensuring the practicality and versatility of the computing system, an opto-electronic hybrid computing system has been proposed and developed. The method aims at utilizing the logic computing and storage capacity of the electrical system to make up the defects of the optical system and constructing a more flexible and efficient computing architecture. The photoelectric hybrid computing system is formed by stacking integrated silicon optical chips and CMOS microelectronic chips in various packaging modes. For example, chinese patent application publication No. CN117112961A, CN117933330a discloses a photoelectric hybrid computing system. For another example, chinese patent application publication No. CN117130099a discloses a very large scale optoelectric hybrid computing array based on multimode interferometers. For another example, chinese patent application publication No. CN116932459a discloses a hybrid calculation method and array for on-chip large-scale matrix multiplication.
Generally, in order to ensure normal operation of the entire link in the optoelectronic hybrid computing system, and at the same time, to simplify the design work, it is necessary to select the resolution of the ADC according to the operating voltage of the TIA, and to set the reference voltage of the ADC according to the operating voltage of the TIA. In order to ensure a sufficient signal input range, the full-scale voltage value of the ADC is selected to be very large, so that the output voltage of the TIA is always smaller than the full-scale voltage value of the ADC, and even the maximum operating voltage of the TIA cannot reach the full-scale (FSR) of the analog signal of the ADC, that is, the maximum range, which results in a certain degree of power waste in the analog and digital domains and also reduces the resolution of the input signal by the whole link.
However, the requirements of the photoelectric hybrid computing system on the resolution are high, and in order to improve the resolution of the input signal in the whole link under the condition that the number of ADC bits in the link (that is, the resolution of the ADC) is set, it is common practice to change the front-stage amplification, that is, to improve the resolution of the input signal by adjusting the gain of the front-stage TIA of the ADC in the link design stage. However, once the gain of the TIA is adjusted, the bandwidth of the TIA is changed. In opto-electronic hybrid computing systems, however, bandwidth of the TIA is typically prioritized. Once the bandwidth is determined, the TIA gain is limited to a certain range accordingly, that is, the TIA gain is adjusted under the condition of a certain bandwidth, and the TIA output voltage is smaller than the full scale range of the ADC. That is, the manner of increasing the resolution of the input signal by adjusting the gain of the ADC front-stage TIA is not applicable to opto-electronic hybrid computing systems.
Also, as previously described, adjusting the gain of the ADC front-end TIA is typically throughout the link design phase. However, this approach is no longer viable once the individual components in the overall link are established, i.e., the transimpedance of the TIA cannot be adjusted.
In addition, a method for automatically adjusting the reference voltage to improve the conversion resolution of the ADC is also provided in the prior art. For example, chinese patent publication No. CN101369815A discloses that the full scale voltage value is automatically changed according to the input signal. However, this approach is not applicable to optoelectronic hybrid computing systems.
On the one hand, after the full-scale voltage value of the ADC is changed each time, the corresponding analog-to-digital conversion can be performed after the reference voltage of the ADC is stabilized, so that the calculation speed of the whole calculation system is greatly reduced. As described above, the reason why the AI algorithm is performed by using the photoelectric hybrid computing system is that the computing power and the computing speed thereof, and thus, the manner of automatically adjusting the ADC reference voltage in real time according to the input signal size is not suitable for the photoelectric hybrid computing system.
On the other hand, after each change of the full scale voltage value of the ADC, multiple conversions are required on the subsequent digital side. For example, the FPGA connected in series to the output side of the ADC performs data processing, otherwise the FPGA cannot recognize the signal output by the ADC or is prone to confusion. For example, the last time the FPGA received 1111, its corresponding full scale range was considered to be 5v; after the automatic adjustment, the full scale of the ADC corresponds to 3V, but when the FPGA receives 1111, if the FPGA processes the data accordingly, the FPGA still considers 5V, which leads to an error.
In view of this, there is a need to find a method that is simpler and that enables appropriate adjustment of the link resolution of an optoelectronic hybrid computing system.
Disclosure of Invention
The invention aims to provide a method and a system for adjusting the resolution of a link in a photoelectric hybrid computing system and a storage medium, which partially solve or alleviate the defects in the prior art and can more simply adjust the resolution of the link.
In order to solve the technical problems, the invention adopts the following technical scheme:
In a first aspect, the present invention provides a method for adjusting link resolution in an optoelectronic hybrid computing system, comprising the steps of:
S101, determining the maximum input optical signal input into a photon computing chip in a link to be tested based on the maximum value in the optical power input range of the photon computing chip in the link to be tested;
S102, providing the maximum input optical signal to the photon computing chip, so that a photocurrent I meeting preset conditions is generated at the input side of a transimpedance amplifier in the link to be tested; the preset conditions include: the product of the photocurrent I and the feedback resistance Rf of the transimpedance amplifier is smaller than the initial reference voltage Vref of the analog-to-digital converter connected in series at the output side of the transimpedance amplifier;
s103, acquiring the photocurrent I, and calculating to obtain a target voltage U according to the photocurrent I and a feedback resistor R f of the transimpedance amplifier;
S104, the initial reference voltage V ref of the analog-to-digital converter is regulated to the target voltage U.
In some embodiments, the method for adjusting the link resolution in the photoelectric hybrid computing system further comprises the steps of:
s105, providing corresponding maximum input optical signals to the photon computing chip again;
S106, obtaining an output signal of the analog-to-digital converter in the link to be tested, judging whether the output signal is the maximum range value of the analog-to-digital converter, and if so, judging that the output signal passes the verification; otherwise, it is determined that the verification is not passed, and steps S104 to S106 are performed again until it is determined that the verification is passed.
In some embodiments, before performing step S101, the method for adjusting a link resolution in the optical-electrical hybrid computing system further includes the steps of:
s201, acquiring an optical power input range of a photon calculation chip in each of a plurality of links to be measured;
S202, grouping a plurality of links to be tested based on a preset grouping rule and the optical power input range to obtain a plurality of link groups to be tested; the preset grouping rule includes: presetting a reference maximum value, and dividing a group of links to be tested, wherein the difference value between the maximum input optical signal and the preset reference maximum value is an integer multiple of a preset difference value threshold value;
s203, sorting a plurality of links to be tested in each link group to be tested according to the sequence from the maximum value to the small value or from the small value to the large value;
S204, preparing corresponding maximum input optical signals for each link to be tested according to the sequence of each link to be tested in each link group to be tested and the corresponding preset difference threshold value.
In some embodiments, a plurality of the links under test are from different production lots or different models and have different optical power input ranges.
In a second aspect, the present invention provides a system for adjusting link resolution in an opto-electronic hybrid computing system, comprising:
the optical signal determining module is used for determining the maximum input optical signal input into the photon computing chip in the link to be tested based on the maximum value in the optical power input range of the photon computing chip in the link to be tested;
The light source module is used for providing the maximum input optical signal for the photon calculation chip according to the maximum input optical signal determined by the optical signal determination module, so that a photocurrent I meeting a preset condition is generated at the input side of the transimpedance amplifier in the link to be detected; the preset conditions include: the product of the photocurrent I and the feedback resistance Rf of the transimpedance amplifier is smaller than the initial reference voltage Vref of the analog-to-digital converter connected in series at the output side of the transimpedance amplifier;
The main control equipment is used for acquiring the photocurrent I and calculating to obtain a target voltage U according to the photocurrent I and a feedback resistor R f of the transimpedance amplifier; the initial reference voltage V ref of the analog-to-digital converter is then prompted to adjust to the target voltage U.
In some embodiments, the master device comprises:
the first data acquisition module is used for acquiring the photocurrent I output by the photon calculation chip;
the calibration module is used for calculating a target voltage U according to the photocurrent I acquired by the first data acquisition module and the feedback resistor Rf of the transimpedance amplifier, outputting the target voltage U when the target voltage U is calculated, and prompting the adjustment of the reference voltage Vref of the analog-to-digital converter to the target voltage U.
In some embodiments, the light source module is further configured to provide the maximum input light signal to the photonic computing chip again for verification.
In some embodiments, the master device further comprises: the second data acquisition module is used for acquiring an output signal of the analog-to-digital converter in the link to be tested when the light source module provides the maximum input light signal to the photon calculation chip again; the checking module is used for judging whether the output signal is the maximum range value of the analog-to-digital converter, if so, the output signal passes the checking; otherwise, judging that the verification is not passed, and prompting to readjust the reference voltage of the analog-to-digital converter until the verification is judged to be passed.
In some embodiments, the adjustment system further comprises:
The grouping module is used for acquiring the optical power input range of the photon calculation chip in each of the links to be tested, and grouping the links to be tested based on a preset grouping rule and the optical power input range to obtain a plurality of link groups to be tested; the preset grouping rule includes: presetting a reference maximum value, and dividing a group of links to be tested, wherein the difference value between the maximum input optical signal and the preset reference maximum value is an integer multiple of a preset difference value threshold value;
The sequencing module is used for sequencing a plurality of links to be tested in each link group to be tested according to the sequence from the maximum value to the small value or from the small value to the large value; and triggering the light source module to prepare a corresponding maximum input light signal for each link to be tested in advance according to the sequence of each link to be tested in each link group to be tested and a corresponding preset difference threshold value.
In a third aspect of the present invention, there is provided a storage medium, where the storage medium includes a stored computer program, where the computer program, when executed, controls a device in which the storage medium is located to perform a method for adjusting a link resolution in an optoelectronic hybrid computing system as described above.
The beneficial effects are that: as described above, the existing method dynamically adjusts the reference voltage of the ADC according to the input signal in real time, which emphasizes a flexibility, and the main purpose is to ensure the resolution of the small input signal, but this method not only greatly reduces the calculation speed of the photoelectric hybrid calculation system, but also needs to perform data processing at the digital end in real time, so as to increase the power consumption of the system. That is, the prior art guarantees the resolution of small input signals by sacrificing the speed and power consumption of the system. However, the photoelectric hybrid computing system is applied to various AI algorithms, that is, the photoelectric hybrid computing system is large in computational power and high in speed. Therefore, based on the prior art, the person skilled in the art would not apply it directly to the opto-electronic hybrid computing system to increase the resolution of the entire link.
The application adopts a completely different technical path from the prior art, and adjusts the reference voltage of the ADC in the link to be tested from the hardware angle on the premise of the predetermined bandwidth and gain of TIA in the link in the testing stage before the product leaves the factory, thereby realizing the adjustment of the resolution of the link to be tested. Specifically, a test signal is provided to the photonic computing chip, for example, the maximum input optical signal of the photonic computing chip in the link to be tested is determined based on the maximum value of the optical power input range of the photonic computing chip in the link to be tested, then a target voltage is obtained according to the optical current output by the photonic computing chip and the feedback resistance of the transimpedance amplifier, and the reference voltage of the ADC is modulated to the target voltage, so that the problem that the link resolution is lower because the ADC reference voltage is always greater than the TIA maximum operating voltage (i.e., the TIA maximum output voltage is smaller than the ADC reference voltage) under the premise that the bandwidth and the gain of the link TIA are established is avoided. For example, even when the maximum input optical signal is provided, the TIA output voltage is less than the ADC reference voltage, resulting in lower link resolution.
As described above, since the adjustment is performed in the factory testing stage, the link structure is not improved once the adjustment is completed, and complex or multiple conversions on the digital side are not needed in the following steps, but in consideration of the actual application process, the optical modulation is performed by changing the electrical signals input into the photon computing chip according to different application scenarios, so that the photon computing chip outputs different photocurrents, and in order to cover all the outputs, what optical signals are provided in the testing stage is a considerable problem. In the application, the reference voltage (namely full scale) of the ADC is set through the maximum value of the optical power input range of the photon calculation chip, so that in the practical application process, even if electric signals with different sizes are input to the photon calculation chip for optical modulation, the output signals can be covered, and the maximum output voltage of the TIA can correspond to the full scale of the ADC, thereby avoiding the problem of lower resolution caused by the fact that the output voltage of the TIA is smaller than the reference voltage of the ADC, further improving the resolution of the whole link more simply on the basis of not affecting the system speed and not increasing the system power consumption, namely ensuring the calculation precision when the photoelectric hybrid calculation system carries out AI algorithm.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. Like elements or portions are generally identified by like reference numerals throughout the several figures. In the drawings, elements or portions thereof are not necessarily drawn to scale. It will be apparent to those of ordinary skill in the art that the drawings in the following description are of some embodiments of the invention and that other drawings may be derived from these drawings without inventive faculty.
FIG. 1 is a schematic diagram of an exemplary link under test;
FIG. 2 is a flow chart of a method for adjusting link resolution in a photoelectric hybrid computing system according to an embodiment of the invention;
FIG. 3 is a functional block diagram of a link resolution adjustment system in a photoelectric hybrid computing system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In this document, suffixes such as "module", "component", or "unit" used to represent elements are used only for facilitating the description of the present invention, and have no particular meaning in themselves. Thus, "module," "component," or "unit" may be used in combination.
The terms "upper," "lower," "inner," "outer," "front," "rear," "one end," "the other end," and the like herein refer to an orientation or positional relationship based on that shown in the drawings, merely for convenience of description and to simplify the description, and do not denote or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The terms "mounted," "configured to," "connected," and the like, herein, are to be construed broadly as, for example, "connected," whether fixedly, detachably, or integrally connected, unless otherwise specifically defined and limited; the two components can be mechanically connected, can be directly connected or can be indirectly connected through an intermediate medium, and can be communicated with each other. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Herein, "and/or" includes any and all combinations of one or more of the associated listed items. Herein, "plurality" means two or more, i.e., it includes two, three, four, five, etc.
Noun paraphrasing:
Optical AI chip: is a chip specifically designed for processing optical data and performing Artificial Intelligence (AI) inference, also known as a photonic or photonic chip, or optical computing chip. It takes as input an optical signal based on optical principles and performs computational operations through a series of optical elements and devices. These optical elements may be components like lasers, optical fibers, optical modulators, etc. to process and transmit optical signals. For example, referring to fig. 1, the photon calculating chip converts an input optical signal into a weak photocurrent signal through a light emitting diode PD, then converts the photocurrent signal into a voltage signal through a transimpedance amplifier TIA, and then converts the voltage signal (i.e., an analog signal) into a digital signal by an analog-to-digital converter ADC to output to a digital terminal, for example, an FPGA, for processing.
A calculation unit: a single computing unit for performing the computation. For example, a single computational unit of photon computation is implemented using a Mach-Zehnder interferometer (MZI) or micro-ring structure (MMR) structure. As another example, a photon counting cell is implemented using the carrier light absorption effect. In particular, the calculation units may be divided into photon calculation units and hybrid calculation units. Photon computing units based on light absorbing effect structures, and hybrid computing units (e.g., hybrid structures based on light absorbing effect and phase change materials).
Computing an array: and constructing an N-by-N computing array based on the computing units, wherein one computing unit exists at the intersection point of each input row waveguide and each output column waveguide in the computing array. If the computing unit adopts a photon computing unit, the computing array can be correspondingly called a photon computing array; if the computing unit employs a hybrid computing unit, the computing array may also be referred to as a hybrid computing array, accordingly. When a computational array (e.g., a photonic computational array) in a photonic computational chip reaches a certain scale (i.e., has a large-scale computational array), the photonic computational chip is also referred to as a high-dimensional matrix photonic computational chip.
Embodiment one: as described above, in the photoelectric hybrid computing system, the initial reference voltage of the ADC is usually set to be larger on the premise of a certain bandwidth, so that the output voltage of the TIA is always smaller than the initial reference voltage of the ADC, for example, even when the maximum input optical signal is provided to the photonic computing chip, the voltage output by the TIA is also smaller than the initial reference voltage, which causes power waste in the analog and digital domains, and also reduces the resolution of the input signal by the whole link.
In the prior art, by redesigning the circuit structure so that the ADC can dynamically adjust the reference voltage of the ADC according to different input signals, when such ADC is applied in a photoelectric hybrid computing system, it still needs to perform signal processing by means of a digital terminal. I.e. it essentially comes at the expense of system speed and power consumption to achieve flexibility regulation. However, in opto-electronic hybrid computing systems, the speed requirements for the computation are very high.
In view of this, in order not to greatly reduce the speed of the photoelectric hybrid computing system and not to increase the power consumption of the photoelectric hybrid computing system, but also to more simply and appropriately increase the resolution of the input signal by the link, so that it is more suitable for industrial applications, see fig. 2, which is a flowchart of a method for adjusting the resolution of the link in the photoelectric hybrid computing system according to an embodiment of the present invention, specifically, the method includes the steps of:
s101, determining the maximum input optical signal of the photon calculation chip in the link to be tested based on the maximum value in the optical power input range of the photon calculation chip in the link to be tested.
In some embodiments, different photonic computing chips have different optical power input ranges, so the maximum input optical signal to the photonic computing chip needs to be determined in advance according to the maximum value in the optical power input ranges of the photonic computing chips in the link to be measured, so that the subsequent determination of the target voltage is facilitated.
S102, providing the maximum input optical signal to the photon calculation chip, so that a photocurrent I meeting preset conditions is generated on the input side of a transimpedance amplifier TIA in a link to be measured.
In some embodiments, the preset conditions include: the product of the photocurrent I and the feedback resistor R f of the transimpedance amplifier TIA is smaller than the initial reference voltage V ref of the analog-to-digital converter connected in series at the output side of the transimpedance amplifier TIA, i.e., (i×r f）＜Vref).
In order to ensure a sufficient input range, the initial reference voltage of the ADC is set to be larger, so that the product of the photocurrent output by the photon calculation chip and the feedback resistance of the TIA, that is, the output voltage of the TIA is always smaller than the reference voltage of the ADC.
S103, obtaining a photocurrent I, and calculating to obtain a target voltage U according to the photocurrent I and a feedback resistor R f of a transimpedance amplifier TIA.
In some embodiments, the target voltage u=i×r f.
S104 adjusts the initial reference voltage V ref of the analog-to-digital converter ADC to the target voltage U.
In order to ensure the resolution of the link, only when the maximum input optical signal is provided for the photon computing chip, the target voltage at the output side of the TIA can reach the reference voltage of the ADC, namely the target voltage at the output side of the TIA can reach the full range of the ADC, so that the problem of lower resolution caused by the fact that the voltage at the output side of the TIA is always smaller than the reference voltage of the ADC due to overlarge reference voltage of the ADC can be avoided to a certain extent.
Illustratively, when a 12-bit resolution ADC is employed, the input voltage is 0V, the resulting number is 0, the input voltage is 5V, and the resulting number is 4095, i.e., the initial reference voltage of the ADC is 5V; thus, for each 1 increase in number, the voltage actually increases by 5/4096=0.0012V.
Once the target voltage U is calculated to be 3.8V, the reference voltage of the ADC is adjusted to 3.8V, and every 1 increase in number, the voltage is actually increased by 3.8/4096=0.0009V (< 0.0012V), i.e., the resolution of the input signal is improved. Accordingly, even if the optical modulation is performed by inputting electrical signals of different magnitudes to the photonic computing chip, the resolution of the input signal of the ADC is improved as compared with the case where the initial reference voltage is 5V, and the TIA output voltage is 2V.
In some embodiments, in order not to affect other components in the link, the power supply to the link is disconnected and then the reference voltage of the ADC is adjusted to the target voltage U. In particular, the manner in which the reference voltage of the ADC is adjusted may be referred to the prior art. For example, the reference voltage is adjusted by adjusting the ADC gain. Of course, other existing ways of adjusting the reference voltage of the ADC may be used.
In this embodiment, since the debugging is performed before leaving the factory, in order to verify whether the debugging is successful or not, so as to ensure the reliability of the link, verification of the link after the debugging is also required, and in other embodiments, the adjusting method further includes the steps of:
S105 again provides the corresponding maximum input optical signal to the photonic computing chip.
In some embodiments, as described above, the ADC reference voltage is adjusted such that the power supply to the link is turned off, so that the link is restarted and initialized before verification is required, and then the corresponding maximum input optical signal is provided to the photonic computing chip for subsequent verification.
S106, obtaining an output signal of an analog-to-digital converter in a link to be tested, judging whether the output signal is a maximum range value of the analog-to-digital converter, and if so, judging that the output signal passes the verification; otherwise, it is determined that the verification is not passed, and steps S104 to S106 are performed again until it is determined that the verification is passed.
In this embodiment, as described above, since the reference voltage of the ADC is adjusted to the target voltage U, when the same maximum input optical signal is provided to the photonic computing chip again, the ADC output should be full scale, if not, it is indicated that the debugging is unsuccessful, and the debugging needs to be repeated, and if the verification is passed, that is, the debugging is successful, the target voltage U can be used as a reference to debug the same links of the same batch or model.
For example, if the reference voltage of the ADC is adjusted from 5V to 3.8V, then when the same maximum input optical signal is again provided to the photonic computing chip, the ADC will output 4095, if the ADC actual output is not 4095, indicating that the verification is failed, i.e., the debugging is successful, and if the actual output is 4095, indicating that the verification is successful.
Embodiment two: the present invention also provides another method for adjusting link resolution in an optoelectronic hybrid computing system, specifically, the method includes the steps of the first embodiment, except that the adjusting method in the present embodiment further includes the steps of, before executing step S101:
S201, acquiring an optical power input range of a photon calculation chip in each of a plurality of links to be measured.
In some embodiments, as mentioned above, since the debugging is performed before the factory, and the whole link is not changed after the factory, for a plurality of identical links to be tested (the photon calculation chips of which are identical and the links are identical) of the same batch or the same model, only at least one sample needs to be extracted therefrom for debugging, so as to find the target voltage thereof, and the plurality of identical links to be tested of the batch can be debugged according to the target voltage.
However, in practical application, different links to be tested are designed based on different application scenarios, that is, the photonic computing chips are different (i.e. have different optical power value ranges), and accordingly, the feedback resistance of TIA, the initial reference voltage of ADC, etc. are different, so when different links to be tested are debugged, especially when different links to be tested are debugged in a large scale, how to efficiently find the target voltage corresponding to each link to be tested and use the target voltage as the reference voltage of the corresponding ADC needs to be considered.
S202, grouping a plurality of links to be tested based on a preset grouping rule and an optical power value range to obtain a plurality of link groups to be tested.
In some embodiments, since the target voltage is finally determined according to the maximum value of the optical power input range of the photon computing chip, and the reference voltage of the ADC is adjusted, it is only necessary to group a plurality of links to be tested according to the maximum value. Specifically, the preset grouping rule includes: presetting a reference maximum value, and dividing a group of links to be tested, wherein the difference value between the maximum input optical signal and the preset reference maximum value is an integer multiple of a preset difference value threshold value.
For example, taking the smallest maximum value A in the maximum values in the optical power input ranges of all the photon calculation chips in the links to be measured as a reference (namely, the maximum value A is a preset reference maximum value of the first group), calculating the difference between other maximum values and the maximum value A respectively, and dividing the difference into a group, wherein the difference is an integer multiple of a preset difference threshold (preferably, the preset difference threshold is the smallest difference delta 1); then, taking the minimum maximum value B in the maximum values in the optical power input range in the rest links to be tested as a reference (namely, the maximum value B is a preset reference maximum value of a second group), respectively calculating the difference between the rest other maximum values and the maximum value B, wherein the difference is an integer multiple of a preset difference threshold (preferably, the preset difference threshold is the minimum difference delta 2) and dividing the change into a group; and so on until no further grouping is possible (e.g., one link under test remains, or no link under test remains).
S203, sorting a plurality of links to be tested in each group according to the order of the maximum value from big to small or from small to big in the optical power value range.
S204, preparing a corresponding maximum input optical signal for each link to be tested according to the sequence of each link to be tested in each group and a corresponding preset difference threshold.
When a plurality of different links to be tested need to be debugged, if the links to be tested are not distinguished, there may be a case that the maximum input optical signal required to be provided by the last link to be tested is a, the maximum input optical signal required to be provided by the next link to be tested is B (the difference between B and a is greater than the difference threshold), the maximum input optical signal required to be provided by the link to be tested is C (the difference between C and a is less than the difference threshold, and the difference between C and B is greater than the difference threshold), that is, the optical signal required to be provided by the light source needs to be increased from a to B, and then properly decreased, that is, the optical signal is called back to C. This adjustment is not a major problem if only a small number of links are to be tested and one-to-one corresponds to one light source. However, if there are many links to be tested, especially a large number of links to be tested, and the light sources are limited, one light source needs to provide different optical signals for different links to be tested, if no group debugging is performed, it is necessary to manually record the links to be tested corresponding to each light source and the optical signal sizes required to be provided by the links to be tested, for example, the links to be tested need to be numbered in advance, then the optical signal sizes corresponding to each link to be tested need to be recorded, when the adjustment is performed, the staff needs to find the number corresponding to the link to be tested first, then find the corresponding optical signal sizes in the record according to the number, and when the batch debugging is performed, this clearly greatly increases the workload of the staff; in addition, if the same light source is used to provide light signals for different links to be tested, and frequent switching is performed between the large light signal and the small light signal, the service life of the light source is shortened.
In view of this, in this embodiment, by setting a preset reference maximum value for each group, then dividing a group of links to be tested, where the difference between the links and the preset reference maximum value is an integer multiple of a preset difference threshold, and ordering the links according to a predetermined order, only the top maximum value is determined, and then the light source can be adjusted according to the preset difference threshold.
For example, if the preset reference maximum value is the smallest of all maximum values, the sorting is performed in the order from large to small, that is, the sorting is performed in such a manner that the difference from the preset reference maximum value gradually decreases; if the sorting is performed in order from small to large, the sorting is performed in such a manner that the difference from the preset reference maximum value gradually increases. For the order from small to large, let the highest value of the first row be A, and the next highest value be A+δ1, the next one is A+δ1+. δ1···and so on, until all links to be tested of the packet are adjusted. Compared with the mode without distinction, only the maximum value of the first bit arranged in each group and the preset difference threshold value corresponding to each group are required to be recorded, each link to be detected is not required to be subjected to field inquiry, and the workload of staff is greatly reduced; and, the light source of each group provides the optical signal in the mode of increasing or decrementing (for example, a light source corresponds to the case of a group), compared with the mode of frequently switching between a big optical signal and a small optical signal, the loss of the light source is reduced to a certain extent, and the service life of the light source is ensured.
Of course, in other embodiments, the preset reference maximum value may be the largest one of all maximum values, and the principle of the grouping rule and the ordering rule is the same as the above principle, which is not described herein.
Of course, in some embodiments, the difference between the corresponding maxima of the links under test in each packet may not be an increasing relationship, but there may be N δ1 differences between the corresponding maxima of two adjacent links under test. For example, the corresponding maximum value of the last link to be measured is a+kδ1, and the corresponding maximum value of the next link to be measured is a+ (k+n) δ1, and only the N and its corresponding link to be measured need to be marked in advance.
Of course, further, if the number of light sources is insufficient, that is, when the plurality of groups need to consider to share one light source, counting the number of links to be tested of each group and the preset difference threshold value between each group, and sharing one light source by the plurality of groups with the smaller number and the smaller difference value (for example, the number of links to be tested is smaller than the preset number, and the difference value between the preset difference threshold values is smaller than the preset threshold value). Of course, in other embodiments, if the number of links to be tested in a certain packet is large, a plurality of light sources may be matched accordingly.
Embodiment III: referring to fig. 3, the functional module of the link resolution adjustment system in the opto-electronic hybrid computing system according to an exemplary embodiment of the present invention specifically includes:
The optical signal determining module is used for acquiring the optical power input range of the photon computing chip in the link to be tested and determining the maximum input optical signal according to the maximum value of the optical power input range;
The light source module is used for providing the maximum input optical signal for the photon calculation chip according to the maximum input optical signal determined by the optical signal determination module, so that the input side of the transimpedance amplifier TIA in the link to be tested generates a photocurrent I meeting the preset condition; wherein, the preset condition includes: the product of the photocurrent I and the feedback resistor R f of the transimpedance amplifier TIA is smaller than the initial reference voltage V ref of the analog-to-digital converter connected in series to the output side of the transimpedance amplifier TIA, i.e., (i×r) f）＜Vref;
The main control equipment is used for acquiring the photocurrent I and calculating to obtain a target voltage U according to the photocurrent I and a feedback resistor R f of the transimpedance amplifier; then prompting to adjust the initial reference voltage V ref of the analog-to-digital converter to the target voltage U; specifically, it includes:
the first data acquisition module is used for acquiring photocurrent I output by the photon calculation chip;
The calibration module is used for calculating a target voltage U (U=I.R f) according to the photocurrent I and the feedback resistance of the transimpedance amplifier TIA; and when the target voltage U is calculated, outputting the target voltage U, and prompting the initial reference voltage V ref of the ADC to be adjusted to the target voltage U.
In some embodiments, the specific manner in which the reference voltage of the ADC is adjusted may be by various adjustment methods known in the art.
In other embodiments, the master control apparatus further includes:
the second data acquisition module is used for acquiring an output signal of the analog-to-digital converter in the link to be tested when the light source module provides the maximum input light signal to the photon calculation chip again;
The checking module is used for judging whether the output signal is the maximum range value of the analog-to-digital converter, if so, the output signal passes the checking; otherwise, judging that the verification is not passed, and prompting to readjust the reference voltage of the analog-to-digital converter until the verification is judged to be passed.
In other embodiments, the conditioning system further comprises:
The grouping module is used for acquiring the optical power input range of the photon calculation chip in each of the links to be tested, and grouping the links to be tested based on a preset grouping rule and the optical power input range to obtain a plurality of link groups to be tested; the preset grouping rule includes: presetting a reference maximum value, and dividing a group of links to be tested, wherein the difference value between the maximum input optical signal and the preset reference maximum value is an integer multiple of a preset difference value threshold value;
The sequencing module is used for sequencing a plurality of links to be tested in each link group to be tested according to the sequence from the maximum value to the small value or from the small value to the large value; and triggering the light source module to prepare a corresponding maximum input light signal for each link to be tested in advance according to the sequence of each link to be tested in each link group to be tested and a corresponding preset difference threshold value.
The invention also provides a storage medium, which comprises a stored computer program, and the computer program controls equipment in which the storage medium is positioned to execute the method for adjusting the link resolution in the photoelectric hybrid computing system in the first or second embodiment.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising several instructions for causing a computer terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.
Claims (10)
1. A method for adjusting link resolution in an opto-electronic hybrid computing system, comprising the steps of:
S101, determining the maximum input optical signal input into a photon computing chip in a link to be tested based on the maximum value in the optical power input range of the photon computing chip in the link to be tested;
S102, providing the maximum input optical signal to the photon computing chip, so that a photocurrent I meeting preset conditions is generated at the input side of a transimpedance amplifier in the link to be tested; the preset conditions include: the product of the photocurrent I and the feedback resistor R f of the transimpedance amplifier is smaller than the initial reference voltage V ref of the analog-to-digital converter connected in series at the output side of the transimpedance amplifier;
s103, acquiring the photocurrent I, and calculating to obtain a target voltage U according to the photocurrent I and a feedback resistor R f of the transimpedance amplifier;
S104, the initial reference voltage V ref of the analog-to-digital converter is regulated to the target voltage U.
2. The method for adjusting link resolution in an opto-electronic hybrid computing system according to claim 1, further comprising the steps of:
s105, providing corresponding maximum input optical signals to the photon computing chip again;
S106, obtaining an output signal of the analog-to-digital converter in the link to be tested, judging whether the output signal is the maximum range value of the analog-to-digital converter, and if so, judging that the output signal passes the verification; otherwise, it is determined that the verification is not passed, and steps S104 to S106 are performed again until it is determined that the verification is passed.
3. The method for adjusting link resolution in an opto-electronic hybrid computing system according to claim 2, further comprising, prior to step S101, the steps of:
s201, acquiring an optical power input range of a photon calculation chip in each of a plurality of links to be measured;
S202, grouping a plurality of links to be tested based on a preset grouping rule and the optical power input range to obtain a plurality of link groups to be tested; the preset grouping rule includes: presetting a reference maximum value, and dividing a group of links to be tested, wherein the difference value between the maximum input optical signal and the preset reference maximum value is an integer multiple of a preset difference value threshold value;
s203, sorting a plurality of links to be tested in each link group to be tested according to the sequence from the maximum value to the small value or from the small value to the large value;
S204, preparing corresponding maximum input optical signals for each link to be tested according to the sequence of each link to be tested in each link group to be tested and the corresponding preset difference threshold value.
4. A method of adjusting link resolution in a optoelectric hybrid computing system according to claim 3, wherein a plurality of said links to be tested are from different production lots or different models and have different optical power input ranges.
5. A system for adjusting link resolution in an opto-electronic hybrid computing system, comprising:
the optical signal determining module is used for determining the maximum input optical signal input into the photon computing chip in the link to be tested based on the maximum value in the optical power input range of the photon computing chip in the link to be tested;
The light source module is used for providing the maximum input optical signal for the photon calculation chip according to the maximum input optical signal determined by the optical signal determination module, so that a photocurrent I meeting a preset condition is generated at the input side of the transimpedance amplifier in the link to be detected; the preset conditions include: the product of the photocurrent I and the feedback resistor R f of the transimpedance amplifier is smaller than the initial reference voltage V ref of the analog-to-digital converter connected in series at the output side of the transimpedance amplifier;
The main control equipment is used for acquiring the photocurrent I and calculating to obtain a target voltage U according to the photocurrent I and a feedback resistor R f of the transimpedance amplifier; the initial reference voltage V ref of the analog-to-digital converter is then prompted to adjust to the target voltage U.
6. The system for adjusting link resolution in an opto-electronic hybrid computing system according to claim 5, wherein the master control device comprises:
the first data acquisition module is used for acquiring the photocurrent I output by the photon calculation chip;
And the calibration module is used for calculating a target voltage U according to the photocurrent I acquired by the first data acquisition module and the feedback resistor R f of the transimpedance amplifier, outputting the target voltage U when the target voltage U is calculated, and prompting the regulation of the reference voltage V ref of the analog-to-digital converter to the target voltage U.
7. The system of claim 6, wherein the light source module is further configured to provide the maximum input light signal to the photonic computing chip again for verification.
8. The system for adjusting link resolution in an opto-electronic hybrid computing system according to claim 7, wherein the master device further comprises:
The second data acquisition module is used for acquiring an output signal of the analog-to-digital converter in the link to be tested when the light source module provides the maximum input light signal to the photon calculation chip again;
The checking module is used for judging whether the output signal is the maximum range value of the analog-to-digital converter, if so, the output signal passes the checking; otherwise, judging that the verification is not passed, and prompting to readjust the reference voltage of the analog-to-digital converter until the verification is judged to be passed.
9. The system for adjusting link resolution in an opto-electronic hybrid computing system as defined in claim 6, further comprising:
The grouping module is used for acquiring the optical power input range of the photon calculation chip in each of the links to be tested, and grouping the links to be tested based on a preset grouping rule and the optical power input range to obtain a plurality of link groups to be tested; the preset grouping rule includes: presetting a reference maximum value, and dividing a group of links to be tested, wherein the difference value between the maximum input optical signal and the preset reference maximum value is an integer multiple of a preset difference value threshold value;
The sequencing module is used for sequencing a plurality of links to be tested in each link group to be tested according to the sequence from the maximum value to the small value or from the small value to the large value; and triggering the light source module to prepare a corresponding maximum input light signal for each link to be tested in advance according to the sequence of each link to be tested in each link group to be tested and a corresponding preset difference threshold value.
10. A storage medium comprising a stored computer program, wherein the computer program, when run, controls a device in which the storage medium is located to perform a method for adjusting link resolution in an opto-electronic hybrid computing system according to any one of claims 1 to 4.
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