CN118522324A - Control method of memory device - Google Patents

Control method of memory device Download PDF

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CN118522324A
CN118522324A CN202410927201.XA CN202410927201A CN118522324A CN 118522324 A CN118522324 A CN 118522324A CN 202410927201 A CN202410927201 A CN 202410927201A CN 118522324 A CN118522324 A CN 118522324A
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word line
voltage
selection
gate
target
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CN118522324B (en
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曹开玮
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Wuhan Xinxin Integrated Circuit Co ltd
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Wuhan Xinxin Integrated Circuit Co ltd
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/08Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

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  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)

Abstract

本发明公开了一种存储器件的控制方法,包括:对存储器件中存储块的多行字线中的至少一行字线执行行选择,以选中的字线作为目标字线;以目标字线所对应的选择字线作为辅助选择字线,对辅助选择字线施加辅助电压;对存储块的多列位线中的至少一列位线执行列选择,以选中的位线作为目标位线;基于选中的目标字线和目标位线确定目标存储单元,并执行存储器件操作;即本申请中对在控制栅的一侧形成选择栅的存储器件,通过目标字线的选择,并对目标字线所对应的辅助选择字线施加辅助电压,进而通过对目标位线的选择确定目标存储单元,以对目标存储单元或存储块执行存储器件操作,能有效提升控制栅和选择栅之间的击穿电压,提升存储器件的性能。

The present invention discloses a control method for a memory device, comprising: performing row selection on at least one row of word lines among multiple rows of word lines of a memory block in the memory device, taking the selected word line as a target word line; taking a selection word line corresponding to the target word line as an auxiliary selection word line, and applying an auxiliary voltage to the auxiliary selection word line; performing column selection on at least one column of bit lines among multiple columns of bit lines of the memory block, taking the selected bit line as a target bit line; determining a target memory cell based on the selected target word line and the target bit line, and performing a memory device operation; that is, in the present application, for a memory device in which a selection gate is formed on one side of a control gate, the target word line is selected, and an auxiliary voltage is applied to the auxiliary selection word line corresponding to the target word line, and then the target memory cell is determined by selecting the target bit line, so that the memory device operation is performed on the target memory cell or the memory block, which can effectively improve the breakdown voltage between the control gate and the selection gate, and improve the performance of the memory device.

Description

一种存储器件的控制方法A control method for a storage device

技术领域Technical Field

本发明涉及半导体技术领域,特别是涉及一种存储器件的控制方法。The present invention relates to the field of semiconductor technology, and in particular to a control method for a storage device.

背景技术Background Art

在集成电路的应用过程中,各类器件的性能会受到各层材料所形成的结构的影响,尤其是晶体管器件,栅极结构的不同,影响了晶体管器件的性能。In the application process of integrated circuits, the performance of various devices will be affected by the structure formed by each layer of materials, especially transistor devices. The different gate structures affect the performance of transistor devices.

在实际操作过程中,本申请的研发人员发现,当前的半导体器件控制方案中,尤其是存储器件的控制方法,通常是对应采用ETOX(Electron Tunneling Oxide device)工艺形成ETOX浮栅结构的存储器件,因为器件的结构原因,依然存在一定的性能局限,影响了存储器件的性能。During actual operation, the researchers of this application discovered that current semiconductor device control schemes, especially control methods for memory devices, usually correspond to memory devices that use an ETOX (Electron Tunneling Oxide device) process to form an ETOX floating gate structure. However, due to the structure of the device, there are still certain performance limitations that affect the performance of the memory device.

发明内容Summary of the invention

本发明主要解决的技术问题是:提供一种存储器件的控制方法,对于在控制栅的一侧形成选择栅所对应的存储器件,通过对目标字线的选择,并对目标字线所对应的辅助选择字线施加辅助电压,进而通过对目标位线的选择确定目标存储单元,以对目标存储单元或存储块执行存储器件操作,能有效提升存储器件中控制栅和选择栅之间的击穿电压,提升存储器件的性能。The main technical problem solved by the present invention is: to provide a control method for a storage device, for a storage device corresponding to a selection gate formed on one side of a control gate, by selecting a target word line and applying an auxiliary voltage to an auxiliary selection word line corresponding to the target word line, and then determining a target storage cell by selecting a target bit line, so as to perform a storage device operation on the target storage cell or storage block, which can effectively improve the breakdown voltage between the control gate and the selection gate in the storage device and improve the performance of the storage device.

为解决上述技术问题,本申请采用的一个技术方案是:提供一种存储器件的控制方法,包括:对所述存储器件中存储块的多行字线中的至少一行所述字线执行行选择,以选中的所述字线作为目标字线;其中,所述存储块的字线中包括多个存储单元,每一所述存储单元具有源极区和漏极区、沟道区、设置在沟道区之上且靠近所述漏极区的浮栅和控制栅、设置沟道区之上且靠近所述源极区的选择栅,所述控制栅对应所述字线,所述选择栅对应选择字线;以所述目标字线所对应的选择字线作为辅助选择字线,对所述辅助选择字线施加辅助电压;对所述存储器件中存储块的多列位线中的至少一列所述位线执行列选择,以选中的所述位线作为目标位线;基于选中的所述目标字线和所述目标位线确定目标存储单元,对所述目标存储单元或所述存储块执行存储器件操作。In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a control method of a memory device, comprising: performing row selection on at least one row of word lines in a plurality of rows of word lines of a memory block in the memory device, and taking the selected word line as a target word line; wherein the word line of the memory block includes a plurality of memory cells, each of the memory cells having a source region and a drain region, a channel region, a floating gate and a control gate arranged above the channel region and close to the drain region, and a selection gate arranged above the channel region and close to the source region, the control gate corresponding to the word line, and the selection gate corresponding to the selection word line; taking the selection word line corresponding to the target word line as an auxiliary selection word line, and applying an auxiliary voltage to the auxiliary selection word line; performing column selection on at least one column of bit lines in a plurality of columns of bit lines of a memory block in the memory device, and taking the selected bit line as a target bit line; determining a target memory cell based on the selected target word line and the target bit line, and performing a memory device operation on the target memory cell or the memory block.

在本申请一实施例中,响应于所述存储器件操作为单个存储单元的读操作,所述控制方法包括:在所述目标字线上施加第一选择电压,以及在所述辅助选择字线上施加第一辅助电压;在所述目标位线上施加读取电压,确定选中的所述目标存储单元是否有电流流过,以确定所述目标存储单元是否存储有电子。In one embodiment of the present application, in response to the memory device operating as a read operation of a single memory cell, the control method includes: applying a first selection voltage on the target word line, and applying a first auxiliary voltage on the auxiliary selection word line; applying a read voltage on the target bit line to determine whether current flows through the selected target memory cell to determine whether the target memory cell stores electrons.

在本申请一实施例中,所述第一选择电压为2V~3V,所述第一辅助电压为2V~3V,所述读取电压为0.5V~1.2V,所述基底电压为0V。In an embodiment of the present application, the first selection voltage is 2V to 3V, the first auxiliary voltage is 2V to 3V, the read voltage is 0.5V to 1.2V, and the base voltage is 0V.

在本申请一实施例中,响应于所述存储器件操作为单个存储单元的写操作,所述控制方法包括:在所述目标字线上施加第二选择电压,以及在所述辅助选择字线上施加第二辅助电压;在所述目标位线上施加写入电压,向选中的目标存储单元的浮栅注入电子。In one embodiment of the present application, in response to the memory device operating as a write operation of a single memory cell, the control method includes: applying a second selection voltage on the target word line, and applying a second auxiliary voltage on the auxiliary selection word line; applying a write voltage on the target bit line to inject electrons into the floating gate of the selected target memory cell.

在本申请一实施例中,所述第二选择电压为5V~10V,所述第二辅助电压为0.5V~1.5V,所述写入电压为3V~4.5V。In an embodiment of the present application, the second selection voltage is 5V to 10V, the second auxiliary voltage is 0.5V to 1.5V, and the write voltage is 3V to 4.5V.

在本申请一实施例中,所述存储器件的存储块包括衬底,所述衬底中还包括阱区,所述存储块中存储单元的所述源极区、所述漏极区和所述沟道区设置在所述阱区中;响应于所述存储器件操作为读操作或写操作,给所述阱区施加基底电压,其中,所述基底电压为0V。In one embodiment of the present application, the storage block of the storage device includes a substrate, the substrate also includes a well region, the source region, the drain region and the channel region of the storage unit in the storage block are arranged in the well region; in response to the storage device operating as a read operation or a write operation, a substrate voltage is applied to the well region, wherein the substrate voltage is 0V.

在本申请一实施例中,所述存储器件的存储块包括衬底,所述衬底中还包括阱区,存储块中存储单元的所述源极区、所述漏极区和所述沟道区设置在所述阱区中,其中,所述选择栅的上表面低于所述控制栅的下表面;响应于所述存储器件操作为擦除操作,给所述阱区施加擦除电压。In one embodiment of the present application, a storage block of the storage device includes a substrate, the substrate also includes a well region, the source region, the drain region and the channel region of the storage cell in the storage block are arranged in the well region, wherein the upper surface of the selection gate is lower than the lower surface of the control gate; in response to the storage device operating as an erase operation, an erase voltage is applied to the well region.

在本申请一实施例中,响应所述存储器件操作为擦除操作,所述控制方法包括:在所述存储块的字线上施加第三选择电压,以及在所述存储块的选择字线上施加第三辅助电压;在所述阱区上施加擦除电压,擦除所述存储块中存储单元的浮栅中的电子;其中,将所述存储块的位线和源极线浮置。In one embodiment of the present application, in response to the memory device operating as an erase operation, the control method includes: applying a third selection voltage to the word line of the memory block, and applying a third auxiliary voltage to the selection word line of the memory block; applying an erase voltage to the well region to erase electrons in the floating gate of the memory cell in the memory block; wherein the bit line and the source line of the memory block are floated.

在本申请一实施例中,所述擦除电压大于或等于所述第三辅助电压,或所述存储块的选择字线为浮置。In an embodiment of the present application, the erase voltage is greater than or equal to the third auxiliary voltage, or the selected word line of the memory block is floating.

在本申请一实施例中,所述第三选择电压为-6V~-10V,所述擦除电压为6V~10V,所述第三辅助电压为0V~10V。In an embodiment of the present application, the third selection voltage is -6V to -10V, the erase voltage is 6V to 10V, and the third auxiliary voltage is 0V to 10V.

在本申请一实施例中,在垂直方向上,所述选择栅的厚度小于所述控制栅的厚度。In an embodiment of the present application, in the vertical direction, the thickness of the select gate is smaller than the thickness of the control gate.

在本申请一实施例中,所述控制栅所对应的衬底上设置有第一栅绝缘层,所述选择栅对应的衬底上设置有第二栅绝缘层,在垂直方向上,所述第二栅绝缘层的厚度大于所述第一栅绝缘层的厚度。In one embodiment of the present application, a first gate insulating layer is provided on the substrate corresponding to the control gate, and a second gate insulating layer is provided on the substrate corresponding to the select gate. In the vertical direction, the thickness of the second gate insulating layer is greater than the thickness of the first gate insulating layer.

区别于现有技术,本申请提供的存储器件的控制方法,包括:对存储器件中存储块的多行字线中的至少一行字线执行行选择,以选中的字线作为目标字线;其中,存储块的字线中包括多个存储单元,每一存储单元具有源极区和漏极区、沟道区、设置在沟道区之上且靠近漏极区的浮栅和控制栅、设置沟道区之上且靠近源极区的选择栅,控制栅对应字线,选择栅对应选择字线;以目标字线所对应的选择字线作为辅助选择字线,对辅助选择字线施加辅助电压;对存储器件中存储块的多列位线中的至少一列位线执行列选择,以选中的位线作为目标位线;基于选中的目标字线和目标位线确定目标存储单元,对目标存储单元或存储块执行存储器件操作;即本申请利用在控制栅的一侧形成选择栅,并设置选择栅的上表面低于控制栅的下表面所对应的存储器件,降低控制栅与选择栅之间的耦合面积,以降低等效的栅极电容,提高器件可靠性,同时提升了控制栅与选择栅之间的击穿电压,使得对应的承压的调节范围增大,通过对目标字线的选择,并对目标字线所对应的辅助选择字线施加辅助电压,进而通过对目标位线的选择确定目标存储单元,以对目标存储单元或存储块执行存储器件操作,进而提升了存储器件的性能。Different from the prior art, the control method of the memory device provided by the present application comprises: performing row selection on at least one row of word lines among multiple rows of word lines of a memory block in the memory device, and taking the selected word line as the target word line; wherein the word line of the memory block comprises multiple memory cells, each memory cell comprises a source region and a drain region, a channel region, a floating gate and a control gate arranged above the channel region and close to the drain region, and a selection gate arranged above the channel region and close to the source region, the control gate corresponds to the word line, and the selection gate corresponds to the selection word line; taking the selection word line corresponding to the target word line as an auxiliary selection word line, and applying an auxiliary voltage to the auxiliary selection word line; performing column selection on at least one column of bit lines among multiple columns of bit lines of a memory block in the memory device, and taking the selected bit line as the target bit line; based on the selected The target word line and the target bit line determine the target memory cell, and perform a memory device operation on the target memory cell or the memory block; that is, the present application forms a selection gate on one side of the control gate, and sets the upper surface of the selection gate to be lower than the lower surface of the control gate corresponding to the memory device, reduces the coupling area between the control gate and the selection gate, so as to reduce the equivalent gate capacitance, improve the device reliability, and at the same time improve the breakdown voltage between the control gate and the selection gate, so that the corresponding pressure adjustment range is increased, and the target word line is selected, and an auxiliary voltage is applied to the auxiliary selection word line corresponding to the target word line, and then the target memory cell is determined by selecting the target bit line, so as to perform a memory device operation on the target memory cell or the memory block, thereby improving the performance of the memory device.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

为了更清楚地说明本申请实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。其中:In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

图1是本申请中存储器件的控制方法一实施例的流程示意图;FIG1 is a flow chart of an embodiment of a method for controlling a storage device in the present application;

图2是本申请中存储单元一实施例的结构示意图;FIG2 is a schematic structural diagram of an embodiment of a storage unit in the present application;

图3是本申请中存储器件中存储块的电路图;FIG3 is a circuit diagram of a storage block in a storage device in the present application;

图4是本申请中读操作一实施例的结构示意图;FIG4 is a schematic diagram of a structure of an embodiment of a read operation in the present application;

图5是本申请中写操作一实施例的结构示意图;FIG5 is a schematic diagram of a structure of an embodiment of a write operation in the present application;

图6是本申请中擦除操作一实施例的结构示意图。FIG. 6 is a schematic structural diagram of an embodiment of an erase operation in the present application.

附图中,存储单元10、衬底100、栅极堆叠结构200、第一栅绝缘层210、浮栅220、第一栅间介质层230、控制栅240、选择栅300、第二栅间介质层310、第二栅绝缘层320、隔离侧墙400、第一隔离侧墙410、第二隔离侧墙420、第三隔离侧墙430、源极区S、漏极区D、第一字线W0、第二字线W1、第三字线W2、第一位线B0、第二位线B1、第三位线B2、第一选择字线S0、第二选择字线S1、第三选择字线S2、第一存储单元A00、第二存储单元A10、第三存储单元A20、第四存储单元A01、第五存储单元A11、第六存储单元A21、第七存储单元A02、第八存储单元A12、第九存储单元A22。In the accompanying drawings, a memory cell 10, a substrate 100, a gate stack structure 200, a first gate insulating layer 210, a floating gate 220, a first inter-gate dielectric layer 230, a control gate 240, a select gate 300, a second inter-gate dielectric layer 310, a second gate insulating layer 320, an isolation sidewall 400, a first isolation sidewall 410, a second isolation sidewall 420, a third isolation sidewall 430, a source region S, a drain region D, a first word line W0, a second word line W1, a third word line W2, a first bit line B0, a second bit line B1, a third bit line B2, a first selection word line S0, a second selection word line S1, a third selection word line S2, a first memory cell A00, a second memory cell A10, a third memory cell A20, a fourth memory cell A01, a fifth memory cell A11, a sixth memory cell A21, a seventh memory cell A02, an eighth memory cell A12, and a ninth memory cell A22.

具体实施方式DETAILED DESCRIPTION

下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅是本申请的一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

在当前的半导体器件控制方法中,尤其是存储器件的控制,通常是对应采用ETOX(Electron Tunneling Oxide device)工艺形成ETOX浮栅结构的存储器件,因为器件的结构原因,依然存在一定的性能局限,进而影响了存储器件的存储性能。In current semiconductor device control methods, especially the control of memory devices, a memory device with an ETOX floating gate structure formed by an ETOX (Electron Tunneling Oxide device) process is usually used. However, due to the structure of the device, there are still certain performance limitations, which in turn affects the storage performance of the memory device.

因此,提供一种存储器件的控制方法,利用在控制栅的一侧形成选择栅,且选择栅的上表面低于控制栅的下表面所对应的存储器件,通过对目标字线的选择,并对目标字线所对应的辅助选择字线施加辅助电压,进而通过对目标位线的选择确定目标存储单元,以对目标存储单元或存储块执行存储器件操作,能有效提升控制栅和选择栅之间的击穿电压,提升存储器件的性能。Therefore, a control method for a storage device is provided, which utilizes a storage device corresponding to a selection gate formed on one side of a control gate, wherein the upper surface of the selection gate is lower than the lower surface of the control gate. By selecting a target word line and applying an auxiliary voltage to an auxiliary selection word line corresponding to the target word line, a target storage cell is determined by selecting a target bit line, so that a storage device operation is performed on the target storage cell or storage block, which can effectively improve the breakdown voltage between the control gate and the selection gate, thereby improving the performance of the storage device.

请参阅图1,图1是本申请中存储器件的控制方法一实施例的流程示意图。Please refer to FIG. 1 , which is a flow chart of an embodiment of a method for controlling a storage device in the present application.

如图1所述,存储器件的控制方法包括:As shown in FIG. 1 , the control method of the storage device includes:

S10、对存储器件中存储块的多行字线中的至少一行字线执行行选择,以选中的字线作为目标字线;S10, performing row selection on at least one row of word lines in a plurality of rows of word lines in a storage block in a storage device, and taking the selected word line as a target word line;

其中,存储器件包括至少一存储块,存储块包括多行字线和多列位线,存储块的字线中包括多个存储单元,每一存储单元具有源极区和漏极区、沟道区、设置在沟道区之上且靠近漏极区的浮栅和控制栅、设置沟道区之上且靠近源极区的选择栅,控制栅对应字线,选择栅对应选择字线,在一些实施例中,选择栅的上表面低于控制栅的下表面。The memory device includes at least one memory block, the memory block includes multiple rows of word lines and multiple columns of bit lines, the word lines of the memory block include multiple memory cells, each memory cell has a source region and a drain region, a channel region, a floating gate and a control gate arranged above the channel region and close to the drain region, and a selection gate arranged above the channel region and close to the source region, the control gate corresponds to the word line, and the selection gate corresponds to the selection word line. In some embodiments, the upper surface of the selection gate is lower than the lower surface of the control gate.

具体地,存储器件包括有存储块,存储块可以包括多行字线和多列位线,每一行的字线对应连接该行字线中每一存储单元的控制栅,因此,在对存储块的多行字线中的至少一行字线执行行选择时,例如对至少一行字线施加选择电压,则可以将选中的字线作为目标字线,则目标字线上的存储单元都被选中。Specifically, the memory device includes a memory block, which may include multiple rows of word lines and multiple columns of bit lines. The word lines in each row correspond to the control gates of each memory cell in the word lines in that row. Therefore, when row selection is performed on at least one row of word lines in the multiple rows of word lines in the memory block, for example, a selection voltage is applied to at least one row of word lines, the selected word line can be used as a target word line, and the memory cells on the target word line are all selected.

S20、以目标字线所对应的选择字线作为辅助选择字线,对辅助选择字线施加辅助电压。S20 , using the selection word line corresponding to the target word line as an auxiliary selection word line, and applying an auxiliary voltage to the auxiliary selection word line.

其中,因为存储单元中还存在有设置在控制栅一侧的选择栅,因此,每一字线都配置有对应的选择字线,即每一行字线有一行对应的选择字线,选择字线也对应连接该行字线中每一存储单元的选择栅。Among them, because there is a selection gate set on one side of the control gate in the memory cell, each word line is configured with a corresponding selection word line, that is, each row of word lines has a corresponding row of selection word lines, and the selection word line also corresponds to the selection gate of each memory cell in the row of word lines.

具体地,在执行行选择,以选中的字线作为目标字线之后,目标字线所对应的选择字线也被选择,且作为辅助选择字线,并对辅助选择字线施加辅助电压,也即对所选择的一行存储单元的选择栅施加辅助电压,以便执行对应的存储器件操作。Specifically, after row selection is performed and the selected word line is used as the target word line, the selection word line corresponding to the target word line is also selected and used as an auxiliary selection word line, and an auxiliary voltage is applied to the auxiliary selection word line, that is, an auxiliary voltage is applied to the selection gates of a selected row of memory cells, so as to perform the corresponding storage device operation.

S30、对存储器件中存储块的多列位线中的至少一列位线执行列选择,以选中的位线作为目标位线。S30 , performing column selection on at least one column of bit lines in a plurality of columns of bit lines in a storage block in a storage device, and taking the selected bit line as a target bit line.

其中,每一列的位线对应连接该列位线中每一存储单元的漏极。Each column of bit lines is correspondingly connected to the drain of each storage unit in the column of bit lines.

具体地,对存储块的多列位线中的至少一列位线执行列选择时,以选中的位线作为目标位线,例如对至少一列位线施加一个电压,则可以将选中的位线作为目标位线,则目标位线上的存储单元都被选中。Specifically, when column selection is performed on at least one column of multiple columns of bit lines in a storage block, the selected bit line is used as the target bit line. For example, a voltage is applied to at least one column of bit lines, and the selected bit line can be used as the target bit line, so that all storage cells on the target bit line are selected.

S40、基于选中的目标字线和目标位线确定目标存储单元,对目标存储单元或存储块执行存储器件操作。S40 , determining a target memory cell based on the selected target word line and target bit line, and performing a memory device operation on the target memory cell or memory block.

具体地,每一行字线与每一列位线有对应连接点,该连接点所对应的存储单元即为目标存储单元,即,目标字线连接目标存储单元的控制栅,目标位线连接目标存储单元的源极区,而辅助选择字线则连接目标存储单元的选择栅;因此,分别对控制栅、源极区和选择栅施加对应的电压,即可对目标存储单元或存储块执行存储器件操作,如读操作、写操作、擦除操作等。Specifically, each row word line has a corresponding connection point with each column bit line, and the storage cell corresponding to the connection point is the target storage cell, that is, the target word line is connected to the control gate of the target storage cell, the target bit line is connected to the source region of the target storage cell, and the auxiliary selection word line is connected to the selection gate of the target storage cell; therefore, by applying corresponding voltages to the control gate, the source region and the selection gate, respectively, the storage device operation, such as read operation, write operation, erase operation, etc., can be performed on the target storage cell or storage block.

在本实施例中,针对在控制栅的一侧形成选择栅,且选择栅的上表面低于控制栅的下表面所对应的存储器件,通过对该存储器件进行目标字线的选择,并对目标字线所对应的辅助选择字线施加辅助电压,进而通过对目标位线的选择确定目标存储单元,以对目标存储单元或存储块执行存储器件操作,能有效提升控制栅和选择栅之间的击穿电压,提升存储器件的性能。In the present embodiment, for a storage device corresponding to a selection gate formed on one side of a control gate and having an upper surface of the selection gate lower than a lower surface of the control gate, a target word line is selected for the storage device, and an auxiliary voltage is applied to an auxiliary selection word line corresponding to the target word line, and then a target storage cell is determined by selecting a target bit line, so that a storage device operation is performed on the target storage cell or storage block, thereby effectively improving the breakdown voltage between the control gate and the selection gate and improving the performance of the storage device.

以下将结合存储单元的具体结构进行控制方法的描述。The control method will be described below in conjunction with the specific structure of the storage unit.

请参阅图2,图2是本申请中存储单元一实施例的结构示意图。Please refer to FIG. 2 , which is a schematic diagram of the structure of a storage unit according to an embodiment of the present application.

如图2所示,存储单元10包括衬底100、栅极堆叠结构200和选择栅300;栅极堆叠结构200设置在衬底100上,栅极堆叠结构200至少包括浮栅和控制栅,选择栅300设置在栅极堆叠结构200的一侧,在一些实施例中,选择栅的上表面低于控制栅的下表面,以降低选择栅和控制栅之间的耦合面积,同时提升控制栅和选择栅之间的击穿电压。As shown in FIG. 2 , the memory cell 10 includes a substrate 100, a gate stack structure 200 and a selection gate 300; the gate stack structure 200 is disposed on the substrate 100, the gate stack structure 200 includes at least a floating gate and a control gate, and the selection gate 300 is disposed on one side of the gate stack structure 200. In some embodiments, the upper surface of the selection gate is lower than the lower surface of the control gate to reduce the coupling area between the selection gate and the control gate, while increasing the breakdown voltage between the control gate and the selection gate.

其中,栅极堆叠结构200包括第一栅绝缘层210、浮栅220、第一栅间介质层230和控制栅240;选择栅300设置在栅极堆叠结构200一侧的衬底100上;栅极堆叠结构200和选择栅300之间设置有第二栅间介质层310,且选择栅300与衬底100之间还设置有第二栅绝缘层320,在一些实施例中,第二栅绝缘层320的上表面高于第一栅绝缘层的上表面,即在垂直方向上,第二栅绝缘层的厚度大于第一栅绝缘层的厚度,可以防止选择栅中的电子进入衬底,即擦除时选择栅300会接电源,如果第二栅绝缘层320太薄会有电子源源不断地涌入衬底,反而不利于擦除。当然这并不意味着第二栅绝缘层320的上表面高于第一栅绝缘层的上表面(第二栅绝缘层320厚度大于第一栅绝缘层的上表面)是本案的必选特征,可以通过控制方法的调整或工艺的调整来达到类似的技术效果。Among them, the gate stack structure 200 includes a first gate insulation layer 210, a floating gate 220, a first inter-gate dielectric layer 230 and a control gate 240; the selection gate 300 is arranged on the substrate 100 on one side of the gate stack structure 200; a second inter-gate dielectric layer 310 is arranged between the gate stack structure 200 and the selection gate 300, and a second gate insulation layer 320 is also arranged between the selection gate 300 and the substrate 100. In some embodiments, the upper surface of the second gate insulation layer 320 is higher than the upper surface of the first gate insulation layer, that is, in the vertical direction, the thickness of the second gate insulation layer is greater than the thickness of the first gate insulation layer, which can prevent electrons in the selection gate from entering the substrate, that is, the selection gate 300 will be connected to the power supply during erasing. If the second gate insulation layer 320 is too thin, electrons will continuously flow into the substrate, which is not conducive to erasing. Of course, this does not mean that the upper surface of the second gate insulation layer 320 is higher than the upper surface of the first gate insulation layer (the thickness of the second gate insulation layer 320 is greater than the upper surface of the first gate insulation layer) is a required feature of this case. Similar technical effects can be achieved by adjusting the control method or the process.

并且,对栅极堆叠结构200和选择栅300设置有隔离侧墙400,覆盖栅极堆叠结构200和控制栅240所裸露的侧壁,其中,隔离侧墙包括第一隔离侧墙410、第二隔离侧墙420和第三隔离侧墙430,第一隔离侧墙410设置在栅极堆叠结构200远离选择栅的一侧,以覆盖栅极堆叠结构200裸露的侧壁;第二隔离侧墙420设置选择栅远离栅极堆叠结构的一侧的侧壁,以覆盖选择栅远离栅极堆叠结构一侧所裸露的侧壁;第三隔离侧墙430设置在栅极堆叠结构200靠近选择栅一侧的选择栅300之上,以覆盖栅极堆叠结构在选择栅一侧裸露的侧壁。在一些实施例中,第三隔离侧墙430可以省略。In addition, an isolation sidewall 400 is provided for the gate stack structure 200 and the selection gate 300 to cover the exposed sidewalls of the gate stack structure 200 and the control gate 240, wherein the isolation sidewall includes a first isolation sidewall 410, a second isolation sidewall 420 and a third isolation sidewall 430, wherein the first isolation sidewall 410 is provided on the side of the gate stack structure 200 away from the selection gate to cover the exposed sidewall of the gate stack structure 200; the second isolation sidewall 420 is provided on the side of the selection gate away from the gate stack structure to cover the exposed sidewall of the selection gate away from the gate stack structure; the third isolation sidewall 430 is provided on the selection gate 300 on the side of the gate stack structure 200 close to the selection gate to cover the exposed sidewall of the gate stack structure on the side of the selection gate. In some embodiments, the third isolation sidewall 430 may be omitted.

进一步地,存储单元还包括源极区S和漏极区D,其中,源极区S设置在选择栅300远离栅极堆叠结构200的一侧的衬底100中,漏极区D则设置在栅极堆叠结构200远离选择栅300的一侧的衬底中。Furthermore, the memory cell further includes a source region S and a drain region D, wherein the source region S is disposed in the substrate 100 on a side of the selection gate 300 away from the gate stack structure 200 , and the drain region D is disposed in the substrate on a side of the gate stack structure 200 away from the selection gate 300 .

在一些实施例中,可以根据设计的不同,源极区S和漏极区D的位置可以互换。In some embodiments, the positions of the source region S and the drain region D may be interchanged according to different designs.

在一实施例中,存储器件的存储块包括衬底,存储单元的源极区、漏极区和沟道区设置在衬底中。In one embodiment, a memory block of a memory device includes a substrate, and a source region, a drain region, and a channel region of a memory cell are disposed in the substrate.

其中,衬底中还包括阱区,存储单元的源极区、漏极区和沟道区的设置在阱区中,以给阱区施加擦除电压或基底电压。The substrate also includes a well region, and the source region, the drain region and the channel region of the storage unit are arranged in the well region so as to apply an erase voltage or a substrate voltage to the well region.

而存储器件中存储块的多个存储单元的连接,则用电路图进行示意。The connection of multiple memory cells of a memory block in a memory device is illustrated by a circuit diagram.

请参阅图3,图3是本申请中存储器件中存储块的电路图。Please refer to FIG. 3 , which is a circuit diagram of a storage block in a storage device in the present application.

如图3所述,存储器件的存储块包括多行字线、多行选择字线和多列位线,以三行字线和三列位线为示例进行具体描述,三行字线包括第一字线W0、第二字线W1和第三字线W2;三列位线包括第一位线B0、第二位线B1和第三位线B2;对应的三行选择字线包括第一选择字线S0、第二选择字线S1和第三选择字线S2;则有,存储单元中包含有控制栅240、浮栅220、选择栅300、源极区S和漏极区D,每一行字线连接该行中存储单元的控制栅240,每一行选择字线连接该行中存储单元的选择栅300,每一列位线则连接该列中存储单元的漏极区D,而每一存储单元的源极区S则接地。As shown in FIG3 , a storage block of a storage device includes a plurality of rows of word lines, a plurality of rows of selection word lines and a plurality of columns of bit lines. A specific description is given by taking three rows of word lines and three columns of bit lines as an example. The three rows of word lines include a first word line W0, a second word line W1 and a third word line W2; the three columns of bit lines include a first bit line B0, a second bit line B1 and a third bit line B2; the corresponding three rows of selection word lines include a first selection word line S0, a second selection word line S1 and a third selection word line S2; then, a storage cell includes a control gate 240, a floating gate 220, a selection gate 300, a source region S and a drain region D, each row of word lines is connected to the control gate 240 of the storage cell in the row, each row of selection word lines is connected to the selection gate 300 of the storage cell in the row, each column of bit lines is connected to the drain region D of the storage cell in the column, and the source region S of each storage cell is grounded.

例如,第一字线W0连接同一行的第一存储单元A00、第二存储单元A10和第三存储单元A20的控制栅,第一选择字线S0连接第一存储单元A00、第二存储单元A10和第三存储单元A20的选择栅;第二字线W1连接同一行的第四存储单元A01、第五存储单元A11和第六存储单元A21的控制栅,第二选择字线S1连接第四存储单元A01、第五存储单元A11和第六存储单元A21的选择栅;第三字线W2连接同一行的第七存储单元A02、第八存储单元A12和第九存储单元A22的控制栅,第三选择字线S2连接第七存储单元A02、第八存储单元A12和第九存储单元A22的选择栅;则第一位线B0则连接同一列的第一存储单元A00、第四存储单元A01和第七存储单元A02的漏极区,第二位线B1则连接同一列的第二存储单元A10、第五存储单元A11和第八存储单元A12的漏极区,第三位线B2则连接同一列的第三存储单元A20、第六存储单元A21和第九存储单元A22的漏极区。For example, the first word line W0 connects the control gates of the first storage cell A00, the second storage cell A10 and the third storage cell A20 in the same row, and the first selection word line S0 connects the selection gates of the first storage cell A00, the second storage cell A10 and the third storage cell A20; the second word line W1 connects the control gates of the fourth storage cell A01, the fifth storage cell A11 and the sixth storage cell A21 in the same row, and the second selection word line S1 connects the selection gates of the fourth storage cell A01, the fifth storage cell A11 and the sixth storage cell A21; the third word line W2 connects the seventh storage cell A02, the eighth storage cell A11 and the sixth storage cell A21 in the same row. The control gates of the storage cells A12 and the ninth storage cell A22, the third selection word line S2 is connected to the selection gates of the seventh storage cell A02, the eighth storage cell A12 and the ninth storage cell A22; the first bit line B0 is connected to the drain regions of the first storage cell A00, the fourth storage cell A01 and the seventh storage cell A02 in the same column, the second bit line B1 is connected to the drain regions of the second storage cell A10, the fifth storage cell A11 and the eighth storage cell A12 in the same column, and the third bit line B2 is connected to the drain regions of the third storage cell A20, the sixth storage cell A21 and the ninth storage cell A22 in the same column.

基于选中的目标字线和目标位线确定目标存储单元,对目标存储单元或存储块执行存储器件操作。A target memory cell is determined based on the selected target word line and target bit line, and a memory device operation is performed on the target memory cell or memory block.

其中,存储器件操作包括读操作、写操作、和/或擦除操作。The storage device operation includes a read operation, a write operation, and/or an erase operation.

在一具体实施方式中,响应于存储器件操作为单个存储单元的读操作,则存储器件的控制方法包括:In a specific implementation, in response to the memory device operating as a read operation of a single memory cell, the control method of the memory device includes:

对存储器件中存储块的多行字线中的至少一行字线施加第一选择电压。A first selection voltage is applied to at least one row of word lines among a plurality of rows of word lines of a memory block in a memory device.

其中,如图3所述,存储块的多行字线可以为三行字线,第一字线W0、第二字线W1和第三字线W2,以第二字线W1为选中的目标字线,因此,可以在存储块中第二字线W1上施加第一选择电压,第一选择电压可以为正电压,比如2V~3V,具体可以是2.5V。As shown in FIG3 , the multiple rows of word lines of the storage block may be three rows of word lines, namely, a first word line W0, a second word line W1 and a third word line W2, with the second word line W1 being the selected target word line. Therefore, a first selection voltage may be applied to the second word line W1 in the storage block. The first selection voltage may be a positive voltage, such as 2V to 3V, and may be specifically 2.5V.

接着对目标字线所对应的辅助选择字线施加第一辅助电压。Then, a first auxiliary voltage is applied to the auxiliary selection word line corresponding to the target word line.

其中,选择字线对应也有三行,第一选择字线S0、第二选择字线S1和第三选择字线S2;即在选中的目标字线时,对应有辅助选择字线,则在目标字线为第二字线W1时,对应的辅助选择字线为第二选择字线S1;因此,可以在存储块中第二选择字线S1上施加第一辅助电压。其中,第一辅助电压可以与第一选择电压相同,即第一辅助电压也可以为正电压,比如2V~3V,具体可以是2.5V。There are also three corresponding lines for the selection word line, the first selection word line S0, the second selection word line S1 and the third selection word line S2; that is, when the target word line is selected, there is a corresponding auxiliary selection word line, and when the target word line is the second word line W1, the corresponding auxiliary selection word line is the second selection word line S1; therefore, the first auxiliary voltage can be applied to the second selection word line S1 in the storage block. The first auxiliary voltage can be the same as the first selection voltage, that is, the first auxiliary voltage can also be a positive voltage, such as 2V to 3V, specifically 2.5V.

对存储块的多列位线中的至少一列位线施加读取电压,确定选中的目标存储单元是否有电流流过,即读取目标存储单元的电流,以确定目标存储单元是否存储有电子。A read voltage is applied to at least one bit line in the plurality of bit lines of the storage block to determine whether current flows through the selected target storage cell, that is, the current of the target storage cell is read to determine whether the target storage cell stores electrons.

继续参阅图3,存储块的多列位线可以为三列位线,包括第一位线B0、第二位线B1和第三位线B2;以第二位线作为目标位线,则有,可以在存储块中第二位线B1上施加读取电压,确定由第二字线W1和第二位线B1所选中的第五存储单元A11为目标存储单元,进而确定第五存储单元A11是否有电流流过,以确定第五存储单元A11是否存储有电子;在一些实施例中,读取电压为正电压,比如0.5V~1.2V,具体可以是0.8V,且存储块中所有存储单元的源极区通过公共源极线被施加0V的源极电压,所有存储单元的阱区被施加0V的基底电压。Continuing to refer to FIG. 3 , the multiple columns of bit lines of the storage block may be three columns of bit lines, including a first bit line B0, a second bit line B1 and a third bit line B2; taking the second bit line as the target bit line, a read voltage may be applied to the second bit line B1 in the storage block to determine that the fifth storage cell A11 selected by the second word line W1 and the second bit line B1 is the target storage cell, and then determine whether current flows through the fifth storage cell A11 to determine whether electrons are stored in the fifth storage cell A11; in some embodiments, the read voltage is a positive voltage, such as 0.5V to 1.2V, specifically 0.8V, and a source voltage of 0V is applied to the source regions of all storage cells in the storage block through a common source line, and a substrate voltage of 0V is applied to the well regions of all storage cells.

其中,若存储单元的栅极堆叠结构中存储有电子,存储单元的阈值电压上升,存储单元的控制栅上接收的2.5V的第一选择电压不足以打开沟道区导电,则存储单元的源极区和漏极区之间可以不产生电流,读取的数据为“0”。若存储单元未存储有电子,存储单元的控制栅上接收的2.5V的第一选择电压足以打开源极区和漏极区之间的沟道区导电,则存储单元的源极区和漏极区之间产生电流,读取的数据为“1”。Among them, if electrons are stored in the gate stack structure of the memory cell, the threshold voltage of the memory cell rises, and the first selection voltage of 2.5V received on the control gate of the memory cell is not enough to open the channel region for conduction, then no current may be generated between the source region and the drain region of the memory cell, and the read data is "0". If no electrons are stored in the memory cell, the first selection voltage of 2.5V received on the control gate of the memory cell is enough to open the channel region between the source region and the drain region for conduction, then current is generated between the source region and the drain region of the memory cell, and the read data is "1".

以下,存储单元的结构进行详细说明存储器件操作为读操作。Below, the structure of the memory cell is described in detail and the memory device operation is a read operation.

请参阅图4,图4是本申请中读操作一实施例的结构示意图。Please refer to FIG. 4 , which is a schematic diagram of the structure of an embodiment of a read operation in the present application.

参阅图4所示,在图2的基础上,对选中的目标存储单元,在控制栅上施加第一选择电压,此时第一选择电压可以为2.5V,并在选择栅上施加第一辅助电压,此时第一辅助电压为2.5V,以及在漏极区D上施加读取电压,此时读取电压为0.8V;而对应源极区和衬底中的阱区,则施加0V的基底电压;若浮栅中存储有电子,则沟道区不导电,源极区S和漏极区D之间不产生电流,读取的数据为“0”;若浮栅中未存储有电子,则沟道区导电,源极区S和漏极区D之间产生电流,且电子从源极区流向漏极区,既检测到有电流通过,读取的数据为“1”。Referring to FIG. 4 , based on FIG. 2 , for the selected target memory cell, a first selection voltage is applied to the control gate, and the first selection voltage may be 2.5V at this time. A first auxiliary voltage is applied to the selection gate, and the first auxiliary voltage is 2.5V at this time. A read voltage is applied to the drain region D, and the read voltage is 0.8V at this time. A substrate voltage of 0V is applied to the corresponding source region and the well region in the substrate. If electrons are stored in the floating gate, the channel region is not conductive, and no current is generated between the source region S and the drain region D, and the read data is "0". If electrons are not stored in the floating gate, the channel region is conductive, and a current is generated between the source region S and the drain region D, and electrons flow from the source region to the drain region, and current is detected to pass through, and the read data is "1".

在另一具体实施例中,响应于存储器件操作为单个存储单元的写操作,则存储器件的控制方法包括:In another specific embodiment, in response to the memory device operating as a write operation of a single memory cell, the control method of the memory device includes:

对存储器件中存储块的多行字线中的至少一行字线施加第二选择电压。A second selection voltage is applied to at least one row of word lines among a plurality of rows of word lines of a memory block in the memory device.

其中,如图3所述,存储块的多行字线可以为三行字线,第一字线W0、第二字线W1和第三字线W2,以第二字线W1为选中的目标字线,因此,可以在存储块中第二字线W1上施加第二选择电压,第二选择电压为正电压,可以为5V~10V,具体可以为8V。As shown in FIG3 , the multiple rows of word lines of the storage block may be three rows of word lines, namely, a first word line W0, a second word line W1 and a third word line W2, with the second word line W1 being the selected target word line. Therefore, a second selection voltage may be applied to the second word line W1 in the storage block. The second selection voltage is a positive voltage and may be 5V to 10V, specifically 8V.

接着对目标字线所对应的辅助选择字线施加第二辅助电压。Then, a second auxiliary voltage is applied to the auxiliary selection word line corresponding to the target word line.

其中,选择字线对应也有三行,第一选择字线S0、第二选择字线S1和第三选择字线S2;即在选中的目标字线时,对应有辅助选择字线,则在目标字线为第二字线W1时,对应的辅助选择字线为第二选择字线S1;因此,可以在存储块中第二选择字线S1上施加第二辅助电压。在一些实施例中,第三辅助电压小于第三选择电压,第二辅助电压为正电压,比如0.5V~1.5V,具体可以为1V。Among them, there are also three corresponding lines of selection word lines, the first selection word line S0, the second selection word line S1 and the third selection word line S2; that is, when the target word line is selected, there is a corresponding auxiliary selection word line, and when the target word line is the second word line W1, the corresponding auxiliary selection word line is the second selection word line S1; therefore, the second auxiliary voltage can be applied to the second selection word line S1 in the storage block. In some embodiments, the third auxiliary voltage is less than the third selection voltage, and the second auxiliary voltage is a positive voltage, such as 0.5V to 1.5V, and can be specifically 1V.

对存储块的多列位线中的至少一列位线施加写入电压,以热载流子注入方式向选中的目标存储单元的浮栅注入电子。A write voltage is applied to at least one column of bit lines in a plurality of columns of bit lines of a storage block, and electrons are injected into the floating gate of a selected target storage unit in a hot carrier injection manner.

继续参阅图3,存储块的多列位线可以为三列位线,包括第一位线B0、第二位线B1和第三位线B2;以第二位线作为目标位线,则有,可以在存储块中第二位线B1上施加写入电压,确定由第二字线W1和第二位线B1所选中的第五存储单元A11为目标存储单元,进而对第五存储单元A11以热载流子注入方式向选中的目标存储单元的浮栅注入电子。Continuing to refer to FIG3 , the multiple columns of bit lines of the storage block can be three columns of bit lines, including a first bit line B0, a second bit line B1 and a third bit line B2; taking the second bit line as the target bit line, a write voltage can be applied to the second bit line B1 in the storage block to determine that the fifth storage cell A11 selected by the second word line W1 and the second bit line B1 is the target storage cell, and then electrons are injected into the floating gate of the selected target storage cell by hot carrier injection into the fifth storage cell A11.

其中,写入电压为正电压,可以为3V~4.5V,具体可以为4V,且存储块中所有存储单元的源极区通过公共源极线被施加0V的源极电压,所有存储单元的阱区被施加0V的基底电压。The write voltage is a positive voltage, which may be 3V to 4.5V, specifically 4V, and a source voltage of 0V is applied to the source regions of all memory cells in the memory block through a common source line, and a substrate voltage of 0V is applied to the well regions of all memory cells.

以下,存储单元的结构进行详细说明存储器件操作为写操作。Below, the structure of the memory cell is described in detail when the memory device operation is a write operation.

请参阅图5,图5是本申请中写操作一实施例的结构示意图。Please refer to FIG. 5 , which is a schematic diagram of the structure of an embodiment of a write operation in the present application.

如图5所示,在图2的基础上,在目标存储单元的控制栅上施加第二选择电压,此时第二选择电压为8V,并在选择栅上施加第二辅助电压,此时第二辅助电压为1V,以及在漏极区D上施加写入电压,此时写入电压为4V;而对应源极区S和衬底中的阱区,则施加0V的基底电压;因为控制栅施加了一个大的正电压(+8V),同时漏极区D施加了4V正电压,即漏极区D正偏置到+4V,且选择栅施加了1V的正电压,从而导致电子从源极区流向漏极区,并从正偏压浮栅下面通过,又由于施加在控制栅的大的正电压,则有一些电子被“拉入”浮栅,即以热载流子注入方式向选中的目标存储单元的浮栅注入电子;其中,电子从源极区流向漏极区时,电流则从漏极区流向源极区。As shown in FIG5 , based on FIG2 , a second selection voltage is applied to the control gate of the target memory cell, and the second selection voltage is 8V at this time. A second auxiliary voltage is applied to the selection gate, and the second auxiliary voltage is 1V at this time. A write voltage is applied to the drain region D, and the write voltage is 4V at this time. A substrate voltage of 0V is applied to the corresponding source region S and the well region in the substrate. Because a large positive voltage (+8V) is applied to the control gate, and a 4V positive voltage is applied to the drain region D at the same time, that is, the drain region D is positively biased to +4V, and a positive voltage of 1V is applied to the selection gate, which causes electrons to flow from the source region to the drain region and pass under the positive bias floating gate. Due to the large positive voltage applied to the control gate, some electrons are "pulled into" the floating gate, that is, electrons are injected into the floating gate of the selected target memory cell in a hot carrier injection manner. When electrons flow from the source region to the drain region, the current flows from the drain region to the source region.

本领域技术人员可以理解的是,上述写操作是针对单个存储单元的写操作。Those skilled in the art will appreciate that the above-mentioned write operation is a write operation for a single storage unit.

在又一具体实施例中,响应于存储器件操作为擦除操作,则控制方法包括:In yet another specific embodiment, in response to the memory device operating as an erase operation, the control method includes:

在存储块的字线上施加第三选择电压。A third selection voltage is applied to the word line of the memory block.

其中,如图3所述,存储块的多行字线可以为三行字线,第一字线W0、第二字线W1和第三字线W2,可以理解的是擦除操作通常为整个存储块的擦除操作,因此,可以在存储块中第一字线W0、第二字线W1和第三字线W2上施加第三选择电压,第三选择电压为负电压,比如-6V~-10V,具体可以为-8V。Among them, as shown in Figure 3, the multiple rows of word lines of the storage block can be three rows of word lines, the first word line W0, the second word line W1 and the third word line W2. It can be understood that the erase operation is usually an erase operation of the entire storage block. Therefore, a third selection voltage can be applied to the first word line W0, the second word line W1 and the third word line W2 in the storage block. The third selection voltage is a negative voltage, such as -6V to -10V, and can be specifically -8V.

以及在存储块的选择字线上施加第三辅助电压。And applying a third auxiliary voltage to the selected word line of the memory block.

其中,选择字线对应也有三行,第一选择字线S0、第二选择字线S1和第三选择字线S2;则在对存储块的字线施加第三选择电压时,还需要对存储块的选择字线施加第三辅助电压;即可以在存储块中第一选择字线S0、第二选择字线S1和第三选择字线S2上施加第五辅助电压。其中,第三辅助电压为正电压,比如6~10V,具体可以为8V。Among them, there are also three rows corresponding to the selection word line, the first selection word line S0, the second selection word line S1 and the third selection word line S2; when the third selection voltage is applied to the word line of the storage block, the third auxiliary voltage needs to be applied to the selection word line of the storage block; that is, the fifth auxiliary voltage can be applied to the first selection word line S0, the second selection word line S1 and the third selection word line S2 in the storage block. Among them, the third auxiliary voltage is a positive voltage, such as 6 to 10V, and can be 8V specifically.

在存储块的阱区施加擦除电压,以F-N隧道效应方式擦除存储块中存储单元的浮栅中的电子。An erase voltage is applied to the well region of the memory block to erase the electrons in the floating gate of the memory cell in the memory block by means of the F-N tunnel effect.

其中,将存储块的位线和源极线都浮置。Wherein, both the bit line and the source line of the memory block are floated.

具体地,存储块的多列位线可以为三列位线,包括第一位线B0、第二位线B1和第三位线B2,则将第一位线B0、第二位线B1和第三位线B2都浮置,并将存储块中存储单元的源极区对应的源极线浮置,使得存储块中所有存储单元的源极区浮置;进而对存储块中的阱区上施加擦除电压,擦除电压为正电压,使得存储块中存储单元的阱区电压高于控制栅电压,即擦除电压高于第三选择电压,进而使得存储单元中的电子从浮栅通过栅绝缘层流动到衬底表面。其中,擦除电压为正电压,比如6V~10V,具体可以为8V;又因为在选择栅上施加了正电压的第三辅助电压,以减小选择栅和阱区之间的电势差,避免电子源源不断从选择栅移动到衬底,而导致的降低擦除效率,影响擦除效果。Specifically, the multi-column bit lines of the storage block can be three columns of bit lines, including the first bit line B0, the second bit line B1 and the third bit line B2, then the first bit line B0, the second bit line B1 and the third bit line B2 are all floated, and the source line corresponding to the source region of the storage unit in the storage block is floated, so that the source region of all the storage units in the storage block is floated; then an erase voltage is applied to the well region in the storage block, and the erase voltage is a positive voltage, so that the well region voltage of the storage unit in the storage block is higher than the control gate voltage, that is, the erase voltage is higher than the third selection voltage, so that the electrons in the storage unit flow from the floating gate through the gate insulation layer to the substrate surface. Among them, the erase voltage is a positive voltage, such as 6V to 10V, and can be specifically 8V; and because a third auxiliary voltage of a positive voltage is applied to the selection gate to reduce the potential difference between the selection gate and the well region, it is avoided that electrons continuously move from the selection gate to the substrate, which reduces the erase efficiency and affects the erase effect.

以下,存储单元的结构进行详细说明存储器件操作为擦除操作。Hereinafter, the structure of the memory cell is described in detail and the memory device operation is an erase operation.

请参阅图6,图6是本申请中擦除操作一实施例的结构示意图。Please refer to FIG. 6 , which is a schematic diagram of the structure of an embodiment of an erase operation in the present application.

如图6所示,在图2的基础上,对存储块中所有的存储单元的控制栅施加-8V的第三选择电压,对存储块的阱区施加+8V的擦除电压,以及对存储块中所有的存储单元的选择栅施加+8V的第三辅助电压;使得存储块中存储单元的阱区电压高于控制栅电压,即+8V的擦除电压高于-8V的第三选择电压,进而使得电子从浮栅220通过第一栅绝缘层210流动到衬底表面;即衬底中+8V的正电压,吸引困在浮栅中的电子,同时,控制栅被施加了-8V的负电压,则浮栅排斥捕获的负电荷;且两个电压叠加形成一个电场,使得电子可以穿过浮栅220与衬底之间的第一栅绝缘层210,进而耗尽浮栅中的电子,从而降低对应的阈值电压;而在选择栅施加了+8V的第三辅助电压,以减小选择栅和阱区之间的电势差,避免电子源源不断从选择栅移动到衬底,而导致的降低擦除效率,影响擦除效果。As shown in FIG. 6 , based on FIG. 2 , a third selection voltage of -8V is applied to the control gates of all the memory cells in the memory block, an erase voltage of +8V is applied to the well region of the memory block, and a third auxiliary voltage of +8V is applied to the select gates of all the memory cells in the memory block; so that the well region voltage of the memory cells in the memory block is higher than the control gate voltage, that is, the erase voltage of +8V is higher than the third selection voltage of -8V, thereby causing electrons to flow from the floating gate 220 through the first gate insulating layer 210 to the substrate surface; that is, the positive voltage of +8V in the substrate , attracting electrons trapped in the floating gate. At the same time, a negative voltage of -8V is applied to the control gate, and the floating gate repels the captured negative charges. The two voltages are superimposed to form an electric field, so that electrons can pass through the first gate insulating layer 210 between the floating gate 220 and the substrate, thereby depleting the electrons in the floating gate, thereby reducing the corresponding threshold voltage. A third auxiliary voltage of +8V is applied to the select gate to reduce the potential difference between the select gate and the well region, so as to avoid electrons continuously moving from the select gate to the substrate, which will reduce the erasing efficiency and affect the erasing effect.

在一些实施例中,在第二栅绝缘层的上表面高于第一栅绝缘层的上表面时,即第二栅绝缘层比第一栅绝缘层厚时,使得电子无法从选择栅移动到衬底,降低了对第二栅绝缘层的损伤,则第三辅助电压可以更小,如第三辅助电压还可以是5.5V,或者存储块中存储单元的选择栅还可以是浮置,也基本能实现电子穿过浮栅与衬底之间的栅绝缘层,进而耗尽浮栅中的电子,从而降低对应的阈值电压。In some embodiments, when the upper surface of the second gate insulating layer is higher than the upper surface of the first gate insulating layer, that is, when the second gate insulating layer is thicker than the first gate insulating layer, electrons cannot move from the selection gate to the substrate, thereby reducing damage to the second gate insulating layer. The third auxiliary voltage can be smaller, such as the third auxiliary voltage can also be 5.5V, or the selection gate of the storage unit in the storage block can also be floating, which can basically enable electrons to pass through the gate insulating layer between the floating gate and the substrate, thereby depleting the electrons in the floating gate, thereby reducing the corresponding threshold voltage.

可以理解的是,可以根据第二栅绝缘层的厚度,调整第三辅助电压的值,能实现存储单元的擦除操作即可,即第二栅绝缘层够厚的话,由于电子过不去,第三辅助电压就可以更小或者浮置。It is understandable that the value of the third auxiliary voltage can be adjusted according to the thickness of the second gate insulating layer to achieve the erase operation of the memory cell. That is, if the second gate insulating layer is thick enough, the third auxiliary voltage can be smaller or floating because electrons cannot pass through.

本实施例中,对于在控制栅的一侧形成选择栅,且选择栅的上表面低于控制栅的下表面所对应的存储器件,通过对目标字线的选择,并对目标字线所对应的辅助选择字线施加辅助电压,进而通过对目标位线的选择确定目标存储单元,以对目标存储单元执行存储器件操作,能有效提升存储器件中控制栅和选择栅之间的击穿电压,提升存储器件的性能。In the present embodiment, for a storage device corresponding to a selection gate formed on one side of a control gate and having an upper surface of the selection gate lower than a lower surface of the control gate, by selecting a target word line and applying an auxiliary voltage to an auxiliary selection word line corresponding to the target word line, and then determining a target storage cell by selecting a target bit line, so as to perform a storage device operation on the target storage cell, the breakdown voltage between the control gate and the selection gate in the storage device can be effectively improved, thereby improving the performance of the storage device.

以上所述仅为本发明的实施方式,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。The above description is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims (12)

1. A control method of a memory device, wherein the memory device comprises at least one memory block, a word line of the memory block comprises a plurality of memory cells, each memory cell comprises a source region, a drain region, a channel region, a floating gate and a control gate which are arranged above the channel region and are close to the drain region, and a selection gate which is arranged above the channel region and is close to the source region, wherein the control gate corresponds to the word line, and the selection gate corresponds to the selection word line; the control method comprises the following steps:
Performing row selection on at least one row of word lines in a plurality of rows of word lines of a memory block in the memory device, wherein the selected word line is used as a target word line;
taking a selected word line corresponding to the target word line as an auxiliary selected word line, and applying auxiliary voltage to the auxiliary selected word line;
Performing column selection on at least one column of bit lines in a plurality of columns of bit lines of a memory block in the memory device, wherein the selected bit line is used as a target bit line;
And determining a target memory cell based on the selected target word line and the target bit line, and performing a memory device operation on the target memory cell or the memory block.
2. The control method according to claim 1, wherein,
In response to the memory device operating as a read operation, the control method includes:
Applying a first select voltage on the target word line and a first auxiliary voltage on the auxiliary select word line;
a read voltage is applied to the target bit line to determine whether the selected target memory cell has current flowing therethrough to determine whether the target memory cell has electrons stored therein.
3. The control method according to claim 2, wherein,
The first selection voltage is 2V-3V, the first auxiliary voltage is 2V-3V, and the reading voltage is 0.5V-1.2V.
4. The control method according to claim 1, wherein,
In response to the memory device operating as a write operation, the control method includes:
Applying a second select voltage on the target word line and a second auxiliary voltage on the auxiliary select word line;
And applying a writing voltage on the target bit line, and injecting electrons into the floating gate of the selected target memory cell.
5. The control method according to claim 4, wherein,
The second selection voltage is 5V-10V, the second auxiliary voltage is 0.5V-1.5V, and the writing voltage is 3V-4.5V.
6. The control method according to claim 2 or 4, characterized in that,
The memory block of the memory device comprises a substrate, wherein the substrate further comprises a well region, and the source region, the drain region and the channel region of a memory unit in the memory block are arranged in the well region;
And applying a substrate voltage to the well region in response to the memory device operating as a read operation or a write operation, wherein the substrate voltage is 0V.
7. The control method according to claim 1, wherein,
The memory block of the memory device comprises a substrate, a well region is further included in the substrate, and the source region, the drain region and the channel region of a memory cell in the memory block are arranged in the well region;
an erase voltage is applied to the well region in response to the memory device operating as an erase operation.
8. The control method according to claim 7, wherein,
In response to the memory device operating as an erase operation, the control method includes:
Applying a third select voltage on a word line of the memory block and a third auxiliary voltage on a selected word line of the memory block;
applying an erasing voltage to the well region, and erasing electrons in the floating gates of the memory cells in the memory block; wherein the bit lines and source lines of the memory block are floated.
9. The control method according to claim 8, wherein,
The erase voltage is greater than or equal to the third auxiliary voltage, or a selected word line of the memory block is floating.
10. The control method according to claim 9, wherein,
The third selection voltage is-6V to-10V, the erasing voltage is 6V to 10V, and the third auxiliary voltage is 0V to 10V.
11. The control method according to claim 1, wherein,
The upper surface of the select gate is lower than the lower surface of the control gate.
12. The control method according to claim 1, wherein,
The control gate is provided with a first gate insulating layer on a substrate corresponding to the control gate, the selection gate is provided with a second gate insulating layer on a substrate corresponding to the selection gate, and the thickness of the second gate insulating layer is larger than that of the first gate insulating layer in the vertical direction.
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