CN118522324A - Control method of memory device - Google Patents

Abstract

The present invention discloses a control method for a memory device, comprising: performing row selection on at least one row of word lines among multiple rows of word lines of a memory block in the memory device, taking the selected word line as a target word line; taking a selection word line corresponding to the target word line as an auxiliary selection word line, and applying an auxiliary voltage to the auxiliary selection word line; performing column selection on at least one column of bit lines among multiple columns of bit lines of the memory block, taking the selected bit line as a target bit line; determining a target memory cell based on the selected target word line and the target bit line, and performing a memory device operation; that is, in the present application, for a memory device in which a selection gate is formed on one side of a control gate, the target word line is selected, and an auxiliary voltage is applied to the auxiliary selection word line corresponding to the target word line, and then the target memory cell is determined by selecting the target bit line, so that the memory device operation is performed on the target memory cell or the memory block, which can effectively improve the breakdown voltage between the control gate and the selection gate, and improve the performance of the memory device.

Description

A control method for a storage device

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a control method for a storage device.

Background Art

In the application process of integrated circuits, the performance of various devices will be affected by the structure formed by each layer of materials, especially transistor devices. The different gate structures affect the performance of transistor devices.

During actual operation, the researchers of this application discovered that current semiconductor device control schemes, especially control methods for memory devices, usually correspond to memory devices that use an ETOX (Electron Tunneling Oxide device) process to form an ETOX floating gate structure. However, due to the structure of the device, there are still certain performance limitations that affect the performance of the memory device.

Summary of the invention

The main technical problem solved by the present invention is: to provide a control method for a storage device, for a storage device corresponding to a selection gate formed on one side of a control gate, by selecting a target word line and applying an auxiliary voltage to an auxiliary selection word line corresponding to the target word line, and then determining a target storage cell by selecting a target bit line, so as to perform a storage device operation on the target storage cell or storage block, which can effectively improve the breakdown voltage between the control gate and the selection gate in the storage device and improve the performance of the storage device.

In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a control method of a memory device, comprising: performing row selection on at least one row of word lines in a plurality of rows of word lines of a memory block in the memory device, and taking the selected word line as a target word line; wherein the word line of the memory block includes a plurality of memory cells, each of the memory cells having a source region and a drain region, a channel region, a floating gate and a control gate arranged above the channel region and close to the drain region, and a selection gate arranged above the channel region and close to the source region, the control gate corresponding to the word line, and the selection gate corresponding to the selection word line; taking the selection word line corresponding to the target word line as an auxiliary selection word line, and applying an auxiliary voltage to the auxiliary selection word line; performing column selection on at least one column of bit lines in a plurality of columns of bit lines of a memory block in the memory device, and taking the selected bit line as a target bit line; determining a target memory cell based on the selected target word line and the target bit line, and performing a memory device operation on the target memory cell or the memory block.

In one embodiment of the present application, in response to the memory device operating as a read operation of a single memory cell, the control method includes: applying a first selection voltage on the target word line, and applying a first auxiliary voltage on the auxiliary selection word line; applying a read voltage on the target bit line to determine whether current flows through the selected target memory cell to determine whether the target memory cell stores electrons.

In an embodiment of the present application, the first selection voltage is 2V to 3V, the first auxiliary voltage is 2V to 3V, the read voltage is 0.5V to 1.2V, and the base voltage is 0V.

In one embodiment of the present application, in response to the memory device operating as a write operation of a single memory cell, the control method includes: applying a second selection voltage on the target word line, and applying a second auxiliary voltage on the auxiliary selection word line; applying a write voltage on the target bit line to inject electrons into the floating gate of the selected target memory cell.

In an embodiment of the present application, the second selection voltage is 5V to 10V, the second auxiliary voltage is 0.5V to 1.5V, and the write voltage is 3V to 4.5V.

In one embodiment of the present application, the storage block of the storage device includes a substrate, the substrate also includes a well region, the source region, the drain region and the channel region of the storage unit in the storage block are arranged in the well region; in response to the storage device operating as a read operation or a write operation, a substrate voltage is applied to the well region, wherein the substrate voltage is 0V.

In one embodiment of the present application, a storage block of the storage device includes a substrate, the substrate also includes a well region, the source region, the drain region and the channel region of the storage cell in the storage block are arranged in the well region, wherein the upper surface of the selection gate is lower than the lower surface of the control gate; in response to the storage device operating as an erase operation, an erase voltage is applied to the well region.

In one embodiment of the present application, in response to the memory device operating as an erase operation, the control method includes: applying a third selection voltage to the word line of the memory block, and applying a third auxiliary voltage to the selection word line of the memory block; applying an erase voltage to the well region to erase electrons in the floating gate of the memory cell in the memory block; wherein the bit line and the source line of the memory block are floated.

In an embodiment of the present application, the erase voltage is greater than or equal to the third auxiliary voltage, or the selected word line of the memory block is floating.

In an embodiment of the present application, the third selection voltage is -6V to -10V, the erase voltage is 6V to 10V, and the third auxiliary voltage is 0V to 10V.

In an embodiment of the present application, in the vertical direction, the thickness of the select gate is smaller than the thickness of the control gate.

In one embodiment of the present application, a first gate insulating layer is provided on the substrate corresponding to the control gate, and a second gate insulating layer is provided on the substrate corresponding to the select gate. In the vertical direction, the thickness of the second gate insulating layer is greater than the thickness of the first gate insulating layer.

Different from the prior art, the control method of the memory device provided by the present application comprises: performing row selection on at least one row of word lines among multiple rows of word lines of a memory block in the memory device, and taking the selected word line as the target word line; wherein the word line of the memory block comprises multiple memory cells, each memory cell comprises a source region and a drain region, a channel region, a floating gate and a control gate arranged above the channel region and close to the drain region, and a selection gate arranged above the channel region and close to the source region, the control gate corresponds to the word line, and the selection gate corresponds to the selection word line; taking the selection word line corresponding to the target word line as an auxiliary selection word line, and applying an auxiliary voltage to the auxiliary selection word line; performing column selection on at least one column of bit lines among multiple columns of bit lines of a memory block in the memory device, and taking the selected bit line as the target bit line; based on the selected The target word line and the target bit line determine the target memory cell, and perform a memory device operation on the target memory cell or the memory block; that is, the present application forms a selection gate on one side of the control gate, and sets the upper surface of the selection gate to be lower than the lower surface of the control gate corresponding to the memory device, reduces the coupling area between the control gate and the selection gate, so as to reduce the equivalent gate capacitance, improve the device reliability, and at the same time improve the breakdown voltage between the control gate and the selection gate, so that the corresponding pressure adjustment range is increased, and the target word line is selected, and an auxiliary voltage is applied to the auxiliary selection word line corresponding to the target word line, and then the target memory cell is determined by selecting the target bit line, so as to perform a memory device operation on the target memory cell or the memory block, thereby improving the performance of the memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

FIG1 is a flow chart of an embodiment of a method for controlling a storage device in the present application;

FIG2 is a schematic structural diagram of an embodiment of a storage unit in the present application;

FIG3 is a circuit diagram of a storage block in a storage device in the present application;

FIG4 is a schematic diagram of a structure of an embodiment of a read operation in the present application;

FIG5 is a schematic diagram of a structure of an embodiment of a write operation in the present application;

FIG. 6 is a schematic structural diagram of an embodiment of an erase operation in the present application.

In the accompanying drawings, a memory cell 10, a substrate 100, a gate stack structure 200, a first gate insulating layer 210, a floating gate 220, a first inter-gate dielectric layer 230, a control gate 240, a select gate 300, a second inter-gate dielectric layer 310, a second gate insulating layer 320, an isolation sidewall 400, a first isolation sidewall 410, a second isolation sidewall 420, a third isolation sidewall 430, a source region S, a drain region D, a first word line W0, a second word line W1, a third word line W2, a first bit line B0, a second bit line B1, a third bit line B2, a first selection word line S0, a second selection word line S1, a third selection word line S2, a first memory cell A00, a second memory cell A10, a third memory cell A20, a fourth memory cell A01, a fifth memory cell A11, a sixth memory cell A21, a seventh memory cell A02, an eighth memory cell A12, and a ninth memory cell A22.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

In current semiconductor device control methods, especially the control of memory devices, a memory device with an ETOX floating gate structure formed by an ETOX (Electron Tunneling Oxide device) process is usually used. However, due to the structure of the device, there are still certain performance limitations, which in turn affects the storage performance of the memory device.

Therefore, a control method for a storage device is provided, which utilizes a storage device corresponding to a selection gate formed on one side of a control gate, wherein the upper surface of the selection gate is lower than the lower surface of the control gate. By selecting a target word line and applying an auxiliary voltage to an auxiliary selection word line corresponding to the target word line, a target storage cell is determined by selecting a target bit line, so that a storage device operation is performed on the target storage cell or storage block, which can effectively improve the breakdown voltage between the control gate and the selection gate, thereby improving the performance of the storage device.

Please refer to FIG. 1 , which is a flow chart of an embodiment of a method for controlling a storage device in the present application.

As shown in FIG. 1 , the control method of the storage device includes:

S10, performing row selection on at least one row of word lines in a plurality of rows of word lines in a storage block in a storage device, and taking the selected word line as a target word line;

The memory device includes at least one memory block, the memory block includes multiple rows of word lines and multiple columns of bit lines, the word lines of the memory block include multiple memory cells, each memory cell has a source region and a drain region, a channel region, a floating gate and a control gate arranged above the channel region and close to the drain region, and a selection gate arranged above the channel region and close to the source region, the control gate corresponds to the word line, and the selection gate corresponds to the selection word line. In some embodiments, the upper surface of the selection gate is lower than the lower surface of the control gate.

Specifically, the memory device includes a memory block, which may include multiple rows of word lines and multiple columns of bit lines. The word lines in each row correspond to the control gates of each memory cell in the word lines in that row. Therefore, when row selection is performed on at least one row of word lines in the multiple rows of word lines in the memory block, for example, a selection voltage is applied to at least one row of word lines, the selected word line can be used as a target word line, and the memory cells on the target word line are all selected.

S20 , using the selection word line corresponding to the target word line as an auxiliary selection word line, and applying an auxiliary voltage to the auxiliary selection word line.

Among them, because there is a selection gate set on one side of the control gate in the memory cell, each word line is configured with a corresponding selection word line, that is, each row of word lines has a corresponding row of selection word lines, and the selection word line also corresponds to the selection gate of each memory cell in the row of word lines.

Specifically, after row selection is performed and the selected word line is used as the target word line, the selection word line corresponding to the target word line is also selected and used as an auxiliary selection word line, and an auxiliary voltage is applied to the auxiliary selection word line, that is, an auxiliary voltage is applied to the selection gates of a selected row of memory cells, so as to perform the corresponding storage device operation.

S30 , performing column selection on at least one column of bit lines in a plurality of columns of bit lines in a storage block in a storage device, and taking the selected bit line as a target bit line.

Each column of bit lines is correspondingly connected to the drain of each storage unit in the column of bit lines.

Specifically, when column selection is performed on at least one column of multiple columns of bit lines in a storage block, the selected bit line is used as the target bit line. For example, a voltage is applied to at least one column of bit lines, and the selected bit line can be used as the target bit line, so that all storage cells on the target bit line are selected.

S40 , determining a target memory cell based on the selected target word line and target bit line, and performing a memory device operation on the target memory cell or memory block.

Specifically, each row word line has a corresponding connection point with each column bit line, and the storage cell corresponding to the connection point is the target storage cell, that is, the target word line is connected to the control gate of the target storage cell, the target bit line is connected to the source region of the target storage cell, and the auxiliary selection word line is connected to the selection gate of the target storage cell; therefore, by applying corresponding voltages to the control gate, the source region and the selection gate, respectively, the storage device operation, such as read operation, write operation, erase operation, etc., can be performed on the target storage cell or storage block.

In the present embodiment, for a storage device corresponding to a selection gate formed on one side of a control gate and having an upper surface of the selection gate lower than a lower surface of the control gate, a target word line is selected for the storage device, and an auxiliary voltage is applied to an auxiliary selection word line corresponding to the target word line, and then a target storage cell is determined by selecting a target bit line, so that a storage device operation is performed on the target storage cell or storage block, thereby effectively improving the breakdown voltage between the control gate and the selection gate and improving the performance of the storage device.

The control method will be described below in conjunction with the specific structure of the storage unit.

Please refer to FIG. 2 , which is a schematic diagram of the structure of a storage unit according to an embodiment of the present application.

As shown in FIG. 2 , the memory cell 10 includes a substrate 100, a gate stack structure 200 and a selection gate 300; the gate stack structure 200 is disposed on the substrate 100, the gate stack structure 200 includes at least a floating gate and a control gate, and the selection gate 300 is disposed on one side of the gate stack structure 200. In some embodiments, the upper surface of the selection gate is lower than the lower surface of the control gate to reduce the coupling area between the selection gate and the control gate, while increasing the breakdown voltage between the control gate and the selection gate.

Among them, the gate stack structure 200 includes a first gate insulation layer 210, a floating gate 220, a first inter-gate dielectric layer 230 and a control gate 240; the selection gate 300 is arranged on the substrate 100 on one side of the gate stack structure 200; a second inter-gate dielectric layer 310 is arranged between the gate stack structure 200 and the selection gate 300, and a second gate insulation layer 320 is also arranged between the selection gate 300 and the substrate 100. In some embodiments, the upper surface of the second gate insulation layer 320 is higher than the upper surface of the first gate insulation layer, that is, in the vertical direction, the thickness of the second gate insulation layer is greater than the thickness of the first gate insulation layer, which can prevent electrons in the selection gate from entering the substrate, that is, the selection gate 300 will be connected to the power supply during erasing. If the second gate insulation layer 320 is too thin, electrons will continuously flow into the substrate, which is not conducive to erasing. Of course, this does not mean that the upper surface of the second gate insulation layer 320 is higher than the upper surface of the first gate insulation layer (the thickness of the second gate insulation layer 320 is greater than the upper surface of the first gate insulation layer) is a required feature of this case. Similar technical effects can be achieved by adjusting the control method or the process.

In addition, an isolation sidewall 400 is provided for the gate stack structure 200 and the selection gate 300 to cover the exposed sidewalls of the gate stack structure 200 and the control gate 240, wherein the isolation sidewall includes a first isolation sidewall 410, a second isolation sidewall 420 and a third isolation sidewall 430, wherein the first isolation sidewall 410 is provided on the side of the gate stack structure 200 away from the selection gate to cover the exposed sidewall of the gate stack structure 200; the second isolation sidewall 420 is provided on the side of the selection gate away from the gate stack structure to cover the exposed sidewall of the selection gate away from the gate stack structure; the third isolation sidewall 430 is provided on the selection gate 300 on the side of the gate stack structure 200 close to the selection gate to cover the exposed sidewall of the gate stack structure on the side of the selection gate. In some embodiments, the third isolation sidewall 430 may be omitted.

Furthermore, the memory cell further includes a source region S and a drain region D, wherein the source region S is disposed in the substrate 100 on a side of the selection gate 300 away from the gate stack structure 200 , and the drain region D is disposed in the substrate on a side of the gate stack structure 200 away from the selection gate 300 .

In some embodiments, the positions of the source region S and the drain region D may be interchanged according to different designs.

In one embodiment, a memory block of a memory device includes a substrate, and a source region, a drain region, and a channel region of a memory cell are disposed in the substrate.

The substrate also includes a well region, and the source region, the drain region and the channel region of the storage unit are arranged in the well region so as to apply an erase voltage or a substrate voltage to the well region.

The connection of multiple memory cells of a memory block in a memory device is illustrated by a circuit diagram.

Please refer to FIG. 3 , which is a circuit diagram of a storage block in a storage device in the present application.

As shown in FIG3 , a storage block of a storage device includes a plurality of rows of word lines, a plurality of rows of selection word lines and a plurality of columns of bit lines. A specific description is given by taking three rows of word lines and three columns of bit lines as an example. The three rows of word lines include a first word line W0, a second word line W1 and a third word line W2; the three columns of bit lines include a first bit line B0, a second bit line B1 and a third bit line B2; the corresponding three rows of selection word lines include a first selection word line S0, a second selection word line S1 and a third selection word line S2; then, a storage cell includes a control gate 240, a floating gate 220, a selection gate 300, a source region S and a drain region D, each row of word lines is connected to the control gate 240 of the storage cell in the row, each row of selection word lines is connected to the selection gate 300 of the storage cell in the row, each column of bit lines is connected to the drain region D of the storage cell in the column, and the source region S of each storage cell is grounded.

For example, the first word line W0 connects the control gates of the first storage cell A00, the second storage cell A10 and the third storage cell A20 in the same row, and the first selection word line S0 connects the selection gates of the first storage cell A00, the second storage cell A10 and the third storage cell A20; the second word line W1 connects the control gates of the fourth storage cell A01, the fifth storage cell A11 and the sixth storage cell A21 in the same row, and the second selection word line S1 connects the selection gates of the fourth storage cell A01, the fifth storage cell A11 and the sixth storage cell A21; the third word line W2 connects the seventh storage cell A02, the eighth storage cell A11 and the sixth storage cell A21 in the same row. The control gates of the storage cells A12 and the ninth storage cell A22, the third selection word line S2 is connected to the selection gates of the seventh storage cell A02, the eighth storage cell A12 and the ninth storage cell A22; the first bit line B0 is connected to the drain regions of the first storage cell A00, the fourth storage cell A01 and the seventh storage cell A02 in the same column, the second bit line B1 is connected to the drain regions of the second storage cell A10, the fifth storage cell A11 and the eighth storage cell A12 in the same column, and the third bit line B2 is connected to the drain regions of the third storage cell A20, the sixth storage cell A21 and the ninth storage cell A22 in the same column.

A target memory cell is determined based on the selected target word line and target bit line, and a memory device operation is performed on the target memory cell or memory block.

The storage device operation includes a read operation, a write operation, and/or an erase operation.

In a specific implementation, in response to the memory device operating as a read operation of a single memory cell, the control method of the memory device includes:

A first selection voltage is applied to at least one row of word lines among a plurality of rows of word lines of a memory block in a memory device.

As shown in FIG3 , the multiple rows of word lines of the storage block may be three rows of word lines, namely, a first word line W0, a second word line W1 and a third word line W2, with the second word line W1 being the selected target word line. Therefore, a first selection voltage may be applied to the second word line W1 in the storage block. The first selection voltage may be a positive voltage, such as 2V to 3V, and may be specifically 2.5V.

Then, a first auxiliary voltage is applied to the auxiliary selection word line corresponding to the target word line.

There are also three corresponding lines for the selection word line, the first selection word line S0, the second selection word line S1 and the third selection word line S2; that is, when the target word line is selected, there is a corresponding auxiliary selection word line, and when the target word line is the second word line W1, the corresponding auxiliary selection word line is the second selection word line S1; therefore, the first auxiliary voltage can be applied to the second selection word line S1 in the storage block. The first auxiliary voltage can be the same as the first selection voltage, that is, the first auxiliary voltage can also be a positive voltage, such as 2V to 3V, specifically 2.5V.

A read voltage is applied to at least one bit line in the plurality of bit lines of the storage block to determine whether current flows through the selected target storage cell, that is, the current of the target storage cell is read to determine whether the target storage cell stores electrons.

Continuing to refer to FIG. 3 , the multiple columns of bit lines of the storage block may be three columns of bit lines, including a first bit line B0, a second bit line B1 and a third bit line B2; taking the second bit line as the target bit line, a read voltage may be applied to the second bit line B1 in the storage block to determine that the fifth storage cell A11 selected by the second word line W1 and the second bit line B1 is the target storage cell, and then determine whether current flows through the fifth storage cell A11 to determine whether electrons are stored in the fifth storage cell A11; in some embodiments, the read voltage is a positive voltage, such as 0.5V to 1.2V, specifically 0.8V, and a source voltage of 0V is applied to the source regions of all storage cells in the storage block through a common source line, and a substrate voltage of 0V is applied to the well regions of all storage cells.

Among them, if electrons are stored in the gate stack structure of the memory cell, the threshold voltage of the memory cell rises, and the first selection voltage of 2.5V received on the control gate of the memory cell is not enough to open the channel region for conduction, then no current may be generated between the source region and the drain region of the memory cell, and the read data is "0". If no electrons are stored in the memory cell, the first selection voltage of 2.5V received on the control gate of the memory cell is enough to open the channel region between the source region and the drain region for conduction, then current is generated between the source region and the drain region of the memory cell, and the read data is "1".

Below, the structure of the memory cell is described in detail and the memory device operation is a read operation.

Please refer to FIG. 4 , which is a schematic diagram of the structure of an embodiment of a read operation in the present application.

Referring to FIG. 4 , based on FIG. 2 , for the selected target memory cell, a first selection voltage is applied to the control gate, and the first selection voltage may be 2.5V at this time. A first auxiliary voltage is applied to the selection gate, and the first auxiliary voltage is 2.5V at this time. A read voltage is applied to the drain region D, and the read voltage is 0.8V at this time. A substrate voltage of 0V is applied to the corresponding source region and the well region in the substrate. If electrons are stored in the floating gate, the channel region is not conductive, and no current is generated between the source region S and the drain region D, and the read data is "0". If electrons are not stored in the floating gate, the channel region is conductive, and a current is generated between the source region S and the drain region D, and electrons flow from the source region to the drain region, and current is detected to pass through, and the read data is "1".

In another specific embodiment, in response to the memory device operating as a write operation of a single memory cell, the control method of the memory device includes:

A second selection voltage is applied to at least one row of word lines among a plurality of rows of word lines of a memory block in the memory device.

As shown in FIG3 , the multiple rows of word lines of the storage block may be three rows of word lines, namely, a first word line W0, a second word line W1 and a third word line W2, with the second word line W1 being the selected target word line. Therefore, a second selection voltage may be applied to the second word line W1 in the storage block. The second selection voltage is a positive voltage and may be 5V to 10V, specifically 8V.

Then, a second auxiliary voltage is applied to the auxiliary selection word line corresponding to the target word line.

Among them, there are also three corresponding lines of selection word lines, the first selection word line S0, the second selection word line S1 and the third selection word line S2; that is, when the target word line is selected, there is a corresponding auxiliary selection word line, and when the target word line is the second word line W1, the corresponding auxiliary selection word line is the second selection word line S1; therefore, the second auxiliary voltage can be applied to the second selection word line S1 in the storage block. In some embodiments, the third auxiliary voltage is less than the third selection voltage, and the second auxiliary voltage is a positive voltage, such as 0.5V to 1.5V, and can be specifically 1V.

A write voltage is applied to at least one column of bit lines in a plurality of columns of bit lines of a storage block, and electrons are injected into the floating gate of a selected target storage unit in a hot carrier injection manner.

Continuing to refer to FIG3 , the multiple columns of bit lines of the storage block can be three columns of bit lines, including a first bit line B0, a second bit line B1 and a third bit line B2; taking the second bit line as the target bit line, a write voltage can be applied to the second bit line B1 in the storage block to determine that the fifth storage cell A11 selected by the second word line W1 and the second bit line B1 is the target storage cell, and then electrons are injected into the floating gate of the selected target storage cell by hot carrier injection into the fifth storage cell A11.

The write voltage is a positive voltage, which may be 3V to 4.5V, specifically 4V, and a source voltage of 0V is applied to the source regions of all memory cells in the memory block through a common source line, and a substrate voltage of 0V is applied to the well regions of all memory cells.

Below, the structure of the memory cell is described in detail when the memory device operation is a write operation.

Please refer to FIG. 5 , which is a schematic diagram of the structure of an embodiment of a write operation in the present application.

As shown in FIG5 , based on FIG2 , a second selection voltage is applied to the control gate of the target memory cell, and the second selection voltage is 8V at this time. A second auxiliary voltage is applied to the selection gate, and the second auxiliary voltage is 1V at this time. A write voltage is applied to the drain region D, and the write voltage is 4V at this time. A substrate voltage of 0V is applied to the corresponding source region S and the well region in the substrate. Because a large positive voltage (+8V) is applied to the control gate, and a 4V positive voltage is applied to the drain region D at the same time, that is, the drain region D is positively biased to +4V, and a positive voltage of 1V is applied to the selection gate, which causes electrons to flow from the source region to the drain region and pass under the positive bias floating gate. Due to the large positive voltage applied to the control gate, some electrons are "pulled into" the floating gate, that is, electrons are injected into the floating gate of the selected target memory cell in a hot carrier injection manner. When electrons flow from the source region to the drain region, the current flows from the drain region to the source region.

Those skilled in the art will appreciate that the above-mentioned write operation is a write operation for a single storage unit.

In yet another specific embodiment, in response to the memory device operating as an erase operation, the control method includes:

A third selection voltage is applied to the word line of the memory block.

Among them, as shown in Figure 3, the multiple rows of word lines of the storage block can be three rows of word lines, the first word line W0, the second word line W1 and the third word line W2. It can be understood that the erase operation is usually an erase operation of the entire storage block. Therefore, a third selection voltage can be applied to the first word line W0, the second word line W1 and the third word line W2 in the storage block. The third selection voltage is a negative voltage, such as -6V to -10V, and can be specifically -8V.

And applying a third auxiliary voltage to the selected word line of the memory block.

Among them, there are also three rows corresponding to the selection word line, the first selection word line S0, the second selection word line S1 and the third selection word line S2; when the third selection voltage is applied to the word line of the storage block, the third auxiliary voltage needs to be applied to the selection word line of the storage block; that is, the fifth auxiliary voltage can be applied to the first selection word line S0, the second selection word line S1 and the third selection word line S2 in the storage block. Among them, the third auxiliary voltage is a positive voltage, such as 6 to 10V, and can be 8V specifically.

An erase voltage is applied to the well region of the memory block to erase the electrons in the floating gate of the memory cell in the memory block by means of the F-N tunnel effect.

Wherein, both the bit line and the source line of the memory block are floated.

Specifically, the multi-column bit lines of the storage block can be three columns of bit lines, including the first bit line B0, the second bit line B1 and the third bit line B2, then the first bit line B0, the second bit line B1 and the third bit line B2 are all floated, and the source line corresponding to the source region of the storage unit in the storage block is floated, so that the source region of all the storage units in the storage block is floated; then an erase voltage is applied to the well region in the storage block, and the erase voltage is a positive voltage, so that the well region voltage of the storage unit in the storage block is higher than the control gate voltage, that is, the erase voltage is higher than the third selection voltage, so that the electrons in the storage unit flow from the floating gate through the gate insulation layer to the substrate surface. Among them, the erase voltage is a positive voltage, such as 6V to 10V, and can be specifically 8V; and because a third auxiliary voltage of a positive voltage is applied to the selection gate to reduce the potential difference between the selection gate and the well region, it is avoided that electrons continuously move from the selection gate to the substrate, which reduces the erase efficiency and affects the erase effect.

Hereinafter, the structure of the memory cell is described in detail and the memory device operation is an erase operation.

Please refer to FIG. 6 , which is a schematic diagram of the structure of an embodiment of an erase operation in the present application.

As shown in FIG. 6 , based on FIG. 2 , a third selection voltage of -8V is applied to the control gates of all the memory cells in the memory block, an erase voltage of +8V is applied to the well region of the memory block, and a third auxiliary voltage of +8V is applied to the select gates of all the memory cells in the memory block; so that the well region voltage of the memory cells in the memory block is higher than the control gate voltage, that is, the erase voltage of +8V is higher than the third selection voltage of -8V, thereby causing electrons to flow from the floating gate 220 through the first gate insulating layer 210 to the substrate surface; that is, the positive voltage of +8V in the substrate , attracting electrons trapped in the floating gate. At the same time, a negative voltage of -8V is applied to the control gate, and the floating gate repels the captured negative charges. The two voltages are superimposed to form an electric field, so that electrons can pass through the first gate insulating layer 210 between the floating gate 220 and the substrate, thereby depleting the electrons in the floating gate, thereby reducing the corresponding threshold voltage. A third auxiliary voltage of +8V is applied to the select gate to reduce the potential difference between the select gate and the well region, so as to avoid electrons continuously moving from the select gate to the substrate, which will reduce the erasing efficiency and affect the erasing effect.

In some embodiments, when the upper surface of the second gate insulating layer is higher than the upper surface of the first gate insulating layer, that is, when the second gate insulating layer is thicker than the first gate insulating layer, electrons cannot move from the selection gate to the substrate, thereby reducing damage to the second gate insulating layer. The third auxiliary voltage can be smaller, such as the third auxiliary voltage can also be 5.5V, or the selection gate of the storage unit in the storage block can also be floating, which can basically enable electrons to pass through the gate insulating layer between the floating gate and the substrate, thereby depleting the electrons in the floating gate, thereby reducing the corresponding threshold voltage.

It is understandable that the value of the third auxiliary voltage can be adjusted according to the thickness of the second gate insulating layer to achieve the erase operation of the memory cell. That is, if the second gate insulating layer is thick enough, the third auxiliary voltage can be smaller or floating because electrons cannot pass through.

In the present embodiment, for a storage device corresponding to a selection gate formed on one side of a control gate and having an upper surface of the selection gate lower than a lower surface of the control gate, by selecting a target word line and applying an auxiliary voltage to an auxiliary selection word line corresponding to the target word line, and then determining a target storage cell by selecting a target bit line, so as to perform a storage device operation on the target storage cell, the breakdown voltage between the control gate and the selection gate in the storage device can be effectively improved, thereby improving the performance of the storage device.

The above description is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims (12)

1. A control method of a memory device, wherein the memory device comprises at least one memory block, a word line of the memory block comprises a plurality of memory cells, each memory cell comprises a source region, a drain region, a channel region, a floating gate and a control gate which are arranged above the channel region and are close to the drain region, and a selection gate which is arranged above the channel region and is close to the source region, wherein the control gate corresponds to the word line, and the selection gate corresponds to the selection word line; the control method comprises the following steps:

Performing row selection on at least one row of word lines in a plurality of rows of word lines of a memory block in the memory device, wherein the selected word line is used as a target word line;

taking a selected word line corresponding to the target word line as an auxiliary selected word line, and applying auxiliary voltage to the auxiliary selected word line;

Performing column selection on at least one column of bit lines in a plurality of columns of bit lines of a memory block in the memory device, wherein the selected bit line is used as a target bit line;

And determining a target memory cell based on the selected target word line and the target bit line, and performing a memory device operation on the target memory cell or the memory block.

2. The control method according to claim 1, wherein,

In response to the memory device operating as a read operation, the control method includes:

Applying a first select voltage on the target word line and a first auxiliary voltage on the auxiliary select word line;

a read voltage is applied to the target bit line to determine whether the selected target memory cell has current flowing therethrough to determine whether the target memory cell has electrons stored therein.

3. The control method according to claim 2, wherein,

The first selection voltage is 2V-3V, the first auxiliary voltage is 2V-3V, and the reading voltage is 0.5V-1.2V.

4. The control method according to claim 1, wherein,

In response to the memory device operating as a write operation, the control method includes:

Applying a second select voltage on the target word line and a second auxiliary voltage on the auxiliary select word line;

And applying a writing voltage on the target bit line, and injecting electrons into the floating gate of the selected target memory cell.

5. The control method according to claim 4, wherein,

The second selection voltage is 5V-10V, the second auxiliary voltage is 0.5V-1.5V, and the writing voltage is 3V-4.5V.

6. The control method according to claim 2 or 4, characterized in that,

The memory block of the memory device comprises a substrate, wherein the substrate further comprises a well region, and the source region, the drain region and the channel region of a memory unit in the memory block are arranged in the well region;

And applying a substrate voltage to the well region in response to the memory device operating as a read operation or a write operation, wherein the substrate voltage is 0V.

7. The control method according to claim 1, wherein,

The memory block of the memory device comprises a substrate, a well region is further included in the substrate, and the source region, the drain region and the channel region of a memory cell in the memory block are arranged in the well region;

an erase voltage is applied to the well region in response to the memory device operating as an erase operation.

8. The control method according to claim 7, wherein,

In response to the memory device operating as an erase operation, the control method includes:

Applying a third select voltage on a word line of the memory block and a third auxiliary voltage on a selected word line of the memory block;

applying an erasing voltage to the well region, and erasing electrons in the floating gates of the memory cells in the memory block; wherein the bit lines and source lines of the memory block are floated.

9. The control method according to claim 8, wherein,

The erase voltage is greater than or equal to the third auxiliary voltage, or a selected word line of the memory block is floating.

10. The control method according to claim 9, wherein,

The third selection voltage is-6V to-10V, the erasing voltage is 6V to 10V, and the third auxiliary voltage is 0V to 10V.

11. The control method according to claim 1, wherein,

The upper surface of the select gate is lower than the lower surface of the control gate.

12. The control method according to claim 1, wherein,

The control gate is provided with a first gate insulating layer on a substrate corresponding to the control gate, the selection gate is provided with a second gate insulating layer on a substrate corresponding to the selection gate, and the thickness of the second gate insulating layer is larger than that of the first gate insulating layer in the vertical direction.