CN118522324A - Control method of memory device - Google Patents
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Abstract
The application discloses a control method of a memory device, which comprises the following steps: performing row selection on at least one of a plurality of rows of word lines of a memory block in a memory device, with the selected word line as a target word line; using a selected word line corresponding to the target word line as an auxiliary selected word line, and applying auxiliary voltage to the auxiliary selected word line; performing column selection on at least one column of bit lines in a plurality of columns of bit lines of the memory block, with the selected bit line as a target bit line; determining a target memory cell based on the selected target word line and target bit line, and performing a memory device operation; in the application, for the memory device with the selection gate formed on one side of the control gate, the auxiliary voltage is applied to the auxiliary selection word line corresponding to the target word line through the selection of the target word line, and then the target memory cell is determined through the selection of the target bit line, so that the memory device operation is carried out on the target memory cell or the memory block, the breakdown voltage between the control gate and the selection gate can be effectively improved, and the performance of the memory device is improved.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a control method of a memory device.
Background
In the application process of the integrated circuit, the performance of various devices can be influenced by structures formed by materials of various layers, particularly the performance of transistor devices is influenced by different gate structures.
In the actual operation process, the research and development personnel of the application find that in the current semiconductor device control scheme, particularly the control method of the memory device, the memory device with the ETOX floating gate structure is formed by adopting a ETOX (Electron Tunneling Oxide device) process, and certain performance limitations still exist due to the structural reasons of the device, so that the performance of the memory device is influenced.
Disclosure of Invention
The invention mainly solves the technical problems that: the control method of the memory device is provided, for the memory device corresponding to the selection gate formed on one side of the control gate, the auxiliary voltage is applied to the auxiliary selection word line corresponding to the target word line through the selection of the target word line, and further the target memory cell is determined through the selection of the target bit line, so that the memory device operation is carried out on the target memory cell or the memory block, the breakdown voltage between the control gate and the selection gate in the memory device can be effectively improved, and the performance of the memory device is improved.
In order to solve the technical problems, the application adopts a technical scheme that: provided is a control method of a memory device, including: performing row selection on at least one row of word lines in a plurality of rows of word lines of a memory block in the memory device, wherein the selected word line is used as a target word line; the word line of the memory block comprises a plurality of memory cells, each memory cell is provided with a source electrode region, a drain electrode region, a channel region, a floating gate and a control gate, wherein the floating gate and the control gate are arranged above the channel region and are close to the drain electrode region, the selection gate is arranged above the channel region and is close to the source electrode region, the control gate corresponds to the word line, and the selection gate corresponds to the selection word line; taking a selected word line corresponding to the target word line as an auxiliary selected word line, and applying auxiliary voltage to the auxiliary selected word line; performing column selection on at least one column of bit lines in a plurality of columns of bit lines of a memory block in the memory device, wherein the selected bit line is used as a target bit line; and determining a target memory cell based on the selected target word line and the target bit line, and performing a memory device operation on the target memory cell or the memory block.
In one embodiment of the present application, in response to a read operation in which the memory device operates as a single memory cell, the control method includes: applying a first select voltage on the target word line and a first auxiliary voltage on the auxiliary select word line; a read voltage is applied to the target bit line to determine whether the selected target memory cell has current flowing therethrough to determine whether the target memory cell has electrons stored therein.
In an embodiment of the present application, the first selection voltage is 2V-3V, the first auxiliary voltage is 2V-3V, the reading voltage is 0.5V-1.2V, and the substrate voltage is 0V.
In one embodiment of the present application, in response to a write operation in which the memory device operates as a single memory cell, the control method includes: applying a second select voltage on the target word line and a second auxiliary voltage on the auxiliary select word line; and applying a writing voltage on the target bit line, and injecting electrons into the floating gate of the selected target memory cell.
In an embodiment of the present application, the second selection voltage is 5V to 10V, the second auxiliary voltage is 0.5V to 1.5V, and the writing voltage is 3V to 4.5V.
In an embodiment of the present application, a memory block of the memory device includes a substrate, and a well region is further included in the substrate, where the source region, the drain region, and the channel region of a memory cell in the memory block are disposed in the well region; and applying a substrate voltage to the well region in response to the memory device operating as a read operation or a write operation, wherein the substrate voltage is 0V.
In an embodiment of the present application, the memory block of the memory device includes a substrate, the substrate further includes a well region, the source region, the drain region and the channel region of the memory cell in the memory block are disposed in the well region, wherein an upper surface of the selection gate is lower than a lower surface of the control gate; an erase voltage is applied to the well region in response to the memory device operating as an erase operation.
In one embodiment of the present application, in response to the memory device operation being an erase operation, the control method includes: applying a third select voltage on a word line of the memory block and a third auxiliary voltage on a selected word line of the memory block; applying an erasing voltage to the well region, and erasing electrons in the floating gates of the memory cells in the memory block; wherein the bit lines and source lines of the memory block are floated.
In an embodiment of the present application, the erase voltage is greater than or equal to the third auxiliary voltage, or the selected word line of the memory block is floating.
In an embodiment of the present application, the third selection voltage is-6V to-10V, the erase voltage is 6V to 10V, and the third auxiliary voltage is 0V to 10V.
In one embodiment of the present application, the thickness of the selection gate is smaller than the thickness of the control gate in the vertical direction.
In an embodiment of the present application, a first gate insulating layer is disposed on a substrate corresponding to the control gate, and a second gate insulating layer is disposed on a substrate corresponding to the selection gate, where a thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer in a vertical direction.
Unlike the prior art, the control method of the memory device provided by the application comprises the following steps: performing row selection on at least one of a plurality of rows of word lines of a memory block in a memory device, with the selected word line as a target word line; the word line of the memory block comprises a plurality of memory cells, wherein each memory cell is provided with a source region, a drain region, a channel region, a floating gate and a control gate which are arranged above the channel region and close to the drain region, and a selection gate which is arranged above the channel region and close to the source region, wherein the control gate corresponds to the word line, and the selection gate corresponds to the selection word line; using a selected word line corresponding to the target word line as an auxiliary selected word line, and applying auxiliary voltage to the auxiliary selected word line; performing column selection on at least one column of bit lines in a plurality of columns of bit lines of a memory block in a memory device, with the selected bit line as a target bit line; determining a target memory cell based on the selected target word line and target bit line, performing a memory device operation on the target memory cell or memory block; the application forms a selection gate on one side of the control gate, sets a storage device with the upper surface lower than the lower surface of the control gate, reduces the coupling area between the control gate and the selection gate, reduces the equivalent gate capacitance, improves the reliability of the device, and improves the breakdown voltage between the control gate and the selection gate, so that the corresponding pressure-bearing adjusting range is enlarged.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 is a flow chart of an embodiment of a method for controlling a memory device according to the present application;
FIG. 2 is a schematic diagram of an embodiment of a memory cell according to the present application;
FIG. 3 is a circuit diagram of a memory block in a memory device of the present application;
FIG. 4 is a schematic diagram of an embodiment of a read operation according to the present application;
FIG. 5 is a schematic diagram illustrating the structure of an embodiment of a write operation in accordance with the present application;
FIG. 6 is a schematic diagram of an embodiment of an erase operation in accordance with the present application.
In the drawings, a memory cell 10, a substrate 100, a gate stack structure 200, a first gate insulating layer 210, a floating gate 220, a first inter-gate dielectric layer 230, a control gate 240, a select gate 300, a second inter-gate dielectric layer 310, a second gate insulating layer 320, an isolation sidewall 400, a first isolation sidewall 410, a second isolation sidewall 420, a third isolation sidewall 430, a source region S, a drain region D, a first word line W0, a second word line W1, a third word line W2, a first bit line B0, a second bit line B1, a third bit line B2, a first select word line S0, a second select word line S1, a third select word line S2, a first memory cell a00, a second memory cell a10, a third memory cell a20, a fourth memory cell a01, a fifth memory cell a11, a sixth memory cell a21, a seventh memory cell a02, an eighth memory cell a12, and a ninth memory cell a22 are illustrated.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the current semiconductor device control method, particularly in the control of a memory device, the memory device with an ETOX floating gate structure is formed by adopting a ETOX (Electron Tunneling Oxide device) process, and certain performance limitations still exist due to the structural reasons of the device, so that the storage performance of the memory device is affected.
Therefore, the control method of the memory device is provided, the memory device is formed on one side of the control gate, the upper surface of the selection gate is lower than the memory device corresponding to the lower surface of the control gate, the auxiliary voltage is applied to the auxiliary selection word line corresponding to the target word line through the selection of the target word line, and further the target memory cell is determined through the selection of the target bit line, so that the memory device operation is performed on the target memory cell or the memory block, the breakdown voltage between the control gate and the selection gate can be effectively improved, and the performance of the memory device is improved.
Referring to fig. 1, fig. 1 is a flowchart illustrating a control method of a memory device according to an embodiment of the application.
As shown in fig. 1, the control method of the memory device includes:
s10, performing row selection on at least one row of word lines in a plurality of rows of word lines of a memory block in a memory device, wherein the selected word line is used as a target word line;
The memory device comprises at least one memory block, the memory block comprises a plurality of rows of word lines and a plurality of columns of bit lines, the word lines of the memory block comprise a plurality of memory cells, each memory cell comprises a source region, a drain region, a channel region, a floating gate and a control gate which are arranged above the channel region and close to the drain region, a selection gate which is arranged above the channel region and close to the source region, the control gate corresponds to the word line, the selection gate corresponds to the selection word line, and in some embodiments, the upper surface of the selection gate is lower than the lower surface of the control gate.
Specifically, the memory device includes a memory block, and the memory block may include a plurality of rows of word lines and a plurality of columns of bit lines, and the word lines of each row are correspondingly connected to the control gates of each memory cell in the row of word lines, so that when a row selection is performed on at least one row of word lines of the memory block, for example, a selection voltage is applied to at least one row of word lines, the selected word line may be regarded as a target word line, and the memory cells on the target word line are all selected.
S20, using the selected word line corresponding to the target word line as an auxiliary selected word line, and applying auxiliary voltage to the auxiliary selected word line.
Because the memory cells also have the select gates disposed on one side of the control gates, each word line is configured with a corresponding select word line, i.e., each row of word lines has a row of corresponding select word lines, which also correspond to the select gates connected to each memory cell in the row of word lines.
Specifically, after performing row selection with the selected word line as the target word line, the selected word line corresponding to the target word line is also selected and serves as an auxiliary selection word line, and an auxiliary voltage is applied to the auxiliary selection word line, that is, to the selection gate of the selected row of memory cells, so that the corresponding memory device operation is performed.
S30, performing row and column selection on at least one column of bit lines in a plurality of columns of bit lines of a memory block in the memory device, and taking the selected bit line as a target bit line.
Wherein, the bit line of each column is correspondingly connected with the drain electrode of each memory cell in the column bit line.
Specifically, when column selection is performed on at least one of the plurality of columns of bit lines of the memory block, the selected bit line is used as a target bit line, for example, a voltage is applied to the at least one column of bit lines, so that the selected bit line can be used as the target bit line, and memory cells on the target bit line are all selected.
S40, determining a target memory cell based on the selected target word line and the target bit line, and executing memory device operation on the target memory cell or the memory block.
Specifically, each row of word lines and each column of bit lines have corresponding connection points, and the memory cell corresponding to the connection point is a target memory cell, namely, the target word line is connected with a control gate of the target memory cell, the target bit line is connected with a source region of the target memory cell, and the auxiliary selection word line is connected with a selection gate of the target memory cell; accordingly, the corresponding voltages are applied to the control gate, the source region, and the select gate, respectively, so that memory device operations, such as a read operation, a write operation, an erase operation, and the like, can be performed on the target memory cell or memory block.
In this embodiment, for the memory device formed on one side of the control gate, where the upper surface of the selection gate is lower than the lower surface of the control gate, the breakdown voltage between the control gate and the selection gate can be effectively improved, and the performance of the memory device can be improved by selecting the target word line for the memory device and applying an auxiliary voltage to the auxiliary selection word line corresponding to the target word line, and further determining the target memory cell by selecting the target bit line, so as to perform the memory device operation on the target memory cell or the memory block.
A description will be made below of a control method in conjunction with a specific structure of the memory cell.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a memory cell according to an embodiment of the application.
As shown in fig. 2, the memory cell 10 includes a substrate 100, a gate stack 200, and a select gate 300; the gate stack structure 200 is disposed on the substrate 100, the gate stack structure 200 includes at least a floating gate and a control gate, and the selection gate 300 is disposed at one side of the gate stack structure 200, and in some embodiments, an upper surface of the selection gate is lower than a lower surface of the control gate to reduce a coupling area between the selection gate and the control gate while enhancing a breakdown voltage between the control gate and the selection gate.
The gate stack structure 200 includes a first gate insulating layer 210, a floating gate 220, a first inter-gate dielectric layer 230, and a control gate 240; the selection gate 300 is disposed on the substrate 100 at one side of the gate stack structure 200; a second inter-gate dielectric layer 310 is disposed between the gate stack structure 200 and the select gate 300, and a second gate insulating layer 320 is further disposed between the select gate 300 and the substrate 100, in some embodiments, the upper surface of the second gate insulating layer 320 is higher than the upper surface of the first gate insulating layer, i.e., the thickness of the second gate insulating layer is greater than the thickness of the first gate insulating layer in the vertical direction, so that electrons in the select gate can be prevented from entering the substrate, i.e., the select gate 300 will receive power during erasing, and if the second gate insulating layer 320 is too thin, electrons will continuously rush into the substrate, which is rather unfavorable for erasing. Of course, this does not mean that the upper surface of the second gate insulating layer 320 is higher than the upper surface of the first gate insulating layer (the thickness of the second gate insulating layer 320 is greater than the upper surface of the first gate insulating layer) is an essential feature of the present application, and similar technical effects can be achieved by adjustment of the control method or adjustment of the process.
And, an isolation sidewall 400 is provided for the gate stack structure 200 and the select gate 300 to cover exposed sidewalls of the gate stack structure 200 and the control gate 240, wherein the isolation sidewall includes a first isolation sidewall 410, a second isolation sidewall 420 and a third isolation sidewall 430, and the first isolation sidewall 410 is disposed at a side of the gate stack structure 200 away from the select gate to cover exposed sidewalls of the gate stack structure 200; the second isolation sidewall 420 is disposed on a sidewall of the side of the select gate away from the gate stack structure, so as to cover the exposed sidewall of the side of the select gate away from the gate stack structure; the third isolation sidewall 430 is disposed over the select gate 300 on the side of the gate stack 200 adjacent to the select gate to cover the exposed sidewall of the gate stack on the select gate side. In some embodiments, the third isolation sidewall 430 may be omitted.
Further, the memory cell further includes a source region S and a drain region D, wherein the source region S is disposed in the substrate 100 on a side of the select gate 300 remote from the gate stack 200, and the drain region D is disposed in the substrate on a side of the gate stack 200 remote from the select gate 300.
In some embodiments, the locations of the source region S and the drain region D may be interchanged depending on the design.
In one embodiment, a memory block of a memory device includes a substrate in which a source region, a drain region, and a channel region of a memory cell are disposed.
The substrate also comprises a well region, and the source region, the drain region and the channel region of the memory unit are arranged in the well region so as to apply an erasing voltage or a base voltage to the well region.
And the connection of a plurality of memory cells of a memory block in a memory device is illustrated by a circuit diagram.
Referring to fig. 3, fig. 3 is a circuit diagram of a memory block in the memory device according to the present application.
As shown in fig. 3, the memory block of the memory device includes a plurality of rows of word lines, a plurality of columns of selection word lines, and a plurality of columns of bit lines, and is specifically described with three rows of word lines and three columns of bit lines as examples, the three rows of word lines including a first word line W0, a second word line W1, and a third word line W2; the three columns of bit lines include a first bit line B0, a second bit line B1, and a third bit line B2; the corresponding three rows of select word lines include a first select word line S0, a second select word line S1, and a third select word line S2; then, the memory cell includes a control gate 240, a floating gate 220, a select gate 300, a source region S and a drain region D, each row word line is connected to the control gate 240 of the memory cell in the row, each row select word line is connected to the select gate 300 of the memory cell in the row, each column bit line is connected to the drain region D of the memory cell in the column, and the source region S of each memory cell is grounded.
For example, the first word line W0 connects the control gates of the first, second and third memory cells a00, a10 and a20 of the same row, and the first selection word line S0 connects the selection gates of the first, second and third memory cells a00, a10 and a 20; the second word line W1 connects control gates of the fourth, fifth and sixth memory cells a01, a11 and a21 of the same row, and the second select word line S1 connects select gates of the fourth, fifth and sixth memory cells a01, a11 and a 21; the third word line W2 connects control gates of the seventh, eighth and ninth memory cells a02, a12 and a22 of the same row, and the third select word line S2 connects select gates of the seventh, eighth and ninth memory cells a02, a12 and a 22; the first bit line B0 connects drain regions of the first, fourth and seventh memory cells a00, a01 and a02 of the same column, the second bit line B1 connects drain regions of the second, fifth and eighth memory cells a10, a11 and a12 of the same column, and the third bit line B2 connects drain regions of the third, sixth and ninth memory cells a20, a21 and a22 of the same column.
A target memory cell is determined based on the selected target word line and target bit line, and a memory device operation is performed on the target memory cell or memory block.
Wherein the memory device operation includes a read operation, a write operation, and/or an erase operation.
In one embodiment, in response to a memory device operating as a read operation of a single memory cell, a method of controlling a memory device includes:
A first selection voltage is applied to at least one of a plurality of rows of word lines of a memory block in a memory device.
As shown in fig. 3, the multiple rows of word lines of the memory block may be three rows of word lines, and the first word line W0, the second word line W1 and the third word line W2 are selected as target word lines, so that a first selection voltage may be applied to the second word line W1 in the memory block, and the first selection voltage may be a positive voltage, for example, 2V to 3V, and in particular, may be 2.5V.
Then, a first auxiliary voltage is applied to an auxiliary selected word line corresponding to the target word line.
Wherein, the selected word lines are correspondingly provided with three rows, and the first selected word line S0, the second selected word line S1 and the third selected word line S2; namely, when the selected target word line corresponds to the auxiliary selection word line, when the target word line is the second word line W1, the corresponding auxiliary selection word line is the second selection word line S1; accordingly, the first auxiliary voltage may be applied to the second selected word line S1 in the memory block. The first auxiliary voltage may be the same as the first selection voltage, i.e. the first auxiliary voltage may also be a positive voltage, such as 2V-3V, and may specifically be 2.5V.
A read voltage is applied to at least one of the plurality of columns of bit lines of the memory block to determine whether a current flows through the selected target memory cell, i.e., to read the current of the target memory cell, to determine whether the target memory cell stores electrons.
With continued reference to FIG. 3, the multiple columns of bit lines of the memory block may be three columns of bit lines, including a first bit line B0, a second bit line B1, and a third bit line B2; with the second bit line as the target bit line, a read voltage may be applied to the second bit line B1 in the memory block, to determine that the fifth memory cell a11 selected by the second word line W1 and the second bit line B1 is the target memory cell, and further to determine whether a current flows through the fifth memory cell a11, to determine whether the fifth memory cell a11 stores electrons; in some embodiments, the read voltage is a positive voltage, such as 0.5V-1.2V, and may be 0.8V in particular, and the source regions of all the memory cells in the memory block are applied with a source voltage of 0V through the common source line, and the well regions of all the memory cells are applied with a base voltage of 0V.
If electrons are stored in the gate stack of the memory cell, the threshold voltage of the memory cell increases, and the first selection voltage of 2.5V received on the control gate of the memory cell is insufficient to open the channel region for conduction, no current may be generated between the source region and the drain region of the memory cell, and the read data is "0". If the memory cell does not store electrons, a first select voltage of 2.5V received on the control gate of the memory cell is sufficient to open the channel region between the source and drain regions for conduction, a current is generated between the source and drain regions of the memory cell, and the read data is "1".
Hereinafter, the structure of the memory cell will be described in detail as a memory device operation as a read operation.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating a read operation according to an embodiment of the application.
Referring to fig. 4, on the basis of fig. 2, a first select voltage is applied to the control gate of the selected target memory cell, wherein the first select voltage may be 2.5V, a first auxiliary voltage is applied to the select gate, wherein the first auxiliary voltage is 2.5V, and a read voltage is applied to the drain region D, wherein the read voltage is 0.8V; and applying a base voltage of 0V corresponding to the source region and the well region in the substrate; if electrons are stored in the floating gate, the channel region is not conductive, no current is generated between the source region S and the drain region D, and the read data is 0; if electrons are not stored in the floating gate, the channel region is conductive, a current is generated between the source region S and the drain region D, and electrons flow from the source region to the drain region, and thus, the current is detected to pass through, and the read data is "1".
In another embodiment, in response to a memory device operation being a write operation of a single memory cell, a method of controlling a memory device includes:
A second selection voltage is applied to at least one of the plurality of rows of word lines of the memory block in the memory device.
As shown in fig. 3, the plurality of word lines of the memory block may be three rows of word lines, and the first word line W0, the second word line W1 and the third word line W2 may be selected as the target word line by using the second word line W1, so that a second selection voltage may be applied to the second word line W1 in the memory block, and the second selection voltage may be a positive voltage, and may be 5V to 10V, and may be specifically 8V.
A second auxiliary voltage is then applied to the auxiliary select word line corresponding to the target word line.
Wherein, the selected word lines are correspondingly provided with three rows, and the first selected word line S0, the second selected word line S1 and the third selected word line S2; namely, when the selected target word line corresponds to the auxiliary selection word line, when the target word line is the second word line W1, the corresponding auxiliary selection word line is the second selection word line S1; accordingly, a second auxiliary voltage may be applied to the second selected word line S1 in the memory block. In some embodiments, the third auxiliary voltage is less than the third select voltage, and the second auxiliary voltage is a positive voltage, such as 0.5V-1.5V, and may be 1V.
And applying a writing voltage to at least one column of bit lines in a plurality of columns of bit lines of the memory block, and injecting electrons into the floating gate of the selected target memory cell in a hot carrier injection mode.
With continued reference to FIG. 3, the multiple columns of bit lines of the memory block may be three columns of bit lines, including a first bit line B0, a second bit line B1, and a third bit line B2; with the second bit line as the target bit line, a write voltage may be applied to the second bit line B1 in the memory block, the fifth memory cell a11 selected by the second word line W1 and the second bit line B1 may be determined as the target memory cell, and electrons may be injected into the floating gate of the selected target memory cell by hot carrier injection into the fifth memory cell a 11.
The writing voltage is a positive voltage, which may be 3V to 4.5V, and may be specifically 4V, and the source voltage of 0V is applied to the source regions of all the memory cells in the memory block through the common source line, and the base voltage of 0V is applied to the well regions of all the memory cells.
Hereinafter, the structure of the memory cell will be described in detail as a memory device operation as a write operation.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating an embodiment of a write operation according to the present application.
As shown in fig. 5, on the basis of fig. 2, a second selection voltage is applied to the control gate of the target memory cell, at which time the second selection voltage is 8V, and a second auxiliary voltage is applied to the selection gate, at which time the second auxiliary voltage is 1V, and a writing voltage is applied to the drain region D, at which time the writing voltage is 4V; and applying a base voltage of 0V corresponding to the source region S and the well region in the substrate; because the control gate is applied with a large positive voltage (+8v) while the drain region D is applied with a positive voltage of 4V, i.e., the drain region D is positively biased to +4v, and the select gate is applied with a positive voltage of 1V, electrons are caused to flow from the source region to the drain region and pass under the positively biased floating gate, and because of the large positive voltage applied to the control gate, some electrons are "pulled" into the floating gate, i.e., electrons are injected into the floating gate of the selected target memory cell in a hot carrier injection manner; wherein electrons flow from the source region to the drain region and current flows from the drain region to the source region.
Those skilled in the art will appreciate that the above-described write operation is for a single memory cell.
In yet another specific embodiment, in response to the memory device operation being an erase operation, the control method includes:
a third select voltage is applied to the word line of the memory block.
As shown in fig. 3, the plurality of word lines of the memory block may be three rows of word lines, and the first word line W0, the second word line W1 and the third word line W2, it is understood that the erase operation is typically an erase operation of the entire memory block, and thus, the third selection voltage may be applied to the first word line W0, the second word line W1 and the third word line W2 in the memory block, and the third selection voltage may be a negative voltage, for example, -6V to-10V, and in particular, -8V.
And applying a third auxiliary voltage on the selected word line of the memory block.
Wherein, the selected word lines are correspondingly provided with three rows, and the first selected word line S0, the second selected word line S1 and the third selected word line S2; then a third auxiliary voltage is also required to be applied to the selected word line of the memory block when a third select voltage is applied to the word line of the memory block; that is, a fifth auxiliary voltage may be applied to the first, second, and third selected word lines S0, S1, and S2 in the memory block. The third auxiliary voltage is a positive voltage, for example, 6-10V, and may be specifically 8V.
And applying an erasing voltage to the well region of the memory block, and erasing electrons in the floating gates of the memory cells in the memory block in an F-N tunnel effect mode.
Wherein both the bit lines and the source lines of the memory block are floated.
Specifically, the multiple columns of bit lines of the memory block may be three columns of bit lines, including a first bit line B0, a second bit line B1 and a third bit line B2, where the first bit line B0, the second bit line B1 and the third bit line B2 are all floating, and the source lines corresponding to the source regions of the memory cells in the memory block are floating, so that the source regions of all the memory cells in the memory block are floating; and then, an erasing voltage is applied to the well region in the storage block, wherein the erasing voltage is positive voltage, so that the well region voltage of the storage unit in the storage block is higher than the control gate voltage, namely the erasing voltage is higher than the third selection voltage, and then electrons in the storage unit flow from the floating gate to the surface of the substrate through the gate insulating layer. Wherein, the erasing voltage is positive voltage, such as 6V-10V, and can be 8V; and because the third auxiliary voltage with positive voltage is applied to the selection gate, the potential difference between the selection gate and the well region is reduced, and the phenomenon that the erasure efficiency is reduced and the erasure effect is influenced due to the fact that electrons continuously move from the selection gate to the substrate is avoided.
Hereinafter, the structure of the memory cell will be described in detail as the memory device operation is an erase operation.
Referring to fig. 6, fig. 6 is a schematic diagram illustrating an embodiment of an erase operation according to the present application.
As shown in fig. 6, on the basis of fig. 2, a third selection voltage of-8V is applied to the control gates of all the memory cells in the memory block, an erase voltage of +8v is applied to the well region of the memory block, and a third auxiliary voltage of +8v is applied to the selection gates of all the memory cells in the memory block; the well voltage of the memory cells in the memory block is made higher than the control gate voltage, that is, the erase voltage of +8v is made higher than the third select voltage of-8V, thereby allowing electrons to flow from the floating gate 220 to the substrate surface through the first gate insulating layer 210; i.e., positive voltage of +8V in the substrate attracts electrons trapped in the floating gate, while the control gate is applied with negative voltage of-8V, the floating gate repels the trapped negative charge; and the two voltages are superposed to form an electric field, so that electrons can pass through the first gate insulating layer 210 between the floating gate 220 and the substrate, and further the electrons in the floating gate are exhausted, thereby reducing the corresponding threshold voltage; and a third auxiliary voltage of +8V is applied to the selection gate to reduce the potential difference between the selection gate and the well region, thereby avoiding the reduction of the erasing efficiency caused by the continuous movement of electrons from the selection gate to the substrate and affecting the erasing effect.
In some embodiments, when the upper surface of the second gate insulating layer is higher than the upper surface of the first gate insulating layer, i.e. when the second gate insulating layer is thicker than the first gate insulating layer, electrons cannot move from the selection gate to the substrate, so that damage to the second gate insulating layer is reduced, the third auxiliary voltage may be smaller, for example, the third auxiliary voltage may be 5.5V, or the selection gate of the memory cell in the memory block may be floating, and electrons can basically pass through the gate insulating layer between the floating gate and the substrate, so that electrons in the floating gate are depleted, thereby reducing the corresponding threshold voltage.
It can be appreciated that the value of the third auxiliary voltage can be adjusted according to the thickness of the second gate insulating layer, so that the erasing operation of the memory cell can be realized, that is, if the second gate insulating layer is thick enough, the third auxiliary voltage can be smaller or floating because electrons go through.
In this embodiment, for the memory device in which the selection gate is formed on one side of the control gate and the upper surface of the selection gate is lower than the lower surface of the control gate, the auxiliary voltage is applied to the auxiliary selection word line corresponding to the target word line by selecting the target word line, and then the target memory cell is determined by selecting the target bit line, so that the memory device operation is performed on the target memory cell, the breakdown voltage between the control gate and the selection gate in the memory device can be effectively improved, and the performance of the memory device is improved.
The foregoing description is only of embodiments of the present invention, and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present invention or directly or indirectly applied to other related technical fields are included in the scope of the present invention.
Claims (12)
1. A control method of a memory device, wherein the memory device comprises at least one memory block, a word line of the memory block comprises a plurality of memory cells, each memory cell comprises a source region, a drain region, a channel region, a floating gate and a control gate which are arranged above the channel region and are close to the drain region, and a selection gate which is arranged above the channel region and is close to the source region, wherein the control gate corresponds to the word line, and the selection gate corresponds to the selection word line; the control method comprises the following steps:
Performing row selection on at least one row of word lines in a plurality of rows of word lines of a memory block in the memory device, wherein the selected word line is used as a target word line;
taking a selected word line corresponding to the target word line as an auxiliary selected word line, and applying auxiliary voltage to the auxiliary selected word line;
Performing column selection on at least one column of bit lines in a plurality of columns of bit lines of a memory block in the memory device, wherein the selected bit line is used as a target bit line;
And determining a target memory cell based on the selected target word line and the target bit line, and performing a memory device operation on the target memory cell or the memory block.
2. The control method according to claim 1, wherein,
In response to the memory device operating as a read operation, the control method includes:
Applying a first select voltage on the target word line and a first auxiliary voltage on the auxiliary select word line;
a read voltage is applied to the target bit line to determine whether the selected target memory cell has current flowing therethrough to determine whether the target memory cell has electrons stored therein.
3. The control method according to claim 2, wherein,
The first selection voltage is 2V-3V, the first auxiliary voltage is 2V-3V, and the reading voltage is 0.5V-1.2V.
4. The control method according to claim 1, wherein,
In response to the memory device operating as a write operation, the control method includes:
Applying a second select voltage on the target word line and a second auxiliary voltage on the auxiliary select word line;
And applying a writing voltage on the target bit line, and injecting electrons into the floating gate of the selected target memory cell.
5. The control method according to claim 4, wherein,
The second selection voltage is 5V-10V, the second auxiliary voltage is 0.5V-1.5V, and the writing voltage is 3V-4.5V.
6. The control method according to claim 2 or 4, characterized in that,
The memory block of the memory device comprises a substrate, wherein the substrate further comprises a well region, and the source region, the drain region and the channel region of a memory unit in the memory block are arranged in the well region;
And applying a substrate voltage to the well region in response to the memory device operating as a read operation or a write operation, wherein the substrate voltage is 0V.
7. The control method according to claim 1, wherein,
The memory block of the memory device comprises a substrate, a well region is further included in the substrate, and the source region, the drain region and the channel region of a memory cell in the memory block are arranged in the well region;
an erase voltage is applied to the well region in response to the memory device operating as an erase operation.
8. The control method according to claim 7, wherein,
In response to the memory device operating as an erase operation, the control method includes:
Applying a third select voltage on a word line of the memory block and a third auxiliary voltage on a selected word line of the memory block;
applying an erasing voltage to the well region, and erasing electrons in the floating gates of the memory cells in the memory block; wherein the bit lines and source lines of the memory block are floated.
9. The control method according to claim 8, wherein,
The erase voltage is greater than or equal to the third auxiliary voltage, or a selected word line of the memory block is floating.
10. The control method according to claim 9, wherein,
The third selection voltage is-6V to-10V, the erasing voltage is 6V to 10V, and the third auxiliary voltage is 0V to 10V.
11. The control method according to claim 1, wherein,
The upper surface of the select gate is lower than the lower surface of the control gate.
12. The control method according to claim 1, wherein,
The control gate is provided with a first gate insulating layer on a substrate corresponding to the control gate, the selection gate is provided with a second gate insulating layer on a substrate corresponding to the selection gate, and the thickness of the second gate insulating layer is larger than that of the first gate insulating layer in the vertical direction.
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