CN118511260A - 包括集成器件之间的间隔件的封装件 - Google Patents

包括集成器件之间的间隔件的封装件 Download PDF

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Publication number
CN118511260A
CN118511260A CN202280087090.5A CN202280087090A CN118511260A CN 118511260 A CN118511260 A CN 118511260A CN 202280087090 A CN202280087090 A CN 202280087090A CN 118511260 A CN118511260 A CN 118511260A
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China
Prior art keywords
integrated device
interconnects
package
integrated
coupled
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Pending
Application number
CN202280087090.5A
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English (en)
Chinese (zh)
Inventor
孙洋洋
D·何
L·赵
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Qualcomm Inc
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Qualcomm Inc
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Publication of CN118511260A publication Critical patent/CN118511260A/zh
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    • HELECTRICITY
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    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/0198Manufacture or treatment batch processes
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    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/20Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • HELECTRICITY
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    • H10BELECTRONIC MEMORY DEVICES
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    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
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    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07251Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07255Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in materials
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    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
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    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/261Functions other than electrical connecting
    • H10W72/267Multiple bump connectors having different functions
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    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01231Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H10W72/01233Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01235Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
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    • H10W72/01255Changing the shapes of bumps by using masks
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    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07321Aligning
    • H10W72/07327Aligning involving guiding structures, e.g. spacers or supporting members
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    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07351Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07354Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in dispositions
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    • H10W72/221Structures or relative sizes
    • H10W72/222Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241Dispositions, e.g. layouts
    • H10W72/244Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
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    • H10W72/251Materials
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    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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CN202280087090.5A 2022-01-12 2022-12-15 包括集成器件之间的间隔件的封装件 Pending CN118511260A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/574,360 2022-01-12
US17/574,360 US11948909B2 (en) 2022-01-12 2022-01-12 Package comprising spacers between integrated devices
PCT/US2022/053063 WO2023136908A1 (en) 2022-01-12 2022-12-15 Package comprising spacers between integrated devices

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CN118511260A true CN118511260A (zh) 2024-08-16

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US (1) US11948909B2 (https=)
EP (1) EP4463886A1 (https=)
JP (1) JP2025501385A (https=)
KR (1) KR20240136950A (https=)
CN (1) CN118511260A (https=)
TW (1) TW202335200A (https=)
WO (1) WO2023136908A1 (https=)

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KR20240135232A (ko) * 2023-03-03 2024-09-10 삼성전자주식회사 반도체 패키지

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US6724084B1 (en) 1999-02-08 2004-04-20 Rohm Co., Ltd. Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device
JP3973340B2 (ja) * 1999-10-05 2007-09-12 Necエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
US7118940B1 (en) 2005-08-05 2006-10-10 Delphi Technologies, Inc. Method of fabricating an electronic package having underfill standoff
US8390109B2 (en) 2011-02-17 2013-03-05 Oracle America, Inc. Chip package with plank stack of semiconductor dies
US9947642B2 (en) * 2015-10-02 2018-04-17 Qualcomm Incorporated Package-on-Package (PoP) device comprising a gap controller between integrated circuit (IC) packages
JP6604211B2 (ja) * 2016-01-15 2019-11-13 富士通株式会社 積層半導体及び積層半導体の製造方法
WO2020264037A1 (en) 2019-06-26 2020-12-30 Flir Commercial Systems, Inc. Semiconductor device interconnection systems and methods

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JP2025501385A (ja) 2025-01-17
US11948909B2 (en) 2024-04-02
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US20230223375A1 (en) 2023-07-13
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KR20240136950A (ko) 2024-09-19

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