CN118410770A

CN118410770A - Method for checking design rule of layout, electronic equipment and storage medium

Info

Publication number: CN118410770A
Application number: CN202410878572.3A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Advanced Manufacturing EDA Co Ltd
Current assignee: Advanced Manufacturing EDA Co Ltd
Priority date: 2024-07-02
Filing date: 2024-07-02
Publication date: 2024-07-30

Abstract

Embodiments of the present disclosure relate to a design rule checking method for a layout, an electronic device, and a storage medium. The embodiment of the disclosure discloses a layout generation method, which comprises the following steps: selecting standard cell arrangements from a standard cell library, wherein each arrangement comprises standard cells arranged according to a corresponding sequence; based on a preset rule, splicing standard units in each arrangement by taking the boundary of each splicing layer as a reference to form each basic splicing structure; and generating corresponding layouts based on the basic splicing structures respectively. According to the technical scheme, adjacent scenes of the analog standard units in the actual layout can be covered to the greatest extent, efficiency is greatly improved, and cost is reduced.

Description

Method for checking design rule of layout, electronic equipment and storage medium

Technical Field

Embodiments of the present disclosure relate generally to integrated circuits and, more particularly, to a layout generation method, an electronic device, and a storage medium.

Background

In the design process of integrated circuits, some basic logic units are generally packaged based on standardized design rules to form standard units (STANDARDCELL, abbreviated as units). The digital design stage may perform more complex circuit designs based on these standard cells and invoke the layout of these standard cells to achieve the final physical layout by automatic placement and routing.

The development of standard cells is typically a separate look-ahead process. The development process can only ensure that the design rules inside a single standard cell layout are correct. The digital back-end physical implementation needs to splice various standard units based on a design netlist, and new design rule problems easily occur at the spliced part, so that the new design rule problems cannot be found by directly using a checking tool in the development process. In the traditional scheme, splicing is usually carried out in a manual mode, and the mode is low in efficiency and high in labor cost.

Disclosure of Invention

In accordance with example embodiments of the present disclosure, a scheme for design rule checking of a layout is provided to at least partially overcome the above-described or other potential drawbacks.

According to one aspect of the present disclosure, a method for layout generation is provided. The method comprises the following steps: selecting standard cell arrangements from a standard cell library, wherein each arrangement comprises standard cells arranged according to a corresponding sequence; based on a preset rule, splicing standard units in each arrangement by taking the boundary of each splicing layer as a reference to form each basic splicing structure; and generating corresponding layouts based on the basic splicing structures respectively. According to the technical scheme, the adjacent or placed scenes of the analog standard units in the actual layout can be covered to the greatest extent, and compared with a manual mode, the efficiency can be greatly improved, the cost is reduced, and the layout generation quality is further remarkably improved.

In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor; and a memory coupled to the processor, the memory having instructions stored therein that, when executed by the processor, cause the device to perform actions comprising: selecting standard cell arrangements from a standard cell library, wherein each arrangement comprises standard cells arranged according to a corresponding sequence; based on a preset rule, splicing standard units in each arrangement by taking the boundary of each splicing layer as a reference to form each basic splicing structure; and generating corresponding layouts based on the basic splicing structures respectively.

In some embodiments, selecting an arrangement of standard cells from a standard cell library comprises: a first number of permutations of standard cells is selected from a library of standard cells, wherein each permutation includes a second number of standard cells arranged in a corresponding order.

In some embodiments, selecting the first number of permutations of standard cells from the standard cell library comprises: traversing the standard cell library to select each standard cell in the standard cell library separately to form a first number of permutations each comprising one standard cell, wherein the first number is equal to the total number of standard cells in the standard cell library.

In some embodiments, stitching the standard cells in each permutation based on the predetermined rules, respectively, with respect to the boundaries of the stitching layer comprises: and splicing the boundary of the splicing layer of each standard unit in the arrangement with the boundary of the splicing layer of the copy of each standard unit respectively to form each basic splicing structure.

In some embodiments, selecting the first number of permutations of standard cells from the standard cell library comprises: determining all permutations of a second number of standard cells from the standard cell library based on the permutation and combination method, wherein the second number is at least two; and randomly selecting a first number of permutations from all permutations.

In some embodiments, stitching the standard cells in each permutation based on the predetermined rules, respectively, with respect to the boundaries of the stitching layer comprises: and splicing the second number of standard units in each arrangement according to the sequence of the standard units in the arrangement and taking the boundary of each splicing layer as a reference, so as to form each basic splicing structure.

In some embodiments, stitching the standard cells in each permutation based on a predetermined rule, respectively, with respect to the boundary of the stitching layer further comprises performing the following operations on the standard cells in each permutation: turning over the basic splicing structure 180 degrees by taking the uppermost boundary of the splicing layer of the basic splicing structure as an axis to form an upper splicing structure adjacent to the basic splicing structure in the first direction, wherein the upper splicing structure is symmetrical to the basic splicing structure; turning over the basic splicing structure 180 degrees by taking the lowest boundary of the splicing layer of the basic splicing structure as an axis to form a lower splicing structure which is symmetrical to the basic splicing structure and is adjacent to the basic splicing structure in a second direction opposite to the first direction; turning over the basic splicing structure by 180 degrees by taking the leftmost boundary of the splicing layer of the basic splicing structure as an axis so as to form a left splicing structure adjacent to the basic splicing structure in a third direction, wherein the left splicing structure is symmetrical to the basic splicing structure; and turning the basic splice structure 180 degrees around the rightmost boundary of the splice layer of the basic splice structure to form a right splice structure adjacent to the basic splice structure in a fourth direction opposite to the third direction.

In some embodiments, generating the respective layout based on the respective base mosaic structure comprises: and respectively taking each layout comprising the basic splicing structure, the upper splicing structure, the lower splicing structure, the left splicing structure and the right splicing structure as a corresponding layout.

In some embodiments, selecting the first number of permutations of standard cells from the standard cell library comprises: a first arrangement of a second number of standard cells is randomly selected from the standard cell library based on the arrangement combination method, wherein the second number is equal to the total number of standard cells in the standard cell library.

In some embodiments, stitching the standard cells in each permutation based on a predetermined rule, respectively, with respect to the boundaries of the stitching layer includes performing the following row-by-row or column-by-column stitching mode: sequentially splicing standard units in the first arrangement in a first row or a first column according to the sequence of the standard units in the first arrangement and by taking the boundary of each splicing layer as a reference; continuing stitching in a second row or column adjacent to the first row or column in response to the number of standard cells stitched reaching a predetermined threshold in the first row or column; and repeating the splicing in each row or column until the splicing of all standard cells in the first arrangement is completed, so as to form a corresponding layout.

In some embodiments, for each standard cell to be spliced in an even row or even column, the splicing is performed sequentially after the standard cell is flipped in a direction perpendicular to the row or column.

In some embodiments, the actions further comprise: selecting a second number of standard cells from the standard cell library to form other arrangements except the first arrangement; respectively splicing standard units in other arrangements in a row-by-row or column-by-column splicing mode until the splicing of the standard units in all other arrangements is completed, so as to form each basic splicing structure; and respectively taking the layout comprising each basic splicing structure as each corresponding layout.

In some embodiments, the standard cells are respectively arranged in independent files in a standard cell library, and the original boundary frame coordinates of the standard cells and the original boundary frame coordinates of the splicing layer are marked in each independent file; wherein splicing the standard cells in each arrangement based on the predetermined rule with respect to the boundary of the spliced layer includes: determining an offset based on given coordinates of a stitching layer of the first standard cell initially placed in a current coordinate system and original bounding box coordinates of the stitching layer; determining coordinates of a bounding box of the first standard cell based on the offset; and determining the boundary frame coordinates of each standard cell to be spliced subsequently based on the position relation between the other standard cells and the first standard cell and the size of each standard cell so as to splice each standard cell to be spliced subsequently.

In some embodiments, the second number of standard cells in each permutation is referred to as a root cell, which is spliced in one or a combination of the following ways: splicing each root unit in an extending manner along a first direction, wherein the boundary of the spliced layer of each root unit has the same or integral multiple size along a second direction perpendicular to the first direction; and splicing the root units in a second direction in an extending manner.

In some embodiments, where the boundaries of the splice layers of the individual standard cells have dimensions that are integer multiples along the second direction, the splice is performed in the following manner: splicing the standard units with the integral multiple number in the second direction to form a first splicing structure; and splicing the first splice structure with a corresponding one of the standard cells in a first direction to form a basic splice structure having aligned splice layer boundaries.

In a third aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon a computer program which when executed by a processor implements a method according to the first aspect of the present disclosure.

As will be appreciated from the following description, the technical solution of the present disclosure can simulate enough splicing scenes to discover and avoid design rule violation caused by random splicing in advance, greatly improve efficiency, and significantly improve subsequent layout generation quality.

The summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the disclosure, nor is it intended to be used to limit the scope of the disclosure.

Drawings

FIG. 1 illustrates a schematic diagram of an example environment in which embodiments of the present disclosure may be implemented;

FIG. 2 illustrates a flow chart of a layout generation method according to some embodiments of the present disclosure;

FIG. 3 illustrates a schematic diagram of a standard cell according to some embodiments of the present disclosure;

FIG. 4 shows a schematic diagram of a cell bounding box of the standard cell shown in FIG. 3;

FIG. 5 illustrates a schematic diagram of splice layers in a standard cell according to some embodiments of the present disclosure;

FIG. 6 shows a schematic view of a layer bounding box of the splice layer shown in FIG. 5;

FIG. 7 illustrates a schematic diagram of a layout formed by standard cell stitching in accordance with some embodiments of the present disclosure;

FIG. 8 illustrates a schematic diagram of a layout formed by standard cell stitching in accordance with further embodiments of the present disclosure;

FIG. 9 illustrates a schematic diagram of a standard cell to be spliced according to some embodiments of the present disclosure;

FIG. 10 is a schematic diagram of a layout spliced from standard cells shown in FIG. 9;

11A and 11B illustrate an algorithm flow diagram for generating a layout according to some embodiments of the present disclosure;

FIG. 12 illustrates an algorithm flow diagram for generating a layout according to further embodiments of the present disclosure;

FIG. 13 illustrates an overall flow diagram of generating a layout based on various patterns according to some embodiments of the present disclosure;

FIG. 14 illustrates a block diagram of a computing device capable of implementing various embodiments of the present disclosure.

Like or corresponding reference characters indicate like or corresponding parts throughout the several views.

Detailed Description

The principles of the present disclosure will be described below with reference to various exemplary embodiments shown in the drawings. It should be understood that these embodiments are merely provided to enable those skilled in the art to better understand and further practice the present disclosure and are not intended to limit the scope of the present disclosure in any way. It should be noted that similar or identical reference numerals may be used, where possible, in the figures and similar or identical reference numerals may designate similar or identical functions. Those skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the invention described herein.

The term "comprising" and variations thereof as used herein means open ended, i.e., "including but not limited to. The term "or" means "and/or" unless specifically stated otherwise. The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment. The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like, may refer to different or the same object.

As mentioned before, digital back-end physical implementation requires that various standard cells be spliced based on the design netlist, where new design rule problems are easily present, which cannot be found directly using inspection tools at the stage of designing standard cells. At this time, if the error in the standard cell is corrected, there is a high possibility that the area of the standard cell itself or the position of the Pin (Pin) is changed, thereby affecting the digital map. In order to find and avoid design rule violations caused by such random stitching in advance, it is necessary to perform enough stitching scene simulations at the stage of designing standard cells and perform design rule checking on the simulated scenes to find problems that may occur at the stitching points in advance.

The conventional scheme is usually performed by manually splicing and checking design rules (DesignRuleCheck, abbreviated as DRC). Manual stitching will take a lot of time and labor cost and the covered stitching scene is limited, thus potentially leading to many potential errors not being found.

In view of this, the present disclosure provides an improved layout generation scheme.

Some embodiments of the present disclosure provide improved layout generation methods. The method comprises the following steps: and selecting the arrangement of the standard units from the standard unit library, wherein each arrangement comprises standard units arranged according to the corresponding sequence. And splicing the standard units in each arrangement based on a preset rule by taking the boundary of each splicing layer as a reference to form each basic splicing structure. And generating corresponding layouts based on the basic splicing structures respectively. The embodiment of the disclosure can cover the adjacent or put scene of the analog standard unit in the actual layout to the greatest extent, and compared with a manual mode, the embodiment of the disclosure can greatly improve the efficiency, reduce the cost and remarkably improve the generation quality of the subsequent layout.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

FIG. 1 illustrates a schematic diagram of an example environment 100 in which embodiments in accordance with the present disclosure can be implemented. As shown in fig. 1, an example environment 100 includes a computing device 110 and a client 120.

In some embodiments, computing device 110 may interact with client 120. For example, computing device 110 may receive an input message from client 120 and output a feedback message to client 120. In some embodiments, the input message from the client 120 may be information of a standard cell library. The computing device 110 may perform corresponding processing for standard cells in the standard cell library and output corresponding results to the client 120.

In some embodiments, computing device 110 may include, but is not limited to, personal computers, server computers, hand-held or laptop devices, mobile devices (such as mobile phones, personal digital assistants PDAs, media players, etc.), consumer electronics, minicomputers, mainframe computers, cloud computing resources, and the like.

It should be understood that the description of the structure and functionality of the example environment 100 is for illustrative purposes only and is not intended to limit the scope of the subject matter described herein. The subject matter described herein may be implemented in different structures and/or functions. The environment is only illustrative and is not intended to limit the application environment of the disclosed embodiments.

In order to more clearly explain the principles of the disclosed solution, a more detailed description will be made below with reference to fig. 2 to 14.

Fig. 2 illustrates a flow chart of a layout generation method 200 according to some embodiments of the present disclosure.

At block 202, an arrangement of standard cells is selected from a library of standard cells, each arrangement including standard cells arranged in a corresponding order.

Quasi-units are typically composed of a number of layers stacked together. Each standard cell has a bounding box (cellboundingbox, abbreviated cellbbox) and each layer has a layer bounding box (layerboundingbox, abbreviated layerbbox).

The cell bounding box and the layer bounding box are further described below in connection with fig. 3-6. Fig. 3 illustrates a schematic diagram of a standard cell according to some embodiments of the present disclosure. As shown in fig. 3, the standard cell includes a first layer 302, a second layer (splice layer) 304, and a third layer 306. It will be appreciated that the several layers shown in the figures are illustrative only and that the number of layers is not limited to the three layers shown in the figures, and that many variations in the shape are possible. As shown in fig. 3, the third layer 306 has a boundary 308.

Referring to fig. 4, fig. 4 shows a schematic diagram of a cell bounding box of the standard cell shown in fig. 3. As shown in fig. 4, where the dashed line represents a cell bounding box 310 of a standard cell, which coincides with the boundary 308. Bounding boxes, as their name implies, represent the smallest bounding rectangular box that can enclose a unit (a unit can be understood as a chip). Typically expressed in terms of coordinates of the lower left and upper right corner vertices of the rectangular box, such as (x 1, y1; x2, y 2) where (x 1, y 1) is the coordinates of the lower left corner vertex of the rectangular box and (x 2, y 2) is the coordinates of the upper right corner vertex of the rectangular box.

Referring to fig. 5, fig. 5 illustrates a schematic diagram of a splice layer in a standard cell according to some embodiments of the present disclosure. The stitching layer 304 is a layer used for stitching adjacent standard cells in the standard cells, and is specifically denoted as layer 1:0 in the layout, as shown in fig. 4. The splice layer 304 may be used as a reference for splicing, i.e., to align or abut the boundaries of the splice layers of adjacent standard cells during splicing, thereby achieving splicing. The splice layer, like the other layers in the standard cell, is defined by two parameters, length and width. The splice layers in the individual standard cells are typically of the same height. However, in some cases the splice layers may have different heights, but the heights of the different splice layers may be in an integer multiple relationship. For example, one splice layer has a height of 20nm and the other splice layer has a height of 40nm. In this case, a splice layer having a height of 40nm may be spliced with two splice layers having a height of 20nm, and the splice layers may have the same height after splicing.

Referring to fig. 6, fig. 6 shows a schematic view of a layer bounding box of the splice layer shown in fig. 5. A layer bounding box refers to the smallest bounding rectangle that can enclose a layer. The representation is also in terms of coordinates of the vertices of the lower left and upper right corners of the rectangular box. The dashed box in fig. 6 represents layer bounding box 312 for layer 1:0.

The description continues back to fig. 2. In some embodiments, selecting an arrangement of standard cells from a standard cell library comprises: a first number of permutations of standard cells is selected from a library of standard cells, wherein each permutation includes a second number of standard cells arranged in a corresponding order.

In some embodiments, a first mode (referred to as mode one) may be employed to select standard cells from a standard cell library and splice. In the first mode, traversing the standard cell library to select each standard cell in the standard cell library to form a first number of arrangements each comprising one standard cell, wherein the first number is equal to the total number of standard cells in the standard cell library. In short, each standard cell in the standard cell library is arranged as a single unit. Assuming that the total number of standard cells in the standard cell library is N, there are N permutations, with only one standard cell in each permutation.

In some embodiments, a second mode (referred to as mode two) may be employed to select standard cells from a standard cell library and splice. In the second mode, two parameters can be specified by a user, one is the number n1 of the layout (or called layout, layout) and the other is the number n2 of the root units in the layout. The number of layouts is the number of layouts that the user wishes to generate. The root element is each standard element in an arrangement selected from a library of standard elements. The root element may be one or more. Assuming that the total number of cells contained in the library is N, the number of root cells N2 is less than or equal to N.

In mode two, all permutations of a second number of standard cells selected from the standard cell library can be determined based on the permutation and combination method, wherein the second number is at least two; and randomly selecting a first number of permutations from all permutations. Specifically, all the arrangements of N2 units are first calculated to be taken out of the N standard units, and then N1 arrangements are randomly selected from all the arrangements to be used as the arrangements of the root units of the N1 layouts. For example, for ease of understanding, assuming that there are 4 standard cells in the standard cell library (in practice, there are typically a large number of standard cells, e.g., hundreds, thousands, or tens of thousands), the user specifies that the number of layouts to be generated (i.e., the first number) n1 is 3 and the number of root cells in the layout n2 is 2. According to the arrangement and combination calculation mode, two standard units are selected from 4 standard units to be arranged, and the total arrangement modes are 12. From the 12 arrangements, 3 arrangements can thus be randomly selected as the arrangement of the root cells of the 3 layouts. If the first number is 12, all 12 arrangements are selected.

In some embodiments, a third mode (referred to as mode three) may be employed to select standard cells from a standard cell library and splice. In this mode, the first arrangement of the second number of standard cells from the standard cell library may be randomly selected based on the arrangement combination method, wherein the second number is equal to the total number of standard cells in the standard cell library. In other words, all standard cells in the standard cell library are randomly arranged and one (first number) of arrangements is selected from them. It should be understood that embodiments of the present disclosure are not limited thereto, and in mode three, a plurality of arrangements may be selected as needed, or all arrangements may be selected to splice. Wherein the number of selected arrangements is the first number. For example, 10 permutations are selected, the first number is 10. The more the selected arrangement is, the more comprehensive the splicing scene of the covered standard units is, so that the possible problems at the splicing position can be found as soon as possible.

At block 204, standard cells in each arrangement are spliced based on the boundaries of the respective splice layers, respectively, based on a predetermined rule, to form each base splice structure.

In some embodiments, for the mode one selection, the boundary of the splice layer (SPLICINGLAYER) of each standard cell in the arrangement is spliced with the boundary of the splice layer of the copy of each standard cell, respectively, to form the respective base splice structure. In some embodiments, the formed basic mosaic structure may be output as a layout for design rule checking.

In some embodiments, the basic splice structure described above may be further extended. Specifically, for each standard cell, this can be achieved by abutting itself and then flipping it. For example, the scheme of mode one can be set forth as the following steps.

Step 1: a standard unit is adjacent to the standard unit by taking a splicing layer as a reference to form a standard unit consisting of two standard units, and the standard unit is named as Cell1;

step 2: the Cell is formed by turning over the upper boundary of the stitching layer of Cell1 and then turning over the lower boundary of the stitching layer of Cell1, thus forming a Cell consisting of 6 units, designated as Cell2. For example, the basic splice structure is turned 180 degrees around the uppermost boundary of the splice layer of the basic splice structure as an axis to form an upper splice structure adjacent in the first direction (above) symmetrical to the basic splice structure; the basic splice structure is flipped 180 degrees about the lowermost boundary of the splice layer of the basic splice structure to form a lower splice structure adjacent (below) in a second direction opposite the first direction that is symmetrical to the basic splice structure.

Step 3: and turning over the left boundary of the Cell2 spliced layer as a reference, and turning over the right boundary of the Cell2 spliced layer as a reference. In other words, the basic splice structure is turned 180 degrees with the leftmost boundary of the splice layer of the basic splice structure as an axis to form a left splice structure adjacent in the third direction (left) symmetrical to the basic splice structure; and turning the basic splice structure 180 degrees around the rightmost boundary of the splice layer of the basic splice structure to form a right splice structure adjacent to the basic splice structure in a fourth direction (right direction) opposite to the third direction, which is symmetrical to the basic splice structure. Finally, a structure consisting of 18 units, designated Cell3, is obtained, as shown in FIG. 7.

Referring to fig. 7, fig. 7 illustrates a schematic diagram of a layout formed by standard cell stitching in accordance with some embodiments of the present disclosure. The graph is the result of the first layout, which is referred to herein as a layout (or layout).

The first standard cell R1 and the second standard cell R2 shown in fig. 7 are two root cells, i.e., two standard cells that are initially spliced. The basic splicing structure formed by the two root units is used for overturning in the upper direction, the lower direction, the left direction and the right direction, so that the splicing structure shown in fig. 7 is formed.

It should be understood that the above-described splicing manner described with respect to fig. 7 is merely illustrative, and embodiments of the present disclosure are not limited thereto. For example, in some embodiments, a basic splice structure of two root elements may be flipped up only, flipped down only, flipped left only, or flipped right only. In addition, further overturning and splicing can be performed according to the requirement. For example, after the flip splice, the flip splice may continue.

Step 4: switching to the next group of arrangement, and repeating the steps 1-3 until all the units are placed.

In some embodiments, for example, for the second mode, after determining a selection manner of all arrangements for selecting the second number of standard cells from the standard cell library based on the arrangement combination method, the second number of standard cells in each arrangement may be sequentially spliced according to the order of the standard cells in the arrangement based on the boundary of each splicing layer, so as to form each basic splicing structure. In other words, the root cells may be adjacent to each other with respect to the splice layer in the order in which they are arranged. And then the basic splicing structure can be turned up and down and left and right according to the requirement, namely the basic splicing structure is turned over 180 degrees by taking the uppermost, lower, left and right side boundaries of the splicing layer of the basic splicing structure as axes, so that the splicing structure which is symmetrical with the basic splicing structure and is adjacent to the basic splicing structure in four directions is formed, and the detailed description of the specific mode is omitted. The resulting splice structure can thus be output as a layout for subsequent DRC checks.

Specifically, the scheme of mode two can be set forth as the following steps.

Step 1: all the arrangements of N2 units are calculated and taken out of the N units, and then N1 (or N1) arrangements are randomly selected from all the arrangements to be used as the arrangements of the root units of the N1 layouts.

Step 2: corresponding units are adjacent together based on the splicing layer according to the sequence of the units in the first arrangement to form a unit (or called a splicing structure) consisting of n2 units, which is named as Cell1.

Step 3: step 2 of the same mode one.

Step 4: step 3 of the same mode one.

Fig. 8 shows a schematic diagram of a typesetting result of mode two. Referring now to fig. 8, as shown in fig. 8, the first standard cell R1 and the second standard cell R2 are root cells. Both flipped along the upper boundary 311 of their splice layer, flipped along the lower boundary 313 of their splice layer, flipped along the left boundary 317 of their splice layer, flipped along the right boundary 319 of their splice layer, whereby a layout comprising 16 cells as shown in fig. 8 can be formed.

Step 5: switching to the next arrangement, and repeating the steps 2-4.

From the above description, the difference between the second mode and the first mode is that the standard cell is selected in different ways and the object to be spliced is different. In mode one, each standard cell is spliced with itself (or a copy of itself). The method can be considered that each standard cell is selected twice from the standard cell library, and then is spliced; alternatively, it may be considered that after one standard cell is selected from the standard cell library, the standard cell is duplicated to form a copy, and then the two are spliced. In mode two, different standard cells in an arrangement are spliced. And the subsequent overturning and splicing processes can adopt the same mode.

The description proceeds back to block 204 of fig. 2. In some embodiments, in mode three, stitching may be performed as follows: sequentially splicing standard units in the first arrangement in a first row or a first column according to the sequence of the standard units in the first arrangement and by taking the boundary of each splicing layer as a reference; continuing the stitching in a second row or column adjacent to the first row or column, in the event that the number of standard cells stitched reaches a predetermined threshold in the first row or column; and repeating the splicing in each row or column until the splicing of all standard cells in the first arrangement is completed, so as to form a corresponding layout.

In some embodiments, for each standard cell to be spliced in an even row or even column, the splicing is performed sequentially after the standard cell is flipped in a direction perpendicular to the row or column. For example, when standard cells are spliced along the second row, the standard cells are taken out of the standard cell library, turned over, and then put into the second row for splicing. In this way, more contiguous scenes can be formed, helping to find more stitching problems.

In mode three, the user is required to specify a parameter: the number of cells per row, n. Let the number of cells contained in the library be N. The typesetting principle of mode three can be summarized as: all units in the library are arranged randomly, the arrangement (one or more arrangements) is selected randomly, then the units in the arrangement are adjacent or spliced based on the splicing layer one by one according to the sequence of the units in the selected arrangement, when the number of the spliced units exceeds n, one row is started up, the second row and the first row are adjacent up and down based on the splicing layer, the first units of each row are aligned left and right based on the splicing layer, and even rows are required to be turned up and down. And after all the units are placed, forming a final layout.

Specifically, the scheme of mode three can be set forth as the following steps.

Step 1: all cells in the library are arranged randomly.

Step 2: and the units in the arrangement are sequentially abutted or spliced according to the sequence of the units in each arrangement.

Step 3: when the number of the arranged rows exceeds n, the method of repeating the step 2 is arranged on the upper surface of the first row by taking the splicing layer as a reference, and the first row is aligned left by taking the splicing layer as a reference (the even rows need to be turned up and down).

Step 4: and repeating the steps 2-3 until all the placement is completed, and forming a layout. The layout after placement is shown in fig. 10.

In the embodiment herein, the description is given taking an example of selecting one arrangement from all arrangements and performing stitching, and the embodiment of the disclosure is not limited thereto, and as mentioned in the foregoing description, in the third mode, a plurality of arrangements may be selected, or all arrangements may be selected to perform stitching as required. The more the selected arrangement is, the more comprehensive the splicing scene of the covered standard units is, so that the possible problems at the splicing position can be found as soon as possible. The above description has been made taking the example of row arrangement, but it is obvious that the arrangement may be made in columns.

In some embodiments, where all permutations are selected for stitching, the following operations may continue: selecting a second number of standard cells from the standard cell library to form other arrangements except the first arrangement; respectively splicing standard units in other arrangements in a row-by-row or column-by-column splicing mode until the splicing of the standard units in all other arrangements is completed, so as to form each basic splicing structure; and the layout comprising each basic splicing structure is used as each corresponding layout.

Further description is provided below with reference to fig. 9 and 10. FIG. 9 illustrates a schematic diagram of a standard cell according to some embodiments of the present disclosure; fig. 10 shows a schematic diagram of a layout spliced from standard cells shown in fig. 9.

As shown in fig. 9, seven standard cells are shown, and cell borders are shown at the boundaries of each standard cell, and a splice layer is disposed in each border. Fig. 10 shows a layout formed by stitching the standard cells shown in fig. 9 according to pattern three. The lowermost row in fig. 10 may be referred to as a first row, and the middle row may be referred to as a second row. The second row is an even number of rows, each standard cell in the row being flipped after being removed from the standard cell library and then spliced to the standard cells in the first row, as is apparent from a comparison with fig. 9, for example, the standard cell labeled letter a therein, in which the orientation of letter a has been flipped in fig. 10.

The above embodiments describe the manner in which standard cells are spliced. In practice, the standard cells are typically set in separate files in a standard cell library, where each separate file is marked with information such as the original bounding box coordinates of the standard cell and the original bounding box coordinates of the splice layer. And in the process of splicing the standard units, the position coordinates of each standard unit are calculated in actual need, and the accurate splicing process of the spliced layer is realized based on the calculated coordinates.

In some embodiments, the following splicing may be performed on standard cells in each arrangement based on the boundary of the splicing layer based on a predetermined rule: determining an offset based on given coordinates of a stitching layer of the first standard cell initially placed in a current coordinate system and original bounding box coordinates of the stitching layer; determining coordinates of a bounding box of the first standard cell based on the offset; and determining the boundary frame coordinates of each standard cell to be spliced subsequently based on the position relation between the other standard cells and the first standard cell and the size of each standard cell so as to splice each standard cell to be spliced subsequently. For a specific calculation, reference may be made to the following description of fig. 11A, 11B and 12.

In some embodiments, the second number of standard cells in each permutation is referred to as a root cell, which is spliced in one or a combination of the following ways: splicing each root unit in an extending manner along a first direction, wherein the boundary of the spliced layer of each root unit has the same or integral multiple size along a second direction perpendicular to the first direction; and splicing the individual root units extending in the second direction.

Furthermore, in some embodiments of the present disclosure, a splice may also be performed using mode four. The fourth mode is a combination of the first mode and the second mode, namely, the layout formed by the two modes is placed in a gds or oas file so as to be convenient for reference. Through the mode, a user can see two layouts by opening one file, and the two layouts can be separated by a preset interval.

At block 206, a corresponding layout is generated based on each of the base stitch structures, respectively.

In some embodiments, the layout including the base splice structure generated at block 204 may be individually taken as the final layout, from which it is output for subsequent DRC checks.

In some embodiments, each layout including a base mosaic, an upper mosaic, a lower mosaic, a left mosaic, and a right mosaic may be taken as a corresponding layout and output for subsequent DRC checks.

In some of the above embodiments, several modes of splicing standard cells are described, wherein the placement principles of modes one, two and four are similar, except that the sampling is different. The second mode is to take n2 different random permutations (exactly the "gds file name different" permutations). Although the file names are different, the units inside may be the same. While pattern one may be considered to take 2 identical permutations.

The term "pose" in all descriptions herein is in fact the process of calculating the coordinates of a unit in an algorithm, and is merely a matter of convenience and is analogous to a pose action. To complete the placing action, the coordinates of the cell need to be calculated. For convenience of description, the coordinate algorithm of the mode one, the mode two and the mode four is named as an a algorithm, and the coordinate algorithm of the mode three is named as a B algorithm. Unless otherwise specified below, the coordinates of the cells are represented using the lower left corner vertex coordinates of the cell bounding box (cellbbox).

The flow chart of the algorithm a is described below in conjunction with fig. 11A and 11B. 11A and 11B (the combination of which is a complete flowchart, both of which are shown as being longer), illustrate an algorithm flow diagram for generating a layout according to some embodiments of the present disclosure. In the figure, abutcoorx is used for recording the x-coordinate of the layout root unit (rootcell) to be placed next, and originy is used for recording the y-coordinate of the layout root unit to be placed next; layoutrightx is used to record the x-coordinate of the right boundary of the widest layout (useful only in pattern four), layoutspacey is a user configured parameter representing the spacing between two different layouts (typically, for ease of reference, the layout after the placement of the different arrangements will be placed in one Topcell).

First, the parameters shown below are described. The following parameters are all data of the units in the original gds file.

Ayerbbox [0] represents the x-coordinate of the left lower corner vertex of the bounding box (boundingbox) of a layer (referred to as a stitching layer in the scheme of the present disclosure);

layerbbox [1] represents the y-coordinate of the left lower corner vertex of the bounding box of a certain layer (referred to as a stitching layer in the scheme of the present disclosure);

layerbbox [2] represents the x-coordinate of the top right corner vertex of the bounding box of a layer (referred to as the stitching layer in the scheme of the present disclosure);

layerbbox [3] represents the y-coordinate of the top right corner vertex of the bounding box of a certain layer (referred to as the stitching layer in the scheme of the present disclosure);

cellbbox [0] represents the x-coordinate of the left lower corner vertex of the bounding box of the whole cell (consisting of multiple layers);

cellbbox [1] represents the y-coordinate of the left lower corner vertex of the bounding box of the whole cell (consisting of multiple layers);

cellbbox [2] represents the x-coordinate of the top right corner vertex of the bounding box of the whole cell (consisting of multiple layers);

cellbbox [3] represents the y-coordinate of the top right corner vertex of the bounding box of the whole cell (consisting of multiple layers);

It should be noted that the coordinates are generic, either in the original gds or in the current layout.

As shown in fig. 11A, at block 1102, a set of standard cell arrangements is input. Assuming that M (M is a positive integer) groups are arranged, the user-configured start coordinates are (x 0, y 0). When standard cells are placed, the lower left corner of the splice layer of the first standard cell is placed at coordinates (x 0, y 0). It should be appreciated that other placement modes may be selected according to actual needs, for example, placing the upper right corner of the splice layer of the first standard cell, or the coordinates of the lower left corner or the upper right corner of the bounding box of the first standard cell, to the coordinates (x 0, y 0). At block 1104, all permutations in the set are traversed and all cells in each permutation are traversed, and the maximum width of the stitching layer, denoted as W, is calculated when the cells are adjacent together. This width can be used to determine the x-coordinate of the right boundary of the widest layout in pattern four.

At block 1106, the permutations in the set are traversed starting from group m (m is initially 1), note abutcoorx =x0, originy =y0 when m=1. That is, the x coordinate of the bottom left corner of the first layout root cell splicing layer to be placed is x0, and the y coordinate is y0.

At block 1108, the height of the splice layer is determined in the permutation is traversed. The height is typically h. Furthermore, the width w of the spliced layers after the units are spliced together is calculated.

At block 1110, the permutation is traversed again. Assume that there are N cells in total in the standard cell library.

At block 1112, the lower left corner of the splice layer of cell number n (initial n=1) is placed at (abutcoorx, originy). It can be determined that the cell has an offset in the x-direction of xshift = layerbbox [0] -x0 and an offset in the y-direction of yshift = layerbbox [1] -y0. The coordinates of the standard cell after placement (i.e., the coordinates of the bounding box of the cell) are (cellbbox [0] -xshift, cellbbox [1] -yshift), and for ease of description, the placed cell number 1 is denoted as cell0.

At block 1114, cell0 is flipped over with the upper boundary of the splice layer as the axis, and the coordinates of the flipped cell are determined to be (cellbbox [0] -xshift, - (cellbbox [3] -layerbbox [1 ]) +2H+y0), which is designated as cell1.

At block 1116, cell0 is flipped around the lower boundary of the splice layer, and the coordinates of the flipped cell are determined to be (cellbbox [0] -xshift, - (cellbbox [3] -layerbbox [1 ]) + originy), which is denoted as cell2.

At block 1118, cell1 is flipped around x=x0, and the coordinates of the flipped cell are determined to be (x0- ((cellbbox [2] -layerbbox [0 ]) + abutcoorx-x 0), - (cellbbox [3] -layerbbox [1 ]) +2h+y0）。

At block 1120, cell0 is flipped around x=x0, and the coordinates of the flipped cell are determined to be (x0- ((cellbbox [2] -layerbbox [0 ]) + abutcoorx-x 0), cellbbox [1] -yshift).

At block 1122, cell2 is flipped about x=x0, and the coordinates of the flipped cell are determined to be (x 0- ((cellbbox [2] -layerbbox [0 ]) + abutcoorx-x 0), - (cellbbox [3] -layerbbox [1 ]) +y0).

At block 1124, cell1 is flipped about x=w, and the coordinates of the flipped Cell are determined to be (2x0+2w+xshift-cellbbox[2]，-(cellbbox[3]-layerbbox[1])+2h+y0）。

At block 1126, cell0 is flipped with x=w as the axis, and the coordinates of the flipped cell are determined to be (2x0+2w+xshift-cellbbox[2]，cellbbox[1]-yshift）。

At block 1128, cell2 is flipped with x=w as the axis, and the coordinates of the flipped cell are determined to be (2x0+2w+xshift-cellbbox[2]，-(cellbbox[3]-layerbbox[1])+y0）。

At block 1130, abutcoorx is updated, i.e., abutcoorx = abutcoorx + layerbbox [2] -layerbbox [0].

At block 1132, a determination is made as to whether the current standard cell is the last in the arrangement? If yes, go to block 1134, otherwise go to block 1138.

At block 1134, the largest layoutrightx =2 is recordedabutcoorx+layerbbox[0]-cellbbox[0]。

At block 1136, originy is updated, i.e., originy = originy +2h+layoutspacey。

At block 1138, let n=n+1, i.e., start stitching the next standard cell.

At block 1140, let m=m+1, i.e., start stitching the standard cells in the next set of permutations.

The flow of algorithm a is described above in connection with fig. 11A and 11B. It should be noted that after the initial conditions and the arrangement mode of each unit are determined, the coordinates of each unit are calculated according to a conventional mathematical method.

11A and 11B illustrate algorithmic implementation flows of layout generation schemes, particularly mode one, mode two, and mode four, of some embodiments of the present disclosure, it being understood that embodiments of the present disclosure are not limited thereto, but may be variously modified as desired.

FIG. 12 illustrates an algorithm flow diagram for generating a layout according to further embodiments of the present disclosure. In principle, the mode three has fewer changes in placement, for example, the mode three can be flipped up and down only in even rows, so the B algorithm is simpler as shown in fig. 12.

At block 1202, a random full permutation is performed on all cells at once. Assuming that the total number of units is N, the user configures a starting position of (x 0, y 0), and designates the number of units placed per row as m.

At block 1204, after traversing the full permutation, put starting with element number n=1, when n=1, note x=x0, y=y0.

At block 1206, it is determined whether the current line is an odd line? If so, go to block 1208, otherwise go to block 1210.

At block 1208, the lower left corner of the splice layer of n-th cells is placed at (x, y), the offset of cells in the x-direction is determined to be xshift = layerbbox [0] -x0, the offset in the y-direction is yshift = layerbbox [1] -y0, and the coordinates of the placed cells are (cellbbox [0] -xshift, cellbbox [1] -yshift).

At block 1210, the n-th cell is flipped vertically, the lower left corner of the flipped n-th cell splice layer is placed at (x, y), the cell offset in the x-direction is determined to be xshift = layerbbox [0] -x0, the cell offset in the y-direction is yshift = -layerbbox [3] -y0, and the placed cell coordinates are (cellbbox [0] -xshift, -cellbbox [3] -yshift).

At block 1212, x is updated, i.e., let x=x+ layerbbox [2] -layerbbox [0].

At block 1214, it is determined whether the number of cells placed in the current row exceeds m? If so, go to block 1216, otherwise go to block 1218.

At block 1216, x and y are updated, i.e., let x=x0; y=y+ layerbbox [3] -layerbbox [1].

At block 1218, n=n+1, i.e., the next standard cell begins to be spliced.

Furthermore, as mentioned previously, for mode three, it is also possible to splice a plurality of arrangements therein, not limited to splice for only units in one of the arrangements.

FIG. 13 illustrates an algorithm flow diagram for generating a layout based on various patterns according to some embodiments of the present disclosure. In other words, FIG. 13 is a generalized overview of the method of the four modes previously mentioned.

At block 1302, the user may specify a folder gdsdir in which the gds file is located, a stitching layer, a number of units per row n, a resulting layout number m, a distance between the layouts in the x-direction and a distance between the layouts in the y-direction, and one of mode one, mode two, mode three, and mode four, among others.

At block 1304, all gds files may be parsed using a self-lapping tool (a piece of software) to obtain all units, which total N.

At block 1306, all cells are traversed, each cell being grouped with itself into a set of permutations. An a algorithm is then implemented at block 1314 to determine the location coordinates of each standard cell.

At block 1308, all permutations of the N cells from the N cells are computed and the m sets of permutations are randomly selected. For example, all permutations that extract two standard cells from 3 standard cells are calculated as 6 groups, from which 2 groups are randomly extracted. An a algorithm is then implemented at block 1316 to determine the location coordinates of each standard cell.

At block 1310, all cells in the cell library are traversed, and then at block 1318 a B algorithm is implemented to determine the location coordinates of each standard cell.

At block 1312, all permutations of the N cells are computed, taken from the N cells, and the m sets of permutations are randomly selected.

Then, at block 1320, an A algorithm is performed to determine the position coordinates of each standard cell.

At block 1322, all cells are traversed, grouping each cell with itself.

At block 1324, an A algorithm is performed to determine the position coordinates of each standard cell. As can be seen from this flow chart, mode four is a combination of mode one and mode two.

At block 1326, data is input to the self-grinding tool to generate resulting gds files, i.e., the coordinates of the foregoing calculations are input to corresponding software to generate layouts, one gds file for each layout, or in the case of pattern four, two separate layouts.

According to aspects of some embodiments of the present disclosure, parameters that a user may need to configure may include:

"inputgdspath (input gds path)"/… … ";

"outputgdspath (output gds path)"/… … ";

"outputtopcell (output top level cell)" "top";

"recognitionlayer (splice layer)" "197:41";

"cellcountinrow (number of cells in each row)": 3;

"rowcount (number of lines)": 2,

"Layoutspacey (layout pitch in y-direction)";

"layoutspacex (layout pitch in x-direction)";

"layoutmode (layout mode)": 3;

further, the above-mentioned flipping operation may be achieved by referring to the same unit, then adding a rotation angle, and performing mirroring.

In the above-mentioned flowchart, for ease of description, the splice layers of the respective standard cells have the same height h as an example. However, as previously mentioned, embodiments of the present disclosure are not limited thereto, and the individual splice layers may have different heights, for example, heights that are integer multiples.

As is known, overlap is allowed between individual standard cells. The splice is not without any rules to connect two standard cells together, and requires alignment of certain patterns (patterns) in the gds. The splicing layer is equivalent to a marker, and the splicing layer is used for splicing, so that no problem on the alignment of patterns can be ensured.

Some embodiments of the present disclosure provide a layout generation method, and the generated layout can be used for subsequent design rule checking. Alternatively stated, embodiments of the present disclosure provide a method of generating a layout for design rule checking.

It should be noted that the examples set forth in the above embodiments are only for the purpose of illustrating the aspects of the embodiments of the present disclosure, and are not intended to limit the aspects of the present disclosure.

Aspects of some embodiments of the present disclosure provide for maximum coverage of adjacent or posed scenes in an actual layout through various different modes of placement, and then inspecting places that may violate DRCs or shorts (shortcuts) through corresponding DRC inspection tools. It should be understood that various modes may be changed, and the present disclosure is not limited thereto.

According to the scheme of some embodiments of the present disclosure, enough splicing scenes can be simulated, so as to discover and avoid design rule violation caused by random splicing in advance, greatly improve efficiency, and remarkably improve subsequent layout generation quality.

It should be understood that the embodiments shown in the drawings are merely for purposes of illustrating schematically the aspects of some embodiments of the disclosure and are not intended to limit the disclosure. Embodiments of the present disclosure may also have various other forms.

An electronic device is also disclosed in the embodiments of the present disclosure. The electronic device includes: a processor; and a memory coupled to the processor, the memory having instructions stored therein that, when executed by the processor, cause the device to perform actions comprising: selecting standard cell arrangements from a standard cell library, wherein each arrangement comprises standard cells arranged according to a corresponding sequence; based on a preset rule, splicing standard units in each arrangement by taking the boundary of each splicing layer as a reference to form each basic splicing structure; and generating corresponding layouts based on the basic splicing structures respectively.

Also disclosed in embodiments of the present disclosure is a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a layout generation method according to embodiments of the present disclosure.

According to the scheme of the embodiment of the disclosure, time and labor cost are remarkably saved through automatic splicing, a more complete splicing scene can be covered, more potential defects are found, and therefore the quality of a layout of a subsequent design can be improved.

Fig. 14 illustrates a schematic block diagram of an electronic device, according to some example embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 14, the apparatus 1400 includes a CPU1401 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 1402 or a computer program loaded from a storage unit 1408 into a Random Access Memory (RAM) 1403. In the RAM1403, various programs and data required for the operation of the device 1400 can also be stored. The CPU1401, ROM1402, and RAM1403 are connected to each other through a bus 1404. An input/output (I/O) interface 1405 is also connected to the bus 1404.

A number of components in device 1400 are connected to I/O interface 1405, including: an input unit 1406 such as a keyboard, a mouse, or the like; an output unit 1407 such as various types of displays, speakers, and the like; a storage unit 1408 such as a magnetic disk, an optical disk, or the like; and a communication unit 1409 such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 1409 allows the device 1400 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunications networks.

Various of the procedures and processes described above, such as method 400, may be performed by CPU 1401. For example, in some embodiments, the method 400 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 1408. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 1400 via the ROM1402 and/or the communication unit 1409. When a computer program is loaded into RAM1403 and executed by CPU1401, one or more steps of method 400 described above may be performed.

Aspects in accordance with embodiments of the present disclosure may be methods, apparatus, systems, and/or computer program products. The computer program product may include a computer readable storage medium having computer readable program instructions embodied thereon for performing aspects of the present disclosure. The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable program instructions may be downloaded from a computer readable storage medium to the respective computing/processing device or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network.

The various embodiments of the present disclosure have been described above, and the above description is exemplary only of alternative embodiments of the present disclosure, and is not intended to be exhaustive or to limit the present disclosure. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same in any claim as presently claimed. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. Various modifications and alterations of this disclosure will become apparent to those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. that fall within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A layout generation method, comprising:

selecting an arrangement of standard units from a standard unit library, wherein each arrangement comprises standard units arranged according to a corresponding sequence;

Based on a preset rule, splicing the standard units in each arrangement by taking the boundary of each splicing layer as a reference to form each basic splicing structure; and

And generating corresponding layouts based on the basic splicing structures respectively.

2. The method of claim 1, wherein selecting an arrangement of standard cells from a library of standard cells comprises:

a first number of permutations of the standard cells are selected from the standard cell library, wherein each permutation includes a second number of the standard cells arranged in a corresponding order.

3. The method of claim 2, wherein selecting a first number of permutations of standard cells from the standard cell library comprises:

Traversing the standard cell library to select each standard cell in the standard cell library separately to form the first number of permutations each comprising one standard cell, wherein the first number is equal to the total number of standard cells in the standard cell library.

4. A method according to claim 3, wherein stitching the standard cells in each of the permutations based on a predetermined rule, respectively, against the boundary of the stitching layer comprises:

And splicing the boundary of the splicing layer of each standard unit in the arrangement with the boundary of the splicing layer of the copy of each standard unit respectively to form each basic splicing structure.

5. The method of claim 2, wherein selecting the first number of permutations of standard cells from the standard cell library comprises:

Determining all permutations of the second number of standard cells selected from the standard cell library based on a permutation and combination method, wherein the second number is at least two; and

Randomly selecting the first number of permutations from the all permutations.

6. The method of claim 5, wherein stitching the standard cells in each of the permutations based on a predetermined rule, respectively, with respect to a boundary of a stitching layer comprises:

and splicing the second number of standard units in each arrangement according to the sequence of the standard units in the arrangement and taking the boundary of each splicing layer as a reference, so as to form each basic splicing structure.

7. The method of claim 5 or 6, wherein stitching the standard cells in each of the permutations, based on a predetermined rule, with respect to the boundaries of the stitching layer, respectively, further comprises performing the following operations on the standard cells in each permutation:

Turning over the basic splicing structure by 180 degrees by taking the uppermost boundary of the splicing layer of the basic splicing structure as an axis so as to form an upper splicing structure adjacent to the basic splicing structure in a first direction, wherein the upper splicing structure is symmetrical to the basic splicing structure;

turning over the basic splicing structure by 180 degrees by taking the lowest boundary of the splicing layer of the basic splicing structure as an axis to form a lower splicing structure which is symmetrical to the basic splicing structure and is adjacent to the basic splicing structure in a second direction opposite to the first direction;

Turning over the basic splicing structure by 180 degrees by taking the leftmost boundary of the splicing layer of the basic splicing structure as an axis so as to form a left splicing structure which is symmetrical with the basic splicing structure and is adjacent to the basic splicing structure in a third direction; and

And turning the basic splicing structure by 180 degrees by taking the rightmost boundary of the splicing layer of the basic splicing structure as an axis so as to form a right splicing structure which is symmetrical to the basic splicing structure and is adjacent to the basic splicing structure in a fourth direction opposite to the third direction.

8. The method of claim 7, wherein generating respective layouts based on the respective base stitch structures comprises:

And respectively taking each layout comprising the basic splicing structure, the upper splicing structure, the lower splicing structure, the left splicing structure and the right splicing structure as the corresponding layout.

9. The method of claim 2, wherein selecting the first number of permutations of standard cells from the standard cell library comprises:

A first permutation of the second number of standard cells is randomly selected from the standard cell library based on a permutation and combination method, wherein the second number is equal to a total number of standard cells in the standard cell library.

10. The method of claim 9, wherein stitching the standard cells in each of the permutations based on a predetermined rule, respectively, against a boundary of a stitching layer comprises performing a row-by-row or column-by-column stitching mode of:

Sequentially splicing standard units in the first arrangement in a first row or a first column according to the sequence of the standard units in the first arrangement and by taking the boundary of each splicing layer as a reference;

Continuing stitching in a second row or column adjacent to the first row or column in response to the number of standard cells stitched reaching a predetermined threshold in the first row or column; and

And repeating the splicing in each row or column until the splicing of all standard cells in the first arrangement is completed, so as to form the corresponding layout.

11. The method according to claim 10, wherein:

For each standard cell to be spliced in even rows or even columns, the standard cells are sequentially spliced after being flipped in a direction perpendicular to the rows or columns.

12. The method of claim 10 or 11, further comprising:

Selecting the second number of standard cells from the standard cell library to form other arrangements except the first arrangement;

Respectively splicing the standard units in the other arrangements in the row-by-row or column-by-column splicing mode until the standard units in all the other arrangements are spliced to form the basic splicing structures; and

And respectively taking the layout comprising each basic splicing structure as each corresponding layout.

13. The method of claim 2, wherein each of the standard cells is respectively arranged in a respective independent file in the standard cell library, each independent file being marked with the original bounding box coordinates of each of the standard cells and the original bounding box coordinates of the stitching layer; wherein splicing the standard units in each of the arrangements based on a predetermined rule with respect to the boundary of the splicing layer includes:

Determining an offset based on a given coordinate of a stitching layer of an initially placed first standard cell in a current coordinate system and an original bounding box coordinate of the stitching layer;

Determining coordinates of a bounding box of the first standard cell based on the offset; and

And determining the boundary frame coordinates of each standard cell spliced subsequently based on the position relation between other standard cells and the first standard cell and the size of each standard cell so as to splice each standard cell subsequently.

14. The method of claim 2, wherein the second number of standard cells in each permutation is referred to as a root cell, the root cells being spliced in one or a combination of the following ways:

Splicing each root unit in an extending manner along a first direction, wherein the boundary of the spliced layer of each root unit has the same or integral multiple of the size along a second direction perpendicular to the first direction; and

Each root unit is spliced to extend along the second direction.

15. The method of claim 14, wherein, with boundaries of the splice layers of the individual standard cells having dimensions that are integer multiples along the second direction, the splice is performed in the following manner:

Splicing the standard units with the integral multiple number in the second direction to form a first splicing structure; and

And splicing the first splicing structure with a corresponding standard unit in the first direction to form the basic splicing structure with aligned splicing layer boundaries.

16. An electronic device, comprising:

A processor; and

A memory coupled to the processor, the memory having instructions stored therein that, when executed by the processor, cause the device to perform actions comprising:

Splicing the standard units in each arrangement based on a preset rule by taking the boundary of each splicing layer as a reference so as to form each basic splicing structure; and

17. A computer readable storage medium having stored thereon machine executable instructions which when executed by a processor cause the processor to implement the method of any one of claims 1 to 15.