CN118398640A - Backside illuminated image sensor and preparation method thereof - Google Patents
Backside illuminated image sensor and preparation method thereof Download PDFInfo
- Publication number
- CN118398640A CN118398640A CN202410841990.5A CN202410841990A CN118398640A CN 118398640 A CN118398640 A CN 118398640A CN 202410841990 A CN202410841990 A CN 202410841990A CN 118398640 A CN118398640 A CN 118398640A
- Authority
- CN
- China
- Prior art keywords
- semiconductor material
- material layer
- layer
- deep trench
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 239000000463 material Substances 0.000 claims abstract description 240
- 239000004065 semiconductor Substances 0.000 claims abstract description 229
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims description 107
- 239000002184 metal Substances 0.000 claims description 107
- 238000000034 method Methods 0.000 claims description 39
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 21
- 239000000945 filler Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 16
- 238000002955 isolation Methods 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000005137 deposition process Methods 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 239000007790 solid phase Substances 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- FAWGZAFXDJGWBB-UHFFFAOYSA-N antimony(3+) Chemical compound [Sb+3] FAWGZAFXDJGWBB-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 4
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 266
- 238000010586 diagram Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- -1 boron ion Chemical class 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention provides a backside illuminated image sensor and a preparation method thereof, wherein the backside illuminated image sensor comprises a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer which are sequentially arranged on a substrate, wherein a first deep trench structure is arranged in the third semiconductor material layer, the second semiconductor material layer and the first semiconductor material layer, a second deep trench structure is arranged in the third semiconductor material layer and the second semiconductor material layer, each first deep trench structure and one second deep trench structure are adjacently arranged, a pixel unit is formed between the adjacent first deep trench structure and the second deep trench structure, a laminated grid structure is formed on the pixel unit, tetravalent elements are doped in the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer, and the atomic weight of the tetravalent elements doped in the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer is sequentially reduced from bottom to top, so that the problem of interference effect caused by the pixel unit formed by ion implantation in the prior art can be solved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a back-illuminated image sensor and a preparation method thereof.
Background
An image sensor refers to a device that converts an optical image into a pixel signal output. Image sensors include Charge Coupled Devices (CCDs) and Complementary Metal Oxide Semiconductor (CMOS) image sensors. CMOS image sensors are generally classified into front-illuminated (FSI) image sensors and back-illuminated (BSI) image sensors. The back-illuminated image sensor has the photosensitive layer element (such as micro lens and photodiode) set on the back side of the substrate and allows light to enter through the back side and be detected by the photodiode, and the light ray does not need to pass through the wiring layer, so that the influence of the circuit and transistor between the micro lens and photodiode on the light ray in the front-illuminated image sensor structure is avoided, the light efficiency is obviously improved, the photosensitive effect of the image sensor under low illumination condition is greatly improved, and the sensitivity is higher than that of the front-illuminated image sensor.
In the advanced process of the back-illuminated image sensor, since an example implantation process using high energy is required to form a Photodiode (PD), damage is caused to a substrate, and an undesirable effect of a cross talk (cross talk) occurs when a light source is incident.
Disclosure of Invention
The invention aims to provide a back-illuminated image sensor and a preparation method thereof, which can reduce interference effects.
In order to solve the above problems, the present invention provides a backside illuminated image sensor, comprising a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer sequentially disposed on one side of a substrate, wherein a first deep trench structure is disposed in the third semiconductor material layer, the second semiconductor material layer and the first semiconductor material layer, a second deep trench structure is disposed in the third semiconductor material layer and the second semiconductor material layer, each of the first deep trench structure and the second deep trench structure is disposed adjacently, and the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer between the first deep trench structure and the second deep trench structure are adjacent to each other to form a pixel unit, the pixel unit is formed with a stacked grid structure thereon,
Wherein the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer are doped with tetravalent elements, and the atomic weight of the doped tetravalent elements is reduced from bottom to top.
Optionally, the first semiconductor material layer is doped with antimony element, the second semiconductor material layer is doped with arsenic element, and the third semiconductor material layer is doped with phosphorus element.
Optionally, the fillers in the first deep trench structure and the second deep trench structure are silicon dioxide, and the edges of the first deep trench structure and the second deep trench structure are doped with a first metal and a second metal, and the first metal is located on the outer side of the second metal, wherein the element weight of the first metal is larger than that of the second metal.
Optionally, the laminated grating structure sequentially includes a barrier layer, a first metal layer and a second metal layer from bottom to top, the material of the barrier layer is HFO 2, the material of the first metal layer is aluminum, and the material of the second metal layer is tantalum nitride.
In another aspect, the present invention provides a method for preparing a backside-illuminated image sensor, where the preparing of the backside-illuminated image sensor includes the following steps:
Sequentially forming a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer on one side of a substrate, wherein tetravalent elements are doped in the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer, and the atomic weight of the doped tetravalent elements is sequentially reduced from bottom to top;
Sequentially etching the third semiconductor material layer, the second semiconductor material layer and the first semiconductor material layer to form a first deep trench structure, and simultaneously sequentially etching the third semiconductor material layer and the second semiconductor material layer to form a second deep trench structure; wherein each first deep trench structure and one second deep trench structure are adjacently arranged, and a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer between the adjacent first deep trench structure and the adjacent second deep trench structure form a pixel unit;
and forming a laminated grid structure on the pixel unit.
Optionally, the method for forming the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer specifically includes:
Providing a substrate, wherein the substrate comprises a front surface and a back surface which are oppositely arranged, and shallow trench isolation structures which are arranged at intervals are formed on the front surface;
performing N-type ion implantation on the shallow trench isolation structure from the front surface by adopting a blanket ion implantation process so as to form a stop layer on one side of the shallow trench isolation structure close to the back surface;
thinning the substrate from the back surface by a chemical mechanical polishing process and polishing stopping on the stop layer;
and sequentially forming a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer on the stop layer by adopting solid-phase diffusion.
Further, antimony is doped in the first semiconductor material layer, arsenic is doped in the second semiconductor material layer, and phosphorus is doped in the third semiconductor material layer.
Further, the method for forming the pixel unit specifically comprises the following steps:
Sequentially forming a buffer layer and a hard mask layer on the third semiconductor material layer through a deposition process;
Sequentially etching the hard mask layer and the buffer layer through an etching process to form a first opening and a second opening, wherein the buffer layer is arranged outside the first opening, the buffer layer and the hard mask layer which are stacked are arranged outside the second opening, and each first opening is adjacent to one second opening;
forming a first deep trench at the first opening and forming a second deep trench at the second opening by adopting a dry etching process, wherein the first deep trench sequentially penetrates through the third semiconductor material layer, the second semiconductor material layer, the first semiconductor material layer and the stop layer from top to bottom so as to expose the bottom of the shallow trench isolation structure, the second deep trench sequentially penetrates through the third semiconductor material layer and the second semiconductor material layer from top to bottom, and each second deep trench structure is opposite to one shallow trench isolation structure;
removing the hard mask layer;
depositing a filler in the first deep trench and the second deep trench, the filler also covering the buffer layer;
And removing the filler on the buffer layer through a chemical mechanical polishing process, and performing a spike annealing process in an oxygen atmosphere to form a first deep trench structure and a second deep trench structure.
Further, the filler is a mixture of silicon, a first metal and a second metal, the filler in the first deep trench structure and the second deep trench structure is silicon dioxide, the edges of the first deep trench structure and the second deep trench structure are doped with the first metal and the second metal, and the first metal is positioned outside the second metal;
Wherein the elemental weight of the first metal is greater than the elemental weight of the second metal.
Further, the method for forming the laminated grid structure specifically comprises the following steps:
sequentially depositing a barrier layer, a first metal layer and a second metal layer on the third semiconductor material layer through a deposition process;
And sequentially etching the second metal layer, the first metal layer and the barrier layer through an etching process to form a laminated grating structure, wherein the laminated grating structure is positioned above the pixel unit, the material of the barrier layer is HFO 2, the material of the first metal layer is aluminum, and the material of the second metal layer is tantalum nitride.
Compared with the prior art, the invention has the following unexpected technical effects:
The invention provides a backside illuminated image sensor and a preparation method thereof, wherein the backside illuminated image sensor comprises a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer which are sequentially arranged on one side of a substrate, wherein a first deep trench structure is arranged in the third semiconductor material layer, the second semiconductor material layer and the first semiconductor material layer, a second deep trench structure is arranged in the third semiconductor material layer and the second semiconductor material layer, each first deep trench structure and one second deep trench structure are adjacently arranged, the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer between the first deep trench structure and the second deep trench structure are adjacently arranged to form a pixel unit, and a laminated grid structure is formed on the pixel unit, wherein the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer are doped with tetravalent elements, and the atomic weight of the tetravalent elements doped in the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer is sequentially reduced from bottom to top, so that the problem of the pixel unit formed by ion implantation interference in the prior art can be solved.
In addition, the laminated grating structure sequentially comprises a blocking layer, a first metal layer and a second metal layer from bottom to top, wherein the blocking layer is made of HFO 2 so as to inhibit surface electron diffusion, and therefore the problem of dark current is solved.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a backside illuminated image sensor according to an embodiment of the invention.
Fig. 2 is a schematic structural diagram of a substrate according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of a structure after forming a metal interconnect structure on a substrate according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of an embodiment of the present invention after thinning a substrate.
Fig. 5 is a schematic structural diagram of a third semiconductor material layer according to an embodiment of the present invention.
FIG. 6 is a schematic diagram of a structure of an embodiment of the present invention after etching the hard mask layer.
Fig. 7 is a schematic structural diagram of the first deep trench and the second deep trench after forming the first deep trench according to an embodiment of the present invention.
Figure 8 is a schematic structural diagram of an embodiment of the present invention after forming the first deep trench structure and the second deep trench structure.
FIG. 9 is a schematic diagram of a structure after a deposition process according to an embodiment of the present invention.
FIG. 10 is a schematic diagram of a laminated grid structure according to an embodiment of the invention.
Fig. 11 is a schematic diagram of a structure of a color filter according to an embodiment of the invention after forming the color filter.
Reference numerals illustrate:
100-a substrate; 100 a-front side; 100 b-back; 101-shallow trench isolation structures; 102-a metal interconnect structure; 110-a stop layer; 120-a first semiconductor material layer; 130-a layer of a second semiconductor material; 140-a third semiconductor material layer; 150-a buffer layer; 160-a hard mask layer; 201-a first deep trench; 202-a second deep trench; 210-a first deep trench structure; 220-a second deep trench structure; 301-a barrier layer; 302-a first metal layer; 303-a second metal layer; 310-laminated grid structure; 320-color filter.
Detailed Description
A backside illuminated image sensor and a method of manufacturing the same according to the present invention will be described in further detail. The present invention will be described in more detail below with reference to the attached drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It should be appreciated that in the development of any such actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as compliance with system-related or business-related constraints, which will vary from one implementation to another. In addition, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments accompanied with figures are described in detail below. It is noted that the drawings are in a very simplified form and utilize non-precise ratios, and are intended to facilitate a convenient, clear, description of the embodiments of the invention.
As shown in fig. 11, the present embodiment provides a backside illuminated image sensor, which includes a first semiconductor material layer 120, a second semiconductor material layer 130 and a third semiconductor material layer 140 sequentially disposed on one side of a substrate 100, wherein a plurality of first deep trench structures 210 are disposed in the third semiconductor material layer 140, the second semiconductor material layer 130 and the first semiconductor material layer 120, a plurality of second deep trench structures 220 are disposed in the third semiconductor material layer 140 and the second semiconductor material layer 130, each of the first deep trench structures 210 and one of the second deep trench structures 220 are adjacently disposed, and the first semiconductor material layer 120, the second semiconductor material layer 130 and the third semiconductor material layer 140 between the adjacent first deep trench structures 210 and the second deep trench structures 220 form a pixel unit, and a laminated grid structure 310 is formed on the pixel unit, wherein tetravalent elements are doped in the first semiconductor material layer 120, the second semiconductor material layer 130 and the third semiconductor material layer 140, and the tetravalent elements are sequentially doped in the weight of the tetravalent elements is reduced, and the conventional problem of the pixel unit is solved by the weight of the doped tetravalent elements being sequentially implanted.
In detail, the substrate 100 may be a silicon substrate 100, but is not limited thereto. The substrate 100 may be a germanium substrate 100, a silicon on insulator (Silicon On Insulator, SOI), a germanium on insulator (Germanium On Insulator, GOI), or the like, and certain doping particles may be implanted into the substrate 100 according to design requirements to change electrical parameters. The substrate 100 may have a semiconductor device such as a CMOS logic device formed therein.
The substrate 100 includes a front surface 100a and a back surface 100b disposed opposite to each other, the back surface 100b is provided with a stop layer 110 doped with N-type ions, an STI 101 (shallow trench isolation structure) is disposed in the substrate 100, the STI 101 penetrates the front surface 100a, the bottom of the STI 101 exposes the stop layer 110, and an opening size of the STI 101 toward the front surface 100a is larger than an opening size of the STI 101 toward the back surface 100 b. A metal interconnection structure 102 is disposed on the front surface 100a, where the metal interconnection structure 102 is used to implement interconnection conduction of devices in the substrate 100.
The stop layer 110 is sequentially provided with a first semiconductor material layer 120, a second semiconductor material layer 130, a third semiconductor material layer 140 and a buffer layer 150, wherein tetravalent elements are doped in the first semiconductor material layer 120, the second semiconductor material layer 130 and the third semiconductor material layer 140, and the atomic weight of the doped tetravalent elements is sequentially reduced from bottom to top. For example, the first semiconductor material layer 120 is doped with antimony, the second semiconductor material layer 130 is doped with arsenic, and the third semiconductor material layer 140 is doped with phosphorus. The buffer layer 150 is used as a light-transmitting protective layer of the back-illuminated image sensor, and may be a silicon oxide layer, specifically a silicon dioxide layer.
The first deep trench structure 210 is formed by disposing a filler in the first deep trench 201, and the first deep trench 201 penetrates the buffer layer 150, the third semiconductor material layer 140, the second semiconductor material layer 130, the first semiconductor material layer 120 and the stop layer 110 from top to bottom in order from the back surface 100b, and contacts the bottom of the STI 101.
The second deep trench structure 220 is formed by arranging a filler in the second deep trench 202, and the second deep trench structure 220 penetrates through the buffer layer 150, the third semiconductor material layer 140 and the second semiconductor material layer 130 from top to bottom in sequence from the back surface 100b, so that the height of the second deep trench structure 220 is smaller than that of the first deep trench structure 210, thereby obtaining a first deep trench structure 210 and a second deep trench structure 220 with shallower heights, avoiding the influence of the deep trench structure on the dark current, and each second deep trench structure 220 is arranged opposite to one STI 101.
The first semiconductor material layer 120, the second semiconductor material layer 130, the third semiconductor material layer 140 between adjacent ones of the first deep trench structures 210 and the second deep trench structures 220 constitute pixel cells such that each of the pixel cells is constituted by the first semiconductor material layer 120, the second semiconductor material layer 130, the third semiconductor material layer 140 between one of the first deep trench structures 210 and one of the second deep trench structures 220.
The fillers in the first deep trench structure 210 and the second deep trench structure 220 are silicon dioxide, and a first metal and a second metal are doped in the silicon dioxide material at the edges of the first deep trench structure 210 and the second deep trench structure 220, and the first metal is located outside the second metal, i.e. the first metal is located at the outermost side at the edge of the first deep trench structure 210, and the first metal is located at the outermost side at the edge of the second deep trench structure 220. The element weight of the first metal is greater than that of the second metal, so that the diffusion coefficient of the first metal is smaller than that of the second metal, and the first metal can be a smaller insulating layer to increase the area of the pixel unit.
The laminated grating structure 310 sequentially comprises a barrier layer 301, a first metal layer 302 and a second metal layer 303 from bottom to top, wherein the material of the barrier layer 301 is HFO 2, which can inhibit surface electron diffusion, so as to solve the problem of dark current. The material of the first metal layer 302 may be aluminum, and the material of the second metal layer 303 may be tantalum nitride, so as to increase the light blocking effect and block electrons from migrating to areas where the light blocking effect is not present, such as electrons in red pixel cells migrating to blue pixel cells.
A color filter 320 is disposed between adjacent laminated grid structures 310, and the color filter 320 is located above the pixel unit. Wherein the color filters 320 include, but are not limited to, three primary color filters, i.e., a red filter, a blue filter, and a green filter, one of the red filter, the blue filter, and the green filter may be disposed between adjacent laminated grating structures 310, and preferably, the red filter, the blue filter, and the green filter are periodically spaced between adjacent laminated grating structures 310.
The embodiment also provides a preparation method of the back-illuminated image sensor, which comprises the following steps:
Step S1: sequentially forming a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer on one side of a substrate, wherein tetravalent elements are doped in the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer, and the atomic weight of the doped tetravalent elements is sequentially reduced from bottom to top;
step S2: sequentially etching the third semiconductor material layer, the second semiconductor material layer and the first semiconductor material layer to form a first deep trench structure, and simultaneously sequentially etching the third semiconductor material layer and the second semiconductor material layer to form a second deep trench structure, wherein each first deep trench structure and one second deep trench structure are adjacently arranged, and the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer between the adjacent first deep trench structure and the second deep trench structure form a pixel unit;
step S3: and forming a laminated grid structure on the pixel unit.
The following describes in detail a method for manufacturing a backside-illuminated image sensor according to this embodiment with reference to fig. 2 to 11.
In step S1, a first semiconductor material layer 120, a second semiconductor material layer 130 and a third semiconductor material layer 140 are sequentially formed on one side of the substrate 100, wherein tetravalent elements are doped in each of the first semiconductor material layer 120, the second semiconductor material layer 130 and the third semiconductor material layer 140, and the atomic weight of the doped tetravalent elements is sequentially reduced from bottom to top.
The method specifically comprises the following steps:
as shown in fig. 2, first, a substrate 100 is provided, and the substrate 100 may be a silicon substrate 100. The substrate 100 includes a front surface 100a and a back surface 100b disposed opposite to each other, and the front surface 100a is formed with STI 101 disposed at intervals. The substrate 100 may have a semiconductor device such as a CMOS logic device formed therein.
Next, an N-type ion implantation process is performed on the STI 101 from the front surface 100a by using a Blanket (Blanket) ion implantation process, so as to form a stop layer 110 on the STI 101 near the back surface 100b, where the stop layer 110 serves as a subsequent polish stop layer 110. Wherein, the N-type ion can be boron ion.
As shown in fig. 3, a metal interconnect structure 102 is then formed on the front surface 100a, the metal interconnect structure 102 being used to effect interconnect conduction of devices in the substrate 100.
As shown in fig. 4, next, the substrate 100 is thinned from the back surface 100b by CMP (Chemical-MECHANICAL PLANARIZATION, chemical mechanical polishing), and the polishing is stopped on the stop layer 110.
As shown in fig. 5, a first semiconductor material layer 120, a second semiconductor material layer 130, and a third semiconductor material layer 140 are sequentially formed on the stop layer 110 using solid phase diffusion (SPD, solid phase diffusion).
The first semiconductor material layer 120, the second semiconductor material layer 130 and the third semiconductor material layer 140 are formed in the same manner. The forming step of the first semiconductor material layer 120 is described as an example: and forming a first epitaxial layer, forming a first sacrificial layer with a doping element on the first epitaxial layer, and performing heat treatment to raise the temperature by solid phase diffusion so that the doping element in the first sacrificial layer with the doping element diffuses into the first epitaxial layer. Wherein the doping element in the first sacrificial layer is a tetravalent element, such as an antimony element, so that the first semiconductor material layer 120 is doped with the antimony element. The second semiconductor material layer 130 and the third semiconductor material layer 140 are formed by the same process, wherein the second semiconductor material layer 130 is doped with arsenic element, and the third semiconductor material layer 140 is doped with phosphorus element.
Next, step S2 is performed to sequentially etch the third semiconductor material layer 140, the second semiconductor material layer 130 and the first semiconductor material layer 120 to form a first deep trench structure 210, and simultaneously sequentially etch the third semiconductor material layer 140 and the second semiconductor material layer 130 to form a second deep trench structure 220, wherein each of the first deep trench structure 210 and the second deep trench structure 220 is disposed adjacent to each other, and the first semiconductor material layer 120, the second semiconductor material layer 130 and the third semiconductor material layer 140 between the adjacent first deep trench structure 210 and the second deep trench structure 220 form a pixel unit.
The method specifically comprises the following steps:
First, a buffer layer 150 and a hard mask layer 160 are sequentially formed on the third semiconductor material layer 140 through a deposition process. The buffer layer 150 is used as a light-transmitting protective layer of the back-illuminated image sensor, and may be a silicon oxide layer, specifically a silicon dioxide layer. The hard mask layer 160 may be a silicon nitride layer.
As shown in fig. 6, the hard mask layer 160 and the buffer layer 150 are then etched in sequence by an etching process to form openings defining the shapes of the first and second deep trench structures 210 and 220.
Next, the hard mask layer 160 is etched to remove a portion of the hard mask layer 160 outside the opening, such that a portion of the opening outside has only the buffer layer 150 (i.e., the first opening) and a portion of the opening outside has the buffer layer 150 and the hard mask layer 160 (i.e., the second opening) stacked. Wherein each first opening is disposed adjacent to one second opening.
As shown in fig. 7, a first deep trench 201 is then formed at the first opening and a second deep trench 202 is formed at the second opening using a dry etching process. The aspect ratio of the second opening is larger than that of the first opening, so that the etching gas entering the second opening in the dry etching process is less, and the depth of the second deep trench 202 formed in this way is shallower than that of the first deep trench 201. The first deep trench 201 penetrates through the third semiconductor material layer 140, the second semiconductor material layer 130, the first semiconductor material layer 120 and the stop layer 110 from top to bottom in order to expose the bottom of the STI 101, the second deep trench 202 penetrates through the third semiconductor material layer 140 and the second semiconductor material layer 130 from top to bottom in order, and each of the second deep trench structures 220 is disposed opposite to one STI 101.
Next, the hard mask layer 160 is removed.
Next, a filler is deposited in the first and second deep trenches 201, 202, the filler being a mixture of silicon, a first metal, a second metal, the filler also covering the buffer layer 150. Wherein the elemental weight of the first metal is greater than the elemental weight of the second metal, e.g., gallium for the first metal and indium for the second metal.
Next, the filler on the buffer layer 150 is removed by a CMP process, forming an initial first deep trench structure and an initial second deep trench structure.
As shown in fig. 8, a spike annealing (SPIKE ANNEALING) process is then performed under an oxygen atmosphere such that the first metal and the second metal and the gallium in the fill of the initial first deep trench structure are diffused to the edge of the initial first deep trench structure and the first metal is diffused to the outermost side, the second metal is disposed inside the first metal while the silicon is oxidized by oxygen to form silicon dioxide, thereby forming a first deep trench structure, and likewise, the first metal and the second metal and the gallium in the fill of the initial second deep trench structure are diffused to the edge of the initial second deep trench structure and the first metal is diffused to the outermost side and the second metal is disposed inside the first metal while the silicon is oxidized by oxygen to form silicon dioxide, thereby forming a second deep trench structure.
In this way, the first deep trench structure 210 and the second deep trench structure 220 are both filled with silicon dioxide, and in the first deep trench structure 210, the first metal is located at the outermost side at the edge of the first deep trench structure 210, and the second metal is located inside the first metal; also, in the second deep trench structure 220, the first metal is located outermost at an edge of the second deep trench structure 220, and the second metal is located inside the first metal. Wherein the elemental weight of the first metal is greater than the elemental weight of the second metal, e.g., gallium for the first metal and indium for the second metal.
Next, step S3 is performed to form a laminated grid structure 310 on the pixel unit.
The method specifically comprises the following steps:
As shown in fig. 9, first, a barrier layer 301, a first metal layer 302, and a second metal layer 303 are sequentially deposited on the buffer layer 150 by a deposition process.
As shown in fig. 10, the second metal layer 303, the first metal layer 302, and the barrier layer 301 are then etched in sequence by an etching process to form a stacked gate structure 310, the stacked gate structure 310 being located above the pixel cell. The material of the first metal layer 302 may be aluminum, and the material of the second metal layer 303 may be tantalum nitride.
As shown in fig. 11, a color filter 320 is then formed on the barrier layer 301 between the stacked grid structures 310 by a deposition process.
In summary, the present invention provides a backside illuminated image sensor and a method for manufacturing the same, where the backside illuminated image sensor includes a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer sequentially disposed on one side of a substrate, a first deep trench structure is disposed in the third semiconductor material layer, the second semiconductor material layer, and the first semiconductor material layer, a second deep trench structure is disposed in the third semiconductor material layer, and each of the first deep trench structure and the second deep trench structure is disposed adjacent to each other, and the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer between the adjacent first deep trench structure and the second deep trench structure form a pixel unit, and a stacked grid structure is formed on the pixel unit, wherein the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer are doped with tetravalent elements, and the atomic weight of the tetravalent elements doped in the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer are sequentially reduced from bottom to top, so that the problem of the pixel unit formed by ion implantation in the prior art can be solved.
In addition, the laminated grating structure sequentially comprises a blocking layer, a first metal layer and a second metal layer from bottom to top, wherein the blocking layer is made of HFO 2 so as to inhibit surface electron diffusion, and therefore the problem of dark current is solved.
Furthermore, unless specifically stated or indicated otherwise, the description of the terms "first," "second," and the like in the specification merely serve to distinguish between various components, elements, steps, etc. in the specification, and do not necessarily represent a logical or sequential relationship between various components, elements, steps, etc.
It will be appreciated that although the invention has been described above in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Claims (10)
1. The backside illuminated image sensor is characterized by comprising a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer which are sequentially arranged on one side of a substrate, wherein a first deep trench structure is arranged in the third semiconductor material layer, the second semiconductor material layer and the first semiconductor material layer, a second deep trench structure is arranged in the third semiconductor material layer and the second semiconductor material layer, each first deep trench structure and one second deep trench structure are adjacently arranged, a pixel unit is formed by the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer which are adjacently arranged between the first deep trench structure and the second deep trench structure, a laminated grid structure is formed on the pixel unit,
Wherein the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer are doped with tetravalent elements, and the atomic weight of the doped tetravalent elements is reduced from bottom to top.
2. The backside illuminated image sensor according to claim 1, wherein the first semiconductor material layer is doped with an antimony element, the second semiconductor material layer is doped with an arsenic element, and the third semiconductor material layer is doped with a phosphorus element.
3. The backside illuminated image sensor of claim 1, wherein the filler in the first and second deep trench structures is silicon dioxide, and a first metal and a second metal are doped at edges of the first and second deep trench structures, and the first metal is located outside the second metal, wherein an elemental weight of the first metal is greater than an elemental weight of the second metal.
4. The backside illuminated image sensor of claim 1, wherein the stacked grid structure comprises, in order from bottom to top, a barrier layer, a first metal layer, and a second metal layer, the barrier layer is made of HFO 2, the first metal layer is made of aluminum, and the second metal layer is made of tantalum nitride.
5. A method for preparing a backside illuminated image sensor according to any one of claims 1 to 4, comprising the steps of:
Sequentially forming a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer on one side of a substrate, wherein tetravalent elements are doped in the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer, and the atomic weight of the doped tetravalent elements is sequentially reduced from bottom to top;
Sequentially etching the third semiconductor material layer, the second semiconductor material layer and the first semiconductor material layer to form a first deep trench structure, and simultaneously sequentially etching the third semiconductor material layer and the second semiconductor material layer to form a second deep trench structure; wherein each first deep trench structure and one second deep trench structure are adjacently arranged, and a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer between the adjacent first deep trench structure and the adjacent second deep trench structure form a pixel unit;
and forming a laminated grid structure on the pixel unit.
6. The method for manufacturing a backside illuminated image sensor according to claim 5, wherein the method for forming the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer comprises:
Providing a substrate, wherein the substrate comprises a front surface and a back surface which are oppositely arranged, and shallow trench isolation structures which are arranged at intervals are formed on the front surface;
performing N-type ion implantation on the shallow trench isolation structure from the front surface by adopting a blanket ion implantation process so as to form a stop layer on one side of the shallow trench isolation structure close to the back surface;
thinning the substrate from the back surface by a chemical mechanical polishing process and polishing stopping on the stop layer;
and sequentially forming a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer on the stop layer by adopting solid-phase diffusion.
7. The method of manufacturing a backside illuminated image sensor according to claim 6, wherein the first semiconductor material layer is doped with antimony, the second semiconductor material layer is doped with arsenic, and the third semiconductor material layer is doped with phosphorus.
8. The method for manufacturing a backside-illuminated image sensor according to claim 6, wherein the method for forming the pixel unit comprises:
Sequentially forming a buffer layer and a hard mask layer on the third semiconductor material layer through a deposition process;
Sequentially etching the hard mask layer and the buffer layer through an etching process to form a first opening and a second opening, wherein the buffer layer is arranged outside the first opening, the buffer layer and the hard mask layer which are stacked are arranged outside the second opening, and each first opening is adjacent to one second opening;
forming a first deep trench at the first opening and forming a second deep trench at the second opening by adopting a dry etching process, wherein the first deep trench sequentially penetrates through the third semiconductor material layer, the second semiconductor material layer, the first semiconductor material layer and the stop layer from top to bottom so as to expose the bottom of the shallow trench isolation structure, the second deep trench sequentially penetrates through the third semiconductor material layer and the second semiconductor material layer from top to bottom, and each second deep trench structure is opposite to one shallow trench isolation structure;
removing the hard mask layer;
depositing a filler in the first deep trench and the second deep trench, the filler also covering the buffer layer;
And removing the filler on the buffer layer through a chemical mechanical polishing process, and performing a spike annealing process in an oxygen atmosphere to form a first deep trench structure and a second deep trench structure.
9. The method for manufacturing a backside illuminated image sensor according to claim 8, wherein the filler is a mixture of silicon, a first metal, and a second metal, the filler in the first deep trench structure and the second deep trench structure is silicon dioxide, the first metal and the second metal are doped at edges of the first deep trench structure and the second deep trench structure, and the first metal is located outside the second metal;
Wherein the elemental weight of the first metal is greater than the elemental weight of the second metal.
10. The method for manufacturing a backside illuminated image sensor according to claim 7, wherein the method for forming the laminated grating structure specifically comprises:
sequentially depositing a barrier layer, a first metal layer and a second metal layer on the third semiconductor material layer through a deposition process;
And sequentially etching the second metal layer, the first metal layer and the barrier layer through an etching process to form a laminated grating structure, wherein the laminated grating structure is positioned above the pixel unit, the material of the barrier layer is HFO 2, the material of the first metal layer is aluminum, and the material of the second metal layer is tantalum nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410841990.5A CN118398640B (en) | 2024-06-27 | 2024-06-27 | Backside illuminated image sensor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410841990.5A CN118398640B (en) | 2024-06-27 | 2024-06-27 | Backside illuminated image sensor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118398640A true CN118398640A (en) | 2024-07-26 |
| CN118398640B CN118398640B (en) | 2024-08-30 |
Family
ID=91999847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410841990.5A Active CN118398640B (en) | 2024-06-27 | 2024-06-27 | Backside illuminated image sensor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118398640B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010134390A1 (en) * | 2009-05-20 | 2010-11-25 | シャープ株式会社 | Method of producing semiconductor device |
| CN104247022A (en) * | 2012-04-19 | 2014-12-24 | 松下知识产权经营株式会社 | Solid-state imaging device and manufacturing method thereof |
| US20170250211A1 (en) * | 2016-02-25 | 2017-08-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor image sensor device and manufacturing method of the same |
| US20210132230A1 (en) * | 2019-10-30 | 2021-05-06 | Kabushiki Kaisha Toshiba | Light detector, light detection system, lidar device, and vehicle |
| CN114141799A (en) * | 2021-12-15 | 2022-03-04 | 华虹半导体(无锡)有限公司 | Backside illuminated image sensor and forming method thereof |
| CN114944358A (en) * | 2022-05-07 | 2022-08-26 | 长江存储科技有限责任公司 | Semiconductor device, manufacturing method thereof, three-dimensional storage device and storage system |
| EP4083656A1 (en) * | 2021-04-28 | 2022-11-02 | Kabushiki Kaisha Toshiba | Light detector, light detection system, lidar device, and mobile body |
| CN118231435A (en) * | 2024-05-24 | 2024-06-21 | 合肥晶合集成电路股份有限公司 | Image sensor and method for manufacturing same |
-
2024
- 2024-06-27 CN CN202410841990.5A patent/CN118398640B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010134390A1 (en) * | 2009-05-20 | 2010-11-25 | シャープ株式会社 | Method of producing semiconductor device |
| CN104247022A (en) * | 2012-04-19 | 2014-12-24 | 松下知识产权经营株式会社 | Solid-state imaging device and manufacturing method thereof |
| US20170250211A1 (en) * | 2016-02-25 | 2017-08-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor image sensor device and manufacturing method of the same |
| US20210132230A1 (en) * | 2019-10-30 | 2021-05-06 | Kabushiki Kaisha Toshiba | Light detector, light detection system, lidar device, and vehicle |
| EP4083656A1 (en) * | 2021-04-28 | 2022-11-02 | Kabushiki Kaisha Toshiba | Light detector, light detection system, lidar device, and mobile body |
| CN114141799A (en) * | 2021-12-15 | 2022-03-04 | 华虹半导体(无锡)有限公司 | Backside illuminated image sensor and forming method thereof |
| CN114944358A (en) * | 2022-05-07 | 2022-08-26 | 长江存储科技有限责任公司 | Semiconductor device, manufacturing method thereof, three-dimensional storage device and storage system |
| CN118231435A (en) * | 2024-05-24 | 2024-06-21 | 合肥晶合集成电路股份有限公司 | Image sensor and method for manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118398640B (en) | 2024-08-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI785120B (en) | Cmos image sensor and method of forming image sensor | |
| US11948956B2 (en) | Image sensors including an amorphous region and an electron suppression region | |
| JP4130891B2 (en) | A method for manufacturing a CMOS image sensor in which the depth of a photodiode differs according to the wavelength of light, and a method for forming the photodiode. | |
| US20060255372A1 (en) | Color pixels with anti-blooming isolation and method of formation | |
| CN1832187A (en) | Image sensor using deep trench isolation | |
| KR101770289B1 (en) | Image sensor and method of forming the same | |
| CN102044549A (en) | Solid state image capture device and method for manufacturing same | |
| JP2022169429A (en) | Image sensor and forming method thereof | |
| CN109192741B (en) | Method for forming back side illumination type image sensor | |
| KR101620706B1 (en) | Pixel isolation structures in backside illuminated image sensors | |
| CN118231435B (en) | Image sensor and method for manufacturing same | |
| CN115224067A (en) | Semiconductor structure and preparation method thereof | |
| CN108470741A (en) | Imaging sensor and forming method thereof | |
| TWI476911B (en) | Method for increasing photodiode full well capacity | |
| CN115810640A (en) | Backside illuminated image sensor and forming method thereof | |
| CN113178458A (en) | Method for forming CIS sensor | |
| CN118398640B (en) | Backside illuminated image sensor and preparation method thereof | |
| CN109216389B (en) | Backside illuminated image sensor and method of manufacturing the same | |
| KR20110079326A (en) | Image sensor and method for manufacturing the same | |
| CN116825796A (en) | Manufacturing method of chip and wafer | |
| CN108538868B (en) | Image sensor and manufacturing method thereof | |
| TWI815124B (en) | Image sensor and method of forming the same | |
| CN115831997B (en) | Backside illuminated image sensor and preparation method thereof | |
| TWI782650B (en) | Manufacturing method of backside illuminated image sensor | |
| KR100326267B1 (en) | Image sensor and method for fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |