CN118398640A - Backside illuminated image sensor and preparation method thereof - Google Patents
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 223
- 239000004065 semiconductor Substances 0.000 claims abstract description 221
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims description 109
- 239000002184 metal Substances 0.000 claims description 109
- 238000000034 method Methods 0.000 claims description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 239000000945 filler Substances 0.000 claims description 21
- 230000004888 barrier function Effects 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 14
- 238000002955 isolation Methods 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 9
- 238000005137 deposition process Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052787 antimony Inorganic materials 0.000 claims description 6
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 4
- 239000007790 solid phase Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 2
- FAWGZAFXDJGWBB-UHFFFAOYSA-N antimony(3+) Chemical compound [Sb+3] FAWGZAFXDJGWBB-UHFFFAOYSA-N 0.000 claims 1
- 230000007423 decrease Effects 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 261
- 238000010586 diagram Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 5
- -1 boron ions Chemical class 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明提供一种背照式图像传感器及其制备方法，背照式图像传感器包括依次设置在衬底的第一半导体材料层、第二半导体材料层和第三半导体材料层，第三半导体材料层、第二半导体材料层和第一半导体材料层中设置有第一深沟槽结构，第三半导体材料层和第二半导体材料层中设置有第二深沟槽结构，每个第一深沟槽结构和一第二深沟槽结构相邻设置，相邻第一深沟槽结构和第二深沟槽结构之间构成像素单元，像素单元上形成有叠层格栅结构，第一半导体材料层、第二半导体材料层和第三半导体材料层中均掺杂有四价元素，且掺杂的四价元素的原子重量由下至上依次减少，可以解决现有技术中因离子注入形成的像素单元造成的干扰效应问题。
The present invention provides a back-illuminated image sensor and a preparation method thereof. The back-illuminated image sensor comprises a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer which are sequentially arranged on a substrate, a first deep trench structure is arranged in the third semiconductor material layer, the second semiconductor material layer and the first semiconductor material layer, a second deep trench structure is arranged in the third semiconductor material layer and the second semiconductor material layer, each first deep trench structure and a second deep trench structure are adjacently arranged, a pixel unit is formed between adjacent first deep trench structures and second deep trench structures, a stacked grid structure is formed on the pixel unit, the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer are doped with a tetravalent element, and the atomic weight of the doped tetravalent element decreases sequentially from bottom to top, so as to solve the interference effect problem caused by the pixel unit formed by ion implantation in the prior art.
Description
技术领域Technical Field
本发明涉及半导体制造技术领域，特别涉及一种背照式图像传感器及其制备方法。The present invention relates to the technical field of semiconductor manufacturing, and in particular to a back-illuminated image sensor and a preparation method thereof.
背景技术Background technique
图像传感器是指光学图像转换成像素信号输出的设备。图像传感器包括电荷耦合器件（CCD）与互补金属氧化物半导体（CMOS）图像传感器。CMOS图像传感器一般分为前照式（FSI）图像传感器和背照式（BSI）图像传感器两种。背照式图像传感器将感光层的元件（例如微透镜和光电二极管）设置在基底的背面一侧，并允许光通过背侧进入并由光电二极管检测，由于光线无需穿过布线层，避免了前照式图像传感器结构中光线会受到微透镜和光电二极管之间的电路和晶体管的影响，从而显著的提高了光的效能，大大改善了图像传感器在低光照条件下的感光效果，且显示比前照式更高的灵敏度。Image sensor refers to a device that converts optical images into pixel signal output. Image sensors include charge coupled devices (CCD) and complementary metal oxide semiconductor (CMOS) image sensors. CMOS image sensors are generally divided into two types: front-illuminated (FSI) image sensors and back-illuminated (BSI) image sensors. Back-illuminated image sensors place the components of the photosensitive layer (such as microlenses and photodiodes) on the back side of the substrate, and allow light to enter through the back side and be detected by the photodiode. Since the light does not need to pass through the wiring layer, the light in the front-illuminated image sensor structure is avoided from being affected by the circuit and transistor between the microlens and the photodiode, thereby significantly improving the efficiency of light, greatly improving the photosensitivity of the image sensor under low light conditions, and showing higher sensitivity than the front-illuminated type.
在背照式图像传感器的先进制程中，由于需要使用高能量的例子注入工艺来形成光电二极管（Photo diode，PD），对衬底造成损伤，并造成光源入射时出现干扰效应（crosstalk）的不理想效应。In the advanced manufacturing process of back-illuminated image sensors, a high-energy electron implantation process is required to form a photodiode (PD), which damages the substrate and causes an undesirable effect of crosstalk when light is incident.
发明内容Summary of the invention
本发明的目的在于，提供一种背照式图像传感器及其制备方法，可以减少干扰效应。The object of the present invention is to provide a back-illuminated image sensor and a method for preparing the same, which can reduce interference effects.
为了解决以上问题，本发明提供一种背照式图像传感器，包括依次设置在衬底一侧的第一半导体材料层、第二半导体材料层和第三半导体材料层，所述第三半导体材料层、第二半导体材料层和第一半导体材料层中设置有第一深沟槽结构，所述第三半导体材料层和第二半导体材料层中设置有第二深沟槽结构，每个所述第一深沟槽结构和一所述第二深沟槽结构相邻设置，且相邻所述第一深沟槽结构和第二深沟槽结构之间的第一半导体材料层、第二半导体材料层和第三半导体材料层构成像素单元，所述像素单元上形成有叠层格栅结构，In order to solve the above problems, the present invention provides a back-illuminated image sensor, comprising a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer sequentially arranged on one side of a substrate, wherein a first deep trench structure is arranged in the third semiconductor material layer, the second semiconductor material layer and the first semiconductor material layer, and a second deep trench structure is arranged in the third semiconductor material layer and the second semiconductor material layer, each of the first deep trench structure and one of the second deep trench structures are arranged adjacent to each other, and the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer between the adjacent first deep trench structures and the second deep trench structures constitute a pixel unit, and a stacked grid structure is formed on the pixel unit.
其中，所述第一半导体材料层、第二半导体材料层和第三半导体材料层中均掺杂有四价元素，且掺杂的四价元素的原子重量由下至上依次减少。The first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer are all doped with tetravalent elements, and the atomic weights of the doped tetravalent elements decrease from bottom to top.
可选的，所述第一半导体材料层中掺杂有锑元素，所述第二半导体材料层中掺杂有砷元素，所述第三半导体材料层掺杂有磷元素。Optionally, the first semiconductor material layer is doped with antimony, the second semiconductor material layer is doped with arsenic, and the third semiconductor material layer is doped with phosphorus.
可选的，所述第一深沟槽结构和第二深沟槽结构中填充物为二氧化硅，且在所述第一深沟槽结构和第二深沟槽结构的边缘处均掺杂有第一金属和第二金属，且所述第一金属位于所述第二金属的外侧，其中，所述第一金属的元素重量较所述第二金属的元素重量大。Optionally, the fillers in the first deep trench structure and the second deep trench structure are silicon dioxide, and the first metal and the second metal are doped at the edges of the first deep trench structure and the second deep trench structure, and the first metal is located on the outside of the second metal, wherein the element weight of the first metal is greater than the element weight of the second metal.
可选的，所述叠层格栅结构由下至上依次包括阻挡层、第一金属层和第二金属层，所述阻挡层的材料为HFO2，所述第一金属层的材料为铝，所述第二金属层的材料为氮化钽。Optionally, the laminated grid structure includes a barrier layer, a first metal layer and a second metal layer in order from bottom to top, the barrier layer is made of HFO 2 , the first metal layer is made of aluminum, and the second metal layer is made of tantalum nitride.
另一方面，本发明提供一种背照式图像传感器的制备方法，制备上述所述的背照式图像传感器，包括以下步骤：In another aspect, the present invention provides a method for preparing a back-illuminated image sensor, and the method comprises the following steps:
在衬底一侧上依次形成第一半导体材料层、第二半导体材料层和第三半导体材料层，所述第一半导体材料层、第二半导体材料层和第三半导体材料层中均掺杂有四价元素，且掺杂的四价元素的原子重量由下至上依次减少；A first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer are sequentially formed on one side of the substrate, wherein the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer are all doped with a tetravalent element, and the atomic weight of the doped tetravalent element decreases sequentially from bottom to top;
依次刻蚀所述第三半导体材料层、第二半导体材料层和第一半导体材料层，以形成第一深沟槽结构，同时，依次刻蚀所述第三半导体材料层和第二半导体材料层，以形成第二深沟槽结构；其中，每个所述第一深沟槽结构和一所述第二深沟槽结构相邻设置，且相邻所述第一深沟槽结构和第二深沟槽结构之间的第一半导体材料层、第二半导体材料层和第三半导体材料层构成像素单元；The third semiconductor material layer, the second semiconductor material layer and the first semiconductor material layer are sequentially etched to form a first deep trench structure, and at the same time, the third semiconductor material layer and the second semiconductor material layer are sequentially etched to form a second deep trench structure; wherein each of the first deep trench structures and one of the second deep trench structures are adjacently arranged, and the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer between the adjacent first deep trench structures and the second deep trench structures constitute a pixel unit;
在所述像素单元上形成叠层格栅结构。A stacked grid structure is formed on the pixel unit.
可选的，形成所述第一半导体材料层、第二半导体材料层和第三半导体材料层的方法具体为：Optionally, the method of forming the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer is specifically:
提供衬底，所述衬底包括相对设置的正面和背面，在所述正面形成有间隔设置的浅沟槽隔离结构；Providing a substrate, the substrate comprising a front side and a back side arranged opposite to each other, and shallow trench isolation structures arranged at intervals are formed on the front side;
采用覆毯式的离子注入工艺，从所述正面对所述浅沟槽隔离结构进行N型离子注入，以在所述浅沟槽隔离结构靠近所述背面一侧形成停止层；Using a blanket ion implantation process, N-type ion implantation is performed on the shallow trench isolation structure from the front surface to form a stop layer on the side of the shallow trench isolation structure close to the back surface;
从所述背面通过化学机械抛光工艺减薄所述衬底，并研磨停止在所述停止层上；Thinning the substrate from the back side by a chemical mechanical polishing process, and grinding to stop on the stop layer;
采用固相扩散在所述停止层上依次形成第一半导体材料层、第二半导体材料层和第三半导体材料层。A first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer are sequentially formed on the stop layer by solid phase diffusion.
进一步的，所述第一半导体材料层中掺杂有锑元素，所述第二半导体材料层中掺杂有砷元素，所述第三半导体材料层掺杂有磷元素。Furthermore, the first semiconductor material layer is doped with antimony, the second semiconductor material layer is doped with arsenic, and the third semiconductor material layer is doped with phosphorus.
进一步的，形成所述像素单元的方法具体为：Furthermore, the method for forming the pixel unit is specifically as follows:
通过沉积工艺在所述第三半导体材料层上依次形成缓冲层和硬掩模层；sequentially forming a buffer layer and a hard mask layer on the third semiconductor material layer through a deposition process;
通过刻蚀工艺依次刻蚀所述硬掩模层和缓冲层，以形成第一开口和第二开口，所述第一开口外侧仅具有缓冲层，所述第二开口外侧具有堆叠设置的缓冲层和硬掩模层，且每个第一开口均与一个第二开口相邻设置；The hard mask layer and the buffer layer are sequentially etched by an etching process to form a first opening and a second opening, wherein the first opening has only the buffer layer outside, and the second opening has the buffer layer and the hard mask layer stacked outside, and each first opening is adjacent to a second opening;
采用干法刻蚀工艺在所述第一开口处形成第一深沟槽，在所述第二开口处形成第二深沟槽，其中，所述第一深沟槽由上至下依次贯通所述第三半导体材料层、第二半导体材料层、第一半导体材料层和停止层，以暴露出所述浅沟槽隔离结构的底部，所述第二深沟槽由上至下依次贯通所述第三半导体材料层和第二半导体材料层，且每个所述第二深沟槽结构均与一个所述浅沟槽隔离结构正对设置；A first deep trench is formed at the first opening by a dry etching process, and a second deep trench is formed at the second opening, wherein the first deep trench sequentially penetrates the third semiconductor material layer, the second semiconductor material layer, the first semiconductor material layer and the stop layer from top to bottom to expose the bottom of the shallow trench isolation structure, and the second deep trench sequentially penetrates the third semiconductor material layer and the second semiconductor material layer from top to bottom, and each of the second deep trench structures is arranged opposite to one of the shallow trench isolation structures;
去除所述硬掩模层；removing the hard mask layer;
在所述第一深沟槽和第二深沟槽中沉积填充物，所述填充物还覆盖所述缓冲层；Depositing a filler in the first deep trench and the second deep trench, wherein the filler also covers the buffer layer;
通过化学机械抛光工艺去除所述缓冲层上的所述填充物，并在氧气氛围下执行尖峰退火工艺，以形成第一深沟槽结构和第二深沟槽结构。The filler on the buffer layer is removed by a chemical mechanical polishing process, and a spike annealing process is performed in an oxygen atmosphere to form a first deep trench structure and a second deep trench structure.
进一步的，所述填充物为硅、第一金属、第二金属的混合物，所述第一深沟槽结构和第二深沟槽结构中的填充物为二氧化硅，且在所述第一深沟槽结构和第二深沟槽结构的边缘处均掺杂有第一金属和第二金属，且所述第一金属位于所述第二金属的外侧；Further, the filler is a mixture of silicon, a first metal, and a second metal, the fillers in the first deep trench structure and the second deep trench structure are silicon dioxide, and the edges of the first deep trench structure and the second deep trench structure are doped with the first metal and the second metal, and the first metal is located outside the second metal;
其中，所述第一金属的元素重量较所述第二金属的元素重量大。The element weight of the first metal is greater than the element weight of the second metal.
进一步的，形成所述叠层格栅结构的方法具体为：Furthermore, the method for forming the laminated grid structure is specifically as follows:
通过沉积工艺在所述第三半导体材料层上依次沉积阻挡层、第一金属层和第二金属层；Depositing a barrier layer, a first metal layer, and a second metal layer in sequence on the third semiconductor material layer by a deposition process;
通过刻蚀工艺依次刻蚀所述第二金属层、第一金属层和阻挡层，以形成叠层格栅结构，所述叠层格栅结构位于所述像素单元上方，其中，所述阻挡层的材料为HFO2，所述第一金属层的材料为铝，所述第二金属层的材料为氮化钽。The second metal layer, the first metal layer and the barrier layer are sequentially etched by an etching process to form a stacked grid structure located above the pixel unit, wherein the barrier layer is made of HFO 2 , the first metal layer is made of aluminum, and the second metal layer is made of tantalum nitride.
与现有技术相比，本发明具有以下意想不到的技术效果：Compared with the prior art, the present invention has the following unexpected technical effects:
本发明提供一种背照式图像传感器及其制备方法，背照式图像传感器包括依次设置在衬底一侧的第一半导体材料层、第二半导体材料层和第三半导体材料层，所述第三半导体材料层、第二半导体材料层和第一半导体材料层中设置有第一深沟槽结构，所述第三半导体材料层和第二半导体材料层中设置有第二深沟槽结构，每个所述第一深沟槽结构和一所述第二深沟槽结构相邻设置，且相邻所述第一深沟槽结构和第二深沟槽结构之间的第一半导体材料层、第二半导体材料层和第三半导体材料层构成像素单元，所述像素单元上形成有叠层格栅结构，其中，所述第一半导体材料层、第二半导体材料层和第三半导体材料层中均掺杂有四价元素，且掺杂的四价元素的原子重量由下至上依次减少，可以解决现有技术中因离子注入形成的像素单元造成的干扰效应问题。The present invention provides a back-illuminated image sensor and a preparation method thereof. The back-illuminated image sensor comprises a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer which are sequentially arranged on one side of a substrate, wherein a first deep trench structure is arranged in the third semiconductor material layer, the second semiconductor material layer and the first semiconductor material layer, and a second deep trench structure is arranged in the third semiconductor material layer and the second semiconductor material layer, each of the first deep trench structure and one of the second deep trench structures are adjacently arranged, and the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer between adjacent first deep trench structures and second deep trench structures constitute a pixel unit, and a stacked grid structure is formed on the pixel unit, wherein the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer are all doped with a tetravalent element, and the atomic weight of the doped tetravalent element decreases sequentially from bottom to top, so as to solve the interference effect problem caused by the pixel unit formed by ion implantation in the prior art.
另外，所述叠层格栅结构由下至上依次包括阻挡层、第一金属层和第二金属层，所述阻挡层的材料为HFO2，以抑制表面电子扩散，从而解决暗电流的问题。In addition, the stacked grid structure includes a barrier layer, a first metal layer and a second metal layer in order from bottom to top. The barrier layer is made of HFO 2 to suppress surface electron diffusion, thereby solving the problem of dark current.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1为本发明一实施例提供的一种背照式图像传感器的制备方法的流程示意图。FIG. 1 is a schematic flow chart of a method for preparing a back-illuminated image sensor provided in accordance with an embodiment of the present invention.
图2为本发明一实施例提供的衬底的结构示意图。FIG. 2 is a schematic diagram of the structure of a substrate provided in one embodiment of the present invention.
图3为本发明一实施例在衬底上形成金属互连结构后的结构示意图。FIG. 3 is a schematic diagram of a structure after a metal interconnection structure is formed on a substrate according to an embodiment of the present invention.
图4为本发明一实施例在减薄衬底后的结构示意图。FIG. 4 is a schematic diagram of the structure of an embodiment of the present invention after the substrate is thinned.
图5为本发明一实施例在形成第三半导体材料层后的结构示意图。FIG. 5 is a schematic diagram of the structure after forming a third semiconductor material layer according to an embodiment of the present invention.
图6为本发明一实施例在刻蚀所述硬掩模层后的结构示意图。FIG. 6 is a schematic diagram of the structure after etching the hard mask layer according to an embodiment of the present invention.
图7为本发明一实施例在形成第一深沟槽和第二深沟槽后的结构示意图。FIG. 7 is a schematic diagram of the structure after forming the first deep trench and the second deep trench according to an embodiment of the present invention.
图8为本发明一实施例在形成第一深沟槽结构和第二深沟槽结构后的结构示意图。FIG. 8 is a schematic structural diagram of an embodiment of the present invention after forming a first deep trench structure and a second deep trench structure.
图9为本发明一实施例在沉积工艺后的结构示意图。FIG. 9 is a schematic diagram of the structure of an embodiment of the present invention after a deposition process.
图10为本发明一实施例在形成叠层格栅结构后的结构示意图。FIG. 10 is a schematic diagram of the structure of an embodiment of the present invention after forming a laminated grid structure.
图11为本发明一实施例在形成彩色滤光片后的结构示意图。FIG. 11 is a schematic diagram of the structure after forming a color filter according to an embodiment of the present invention.
附图标记说明：Description of reference numerals:
100-衬底；100a-正面；100b-背面；101-浅沟槽隔离结构；102-金属互连结构；110-停止层；120-第一半导体材料层；130-第二半导体材料层；140-第三半导体材料层；150-缓冲层；160-硬掩模层；201-第一深沟槽；202-第二深沟槽；210-第一深沟槽结构；220-第二深沟槽结构；301-阻挡层；302-第一金属层；303-第二金属层；310-叠层格栅结构；320-彩色滤光片。100-substrate; 100a-front side; 100b-back side; 101-shallow trench isolation structure; 102-metal interconnection structure; 110-stop layer; 120-first semiconductor material layer; 130-second semiconductor material layer; 140-third semiconductor material layer; 150-buffer layer; 160-hard mask layer; 201-first deep trench; 202-second deep trench; 210-first deep trench structure; 220-second deep trench structure; 301-barrier layer; 302-first metal layer; 303-second metal layer; 310-laminated grid structure; 320-color filter.
具体实施方式Detailed ways
以下将对本发明的一种背照式图像传感器及其制备方法作进一步的详细描述。下面将参照附图对本发明进行更详细的描述，其中表示了本发明的优选实施例，应该理解本领域技术人员可以修改在此描述的本发明而仍然实现本发明的有利效果。因此，下列描述应当被理解为对于本领域技术人员的广泛知道，而并不作为对本发明的限制。A back-illuminated image sensor and a method for manufacturing the same of the present invention will be described in further detail below. The present invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein and still achieve the beneficial effects of the present invention. Therefore, the following description should be understood as being broadly known to those skilled in the art and not as a limitation of the present invention.
为了清楚，不描述实际实施例的全部特征。在下列描述中，不详细描述公知的功能和结构，因为它们会使本发明由于不必要的细节而混乱。应当认为在任何实际实施例的开发中，必须做出大量实施细节以实现开发者的特定目标，例如按照有关系统或有关商业的限制，由一个实施例改变为另一个实施例。另外，应当认为这种开发工作可能是复杂和耗费时间的，但是对于本领域技术人员来说仅仅是常规工作。For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would clutter the invention with unnecessary detail. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just a routine task for those skilled in the art.
为使本发明的目的、特征更明显易懂，下面结合附图对本发明的具体实施方式作进一步的说明。需说明的是，附图均采用非常简化的形式且均使用非精准的比率，仅用以方便、明晰地辅助说明本发明实施例的目的。In order to make the purpose and features of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
如图11所示，本实施例提供一种背照式图像传感器，包括依次设置在衬底100一侧的第一半导体材料层120、第二半导体材料层130和第三半导体材料层140，所述第三半导体材料层140、第二半导体材料层130和第一半导体材料层120中设置有多个第一深沟槽结构210，所述第三半导体材料层140和第二半导体材料层130中设置有多个第二深沟槽结构220，每个所述第一深沟槽结构210和一所述第二深沟槽结构220相邻设置，且相邻所述第一深沟槽结构210和第二深沟槽结构220之间的第一半导体材料层120、第二半导体材料层130和第三半导体材料层140构成像素单元，所述像素单元上形成有叠层格栅结构310，其中，所述第一半导体材料层120、第二半导体材料层130和第三半导体材料层140中均掺杂有四价元素，且掺杂的四价元素的原子重量由下至上依次减少，可以解决现有技术中因离子注入形成的像素单元造成的干扰效应问题。As shown in FIG11 , this embodiment provides a back-illuminated image sensor, comprising a first semiconductor material layer 120, a second semiconductor material layer 130, and a third semiconductor material layer 140 sequentially arranged on one side of a substrate 100, wherein a plurality of first deep trench structures 210 are arranged in the third semiconductor material layer 140, the second semiconductor material layer 130, and the first semiconductor material layer 120, and a plurality of second deep trench structures 220 are arranged in the third semiconductor material layer 140 and the second semiconductor material layer 130, wherein each of the first deep trench structures 210 and the second deep trench structures 220 The first semiconductor material layer 120, the second semiconductor material layer 130 and the third semiconductor material layer 140 which are adjacently arranged and between the first deep trench structure 210 and the second deep trench structure 220 constitute a pixel unit, on which a stacked grid structure 310 is formed, wherein the first semiconductor material layer 120, the second semiconductor material layer 130 and the third semiconductor material layer 140 are all doped with tetravalent elements, and the atomic weight of the doped tetravalent elements decreases from bottom to top, which can solve the interference effect problem caused by the pixel unit formed by ion implantation in the prior art.
详细的，所述衬底100可以为硅衬底100，但是不限于此。所述衬底100可以是锗衬底100、硅锗衬底100、绝缘体上硅（Silicon On Insulator，SOI）或绝缘体上锗（GermaniumOn Insulator，GOI）等，所述衬底100中还可以根据设计需求注入一定的掺杂粒子以改变电学参数。所述衬底100中可以形成有CMOS逻辑器件等半导体器件。In detail, the substrate 100 may be a silicon substrate 100, but is not limited thereto. The substrate 100 may be a germanium substrate 100, a silicon germanium substrate 100, a silicon on insulator (SOI) or a germanium on insulator (GOI), etc. Certain doping particles may be implanted into the substrate 100 according to design requirements to change electrical parameters. Semiconductor devices such as CMOS logic devices may be formed in the substrate 100.
所述衬底100包括相对设置的正面100a和背面100b，所述背面100b设置有掺杂有N型离子的停止层110，所述衬底100中设置有STI 101（浅沟槽隔离结构），所述STI 101贯通所述正面100a，所述STI 101的底部暴露出所述停止层110，且所述STI 101朝向所述正面100a的开口尺寸大于所述STI 101朝向背面100b的开口尺寸。所述正面100a上设置有金属互连结构102，所述金属互连结构102用于实现所述衬底100中的器件的互联导通。The substrate 100 includes a front side 100a and a back side 100b which are arranged opposite to each other, the back side 100b is provided with a stop layer 110 doped with N-type ions, and an STI 101 (shallow trench isolation structure) is provided in the substrate 100, the STI 101 passes through the front side 100a, the bottom of the STI 101 exposes the stop layer 110, and the opening size of the STI 101 toward the front side 100a is larger than the opening size of the STI 101 toward the back side 100b. A metal interconnection structure 102 is provided on the front side 100a, and the metal interconnection structure 102 is used to realize the interconnection and conduction of the devices in the substrate 100.
所述停止层110上依次设置有第一半导体材料层120、第二半导体材料层130、第三半导体材料层140和缓冲层150，所述第一半导体材料层120、第二半导体材料层130和第三半导体材料层140中均掺杂有四价元素，且掺杂的四价元素的原子重量由下至上依次减少。例如，所述第一半导体材料层120中掺杂有锑元素，所述第二半导体材料层130中掺杂有砷元素，所述第三半导体材料层140掺杂有磷元素。所述缓冲层150作为背照式图像传感器的透光保护层，其可以为氧化硅层，具体为二氧化硅层。The stop layer 110 is sequentially provided with a first semiconductor material layer 120, a second semiconductor material layer 130, a third semiconductor material layer 140 and a buffer layer 150, wherein the first semiconductor material layer 120, the second semiconductor material layer 130 and the third semiconductor material layer 140 are all doped with tetravalent elements, and the atomic weight of the doped tetravalent elements decreases from bottom to top. For example, the first semiconductor material layer 120 is doped with antimony, the second semiconductor material layer 130 is doped with arsenic, and the third semiconductor material layer 140 is doped with phosphorus. The buffer layer 150 serves as a light-transmitting protective layer of the back-illuminated image sensor, and may be a silicon oxide layer, specifically a silicon dioxide layer.
所述第一深沟槽结构210为在第一深沟槽201中设置填充物形成，且所述第一深沟槽201从所述背面100b由上至下依次贯通所述缓冲层150、第三半导体材料层140、第二半导体材料层130、第一半导体材料层120和停止层110，并与所述STI 101的底部接触。The first deep trench structure 210 is formed by setting a filler in the first deep trench 201, and the first deep trench 201 passes through the buffer layer 150, the third semiconductor material layer 140, the second semiconductor material layer 130, the first semiconductor material layer 120 and the stop layer 110 from top to bottom from the back side 100b, and contacts the bottom of the STI 101.
所述第二深沟槽结构220为在第二深沟槽202中设置填充物形成，且所述第二深沟槽结构220从所述背面100b由上至下依次贯通所述缓冲层150、第三半导体材料层140和第二半导体材料层130，使得所述第二深沟槽结构220的高度小于所述第一深沟槽结构210的高度，以得到高度较浅的第一深沟槽结构210和第二深沟槽结构220，并避免深的深沟槽结构对暗电流的影响，且每个所述第二深沟槽结构220均与一个STI 101正对设置。The second deep trench structure 220 is formed by setting a filler in the second deep trench 202, and the second deep trench structure 220 passes through the buffer layer 150, the third semiconductor material layer 140 and the second semiconductor material layer 130 from the back side 100b from top to bottom, so that the height of the second deep trench structure 220 is less than the height of the first deep trench structure 210, so as to obtain the first deep trench structure 210 and the second deep trench structure 220 with shallower heights, and avoid the influence of the deep deep trench structure on the dark current, and each of the second deep trench structures 220 is arranged opposite to an STI 101.
相邻所述第一深沟槽结构210和第二深沟槽结构220之间的第一半导体材料层120、第二半导体材料层130、第三半导体材料层140构成像素单元，使得每个所述像素单元均由一个第一深沟槽结构210和一个第二深沟槽结构220之间的第一半导体材料层120、第二半导体材料层130、第三半导体材料层140构成。The first semiconductor material layer 120, the second semiconductor material layer 130, and the third semiconductor material layer 140 between the adjacent first deep trench structures 210 and the second deep trench structures 220 constitute a pixel unit, so that each of the pixel units is composed of the first semiconductor material layer 120, the second semiconductor material layer 130, and the third semiconductor material layer 140 between a first deep trench structure 210 and a second deep trench structure 220.
所述第一深沟槽结构210和第二深沟槽结构220中均的填充物均为二氧化硅，且在所述第一深沟槽结构210和第二深沟槽结构220的边缘处的二氧化硅材料中掺杂有第一金属和第二金属，且所述第一金属位于所述第二金属的外侧，即所述第一金属位于所述第一深沟槽结构210的边缘处的最外侧，所述第一金属位于所述第二深沟槽结构220的边缘处的最外侧。其中，所述第一金属的元素重量较所述第二金属的元素重量大，使得第一金属的扩散系数较第二金属的扩散系数小，并使得所述第一金属可以做到更小的绝缘层来增加像素单元的区域，在本实施例中，所述第一金属为镓，所述第二金属为铟。The fillers in the first deep trench structure 210 and the second deep trench structure 220 are both silicon dioxide, and the silicon dioxide material at the edges of the first deep trench structure 210 and the second deep trench structure 220 is doped with a first metal and a second metal, and the first metal is located outside the second metal, that is, the first metal is located at the outermost side of the edge of the first deep trench structure 210, and the first metal is located at the outermost side of the edge of the second deep trench structure 220. The element weight of the first metal is greater than the element weight of the second metal, so that the diffusion coefficient of the first metal is smaller than the diffusion coefficient of the second metal, and the first metal can be made into a smaller insulating layer to increase the area of the pixel unit. In this embodiment, the first metal is gallium and the second metal is indium.
所述叠层格栅结构310由下至上依次包括阻挡层301、第一金属层302和第二金属层303，所述阻挡层301的材料为HFO2，该材料可以抑制表面电子扩散，从而解决暗电流的问题。所述第一金属层302的材料可以为铝，所述第二金属层303的材料可以为氮化钽，以增加挡光的效果，并阻挡电子迁移至不该出现的区域，如红色像素单元中的电子迁移至蓝色素单元中。The stacked grid structure 310 includes a barrier layer 301, a first metal layer 302, and a second metal layer 303 from bottom to top. The barrier layer 301 is made of HFO 2 , which can inhibit surface electron diffusion, thereby solving the problem of dark current. The first metal layer 302 can be made of aluminum, and the second metal layer 303 can be made of tantalum nitride to increase the light blocking effect and prevent electrons from migrating to areas where they should not appear, such as electrons in red pixel units migrating to blue pixel units.
相邻所述叠层格栅结构310之间设置有彩色滤光片320，所述彩色滤光片320位于所述像素单元的上方。其中，所述彩色滤光片320包括但不限于三原色滤光片，即红色滤光片、蓝色滤光片和绿色滤光片，相邻所述叠层格栅结构310之间可以设置红色滤光片、蓝色滤光片和绿色滤光片中的一种，优选的，红色滤光片、蓝色滤光片和绿色滤光片周期性间隔设置在相邻所述叠层格栅结构310之间。Color filters 320 are arranged between adjacent laminated grid structures 310, and the color filters 320 are located above the pixel units. The color filters 320 include but are not limited to three primary color filters, namely, red filter, blue filter and green filter. One of the red filter, blue filter and green filter can be arranged between adjacent laminated grid structures 310. Preferably, the red filter, blue filter and green filter are arranged between adjacent laminated grid structures 310 at intervals.
本实施例还提供一种背照式图像传感器的制备方法，包括以下步骤：This embodiment also provides a method for preparing a back-illuminated image sensor, comprising the following steps:
步骤S1：在衬底一侧上依次形成第一半导体材料层、第二半导体材料层和第三半导体材料层，所述第一半导体材料层、第二半导体材料层和第三半导体材料层中均掺杂有四价元素，且掺杂的四价元素的原子重量由下至上依次减少；Step S1: forming a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer in sequence on one side of the substrate, wherein the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer are all doped with a tetravalent element, and the atomic weight of the doped tetravalent element decreases in sequence from bottom to top;
步骤S2：依次刻蚀所述第三半导体材料层、第二半导体材料层和第一半导体材料层，以形成第一深沟槽结构，同时，依次刻蚀所述第三半导体材料层和第二半导体材料层，以形成第二深沟槽结构，其中，每个所述第一深沟槽结构和一所述第二深沟槽结构相邻设置，且相邻所述第一深沟槽结构和第二深沟槽结构之间的第一半导体材料层、第二半导体材料层和第三半导体材料层构成像素单元；Step S2: etching the third semiconductor material layer, the second semiconductor material layer and the first semiconductor material layer in sequence to form a first deep trench structure, and at the same time, etching the third semiconductor material layer and the second semiconductor material layer in sequence to form a second deep trench structure, wherein each of the first deep trench structures and one of the second deep trench structures are adjacently arranged, and the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer between adjacent first deep trench structures and second deep trench structures constitute a pixel unit;
步骤S3：在所述像素单元上形成叠层格栅结构。Step S3: forming a stacked grid structure on the pixel unit.
以下结合图2-图11对本实施例提供的一种背照式图像传感器的制备方法进行详细说明。A method for preparing a back-illuminated image sensor provided in this embodiment is described in detail below with reference to FIGS. 2 to 11 .
步骤S1，在衬底100一侧上依次形成第一半导体材料层120、第二半导体材料层130和第三半导体材料层140，所述第一半导体材料层120、第二半导体材料层130和第三半导体材料层140中均掺杂有四价元素，且掺杂的四价元素的原子重量由下至上依次减少。Step S1, forming a first semiconductor material layer 120, a second semiconductor material layer 130 and a third semiconductor material layer 140 in sequence on one side of a substrate 100, wherein the first semiconductor material layer 120, the second semiconductor material layer 130 and the third semiconductor material layer 140 are all doped with tetravalent elements, and the atomic weight of the doped tetravalent elements decreases from bottom to top.
本步骤具体包括：This step specifically includes:
如图2所示，首先，提供衬底100，所述衬底100可以为硅衬底100。所述衬底100包括相对设置的正面100a和背面100b，所述正面100a形成有间隔设置的STI 101。所述衬底100中可以形成有CMOS逻辑器件等半导体器件。As shown in Fig. 2, first, a substrate 100 is provided, and the substrate 100 may be a silicon substrate 100. The substrate 100 includes a front side 100a and a back side 100b arranged opposite to each other, and the front side 100a is formed with a spaced STI 101. Semiconductor devices such as CMOS logic devices may be formed in the substrate 100.
接着，采用覆毯式(Blanket)的离子注入工艺，从所述正面100a对所述STI 101进行N型离子注入，以在所述STI 101靠近所述背面100b一侧形成停止层110，所述停止层110作为后续研磨停止层110。其中，所述N型离子可以为硼离子。Next, a blanket ion implantation process is used to implant N-type ions into the STI 101 from the front surface 100a to form a stop layer 110 on the side of the STI 101 close to the back surface 100b, and the stop layer 110 is used as a subsequent polishing stop layer 110. The N-type ions may be boron ions.
如图3所示，接着，在所述正面100a上形成金属互连结构102，所述金属互连结构102用于实现衬底100中的器件的互联导通。As shown in FIG. 3 , next, a metal interconnection structure 102 is formed on the front surface 100 a . The metal interconnection structure 102 is used to realize interconnection and conduction of devices in the substrate 100 .
如图4所示，接着，从所述背面100b通过CMP（Chemical-MechanicalPlanarization，化学机械抛光）减薄所述衬底100，并研磨停止在所述停止层110上。As shown in FIG. 4 , the substrate 100 is then thinned from the back side 100 b by CMP (Chemical-Mechanical Planning) and polished to stop on the stop layer 110 .
如图5所示，采用固相扩散（SPD，solid phase diffusion）在所述停止层110上依次形成第一半导体材料层120、第二半导体材料层130和第三半导体材料层140。As shown in FIG. 5 , a first semiconductor material layer 120 , a second semiconductor material layer 130 and a third semiconductor material layer 140 are sequentially formed on the stop layer 110 by solid phase diffusion (SPD).
所述第一半导体材料层120、第二半导体材料层130和第三半导体材料层140的形成方法相同。以形成所述第一半导体材料层120的形成步骤为例进行说明：先形成第一外延层，在所述第一外延层上形成具有掺杂元素的第一牺牲层，所述固相扩散通过进行热处理升高温度，使得具有掺杂元素的第一牺牲层中的掺杂元素扩散至所述第一外延层内。其中，所述第一牺牲层中掺杂元素为四价元素，例如锑元素，使得第一半导体材料层120中掺杂有锑元素。采用相同的工艺形成第二半导体材料层130和第三半导体材料层140，其中，所述第二半导体材料层130中掺杂有砷元素，所述第三半导体材料层140掺杂有磷元素。The formation methods of the first semiconductor material layer 120, the second semiconductor material layer 130 and the third semiconductor material layer 140 are the same. Take the formation steps of the first semiconductor material layer 120 as an example for explanation: first form a first epitaxial layer, form a first sacrificial layer with doping elements on the first epitaxial layer, and the solid phase diffusion increases the temperature by heat treatment so that the doping elements in the first sacrificial layer with doping elements diffuse into the first epitaxial layer. The doping element in the first sacrificial layer is a tetravalent element, such as antimony, so that the first semiconductor material layer 120 is doped with antimony. The second semiconductor material layer 130 and the third semiconductor material layer 140 are formed by the same process, wherein the second semiconductor material layer 130 is doped with arsenic, and the third semiconductor material layer 140 is doped with phosphorus.
接着执行步骤S2，依次刻蚀所述第三半导体材料层140、第二半导体材料层130和第一半导体材料层120，以形成第一深沟槽结构210，同时，依次刻蚀所述第三半导体材料层140和第二半导体材料层130，以形成第二深沟槽结构220，其中，每个所述第一深沟槽结构210和一所述第二深沟槽结构220相邻设置，且相邻所述第一深沟槽结构210和第二深沟槽结构220之间的第一半导体材料层120、第二半导体材料层130和第三半导体材料层140构成像素单元。Then, step S2 is performed to sequentially etch the third semiconductor material layer 140, the second semiconductor material layer 130 and the first semiconductor material layer 120 to form a first deep trench structure 210. At the same time, the third semiconductor material layer 140 and the second semiconductor material layer 130 are sequentially etched to form a second deep trench structure 220, wherein each of the first deep trench structures 210 and one of the second deep trench structures 220 are adjacently arranged, and the first semiconductor material layer 120, the second semiconductor material layer 130 and the third semiconductor material layer 140 between the adjacent first deep trench structures 210 and the second deep trench structures 220 constitute a pixel unit.
本步骤具体包括：This step specifically includes:
首先，通过沉积工艺在所述第三半导体材料层140上依次形成缓冲层150和硬掩模层160。其中，所述缓冲层150作为背照式图像传感器的透光保护层，其可以为氧化硅层，具体为二氧化硅层。所述硬掩模层160可以为氮化硅层。First, a buffer layer 150 and a hard mask layer 160 are sequentially formed on the third semiconductor material layer 140 by a deposition process. The buffer layer 150 is used as a light-transmitting protective layer of the back-illuminated image sensor, and can be a silicon oxide layer, specifically a silicon dioxide layer. The hard mask layer 160 can be a silicon nitride layer.
如图6所示，接着，通过刻蚀工艺依次刻蚀所述硬掩模层160和缓冲层150，以形成开口，所述开口定义所述第一深沟槽结构210和第二深沟槽结构220的形状。As shown in FIG. 6 , the hard mask layer 160 and the buffer layer 150 are then etched in sequence by an etching process to form openings, wherein the openings define the shapes of the first deep trench structure 210 and the second deep trench structure 220 .
接着，刻蚀所述硬掩模层160，以去除部分所述开口外侧的所述硬掩模层160，使得部分所述开口外侧仅具有缓冲层150（即第一开口），部分所述开口外侧具有堆叠设置的缓冲层150和硬掩模层160（即第二开口）。其中，每个第一开口均与一个第二开口相邻设置。Next, the hard mask layer 160 is etched to remove the hard mask layer 160 outside the openings, so that only the buffer layer 150 (i.e., the first opening) is located outside the openings, and the buffer layer 150 and the hard mask layer 160 (i.e., the second opening) are stacked outside the openings. Each first opening is adjacent to a second opening.
如图7所示，接着，采用干法刻蚀工艺在所述第一开口处形成第一深沟槽201，在所述第二开口处形成第二深沟槽202。与第一开口相比，第二开口的深宽比较大，使得干法刻蚀工艺中进入第二开口的刻蚀气体较少，这样形成的第二深沟槽202的深度较第一深沟槽201的深度浅。其中，所述第一深沟槽201由上至下依次贯通所述第三半导体材料层140、第二半导体材料层130、第一半导体材料层120和停止层110，以暴露出所述STI 101的底部，所述第二深沟槽202由上至下依次贯通所述第三半导体材料层140和第二半导体材料层130，且每个所述第二深沟槽结构220均与一个STI 101正对设置。As shown in FIG7 , then, a dry etching process is used to form a first deep trench 201 at the first opening, and a second deep trench 202 at the second opening. Compared with the first opening, the second opening has a larger depth-to-width ratio, so that less etching gas enters the second opening during the dry etching process, and the depth of the second deep trench 202 formed in this way is shallower than the depth of the first deep trench 201. The first deep trench 201 sequentially penetrates the third semiconductor material layer 140, the second semiconductor material layer 130, the first semiconductor material layer 120 and the stop layer 110 from top to bottom to expose the bottom of the STI 101, and the second deep trench 202 sequentially penetrates the third semiconductor material layer 140 and the second semiconductor material layer 130 from top to bottom, and each of the second deep trench structures 220 is arranged opposite to one STI 101.
接着，去除所述硬掩模层160。Next, the hard mask layer 160 is removed.
接着，在所述第一深沟槽201和第二深沟槽202中沉积填充物，所述填充物为硅、第一金属、第二金属的混合物，所述填充物还覆盖所述缓冲层150。其中，所述第一金属的元素重量较所述第二金属的元素重量大，例如，所述第一金属为镓，所述第二金属为铟。Next, a filler is deposited in the first deep trench 201 and the second deep trench 202, wherein the filler is a mixture of silicon, a first metal, and a second metal, and the filler also covers the buffer layer 150. The element weight of the first metal is greater than the element weight of the second metal, for example, the first metal is gallium, and the second metal is indium.
接着，通过CMP工艺去除所述缓冲层150上的所述填充物，形成初始第一深沟槽结构和初始第二深沟槽结构。Next, the filler on the buffer layer 150 is removed by a CMP process to form an initial first deep trench structure and an initial second deep trench structure.
如图8所示，接着，在氧气氛围下执行尖峰退火（Spike annealing）工艺，使得初始第一深沟槽结构的填充物中的第一金属和第二金属和镓扩散至初始第一深沟槽结构的边缘，且第一金属扩散至最外侧，第二金属位于所述第一金属内侧设置，同时，硅被氧气氧化形成二氧化硅，从而形成第一深沟槽结构，同样的，初始第二深沟槽结构的填充物中的第一金属和第二金属和镓扩散至初始第二深沟槽结构的边缘，且第一金属扩散至最外侧，第二金属位于所述第一金属内侧设置，同时，硅被氧气氧化形成二氧化硅，从而形成第二深沟槽结构。As shown in FIG8 , a spike annealing process is then performed in an oxygen atmosphere, so that the first metal, the second metal and gallium in the filler of the initial first deep trench structure diffuse to the edge of the initial first deep trench structure, and the first metal diffuses to the outermost side, and the second metal is disposed inside the first metal, and at the same time, silicon is oxidized by oxygen to form silicon dioxide, thereby forming a first deep trench structure. Similarly, the first metal, the second metal and gallium in the filler of the initial second deep trench structure diffuse to the edge of the initial second deep trench structure, and the first metal diffuses to the outermost side, and the second metal is disposed inside the first metal, and at the same time, silicon is oxidized by oxygen to form silicon dioxide, thereby forming a second deep trench structure.
这样，所述第一深沟槽结构210和第二深沟槽结构220中均填充有二氧化硅，且在第一深沟槽结构210中，所述第一金属位于所述第一深沟槽结构210的边缘处的最外侧，所述第二金属位于所述第一金属内侧；同样的，在第二深沟槽结构220中，所述第一金属位于所述第二深沟槽结构220的边缘处的最外侧，所述第二金属位于所述第一金属内侧。其中，所述第一金属的元素重量较所述第二金属的元素重量大，例如，所述第一金属为镓，所述第二金属为铟。Thus, the first deep trench structure 210 and the second deep trench structure 220 are both filled with silicon dioxide, and in the first deep trench structure 210, the first metal is located at the outermost side of the edge of the first deep trench structure 210, and the second metal is located inside the first metal; similarly, in the second deep trench structure 220, the first metal is located at the outermost side of the edge of the second deep trench structure 220, and the second metal is located inside the first metal. The element weight of the first metal is greater than the element weight of the second metal, for example, the first metal is gallium, and the second metal is indium.
接着执行步骤S3，在所述像素单元上形成叠层格栅结构310。Then, step S3 is performed to form a stacked grid structure 310 on the pixel unit.
本步骤具体包括：This step specifically includes:
如图9所示，首先，通过沉积工艺在所述缓冲层150上依次沉积阻挡层301、第一金属层302和第二金属层303。As shown in FIG. 9 , first, a barrier layer 301 , a first metal layer 302 , and a second metal layer 303 are sequentially deposited on the buffer layer 150 through a deposition process.
如图10所示，接着，通过刻蚀工艺依次刻蚀所述第二金属层303、第一金属层302和阻挡层301，以形成叠层格栅结构310，所述叠层格栅结构310位于所述像素单元上方。其中，所述第一金属层302的材料可以为铝，所述第二金属层303的材料可以为氮化钽。As shown in Fig. 10, the second metal layer 303, the first metal layer 302 and the barrier layer 301 are then etched in sequence by an etching process to form a stacked grid structure 310, and the stacked grid structure 310 is located above the pixel unit. The material of the first metal layer 302 can be aluminum, and the material of the second metal layer 303 can be tantalum nitride.
如图11所示，接着，通过沉积工艺在所述叠层格栅结构310之间的所述阻挡层301上形成彩色滤光片320。As shown in FIG. 11 , then, a color filter 320 is formed on the barrier layer 301 between the stacked grid structures 310 by a deposition process.
综上所述，本发明提供一种背照式图像传感器及其制备方法，背照式图像传感器包括依次设置在衬底一侧的第一半导体材料层、第二半导体材料层和第三半导体材料层，所述第三半导体材料层、第二半导体材料层和第一半导体材料层中设置有第一深沟槽结构，所述第三半导体材料层和第二半导体材料层中设置有第二深沟槽结构，每个所述第一深沟槽结构和一所述第二深沟槽结构相邻设置，且相邻所述第一深沟槽结构和第二深沟槽结构之间的第一半导体材料层、第二半导体材料层和第三半导体材料层构成像素单元，所述像素单元上形成有叠层格栅结构，其中，所述第一半导体材料层、第二半导体材料层和第三半导体材料层中均掺杂有四价元素，且掺杂的四价元素的原子重量由下至上依次减少，可以解决现有技术中因离子注入形成的像素单元造成的干扰效应问题。In summary, the present invention provides a back-illuminated image sensor and a preparation method thereof. The back-illuminated image sensor includes a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer which are sequentially arranged on one side of a substrate. A first deep trench structure is arranged in the third semiconductor material layer, the second semiconductor material layer and the first semiconductor material layer, and a second deep trench structure is arranged in the third semiconductor material layer and the second semiconductor material layer. Each of the first deep trench structures and one of the second deep trench structures are adjacent to each other, and the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer between adjacent first deep trench structures and second deep trench structures constitute a pixel unit. A stacked grid structure is formed on the pixel unit, wherein the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer are all doped with tetravalent elements, and the atomic weight of the doped tetravalent elements decreases from bottom to top, which can solve the interference effect problem caused by the pixel unit formed by ion implantation in the prior art.
另外，所述叠层格栅结构由下至上依次包括阻挡层、第一金属层和第二金属层，所述阻挡层的材料为HFO2，以抑制表面电子扩散，从而解决暗电流的问题。In addition, the stacked grid structure includes a barrier layer, a first metal layer and a second metal layer in order from bottom to top. The barrier layer is made of HFO 2 to suppress surface electron diffusion, thereby solving the problem of dark current.
此外，需要说明的是，除非特别说明或者指出，否则说明书中的术语 “第一”、“第二”的描述仅仅用于区分说明书中的各个组件、元素、步骤等，而不是用于表示各个组件、元素、步骤之间的逻辑关系或者顺序关系等。In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.
可以理解的是，虽然本发明已以较佳实施例披露如上，然而上述实施例并非用以限定本发明。对于任何熟悉本领域的技术人员而言，在不脱离本发明技术方案范围情况下，都可利用上述揭示的技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。It is to be understood that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.
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| CN119815950B (en) * | 2025-01-23 | 2025-06-13 | 合肥晶合集成电路股份有限公司 | Image sensor and preparation method thereof |
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