CN1183710C - Code on-line parallel loading method for communication apparatus microprocessor - Google Patents

Abstract

The present invention relates to a code on-line parallel loading method for microprocessors of communication apparatuses. The method saves a code file of a microprocessor in a read only memory of a main control plate; code loading control registers of the same type of microprocessor of all service plates are mapped in the same section of addressing space of a main control central processing unit through an address decoding mode; simultaneously, the main control central processing unit reserves a section of address mapping independently for each loading control register of the microprocessor of each service plate in the addressing space; when the main control central processing unit operates a public code loading controller for writing data, each service plate simultaneously receives the data loaded in a random access memory for realizing parallel loading. The present invention can largely reduce the expensive time of loading microprocessor codes when a system is started under the condition that hardware cost is not increased.

Description

The online while loading method of communication equipment microprocessor code polylith business board

Affiliated field:

The present invention relates to the online while loading method of microprocessor code polylith business board, as programmable logic device (PLD) and Digital Signal Processing microprocessors such as (DSP), relate in particular to the online while loading method of microprocessor code polylith business board on the communication equipment.

Background technology:

At present, communication equipment such as digital SLM subscriber loop multiplex device DSLAM (Digital SubscriberLine Access Multiplexer) equipment adopts the modulation and demodulation signal of DSP process user circuit pack mostly, or the solution that adopts professional chip manufacturer to provide, comprise the chipset (general embedded DSP) that is called nest plate and drive code, and adopt programmable logic device (as on-site programmable gate array FPGA) to finish the subscriber's line two-layer protocol to the adaption function of exchcange core two-layer protocol and forwarding fast.The code of programmable logic device and nest plate microprocessors such as (or DSP) generally is stored in power down such as electricallyerasable ROM (EEROM) EEPROM and flash memory FLASH not in the read only memory ROM of obliterated data, then is loaded into operation fast among the static memory SRAM after system powers on from ROM.The code of some microprocessor is little, self is integrated in low capacity ROM preservations such as EEPROM, reads code automatically by microprocessor from memory after system powers on and loads fast, need not the intervention of master control.For the big microprocessor of code, self there is not integrated ROM for reasons such as costs, preservation codes such as ROM (as FLASH) need be provided by system, be loaded among the SRAM by the cooperation of master control software and hardware after the system start-up.Loading microprocessor code when communication device initiated need take a long time, especially along with the communication equipment deal with data becomes increasingly complex, number of users more and more, cause size of code increase, equipment user's business board of microprocessors such as programmable logic device or DSP to increase.Traditional method be communication equipment in turn to every customer service plate loading code, but size of code is big and the customer service plate for a long time, the time of system loads code can not put up with, system upgrade or restart after need considerable time could recover customer service.

European patent EP 0306855 " Arrangement for loading the parameters intoactive modules in a computer system " has been announced the method that multimode computer system each module in running can not be obtained system's real-time running state information problem efficiently that solves.Traditional method is the directly parallel connection of the input port of each module, by existing data wire and address wire reading of data, therefore each module can only read information in limited connection and official hour, and needs specific decoder with the parallel encoding data decode.This patent provides a kind of plug-in card to insert in the computer system and addresses the above problem.Need the extra hardware cost that increases.The present invention is not then needing additionally to increase under the situation of hardware cost, only passes through the just loaded in parallel of code of memory-mapped.Indication of the present invention " walking abreast " is meant the polylith Target Board loaded simultaneously simultaneously, but not loads by parallel port.

Summary of the invention:

The objective of the invention is on communication equipment, to realize the online loading simultaneously of polylith business board of microprocessor code such as programmable logic device, nest plate or DSP.

The invention provides a kind of method that realizes microprocessor code such as the online while programmable logic device of polylith business board, nest plate or DSP on communication equipment, its scheme is as follows:

Communication equipment generally comprises user interface business board, backboard, master control borad.Wherein, master control borad comprises exchcange core module, master control CPU module, upstream Interface module; Backboard is finished being connected of master control borad and user interface business board; The user interface business board comprises subscriber's line data modem module and two-layer protocol adaptation module.Microprocessors such as programmable logic device, network nest plate and DSP are positioned on the user interface business board.

The microprocessor code file is remained on together among the ROM of master control borad, mode by address decoding is with the code Loading Control register mappings of same a kind of microprocessor code of all business boards in the same segment addressing space of master cpu (being called the public code loading control), and master cpu shines upon for the microprocessor code Loading Control register of each business board keeps a sector address separately in addressing space simultaneously.When master cpu operation public code loading control writes data, same a kind of microprocessor of each business board receives data load simultaneously in its RAM, realize loaded in parallel, the code load time of all business boards of equipment is equivalent to the load time of a business board like this, has significantly reduced the start-up time of system.

Master cpu can be inquired about the corresponding code Loading Control of each business board register detection of code loaded condition in loading procedure, if find to have business board to load failure or other reason (as resetting at system's business board in service or heat is inserted) need be to the independent loading code of a certain business board the time, master cpu is operated independently code control register of this business board, realizes this business board is loaded separately.Realized simultaneously the business board code of all business board codes of loaded in parallel and independent loading selected neatly.

Beneficial effect of the present invention:

The time of loading code cost when the present invention can significantly reduce system start-up under the situation that does not increase hardware cost increases system start-up speed, makes communication equipment quick-recovery customer service soon in upgrading or after restarting.

Description of drawings:

The system construction drawing of Fig. 1 communication equipment

Fig. 2 FPGA code Loading Control signal and nest plate code Loading Control register and CPU addressing space mapping schematic diagram

All business board loaded in parallel FPGA code flow schematic diagrames of Fig. 3

Fig. 4 business board 1 loads FPGA code flow schematic diagram separately

Specific embodiment:

The present invention is further described below in conjunction with drawings and Examples.

The system construction drawing that it is communication equipments of the present invention that the present invention comprises system, hardware, three part: Fig. 1 of software.A is a master control borad, and B is a business board 1, and C is business board n, D is CPU, and E is FLASH, and F is the core exchange chip, G is synchronous DRAM SDRAM (Synchronous Dynamic RAM), F is complex programmable logic device (CPLD) (Complex Programable Logic Device), and I is the backboard high-speed bus, and J is a nest plate, K is FPGA, L is SRAM, (1) (2) (3) (4) expression data channel, and other lines are represented control channel.Be connected by the backboard high-speed bus between master control borad and each business board among Fig. 1, core bus carried out address decoding by CPLD.FGPA code and nest plate code are kept among the FLASH of master control borad, and system's back master cpu that powers on takes out code and is loaded into respectively among the SRAM of FPGA and nest plate by core bus from FLASH.

Fig. 2 is FPGA and code Loading Control signal and register and CPU addressing space mapping schematic diagram.A is CPU addressing space (D, E, F, G, H and J are respectively a segment addressing space), B is a business board 1, C is business board n, J is that (wherein (1) is data input signal DIN to FPGA Loading Control signal, (2) be clock signal C CLK, (3) be code signal PROG, (4) are to load to finish signal DONE), K is nest plate Loading Control register district.Among Fig. 2 the FPGA code Loading Control signal unification of all business boards is mapped to the D addressing space of CPU, the nest plate code Loading Control register unification of all business boards is mapped to the E addressing space of CPU; F and G shine upon the FPGA and the nest plate code Loading Control register of business board 1 respectively, and H and J shine upon FPGA and the nest plate code Loading Control register of business board n respectively.

Fig. 3 is loaded as example with the FPGA code the online flow process that loads simultaneously of all business boards is described respectively.The loading of nest plate code is similar with it, is that concrete register is provided with different.(having had microprocessor code among the FLASH before the system start-up)

Finish relevant initialization during first step system start-up, run to the initialization FPGA stage, from FLASH, take out the FPGA code, copy among the SDRAM;

Second goes on foot the FPGA of all business boards that reset.With being mapped to the PROG signal zero clearing of D address space, put 1 again, the FPGA of all business boards is resetted and remove the content of RAM, this moment, FPGA waited for loading code;

The 3rd step is to the FPGA of all business boards loading code.The code Loading Control sequential that provides according to FPGA, the Loading Control signal (see figure 3) of all business board FPGA by being mapped to the D address space, the FPGA code that will be positioned at SDRAM is loaded into the RAM of FPGA by turn, the CCLK clock line that enters data into the DIN holding wire 1 (see figure 2) relief FPGA of FPGA produces a rising edge, FPGA is saved in data interlock among the RAM, and FPGA carries out verification to the data that receive simultaneously.

The 4th step checked whether the FPGA of each business board loads success.After FPGA carries out verification and passes through the data of receiving,, otherwise export 0 in DONE signal output 1.Each business board will separately be checked, carries out subsequent treatment according to check result.Finish.

Fig. 4 is loaded as example with the FPGA code and illustrates that respectively monolithic business board (business board 1) loads flow process separately.The loading of nest plate code is similar with it, is that concrete register is provided with different.(system powers on or restarts before and had microprocessor code among the FLASH)

Finish relevant initialization during first step system start-up, run to the initialization FPGA stage, from FLASH, take out the FPGA code, copy among the SDRAM;

Second goes on foot the FPGA of all business boards 1 that reset.With being mapped to the PROG signal (see figure 3) zero clearing of F address space, put 1 again, the FPGA of business board 1 is resetted and remove the content of RAM, this moment, FPGA waited for loading code;

The 3rd step is to the FPGA of business board 1 loading code.The code Loading Control sequential that provides according to FPGA, by being mapped to the FPGA Loading Control signal (see figure 3) of F address space business board 1, the FPGA code that will be positioned at SDRAM is loaded into the RAM of FPGA by turn, the CCLK clock line that enters data into the DIN holding wire 1 (see figure 2) relief FPGA of FPGA produces a rising edge, FPGA is saved in data interlock among the RAM, and FPGA carries out verification to the data that receive simultaneously.

The 4th step checked whether the FPGA of business board 1 loads success.After FPGA carries out verification and passes through the data of receiving,, otherwise export 0 in DONE signal (being positioned at the DONE signal of F address space) output 1.Finish.

Claims (2)

1. online while loading method of communication equipment microprocessor code polylith business board, the code storage of microprocessor is in read only memory ROM, be loaded into operation fast in the random access memory ram after system powers on from read-only memory, loading procedure may further comprise the steps:

One, finish relevant initialization during system start-up, the initialization microprocessor took out from flash memory and treats initialized microprocessor code during the stage, copied in the memory of master cpu;

Two, the microprocessor of all business boards of warm reset resets the reseting register in the public code loading control;

Three, to the microprocessor loading code of all business boards, will be arranged in the microprocessor code of the memory of master cpu, be written to the public code loading control, each business board microprocessor carries out verification to the data that receive, and data are saved among the RAM;

Four, whether the microprocessor code of checking each business board loads success, and each business board separately checks, microprocessor will indicate to be changed to load successfully after the data of receiving are carried out verification and passed through accordingly.

2. the online while loading method of communication equipment microprocessor code polylith business board according to claim 1, it is characterized in that: master cpu is inquired about the corresponding code Loading Control of each business board register detection of code stress state in loading procedure, if find to have business board to load in failure cause or the system's running that business board resets or heat is inserted reason need be to the independent loading code of a certain business board the time, master cpu is operated independently code control register of this business board, and this business board is loaded separately.

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