CN118353458A

CN118353458A - Low-noise reference driving circuit based on output sampling feedback

Info

Publication number: CN118353458A
Application number: CN202410243691.1A
Authority: CN
Inventors: 李福乐; 池保勇; 沈凌霄; 周科吉; 袁胜丽; 张跃
Original assignee: Chengdu Jiujin Technology Co ltd; Tsinghua University
Current assignee: Chengdu Jiujin Technology Co ltd; Tsinghua University
Filing date: 2024-03-04
Publication date: 2024-07-16

Abstract

The application relates to the technical field of circuit development, in particular to a low-noise reference driving circuit based on output sampling feedback, which comprises the following components: the single slip circuit is used for outputting a first bias voltage and a second bias voltage; the driving circuit comprises a first capacitor, a switch capacitor network, a second capacitor and a switch capacitor network, and is used for outputting a first driving voltage at the current moment according to a first driving voltage and a first bias voltage at the last moment acquired by the first capacitor and the switch capacitor network and outputting a second driving voltage according to a second driving voltage and a second bias voltage at the last moment acquired by the second capacitor and the switch capacitor network. Therefore, the problems of voltage jitter caused by current extraction at the later stage, power consumption, noise and the like caused by the duplication branch are solved, a sampling feedback network is formed by using the capacitor and the switch capacitor, the introduction of the duplication branch is avoided, the power consumption of a circuit is reduced, and meanwhile, the output noise is reduced.

Description

Low-noise reference driving circuit based on output sampling feedback

Technical Field

The application relates to the field of circuit development, in particular to a low-noise reference driving circuit based on output sampling feedback.

Background

In a traditional high sampling rate analog-to-digital converter, an internal reference voltage driving circuit is generally used for improving the driving precision of a reference voltage, with the improvement of the sampling rate, the available recovery time of the voltage of the reference voltage circuit is shortened, the reference voltage circuit only consumes more current for improving the establishment speed of an output voltage, and the precision of the analog-to-digital converter is ensured.

In the related art, a common implementation mode is that an on-chip narrow-band source follower is matched with an off-chip large decoupling capacitor, load impact is absorbed through the large capacitor, and another implementation mode is that an on-chip wide-band reference voltage driving circuit is adopted and consists of a low-speed closed-loop negative feedback loop and a high-speed open-loop source follower circuit, so that the high-speed high-precision requirement is realized.

However, the above-mentioned manner of coupling the on-chip narrow-band source follower to the off-chip large decoupling capacitor requires adding an additional PAD (PAD), increasing the area, and the parasitism of the semiconductor bond Wire (Bonding Wire) may generate oscillation, reducing the stability; the above-mentioned method of using the on-chip broadband reference voltage driving circuit can cause the problems of high power consumption and large noise in the duplication branch, and needs to be improved.

Disclosure of Invention

The application provides a low-noise reference driving circuit based on output sampling feedback, which aims to solve the problems of voltage jitter caused by current extraction at a later stage, power consumption, noise and the like caused by a replication branch.

An embodiment of a first aspect of the present application provides a low noise reference driving circuit based on output sampling feedback, including: a single slip circuit and a drive circuit, wherein,

The single slip circuit is used for outputting a first bias voltage and a second bias voltage;

The driving circuit comprises a first capacitor, a switch capacitor network, a second capacitor and a switch capacitor network, and is used for outputting a first driving voltage at the current moment according to a first driving voltage at the last moment acquired by the first capacitor and the switch capacitor network and a first bias voltage, and outputting a second driving voltage according to a second driving voltage at the last moment acquired by the second capacitor and the switch capacitor network and a second bias voltage.

According to one embodiment of the application, the single slip circuit comprises a resistor network and a full differential operational amplifier, wherein the resistor network comprises:

One end of the first resistor is connected with a first reference voltage input node, and the other end of the first resistor is connected with a first input end of the full differential operational amplifier;

one end of the second resistor is respectively connected with the other end of the first resistor and the first input end of the full differential operational amplifier, and the other end of the second resistor is respectively connected with the first output end of the full differential operational amplifier and the driving circuit;

one end of the third resistor is connected with the ground input node, and the other end of the third resistor is connected with the second input end of the full differential operational amplifier;

And one end of the fourth resistor is respectively connected with the other end of the third resistor and the second input end of the full differential operational amplifier, and the other end of the fourth resistor is respectively connected with the second output end of the full differential operational amplifier and the driving circuit.

According to an embodiment of the present application, the driving circuit further includes:

the first input end of the first differential operational amplifier is connected with the first output end of the full differential operational amplifier, and the second input end of the first differential operational amplifier is connected with the first capacitor and the switched capacitor network;

The first input end of the second differential operational amplifier is connected with the second output end of the full differential operational amplifier, and the second input end of the second differential operational amplifier is connected with the second capacitor and the switched capacitor network;

The first input end of the filter circuit is connected with the output end of the first differential operational amplifier, and the second input end of the filter circuit is connected with the output end of the second differential operational amplifier;

the output driving branch circuit is respectively connected with the first output end of the filter circuit, the second output end of the filter circuit, the first capacitor and switch capacitor network and the second capacitor and switch capacitor network.

According to one embodiment of the application, the first capacitor and switched capacitor network comprises:

one end of the first capacitor is connected with the second input end of the first differential operational amplifier, and the other end of the first capacitor is connected with the grounding node;

one end of the first switch is respectively connected with one end of the first capacitor and the second input end of the first differential operational amplifier;

One end of the second switch is connected with the other end of the first switch, and the other end of the second switch is connected with the output driving branch circuit;

And one end of the second capacitor is connected with the connecting node between the first switch and the second switch, and the other end of the second capacitor is connected with the grounding node.

According to one embodiment of the application, the second capacitor and switched capacitor network comprises:

one end of the third capacitor is connected with the second input end of the second differential operational amplifier, and the other end of the third capacitor is connected with the grounding node;

one end of the third switch is respectively connected with one end of the third capacitor and the second input end of the second differential operational amplifier;

one end of the fourth switch is connected with the other end of the third switch, and the other end of the fourth switch is connected with the output driving branch circuit;

and one end of the fourth capacitor is connected with a connecting node between the third switch and the fourth switch, and the other end of the fourth capacitor is connected with the grounding node.

According to one embodiment of the application, the filter circuit comprises:

One end of the fifth resistor is connected with the output end of the first differential operational amplifier, and the other end of the fifth resistor is connected with the output driving branch circuit;

One end of the sixth resistor is connected with the output end of the second differential operational amplifier, and the other end of the sixth resistor is connected with the output driving branch circuit;

And one end of the fifth capacitor is connected with a connecting node between the fifth resistor and the output driving branch, and the other end of the fifth capacitor is connected with a connecting node between the sixth resistor and the output driving branch.

According to one embodiment of the present application, one ends of the first capacitor to the fifth capacitor are positive ends, and the other ends of the first capacitor to the fifth capacitor are negative ends.

According to one embodiment of the present application, the output driving branch includes:

The grid electrode of the first switching tube is respectively connected with the other end of the fifth resistor and one end of the fifth capacitor, the drain electrode of the first switching tube is connected with a power supply access node, and the source electrode of the first switching tube is connected with the other end of the second switch;

The grid electrode of the second switching tube is respectively connected with the other end of the sixth resistor and the other end of the fifth capacitor, the drain electrode of the second switching tube is respectively connected with the source electrode of the first switching tube and the other end of the second switch, and the source stage of the second switching tube is connected with the other end of the fourth switch;

The drain electrode of the third switching tube is respectively connected with the source electrode of the second switching tube and the other end of the fourth switch, and the source electrode of the third switching tube is connected with the grounding node;

The source electrode of the fourth switching tube is connected with the grounding node;

And the grid electrode of the fifth switching tube is connected with the grid electrode of the second switching tube, the source electrode of the fifth switching tube is connected with the drain electrode of the fourth switching tube, and the drain electrode of the fifth switching tube is respectively connected with the grid electrode of the fourth switching tube and the power supply access node.

According to an embodiment of the present application, the output driving branch further includes:

One end of the seventh resistor is connected with the grid electrode of the fourth switching tube and the drain electrode of the fifth switching tube respectively, and the other end of the seventh resistor is connected with the grid electrode of the third switching tube;

And one end of the sixth capacitor is connected with the connecting node between the seventh resistor and the third switching tube, and the other end of the sixth capacitor is connected with the grounding node.

One end of the sixth capacitor is a positive electrode end, and the other end of the sixth capacitor is a negative electrode end.

According to one embodiment of the application, the first switch and the third switch operate in a first phase and the second switch and the fourth switch operate in a second phase, wherein the first phase and the second phase are non-overlapping phases.

According to the low-noise reference driving circuit based on output sampling feedback, a single slip circuit outputs a first bias voltage and a second bias voltage; the driving circuit outputs a first driving voltage at the current moment according to a first driving voltage and a first bias voltage at the last moment acquired by the first capacitor and the switched capacitor network, and outputs a second driving voltage according to a second driving voltage and a second bias voltage at the last moment acquired by the second capacitor and the switched capacitor network. Therefore, the problems of voltage jitter caused by current extraction at the later stage, power consumption, noise and the like caused by the duplication branch are solved, a sampling feedback network is formed by using the capacitor and the switch capacitor, the introduction of the duplication branch is avoided, the power consumption of a circuit is reduced, and meanwhile, the output noise is reduced.

Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.

Drawings

The foregoing and/or additional aspects and advantages of the application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a conventional reference voltage single slip driving circuit;

fig. 2 is a schematic structural diagram of a low noise reference driving circuit based on output sampling feedback according to an embodiment of the present application.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present application and should not be construed as limiting the application.

The application provides a low-noise reference driving circuit based on output sampling feedback, which aims at solving the problems of voltage jitter caused by post-stage extraction current, power consumption, noise and the like caused by a replication branch and provides a single slip circuit for outputting a first bias voltage and a second bias voltage; the driving circuit outputs a first driving voltage at the current moment according to a first driving voltage and a first bias voltage at the last moment acquired by the first capacitor and the switched capacitor network, and outputs a second driving voltage according to a second driving voltage and a second bias voltage at the last moment acquired by the second capacitor and the switched capacitor network. Therefore, the problems of voltage jitter caused by current extraction at the later stage, power consumption, noise and the like caused by the duplication branch are solved, a sampling feedback network is formed by using the capacitor and the switch capacitor, the introduction of the duplication branch is avoided, the power consumption of a circuit is reduced, and meanwhile, the output noise is reduced.

Before describing the low noise reference driving circuit based on output sampling feedback of the present application, a conventional wideband reference voltage single slip driving circuit will be described first. Specifically, as shown in fig. 1, the broadband reference voltage single slip drive circuit is composed of a single slip circuit, a closed loop drive loop, a low pass filter, and an output drive branch.

The single slip circuit is composed of a resistor network and a full differential operational amplifier OTA, and converts single-ended input reference VREF into differential reference voltages VRP1 and VRN1, wherein VRP1=VCM+VREF/2 and VRN1=VCM-VREF/2.

Further, the closed-loop driving loop is composed of operational amplifiers OP1, OP2 and a replication branch, outputs vrp2=vrp1 and vrn2=vrn1, the replication branch is composed of NMOS transistors MN1, MN2 and MN3, wherein MN3 provides bias current, and MN1 and MN2 constitute a source follower.

Further, the low-pass filter circuit is composed of resistors R5 and R6 and a capacitor C1, performs low-pass filtering on the voltage output by the closed-loop driving loop, and isolates kickback interference of a subsequent output driving branch.

Further, the output driving branch is formed by NMOS transistors MN4, MN5 and MN6, wherein MN6 provides bias current, MN4 and MN5 form a source follower, the output branch is designed according to K times of the replica branch, and is used for driving differential reference voltages VREFP and VREFN, and since the output driving branch and the replica branch are designed in proportion, vrefp=vrp2, vrefn=vrn2, and finally vrefp=vcm+vref/2, vrefn=vcm-VREF/2, and the whole circuit realizes single slip and output driving.

As can be seen from the above description, the closed-loop driving circuit generates the gate driving voltage required by the output driving branch by embedding the replica branch which is proportionally matched with the output driving branch, so as to drive the positive and negative reference voltages with accurately controllable output. Specific analysis can find that in the traditional broadband reference voltage driving circuit, extra current consumption is generated by the replication branch, in order to reduce the power consumption, the current of the replication branch is usually smaller, so that the noise of an NMOS (N-channel metal oxide semiconductor) tube on the replication branch is larger, and the noise of the MOS tube is not inhibited by the fact that the NMOS tube on the replication branch is connected into a source follower, so that the noise on the replication branch cannot be ignored; and the copy branch and the drive branch are not identical, and there are differences between VRP2 and VRN2 and between VREFP and VREFN.

Aiming at the problems of power consumption of the traditional circuit in fig. 1, the problem that the bias current of the copying branch is smaller and thus the noise of the MOS tube is larger due to the reduction of the power consumption, and the problem that the voltages VRP2 and VRN2 on the copying branch are not the voltages VREFP and VREFN on the driving branch and are possibly unmatched due to the reduction of the power consumption, the low-noise reference driving circuit based on output sampling feedback reduces the copying branch to reduce the power consumption and the noise, and the circuit provided by the application directly samples and feeds back the output voltage of the driving branch to eliminate the unmatched problem, so that more accurate output voltage is realized.

Specifically, fig. 2 is a schematic structural diagram of a low noise reference driving circuit 10 based on output sampling feedback according to an embodiment of the present application.

As shown in fig. 2, the low noise reference driving circuit 10 based on output sampling feedback includes: a single slip circuit 100 and a driving circuit 200, wherein the single slip circuit 100 is configured to output a first bias voltage and a second bias voltage; the driving circuit 200 includes a first capacitor and switch capacitor network 201, a second capacitor and switch capacitor network 202, and the driving circuit 200 is configured to output a first driving voltage at a current time according to a first driving voltage and a first bias voltage at a previous time acquired by the first capacitor and switch capacitor network 201, and output a second driving voltage according to a second driving voltage and a second bias voltage at a previous time acquired by the second capacitor and switch capacitor network 202.

Wherein the first bias voltage is VCM+VREF/2, the second bias voltage is VCM-VREF/2, VREF is the first reference voltage, and VCM is the second reference voltage.

Specifically, the driving circuit 200 receives the stable first bias voltage and the stable second bias voltage provided by the single slip circuit 100 and outputs a driving current, generates the first driving voltage and the second driving voltage, and the driving circuit 200 does not need to copy a branch circuit, and forms a sampling feedback network by using a capacitor and a switched capacitor, so that the influence of capacitance switching of the output ends VRP and VRN on the differential operational amplifier input end can be isolated, the power consumption of the circuit is reduced, and the output noise is reduced.

Further, in some embodiments, as shown in fig. 2, the single slip circuit 100 includes a resistor network and a full differential operational amplifier OTA, wherein the resistor network includes: one end of the first resistor R1 is connected with a first reference voltage VREF input node, and the other end of the first resistor R1 is connected with a first input end of the full-differential operational amplifier OTA; one end of the second resistor R2 is respectively connected with the other end of the first resistor R1 and the first input end of the full differential operational amplifier OTA, and the other end of the second resistor R2 is respectively connected with the first output end of the full differential operational amplifier OTA and the driving circuit 200; one end of the third resistor R3 is connected with the grounding input node, and the other end of the third resistor R3 is connected with the second input end of the full-differential operational amplifier OTA; and one end of the fourth resistor R4 is respectively connected with the other end of the third resistor R3 and the second input end of the full differential operational amplifier OTA, and the other end of the fourth resistor R4 is respectively connected with the second output end of the full differential operational amplifier OTA and the driving circuit 200.

The first input end of the full differential operational amplifier OTA is the positive input end of the full differential operational amplifier OTA, the first output end of the full differential operational amplifier OTA is the negative output end of the full differential operational amplifier OTA, the second input end of the full differential operational amplifier OTA is the negative input end of the full differential operational amplifier OTA, and the second output end of the full differential operational amplifier OTA is the positive output end of the full differential operational amplifier OTA.

Specifically, as shown in fig. 2, the resistor network is composed of a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4, one end of the first resistor R1 is connected to a first reference voltage VREF, the other end is connected to a positive input end of the full differential operational amplifier OTA, one end of the second resistor R2 is connected to a positive input end of the full differential operational amplifier OTA, the other end is connected to a negative output end of the full differential operational amplifier OTA, one end of the third resistor R3 is connected to ground, the other end is connected to a negative input end of the full differential operational amplifier OTA, one end of the fourth resistor R4 is connected to a negative input end of the full differential operational amplifier OTA, the other end is connected to a positive output end of the full differential operational amplifier OTA, and one end of the full differential operational amplifier OTA is further connected to a second reference voltage VCM input node.

Further, in some embodiments, as shown in fig. 2, the driving circuit 200 further includes: the first differential operational amplifier OP1, a first input end of the first differential operational amplifier OP1 is connected with a first output end of the full differential operational amplifier OTA, and a second input end of the first differential operational amplifier OP1 is connected with the first capacitor and the switched capacitor network 201; the first input end of the second differential operational amplifier OP2 is connected with the second output end of the full differential operational amplifier OTA, and the second input end of the second differential operational amplifier OP2 is connected with the second capacitor and the switched capacitor network 202; the first input end of the filter circuit 203 is connected with the output end of the first differential operational amplifier OP1, and the second input end of the filter circuit 203 is connected with the output end of the second differential operational amplifier OP 2; the output driving branch 204, the output driving branch 204 is connected to the first output terminal of the filter circuit 203, the second output terminal of the filter circuit 203, the first capacitor and switch capacitor network 201 and the second capacitor and switch capacitor network 202, respectively.

The first input end of the first differential operational amplifier OP1 is the positive input end of the first differential operational amplifier OP1, and the second input end of the first differential operational amplifier OP1 is the negative input end of the first differential operational amplifier OP 1; the first input end of the second differential operational amplifier OP2 is the positive input end of the second differential operational amplifier OP2, and the second input end of the second differential operational amplifier OP2 is the negative input end of the second differential operational amplifier OP 2.

Specifically, the driving circuit 200 is composed of a first differential operational amplifier OP1, a second differential operational amplifier OP2, a first capacitor and switch capacitor network 201, a second capacitor and switch capacitor network 202, a filter circuit 203 and an output driving branch 204, wherein the positive input end of the first differential operational amplifier OP1 is connected with the negative output end of the full differential operational amplifier OTA, and the positive input end of the second differential operational amplifier OP2 is connected with the positive output end of the full differential operational amplifier OTA; the output ends of the first differential operational amplifier OP1 and the second differential operational amplifier OP2 are respectively connected with the filter circuit 203.

Further, the first differential operational amplifier OP1 is configured to detect the voltage output by the negative output end of the single slip circuit 100 and the VRP voltage output by the output driving branch 204, and the output signal of the first differential operational amplifier OP1 passes through the filter circuit 203 to adjust the output VRP of the output driving branch 204. The second differential operational amplifier OP2 is configured to detect the voltage output by the positive output terminal of the single slip circuit 100 and the VRN voltage output by the output driving branch 204, and the output signal of the second differential operational amplifier OP2 passes through the filter circuit 203 to adjust the output VRN of the output driving branch 204. The first differential operational amplifier OP1 and the second differential operational amplifier OP2 realize the isolation of the single slip circuit 100 by the later stage circuit, thereby ensuring the stability of the output of the single slip circuit 100.

Further, in some embodiments, as shown in fig. 2, the first capacitor and switched capacitor network 201 comprises: one end of the first capacitor C1 is connected with the second input end of the first differential operational amplifier OP1, and the other end of the first capacitor C1 is connected with the grounding node; one end of the first switch S1 is respectively connected with one end of the first capacitor C1 and the second input end of the first differential operational amplifier OP 1; the second switch S2, one end of the second switch S2 is connected with the other end of the first switch S1, and the other end of the second switch S2 is connected with the output driving branch 204; and one end of the second capacitor C2 is connected with a connecting node between the first switch S1 and the second switch S2.

Specifically, the first capacitor and switched capacitor network 201 is composed of a first capacitor C1, a first switch S1, a second capacitor C2 and a second switch S2, wherein the first switch S1, the second capacitor C2 and the second switch S2 form a first switched capacitor, a positive plate of the first capacitor C1 is connected to a positive plate of the second capacitor C2 through the first switch S1, the positive plate of the first capacitor C1 is also connected with a negative input end of the first differential operational amplifier OP1, and a negative plate of the first capacitor C1 is grounded; the positive plate of the second capacitor C2 is connected to the negative input end of the first differential operational amplifier OP1 through the first switch S1, the positive plate of the second capacitor C2 is also connected to the source of the first switch tube MN1 in the output driving branch 204 through the second switch S2, the source of the first switch tube MN1 directly outputs the reference voltage VRP, and the negative plate of the second capacitor C2 is grounded.

Further, in some embodiments, as shown in fig. 2, the second capacitor and switched capacitor network 202 includes: one end of the third capacitor C3 is connected with the second input end of the second differential operational amplifier OP2, and the other end of the third capacitor C3 is connected with the grounding node; one end of the third switch S3 is respectively connected with one end of the third capacitor C3 and the second input end of the second differential operational amplifier OP 2; a fourth switch S4, one end of the fourth switch S4 is connected to the other end of the third switch S3, and the other end of the fourth switch S4 is connected to the output driving branch 204; and one end of the fourth capacitor C4 is connected with a connecting node between the third switch S3 and the fourth switch S4, and the other end of the fourth capacitor C4 is connected with a grounding node.

Specifically, the second capacitor and switched capacitor network 202 is composed of a third capacitor C3, a third switch S3, a fourth capacitor C4 and a fourth switch S4, where the third switch S3, the fourth capacitor C4 and the fourth switch S4 form a second switched capacitor, a positive plate of the third capacitor C3 is connected to a positive plate of the fourth capacitor C4 through the third switch S3, a positive plate of the third capacitor C3 is further connected to a negative input terminal of the second differential amplifier OP2, a negative plate of the third capacitor C3 is grounded, a positive plate of the fourth capacitor C4 is connected to a negative input terminal of the second differential amplifier OP2 through the third switch S3, a positive plate of the fourth capacitor C4 is further connected to a source of the second switch tube MN2 in the output driving branch 204 through the fourth switch S4, the source of the second switch tube MN2 directly outputs the reference voltage VRN, and a negative plate of the fourth capacitor C4 is grounded.

Therefore, the output reference voltage is sampled by adopting the switch capacitor and then fed back to the input end of the differential operational amplifier, so that the introduction of a copying branch is avoided, the noise caused by the copying branch is reduced while the power consumption is reduced, meanwhile, the signal fed back to the input end of the differential operational amplifier is directly the output reference voltage signal, the problem that the voltage of the copying branch is different from that of the driving branch is solved, the circuit structure is simple, an additional chip bonding pad and an additional packaging pin are not required to be added, the power consumption of the circuit is reduced, and the circuit performance is optimized.

Further, in some embodiments, as shown in fig. 2, the filtering circuit 203 includes: a fifth resistor R5, one end of the fifth resistor R5 is connected to the output end of the first differential operational amplifier OP1, and the other end of the fifth resistor R5 is connected to the output driving branch 204; a sixth resistor R6, one end of the sixth resistor R6 is connected to the output end of the second differential operational amplifier OP2, and the other end of the sixth resistor R6 is connected to the output driving branch 204; and one end of the fifth capacitor C5 is connected with a connecting node between the fifth resistor R5 and the output driving branch 204, and the other end of the fifth capacitor C5 is connected with a connecting node between the sixth resistor R6 and the output driving branch 204.

In some embodiments, one ends of the first capacitor C1 to the fifth capacitor C5 are all positive ends, and the other ends of the first capacitor C1 to the fifth capacitor C5 are all negative ends.

Specifically, the filter circuit 203 is an RCR filter circuit, that is, is composed of a fifth resistor R5, a fifth capacitor C5, and a sixth resistor R6, one end of the fifth resistor R5 is connected to the output end of the first differential operational amplifier OP1, the other end of the fifth resistor R5 is connected to the positive plate of the fifth capacitor C5 and to the gate of the first switching tube MN1 in the output driving branch 204, one end of the sixth resistor R6 is connected to the output end of the second differential operational amplifier OP2, the other end of the sixth resistor R6 is connected to the negative plate of the fifth capacitor C5 and to the gate of the second switching tube MN2 in the output driving branch 204, so as to perform dc bias on the source follower and reduce the impact of jitter caused by high-frequency periodic charge extraction of the sampling capacitor coupled to the gate through the gate-source parasitic capacitance of the switching tube, and the fifth capacitor C5 is connected across the gates of the first switching tube MN1 and the second switching tube MN2 to further reduce the voltage fluctuation of the gate, thereby realizing the voltage stabilizing effect on the first switching tube MN1 and the second switching tube MN2 in the output driving branch 204.

Further, in some embodiments, as shown in fig. 2, the output drive leg 204 includes: the grid electrode of the first switching tube MN1 is respectively connected with the other end of the fifth resistor R5 and one end of the fifth capacitor C5, the drain electrode of the first switching tube MN1 is connected with the power supply access node, and the source electrode of the first switching tube MN1 is connected with the other end of the second switch S2; the grid electrode of the second switch tube MN2 is respectively connected with the other end of the sixth resistor R6 and the other end of the fifth capacitor C5, the drain electrode of the second switch tube MN2 is respectively connected with the source electrode of the first switch tube MN1 and the other end of the second switch S2, and the source electrode of the second switch tube MN2 is connected with the other end of the fourth switch S4; the drain electrode of the third switching tube MN3 is respectively connected with the source electrode of the second switching tube MN2 and the other end of the fourth switching tube S4, and the source electrode of the third switching tube MN3 is connected with a grounding node; the source electrode of the fourth switching tube MN4 is connected with the grounding node; and the grid electrode of the fifth switching tube MN5 is connected with the grid electrode of the second switching tube MN2, the source electrode of the fifth switching tube MN5 is connected with the drain electrode of the fourth switching tube MN4, and the drain electrode of the fifth switching tube MN5 is respectively connected with the grid electrode of the fourth switching tube MN4 and the power supply access node.

Preferably, the first switching tube MN1, the second switching tube MN2, the third switching tube MN3, the fourth switching tube MN4 and the fifth switching tube MN5 are all N-type MOS tubes, and the N-type MOS tubes have higher current efficiency, so that the size of the output tube can be reduced, and the parasitic capacitance of the output tube can be reduced; on the other hand, the PSRR of the circuit can be improved by adopting the N-type MOS tube, and the anti-interference capability is enhanced.

Specifically, the output driving branch circuit includes a first switching tube MN1, a second switching tube MN2, a third switching tube MN3, a fourth switching tube MN4, and a fifth switching tube MN5, where the first switching tube MN1 and the second switching tube MN2 are used as driving tubes, a source electrode of the first switching tube MN1 is connected to a drain electrode of the second switching tube MN2, and a drain electrode of the first switching tube MN1 is connected to a power supply VDD; the third switching tube MN3, the fourth switching tube MN4 and the fifth switching tube MN5 are used as current bias tubes, the drain electrode of the third switching tube MN3 is connected to the source electrode of the second switching tube MN2, the source electrode of the third switching tube MN3 is connected to the ground, the drain electrode of the fourth switching tube MN4 is connected to the source electrode of the fifth switching tube MN5, the source electrode of the fourth switching tube MN4 is connected to the ground, the grid electrode of the fifth switching tube MN5 is connected to the grid electrode of the second switching tube MN2, and the drain electrode of the fifth switching tube MN5 is connected to the grid electrode of the fourth switching tube MN4 and the output end of the bias current source; the grid electrode of the first switch tube MN1 is connected to the positive plate of a fifth capacitor C5 in the filter circuit 203, and the source electrode of the first switch tube MN1 is connected to the first capacitor and switch capacitor network 201; the gate of the second switching tube MN2 is connected to the negative plate of the capacitor C5 in the RCR filter circuit 203, and the source of the second switching tube MN2 is connected to the second capacitor and switched capacitor network 202.

Further, in some embodiments, as shown in fig. 2, the output drive leg 204 further includes: one end of the seventh resistor R7 is connected with the grid electrode of the fourth switching tube MN4 and the drain electrode of the fifth switching tube MN5 respectively, and the other end of the seventh resistor R7 is connected with the grid electrode of the third switching tube MN 3; and one end of the sixth capacitor C6 is connected with a connecting node between the seventh resistor R7 and the third switch tube MN3, and the other end of the sixth capacitor C6 is connected with a grounding node.

In some embodiments, one end of the sixth capacitor C6 is a positive end, and the other end of the sixth capacitor C6 is a negative end.

Specifically, a simple RC filter circuit is formed by the seventh resistor R7 and the sixth capacitor C6 to realize a voltage stabilizing effect for the gate voltage, one end of the seventh resistor R7 is connected to the gate of the fourth switching tube MN4, the other end of the seventh resistor R7 is connected to the gate of the third switching tube MN3 and the upper plate of the sixth capacitor C6, and the lower plate of the sixth capacitor C6 is grounded.

Further, in some embodiments, the first switch S1 and the third switch S3 operate in a first phase F1, and the second switch S2 and the fourth switch S4 operate in a second phase F2, wherein the first phase and the second phase are non-overlapping phases.

Specifically, at the first phase F1, the driving circuit 200 enters the holding phase, the second switch S2 and the fourth switch S4 are opened, the first switch S1 and the third switch S3 are closed, and positive plates of the second capacitor C2 and the fourth capacitor C4 are connected to positive plates of the first capacitor C1 and the third capacitor C3, respectively. The output driving branch is an open-loop source follower structure, has very high bandwidth and response speed, and the output voltages VRP and VRN are always completely established at the end of the first phase F1.

Further, at the second phase F2, the driving circuit 200 enters the sampling phase, the first switch S1 and the third switch S3 are opened, the second switch S2 and the fourth switch S4 are closed, and positive plates of the second capacitor C2 and the fourth capacitor C4 are connected to the output voltages VRP and VRN, respectively. Since the second capacitor C2 and the fourth capacitor C4 sample the output voltages VRP and VRN at the second phase F2, the output voltage is always sampled at the end of the second phase F2, that is, at the end point of the output voltage establishment, the transient impact of the latter circuit on the source buffer will not affect the feedback loop of the reference buffer.

Preferably, the source follower adopts an N-type MOS tube, so that the size of an output tube is reduced, the parasitic capacitance of the output tube is reduced, the PSRR of the circuit is improved, and the anti-interference capability is enhanced.

Therefore, the output is sampled at the second phase F2 by using the switch capacitor, the first phase F1 is connected to the input end of the differential operational amplifier, the first phase F1 and the second phase F2 are non-overlapped phases to replace the role of a duplication branch, and the end point established by the output voltage is always sampled when the output voltages VRP and VRN are sampled by the switch capacitor, so that the instantaneous impact of the rear-stage circuit on the source-stage buffer can not affect the feedback loop of the reference buffer.

According to the low-noise reference driving circuit based on output sampling feedback, a single slip circuit outputs a first bias voltage and a second bias voltage; the driving circuit outputs a first driving voltage at the current moment according to a first driving voltage and a first bias voltage at the last moment acquired by the first capacitor and the switched capacitor network, and outputs a second driving voltage according to a second driving voltage and a second bias voltage at the last moment acquired by the second capacitor and the switched capacitor network. Therefore, the problems of voltage jitter caused by current extraction at the later stage, power consumption, noise and the like caused by the duplication of the branch are solved, the capacitor and the switch capacitor are utilized to form a sampling feedback network, the introduction of the duplication of the branch is avoided, the circuit structure is simple, the large-capacity capacitor and the reference branch outside the chip are not needed, the circuit power consumption is reduced, the circuit performance is optimized, the universal type of the circuit is improved, and the circuit is convenient for practical use.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or N embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.

While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.

Claims

1. A low noise reference drive circuit based on output sampling feedback, comprising: a single slip circuit and a drive circuit, wherein,

2. The output sample feedback based low noise reference drive circuit of claim 1, wherein the single slip circuit comprises a resistor network and a full differential op-amp, wherein the resistor network comprises:

3. The low noise reference drive circuit based on output sample feedback of claim 2, wherein the drive circuit further comprises:

4. The output sample feedback based low noise reference drive circuit of claim 3, wherein the first capacitor and switched capacitor network comprises:

5. The output sample feedback based low noise reference drive circuit of claim 4, wherein the second capacitor and switched capacitor network comprises:

6. The low noise reference drive circuit based on output sample feedback of claim 5, wherein the filter circuit comprises:

7. The low noise reference driving circuit of claim 6, wherein one ends of the first to fifth capacitors are positive ends, and the other ends of the first to fifth capacitors are negative ends.

8. The output sample feedback based low noise reference drive circuit of claim 6, wherein the output drive leg comprises:

9. The output sample feedback based low noise reference drive circuit of claim 8, wherein the output drive leg further comprises:

one end of the sixth capacitor is connected with a connecting node between the seventh resistor and the third switching tube, and the other end of the sixth capacitor is connected with the grounding node;

10. The output sample feedback based low noise reference drive circuit of claim 6, wherein the first switch and the third switch operate in a first phase and the second switch and the fourth switch operate in a second phase, wherein the first phase and the second phase are non-overlapping phases.