CN118352308A

CN118352308A - Semiconductor structure and preparation method thereof

Info

Publication number: CN118352308A
Application number: CN202310027491.8A
Authority: CN
Inventors: 刘翔
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-01-09
Filing date: 2023-01-09
Publication date: 2024-07-16
Also published as: WO2024148757A1

Abstract

The present disclosure relates to a semiconductor structure and a method of fabricating the same, the method of fabricating the semiconductor structure comprising: providing a semiconductor substrate; forming a plurality of first isolation trenches in the semiconductor substrate at intervals; forming a plurality of gap grooves which are arranged at intervals in the semiconductor substrate, wherein the extending direction of the gap grooves is intersected with that of the first isolation grooves, and the bottom surfaces of the gap grooves are higher than the bottom surfaces of the first isolation grooves; forming a first patterned mask layer which covers and partially fills the gap trench, wherein an air gap is formed between the first patterned mask layer and the bottom of the gap trench; and etching the semiconductor substrate by taking the first patterned mask layer as a mask to form a second isolation trench, wherein the bottom surface of the second isolation trench is lower than the bottom surface of the gap trench, the second isolation trench and the first isolation trench isolate the semiconductor substrate into a plurality of active columns, and the active columns comprise a first sub-column and a second sub-column which are positioned at two sides of the air gap. The embodiment of the disclosure can improve the structural uniformity of the active column.

Description

Semiconductor structure and preparation method thereof

Technical Field

The present disclosure relates to the field of integrated circuit technology, and in particular, to a semiconductor structure and a method for fabricating the same.

Background

With the continued scaling of semiconductor device dimensions, the process and design of semiconductor chips has presented a new set of challenges. In order to reduce the area of individual array region transistors as much as possible, and pursue higher chip area utilization, vertical Channel Array Transistor (VCAT) technology has emerged.

However, for the vertical channel array transistor, since the top surface of the semiconductor active column is small in size, the uniformity of the structure is poor, and a positional deviation or a dimensional deviation is liable to occur, thereby affecting the performance of the memory array transistor.

Disclosure of Invention

Based on the above, the embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, which can effectively improve the structural uniformity of an active column.

A method of fabricating a semiconductor structure, comprising:

Providing a semiconductor substrate;

Forming a plurality of first isolation trenches in the semiconductor substrate at intervals;

Forming a plurality of gap grooves which are arranged at intervals in the semiconductor substrate, wherein the extending direction of the gap grooves is intersected with the extending direction of the first isolation groove, and the bottom surface of the gap grooves is higher than the bottom surface of the first isolation groove;

forming a first patterned mask layer which covers and partially fills the gap trench, wherein an air gap is formed between the first patterned mask layer and the bottom of the gap trench;

And etching the semiconductor substrate by taking the first patterned mask layer as a mask to form a second isolation trench, wherein the bottom surface of the second isolation trench is lower than the bottom surface of the gap trench, the second isolation trench and the first isolation trench isolate the semiconductor substrate into a plurality of active pillars, and the active pillars comprise a first sub-pillar and a second sub-pillar which are positioned at two sides of the air gap.

In one of the embodiments of the present invention,

The forming a plurality of gap trenches in the semiconductor substrate, wherein the gap trenches are arranged at intervals, comprises:

Forming a second patterned mask layer on the semiconductor substrate;

And forming the clearance groove based on the second patterned mask layer.

In one embodiment, the second patterned mask layer includes a second mask pattern and a mask sidewall located on a sidewall of the second mask pattern;

the forming a first patterned mask layer covering the gap trench includes:

Filling a first mask pattern in an opening area of the second patterned mask layer, wherein the first mask pattern partially fills the gap groove;

and removing the second mask pattern, and forming the first patterned mask layer by the reserved mask side wall and the first mask pattern.

In one embodiment, the first mask pattern is made of the same material as the mask sidewall.

In one embodiment, the forming a second patterned mask layer on the semiconductor substrate includes:

forming a second mask pattern on the semiconductor substrate;

Forming a side wall material layer on the surface of the second mask pattern and the surface of the semiconductor substrate;

and carrying out anisotropic etching on the side wall material layer to form a mask side wall positioned on the side wall of the second mask pattern.

In one embodiment, the forming the second mask pattern on the semiconductor substrate includes:

forming a third patterned mask layer on the semiconductor substrate;

forming the second mask pattern in the opening of the third patterned mask layer;

and removing the third patterned mask layer.

In one embodiment, after forming a plurality of spaced gap trenches in the semiconductor substrate, the method further includes:

and forming an insulating medium layer on the side wall and the bottom of the semiconductor substrate exposed in the clearance groove.

In one embodiment, the first patterned mask layer is a mask, and after etching the semiconductor substrate, the method further includes:

And forming word lines on the outer side walls of the first sub-column and the second sub-column.

In one embodiment, the forming the word line at the sidewalls of the first sub-pillar and the second sub-pillar includes:

Forming a liner isolation layer in the second isolation trench between the active pillars;

Sequentially forming a gate dielectric material layer on the upper surface of the liner isolation layer, the side walls of the first sub-column and the second sub-column, the side wall of the first patterned mask layer and the upper surface;

Forming a word line material layer on the surface of the gate dielectric material layer;

And anisotropically etching the word line material layer to form the word line.

In one embodiment, the forming a liner spacer layer in the region between the active pillars comprises:

Forming a liner isolation material layer covering the first patterned mask layer and filling the second isolation trench;

taking the first patterned mask layer as a polishing stop layer, and carrying out chemical mechanical polishing treatment on the liner isolation material layer;

and carrying out back etching on the liner isolation material layer subjected to chemical mechanical polishing treatment to form the liner isolation layer.

In one embodiment, the anisotropic etching of the word line material layer, after forming the word lines on both sides of the air gap, includes:

forming a filling isolation material layer covering the first patterned mask layer, the active column, the word line and the liner isolation layer;

And removing the filling isolation material layer and the first patterned mask layer above the active column through chemical mechanical polishing, wherein the remaining filling isolation material layer forms a filling isolation layer, and the remaining first patterned mask layer forms a gap sealing layer.

In one embodiment, after the forming of the plurality of first isolation trenches in the semiconductor substrate and before the forming of the plurality of gap trenches in the semiconductor substrate, the method further includes:

Forming an initial trench isolation layer in the first isolation trench;

and forming a first groove isolation layer after the initial groove isolation layer is sequentially etched to form a clearance groove and a second isolation groove.

A semiconductor structure, comprising:

The semiconductor substrate comprises a plurality of active columns which are arranged in an array manner and is provided with clearance grooves which extend along the row direction or the column direction of the array, the bottom surface of each clearance groove is higher than the bottom surface of each active column, and the active columns positioned in the same row or the same column are separated by Cheng Diyi sub-columns and second sub-columns by the same clearance groove;

an air gap located at a lower portion of the gap trench;

and the gap sealing layer is positioned at the upper part of the gap groove and is used for sealing the air gap.

In one embodiment, the semiconductor structure further comprises:

A word line extending along the extending direction of the air gap and positioned on the outer side walls of the first sub-column and the second sub-column;

and the trench isolation structure is filled between the active columns between adjacent columns and between the active columns between adjacent rows, and the bottom surface of the trench isolation structure is lower than the air gap.

In one embodiment, the bottom surface of the word line is flush with or above the bottom surface of the air gap, and the top surface of the word line is flush with or below the top surface of the air gap.

In one embodiment, the semiconductor structure further comprises an insulating dielectric layer, wherein the insulating dielectric layer covers the side wall and the bottom of the semiconductor substrate exposed by the gap trench;

The gap sealing layer extends along the extending direction of the air gap, and in the extending direction, the size of a first part between the first sub-column and the second sub-column of the same active column is smaller than that of a second part between adjacent active columns.

According to the semiconductor structure and the preparation method thereof, the clearance groove is formed firstly, so that two vertical channel transistors can be formed on the same active column. Meanwhile, the floating body effect between the two vertical channel transistors can be reduced by the air gap between the two vertical channel transistors, so that leakage current between the gates of the two vertical channel transistors is prevented. Meanwhile, according to the embodiment of the disclosure, the air gap is formed in the semiconductor substrate, and then the active column is formed, so that the active column cannot incline or collapse in the forming process of the air gap, and the structural uniformity of the active column can be improved. The active pillars (including the first and second sub-pillars) are accurate in position and size and are not easily biased.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present disclosure, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to the drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;

FIG. 2 is a flow chart of a method of fabricating a semiconductor structure provided in another embodiment;

fig. 3 to 24 are schematic structural views of a structure obtained in a process of manufacturing a semiconductor structure according to an embodiment, wherein (a) is a schematic perspective view and (b) is a schematic cross-sectional view;

FIG. 25 is a schematic top view of the semiconductor structure provided in FIG. 24, after being sectioned along the AA' direction;

fig. 26 is a schematic top view of the semiconductor structure provided in fig. 24 after cross-section along the BB' direction;

fig. 27 is an enlarged partial schematic view of a semiconductor structure according to an embodiment.

Reference numerals illustrate:

100-semiconductor substrate, 100 a-first isolation trench, 100 b-gap trench, 100-c air gap, 100 d-second isolation trench, 110-active pillar, 111-first sub-pillar, 112-second sub-pillar, 210-first patterned mask layer, 211-first mask pattern, 2111-gap seal layer, 212-mask sidewall, 2121-sidewall material layer, 220-second patterned mask layer, 221-second mask pattern, 230-third patterned mask layer, 240-fourth patterned mask layer, 250-fifth patterned mask layer, 310-first patterned photoresist, 320-second patterned photoresist, 400-insulating dielectric layer, 500-word line, 501-word line material layer, 600-gate dielectric layer, 601-gate dielectric material layer, 710-liner isolation layer, 711-substrate isolation material layer, 720-fill isolation layer, 730-first trench 731, initial trench isolation layer, 800-capacitor contact structure.

Detailed Description

In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

In one embodiment, referring to fig. 1, a method for fabricating a semiconductor structure is provided, including the following steps:

Step S10, providing a semiconductor substrate 100, please refer to fig. 3;

step S20, forming a plurality of first isolation trenches 100a in the semiconductor substrate 100 at intervals, please refer to fig. 6;

step S40, forming a plurality of spaced-apart gap trenches 100b in the semiconductor substrate 100, wherein the extending direction of the gap trenches 100b intersects with the extending direction of the first isolation trench 100a, and the bottom surface of the gap trench 100b is higher than the bottom surface of the first isolation trench 100a, refer to fig. 14;

Step S60, forming a first patterned mask layer 210 covering and partially filling the gap trench 100b, wherein an air gap 100c is formed between the first patterned mask layer 210 and the bottom of the gap trench 100b, please refer to fig. 16;

in step S70, the semiconductor substrate 100 is etched to form the second isolation trench 100d by using the first patterned mask layer 210 as a mask, the bottom surface of the second isolation trench 100d is lower than the bottom surface of the gap trench 100b, the second isolation trench 100d and the first isolation trench 100a isolate the semiconductor substrate 100 into a plurality of active pillars 110, and the active pillars 110 include the first sub-pillars 111 and the second sub-pillars 112 located at two sides of the air gap 100c, see fig. 17.

In step S10, the semiconductor substrate 100 may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate 100 or II/VI semiconductor substrate 100. Alternatively, the semiconductor substrate 100 may comprise a Si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator substrate, or the like.

In step S20, a fourth patterned mask layer 240 may be first formed on the semiconductor substrate 100. The first isolation trench 100a is then formed based on the fourth patterned mask layer 240.

As an example, the fourth patterned mask layer 240 may be formed by a self-aligned multiple patterning technique. Referring to fig. 4, a fourth mask material layer 241 may be formed first. A plurality of self-aligned mask material layers 261 are then formed on top of the fourth mask material layer 241, and a first patterned photoresist 310 is formed on the self-aligned mask material layers 261. Then, the respective alignment mask material layer 261 and the fourth mask material layer 241 are etched based on the first patterned photoresist 310 and the self-aligned multiple patterning technique, thereby forming a fourth patterned mask layer 240, see fig. 5. The plurality of self-aligned mask material layers 261 may be stacked structures in which organic hard masks and nitrides are alternately stacked, for example, stacked structures formed by spin-coating carbon and silicon oxynitride. The fourth mask material layer 241 may be polysilicon, which may make the pattern profile transferred from the self-aligned mask material layer 261 better.

Referring to fig. 4, a fifth mask material layer 251 may also be formed before the fourth mask material layer is formed. Referring to fig. 5, after forming the fourth patterned mask layer 240 by the self-aligned multiple patterning technique, the fifth mask material layer 251 may be etched based on the fourth patterned mask layer 240 to form a fifth patterned mask layer 250, referring to fig. 6. Thereafter, the semiconductor substrate 100 is etched based on the fourth patterned mask layer 240 and the fifth patterned mask layer 250, thereby forming the first isolation trench 100a. The fifth mask material layer 251 may be an oxide, such as silicon dioxide.

Of course, the fourth patterned mask layer 240 and the fifth patterned mask layer 250 may be directly formed through a photolithography process under a condition having sufficient photolithography accuracy.

The first isolation trenches 100a may extend in a first direction, and the plurality of first isolation trenches 100a initially separate the semiconductor substrate. As an example, the first direction may be a bit line direction. The plurality of first isolation trenches 100a may be disposed in parallel at equal intervals.

As an example, step S20 may further include:

in step S30, an initial trench isolation layer 731 is formed in the first isolation trench 100a, as shown in fig. 7. The material of the initial trench isolation layer 731 may include silicon oxide or the like.

Before the gap trench 100b is formed, an initial trench isolation layer 731 is formed within the first isolation trench 100a, so that the stability of the structure can be improved.

In step S40, referring to fig. 14, the extending direction of the clearance trench 100b may be the second direction. The extension direction of the gap trench 100b intersects with the extension direction of the first isolation trench 100 a. I.e. the first direction and the second direction intersect, which may be perpendicular to each other, or may be acute or obtuse, which is not limited herein. As an example, the first direction may be a word line extending direction. The plurality of first clearance grooves 100b may be disposed in parallel at equal intervals.

In step S60, referring to fig. 17, the mask pattern of the first patterned mask layer 210 may extend along the same direction (i.e., the second direction) as the gap trench 100b, thereby covering the gap trench 100b. An air gap 100c is formed between the first patterned mask layer 210 and the bottom of the gap trench 100b, i.e., the air gap 100c is formed at the lower portion of the gap trench 100b. Accordingly, the air gap 100c has the same extension direction as the gap trench 100b.

Meanwhile, the mask pattern of the first patterned mask layer 210 may have a shape of a "T" in a cross section perpendicular to the second direction, which may protrude downward at a portion opposite to the gap trench 100b, thereby filling an upper portion of the gap trench 100b, thereby closing an air gap 100c formed between a bottom portion of the gap trench 100b and the first patterned mask layer 210.

Meanwhile, since the bottom surface of the gap trench 100b is higher than the bottom surface of the first isolation trench 100a, the bottom surface of the air gap 100c is higher than the bottom surface of the first isolation trench 100 a.

In step S70, referring to fig. 17, after the semiconductor substrate 100 is etched based on the first patterned mask layer 210, a second isolation trench 100d having the same extension direction (i.e., the same extension direction as the gap trench 100b or the air gap 100c, i.e., the second direction) as the first patterned mask layer 210 may be formed in the semiconductor substrate 100.

Meanwhile, at this time, after the etching, the initial trench isolation layer 731 formed at step S30 may form the first trench isolation layer 730. I.e., the initial trench isolation layer 731 is etched in sequence to form the gap trench 100b and the second isolation trench 100d, followed by forming the first trench isolation layer 730.

The extension direction of the second isolation trench 100d intersects with the extension direction of the first isolation trench 100a, so that a plurality of active pillars 110 surrounded by the intersection region of the two can be formed. The plurality of active pillars 110 may be arranged in an array.

Meanwhile, the bottom surface of the second isolation trench 100d and the bottom surface of the first isolation trench 100a are lower than the bottom surface of the gap trench 100 b. Therefore, the bottom surface of the active pillar 110 surrounded by the intersection region of the second isolation trench 100d and the second isolation trench 100d is lower than the bottom surface of the gap trench 100b (i.e., lower than the bottom surface of the air gap 100 c). Thus, the active pillars 110 are integrally formed below the bottom surface of the gap trench 100b, and the sub-pillars 111 and the second sub-pillars 112 are separated Cheng Diyi above the bottom surface of the gap trench 100b by the gap trench 100 b. The first sub-pillar 111 and the second sub-pillar 112 may be used to form two vertical channel transistors, respectively.

In this embodiment, the gap trench 100b may enable two vertical channel transistors to be formed on the same active pillar 110. Meanwhile, the air gap 100c between the two vertical channel transistors can reduce the floating body effect therebetween and can prevent leakage between the gates of the two vertical channel transistors. Meanwhile, the present embodiment first forms the air gap 100c in the semiconductor substrate 100 and then forms the active column 110, so that the active column 110 does not tilt or collapse during the formation of the air gap 100 c. The active pillars 110 (including the first sub-pillars 111 and the second sub-pillars 112) are accurately positioned without being easily biased. Therefore, in the subsequent process, the capacitor contact structure 800 aligned with the first sub-pillar 111 and the second sub-pillar 112 is formed, so that the alignment between the capacitor contact structure 800 and the active pillar 110 is improved (see fig. 27).

In one embodiment, step S40 includes:

step S41, forming a second patterned mask layer 220 on the semiconductor substrate 100, please refer to fig. 13;

In step S42, a gap trench 100b is formed based on the second patterned mask layer 220, see fig. 14.

In step S41, the second patterned mask layer 220 may have a plurality of openings extending in the second direction. The extending direction of these openings may intersect with the extending direction of the first isolation trench 100 a.

The second patterned mask layer 220 may be a single film layer or may include multiple film layers. When the second patterned mask layer 220 includes a plurality of film layers, the plurality of film layers may be stacked in a longitudinal direction or may be arranged in a lateral direction.

In step S42, the semiconductor substrate 100 may be dry etched or the like based on the opening of the second patterned mask layer 220, thereby forming a plurality of gap trenches 100b.

In one embodiment, referring to fig. 13, the second patterned mask layer 220 includes a second mask pattern 221 and a mask sidewall 212 located on a sidewall of the second mask pattern 221. The material of the mask sidewall 212 is different from that of the second mask pattern 221. The mask sidewall 212 is located on a sidewall of the second mask pattern 221 perpendicular to the first direction.

Step S60 includes:

Step S61, filling the first mask pattern 211 in the opening region of the second patterned mask layer 220, and partially filling the first mask pattern 211 with the gap trench 100b, please refer to fig. 16;

in step S62, the second mask pattern 221 is removed, and the remaining mask sidewall 212 and the first mask pattern 211 form the first patterned mask layer 210, see fig. 16 and 17.

In step S61, the opening of the second patterned mask layer 220 is an opening for etching to form the gap trench 100 b. After the formation of the gap trench 100b, the first mask pattern 211 is filled in the opening region of the second patterned mask layer 220, so that the first mask pattern 211 extending in the second direction may be obtained.

Meanwhile, the first mask pattern 211 partially fills the gap trench 100b, so that the air gap 100c formed at the lower portion of the gap trench 100b may be closed.

In step S62, since the material of the mask sidewall 212 is different from that of the second mask pattern 221, the mask sidewall 212 may be left when the second mask pattern 221 is removed. And the remaining mask sidewall 212 and the first mask pattern 211 form a first patterned mask layer 210.

At this time, the mask pattern shape of the first patterned mask layer 210 having a "T" shape may be effectively formed. After etching based on the first patterned mask layer 210, the semiconductor substrate 100 under the mask sidewall 212 at two sides of the first mask pattern 211 may form the first sub-pillar 111 and the second sub-pillar 112 respectively. Therefore, the dimensions of the first sub-column 111 and the second sub-column 112 can be defined by the dimensions of the mask sidewall 212, so as to facilitate the dimension control of the first sub-column 111 and the second sub-column 112.

At this time, as an example, the material of the first mask pattern 211 may be the same as that of the mask sidewall 212, so that the first mask pattern 211 and the mask sidewall 212 of the first patterned mask layer 210 may be uniformly processed after the active pillars 110 are etched. For example, the material of the first mask pattern 211 and the mask sidewall 212 may be silicon nitride, and the material of the second mask pattern 221 may be silicon dioxide or spin-on carbon.

Of course, the material of the first mask pattern 211 may be different from the material of the mask sidewall 212, which is not limited herein. For example, the material of the first mask pattern 211 and the mask sidewall 212 may be one of silicon nitride and silicon carbide nitride and the other.

In one embodiment, step S41 may include:

Step S411, a second mask pattern 221 is formed on the semiconductor substrate 100, please refer to fig. 11;

In step S412, a sidewall material layer 2121 is formed on the surface of the second mask pattern 221 and the surface of the semiconductor substrate 100, see fig. 12;

In step S413, the sidewall material layer 2121 is anisotropically etched to form a mask sidewall 212 on the sidewall of the second mask pattern 221, see fig. 13.

In step S411, referring to fig. 11, the second mask patterns 221 may extend along the second direction and be arranged at intervals along the second direction. A plurality of second mask patterns 221 are formed on the semiconductor substrate 100. The material of the second mask pattern 221 may include, but is not limited to, polysilicon.

In step S412, referring to fig. 12, a sidewall material layer 2121 may be formed on the surface of the second mask pattern 221 and the surface of the semiconductor substrate 100 through a deposition process. The material of the sidewall material layer 2121 may include silicon nitride, silicon oxynitride, and the like.

In step S413, referring to fig. 13, the sidewall material layer 2121 on the upper surface of the second mask pattern 221 and the surface of the semiconductor substrate 100 may be removed by anisotropic etching, and the sidewall material layer 2121 on the sidewall of the second mask pattern 221 is remained to form the mask sidewall 212.

At this time, the thicknesses of the mask spacers 212 formed on the sidewalls of the second mask patterns 221 in a self-aligned manner are consistent, so that after the subsequent mask spacers 212 and the first mask patterns 211 together form the first patterned mask layer 210, the thicknesses of the first sub-pillars 111 and the second sub-pillars 112 of the active pillars 110 formed by etching the first patterned mask layer 210 are consistent, thereby facilitating the formation of transistors with uniform performance.

Of course, in other embodiments, the forming manner of the mask sidewall 212 in the second patterned mask layer 220 may be different from this.

In one embodiment, step S411 includes:

In step S4111, a third patterned mask layer 230 is formed on the semiconductor substrate 100, please refer to fig. 9;

In step S4112, a second mask pattern 221 is formed in the opening of the third patterned mask layer 230, please refer to fig. 10;

In step S4113, the third patterned mask layer 230 is removed, see fig. 11.

In step S4111, the third patterned mask layer 230 may be formed by a self-aligned multiple patterning technique. At this time, a third mask material layer may be first formed on the semiconductor substrate 100. Then forming a plurality of self-aligned mask material layers on the third mask material layer, and forming a second patterned photoresist on the self-aligned mask material layers. The alignment mask material layers and the third mask material layer are then etched based on the second patterned photoresist and the self-aligned multiple patterning technique, thereby forming a third patterned mask layer 230.

Of course, the third patterned mask layer 230 may be directly formed through a photolithography process under a condition having sufficient photolithography accuracy.

In step S4112, a second mask pattern 221 may be formed in the opening of the third patterned mask layer 230 by a Spin-on Dielectric (SOD) process or the like.

In step S4113, since the material of the second mask pattern 221 is different from the material of the third patterned mask layer 230, the second mask pattern 221 may remain after the third patterned mask layer 230 is removed.

In one embodiment, referring to fig. 2, step S40 further includes:

In step S50, an insulating dielectric layer 400 is formed on the sidewalls and bottom of the semiconductor substrate 100 exposed in the gap trench 100 b.

As an example, the material of the insulating dielectric layer 400 may be an oxide layer. An insulating dielectric layer 400 may be formed on the sidewalls and bottom of the gap trench 100b by thermal oxidation.

In this embodiment, the formation of the insulating dielectric layer 400 can more effectively isolate the transistors formed on both sides of the air gap 100 c.

In one embodiment, after step S70, further comprising:

In step S80, word lines 500 are formed on the outer sidewalls of the first sub-pillars 111 and the second sub-pillars 112, see fig. 23.

At this time, the word line 500 is formed along the outer sidewalls of the first and second sub-pillars 111 and 112, reducing the possibility of the word line 500 toppling.

In one embodiment, step S80 includes:

step S81, a liner isolation layer 710 is formed in the second isolation trench 100d between the active pillars 110, please refer to fig. 20;

step S82, sequentially forming a gate dielectric material layer 601 on the upper surface of the liner isolation layer 710, the sidewalls of the first sub-pillars 111 and the second sub-pillars 112, and the sidewalls and upper surface of the first patterned mask layer 210, as shown in fig. 21;

step S83, forming a word line material layer 501 on the surface of the gate dielectric material layer 601, please refer to fig. 22;

in step S84, the word line material layer 501 is anisotropically etched to form word lines 500, see fig. 23.

In step S81, the material of the pad isolation layer 710 may include an oxide material.

Referring to fig. 20, the liner isolation layer 710 partially fills the second isolation trench 100d. An upper surface of the liner isolation layer 710 filled in the second isolation trench 100d may be located near a bottom surface of the air gap 100 c. For example, an upper surface of the liner isolation layer 710 in the second isolation trench 100d may be flush with a bottom surface of the air gap 100 c. Or the upper surface of the liner isolation layer 710 in the second isolation trench 100d may be slightly higher than the bottom surface of the air gap 100 c. Or the upper surface of the liner isolation layer 710 in the second isolation trench 100d may be slightly lower than the bottom surface of the air gap 100 c.

By first forming the liner isolation layer 710 in the second isolation trench 100d, the subsequently formed word line 500 may be allowed to cover the first sub-pillars 111 and the second sub-pillars 112 of the active pillars 110. While the lower non-bifurcated portions of the active pillars 110 are at least partially uncovered by the word lines 500 and thus may serve as source or drain regions for the transistors. Two transistors formed on the same active pillar 110 may share the source or drain region.

In step S82, referring to fig. 21, a gate dielectric material layer 601 may be formed by in-situ vapor growth (in-situ steam generation, ISSG) and/or atomic layer deposition (Atomic layer deposition, ALD) or the like. The material of the gate dielectric material layer 601 may be oxide or the like.

In step S83, referring to fig. 22, a metal material may be formed on the surface of the gate dielectric material layer 601 by physical vapor deposition or evaporation to serve as the word line material layer 501. The material of the word line material layer 501 may be tungsten, molybdenum, titanium nitride, or the like.

In step S84, referring to fig. 23, the word line material layer 501 may be subjected to anisotropic etching in a vertical direction.

At this time, the word line material layer 501 formed on the horizontal plane is removed, and the word line material layer 501 formed on the sidewall of the gate dielectric material layer 601 may be left. Meanwhile, as the anisotropic etching time increases, after the word line material layer 501 located on the horizontal plane is removed, the word line material layer 501 on the sidewall of the gate dielectric material layer 601 may be etched downward from the top.

Accordingly, the word line 500 having an upper surface lower than the second isolation trench 100d may be formed by control of the anisotropic etching conditions. At this time, the portions of the first sub-pillars 111 and the second sub-pillars 112 not covered with the word lines 500 may serve as transistor drain regions or source regions.

In one embodiment, step S81 includes:

step S811, forming a liner isolation material layer 711 covering the first patterned mask layer 210 and filling the second isolation trench 100d, please refer to fig. 18;

step S812, performing chemical mechanical polishing on the pad isolation material layer 711 by using the first patterned mask layer 210 as a polishing stop layer, please refer to fig. 19;

in step S813, the pad isolation material layer 711 after the cmp is etched back to form the pad isolation layer 710, see fig. 20.

In step S811, a liner isolation material layer 711 covering the first patterned mask layer 210 and filling the second isolation trench 100d may be formed through a deposition process.

The deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high-density plasma deposition (HIGH DENSITY PLASMA, HDP) process, and Spin-on Dielectric (SOD) processes.

In step S812, the pad isolation material layer 711 above the first patterned mask layer 210 may be removed through a chemical mechanical polishing process. As an example, when the first patterned mask layer 210 includes the first mask pattern 211 and the mask sidewall 212, both materials may be silicon nitride, so that they may be used as a polishing stop layer during the cmp process.

In step S813, the liner isolation material layer 711 may be etched back by wet or dry etching.

In this embodiment, after the spacer isolation material layer 711 is formed, it is first subjected to chemical mechanical polishing treatment and then etched back. The chemical mechanical polishing treatment has high removal speed, so that the process efficiency can be effectively improved.

Of course, in some embodiments, after forming the liner isolation material layer 711, it may also be etched directly until the liner isolation layer 710 partially filling the second isolation trench 100d is formed.

In one embodiment, referring to fig. 23 and fig. 24, after step S80, the method further includes:

Step S91, forming a filling isolation material layer covering the first patterned mask layer 210, the active pillars 110, the word lines 500, and the pad isolation layer 710;

In step S92, the filling isolation material layer and the first patterned mask layer 210 above the active pillars 110 are removed by chemical mechanical polishing, the remaining filling isolation material layer forms a filling isolation layer 720, and the remaining first patterned mask layer 210 forms a gap seal layer 2111.

In step S91, the filled isolation material layer may be formed by high-density plasma deposition (HIGH DENSITY PLASMA, HDP) or the like. The material filling the isolation material layer can be an insulating medium such as silicon oxide.

In step S92, a planarized surface may be formed by a chemical mechanical polishing process.

After the cmp process, the remaining filling isolation layer 720 formed by the filling isolation material layer fills the second isolation trench 100d together with the liner isolation layer 710 formed in the previous step. At this time, the filling isolation layer 720 and the liner isolation layer 710 located in the second isolation trench 100d and the first trench isolation layer 730 located in the first isolation trench 100a may together constitute a trench isolation structure around the transistor.

Meanwhile, after performing the cmp process, the remaining first patterned mask layer 210 forms a gap-sealing layer 2111, thereby sealing the air gap 100 c.

If the step S30 is included before the preceding step S20, and the steps S40 and S60 include the step S50, and the insulating dielectric layer 400 is formed by thermal oxidation after the formation of the gap trench 100b in the step S50, the insulating dielectric layer 400 is formed on the surface of the semiconductor substrate 100 but not on the surface of the initial trench isolation layer 731. Therefore, after step S50, the gap trench 100b is narrower in the region opposite to the semiconductor substrate 100 than in the region opposite to the initial trench isolation layer 731.

Therefore, the gap seal layer 2111 (the portion of the first patterned mask layer 210 filled in the gap trench 100 b) and the air gap 100c formed at this time have different dimensions in different regions in the extending direction thereof.

Referring to fig. 24 to 27, in the extending direction (the second direction) of the gap-seal layer 2111, the size of a first portion of the gap-seal layer 2111 between the first sub-pillars 111 and the second sub-pillars 112 of the same active pillar 110 is smaller than the size of a second portion of the gap-seal layer 2111 between adjacent active pillars 110. In the extending direction (second direction) of the air gap 100c, the size of a first portion of the air gap 100c between the first sub-column 111 and the second sub-column 112 of the same active column 110 is smaller than the size of a second portion of the gap seal layer 2111 between adjacent active columns 110.

Meanwhile, after performing the chemical mechanical polishing process, the gate dielectric layer 600 is formed by the remaining gate dielectric material layer 601. The gate dielectric layer 600 is located on the sidewalls of the first sub-pillars 111 and the second sub-pillars 112 above the spacer layer 710.

At this time, the partial structure of the first patterned mask layer 210 is used as the gap sealing layer 2111 to seal the air gap 100c, so that the first patterned mask layer 210 can be effectively used.

It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.

Referring to fig. 24 to 27, in an embodiment of the present disclosure, a semiconductor structure is further provided.

In one embodiment, the semiconductor structure includes a semiconductor substrate 100, an air gap 100c, and a gap closure layer 2111.

The semiconductor substrate 100 may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate 100 or II/VI semiconductor substrate 100. Alternatively, the semiconductor substrate 100 may comprise a Si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator substrate, or the like.

The semiconductor substrate 100 includes a plurality of active pillars 110 arranged in an array. And has clearance trenches 100b extending in the row or column direction of the array (i.e., the aforementioned second direction).

The active pillars 110 located in the same row or column are each separated Cheng Diyi by a common-gap trench 100b by a sub-pillar 111 and a second sub-pillar 112. The bottom surface of the gap trench 100b is higher than the bottom surface of the active pillar 110 such that the active pillar 110 is of unitary construction below the bottom surface of the gap trench 100b, and is separated Cheng Diyi by the gap trench 100b between the sub-pillar 111 and the second sub-pillar 112 above the bottom surface of the gap trench 100 b. The first sub-pillar 111 and the second sub-pillar 112 may be used to form two vertical channel transistors, respectively.

The air gap 100c is located at a lower portion of the gap trench 100 b. The gap seal layer 2111 is located at an upper portion of the gap trench 100 b. Accordingly, the air gap 100c and the gap seal layer 2111 extend in the extending direction (i.e., the second direction) of the air gap 100 c.

The material of the gap closure layer 2111 may include, but is not limited to, silicon nitride, silicon oxynitride, silicon oxide, and the like.

The gap seal layer 2111 serves to close the air gap 100c, so that the air gap 100c stably exists. At this time, the air gap 100c between the two vertical channel transistors can reduce the floating body effect therebetween, thereby preventing leakage between the gates of the two vertical channel transistors.

In one embodiment, the semiconductor structure further includes a word line 500 and a trench isolation structure.

The word line 500 extends along the extending direction of the air gap 100c, and the word line 500 is located at the outer sidewalls of the first sub-column 111 and the second sub-column 112, so that the possibility of toppling of the word line 500 can be reduced. The material of the word line 500 may include, but is not limited to, a metal material.

Meanwhile, a gate dielectric layer 600 may be further disposed between the word line 500 and the outer sidewalls of the first sub-pillars 111 and the second sub-pillars 112. The bottom surface of the gate dielectric layer 600 may be flush with the bottom surface of the word line 500, and the top surface of the gate dielectric layer 600 may be flush with the top surfaces of the first sub-pillars 111 and the second sub-pillars 112.

The trench isolation structures are filled between active pillars 110 between adjacent columns and between active pillars 110 between adjacent rows, with the bottom surfaces of the trench isolation structures being below the air gaps 100c.

The trench isolation structure may include the first trench isolation layer 730 within the first isolation trench 100a and the fill isolation layer 720 and liner isolation layer 710 within the second isolation trench 100d as described above. The materials of the first trench isolation layer 730, the liner isolation layer 710, and the filling isolation layer 720 may be the same or different, which is not limited herein.

The air gap 100c may extend in the second direction across the semiconductor substrate 100 and the trench isolation structure.

In one embodiment, the bottom surface of word line 500 is flush with the bottom surface of air gap 100c or is higher than the bottom surface of air gap 100c, and the top surface of word line 500 is flush with the top surface of air gap 100c or is lower than the top surface of air gap 100 c. At this time, the air gap 100c completely isolates the word line 500 located at the outer sidewall of the first sub-column 111 from the outer sidewall of the second sub-column 112, thereby more effectively preventing leakage from occurring therebetween.

In one embodiment, the semiconductor structure further includes an insulating dielectric layer 400. The insulating dielectric layer 400 covers the sidewalls and bottom of the semiconductor substrate 100 exposed by the gap trench 100 b. The material of the insulating dielectric layer 400 may include, but is not limited to, an oxide material.

The gap seal layer 2111 extends in the extending direction of the air gap 100 c. In the extending direction (i.e., the second direction) of the gap-seal layer 2111, the size of a first portion of the gap-seal layer 2111 between the first sub-pillars 111 and the second sub-pillars 112 of the same active pillar 110 is smaller than the size of a second portion of the gap-seal layer 2111 between adjacent active pillars 110.

In one embodiment, the semiconductor structure further includes a capacitor contact structure 800 located on the first sub-pillar 111 and the second sub-pillar 112, respectively, and a capacitor structure (not shown) located above the capacitor contact structure 800. Since the first sub-pillars 111 and the second sub-pillars 112 are formed in a self-aligned manner, the first sub-pillars 111 and the second sub-pillars 112 have a better structural uniformity, so that an alignment contact with the capacitor contact structure 800 can be performed.

The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the following claims.

Claims

1. A method of fabricating a semiconductor structure, comprising:

Providing a semiconductor substrate;

2. The method of manufacturing a semiconductor structure as claimed in claim 1, wherein,

Forming a second patterned mask layer on the semiconductor substrate;

And forming the clearance groove based on the second patterned mask layer.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein the second patterned mask layer comprises a second mask pattern and a mask sidewall located on a sidewall of the second mask pattern;

the forming a first patterned mask layer covering the gap trench includes:

4. The method of claim 3, wherein the first mask pattern is the same material as the mask sidewall.

5. The method of manufacturing a semiconductor structure according to claim 3 or 4, wherein forming a second patterned mask layer on the semiconductor substrate comprises:

forming a second mask pattern on the semiconductor substrate;

6. The method of claim 5, wherein forming a second mask pattern on the semiconductor substrate comprises:

forming a third patterned mask layer on the semiconductor substrate;

and removing the third patterned mask layer.

7. The method of manufacturing a semiconductor structure according to claim 1, wherein after forming a plurality of spaced apart gap trenches in the semiconductor substrate, further comprising:

8. The method of claim 1, wherein the first patterned mask layer is a mask, and further comprising, after etching the semiconductor substrate:

9. The method of fabricating a semiconductor structure of claim 8, wherein forming word lines on sidewalls of the first sub-pillars and the second sub-pillars comprises:

And anisotropically etching the word line material layer to form the word line.

10. The method of claim 9, wherein forming a liner spacer in the region between the active pillars comprises:

11. The method of claim 9, wherein anisotropically etching the word line material layer to form the word lines on both sides of the air gap, comprises:

12. The method of manufacturing a semiconductor structure according to claim 1, wherein after the forming of the plurality of first isolation trenches in the semiconductor substrate at intervals and before the forming of the plurality of gap trenches in the semiconductor substrate at intervals, further comprising:

Forming an initial trench isolation layer in the first isolation trench;

13. A semiconductor structure, comprising:

an air gap located at a lower portion of the gap trench;

14. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises:

And the trench isolation structures are filled between the active columns between adjacent columns and between the active columns between adjacent rows, and the bottom surfaces of the trench isolation structures are lower than the air gaps.

15. The semiconductor structure of claim 14, wherein a bottom surface of the word line is flush with or above a bottom surface of the air gap and a top surface of the word line is flush with or below a top surface of the air gap.

16. The semiconductor structure of claim 13, further comprising an insulating dielectric layer covering sidewalls and a bottom of the semiconductor substrate exposed by the gap trench;