CN118351915A - Storage structure, storage module, storage system and preparation method - Google Patents

Abstract

The invention relates to the technical field of semiconductors, in particular to a storage structure, a storage unit, a storage module, a storage system and a preparation method, wherein the storage structure comprises a storage element; a switching element; and a bit line, one pole of the switching element being connected to one electrode of the memory element, the other pole being connected to the bit line; the memory element and the adjacent switch element form a memory unit, the memory unit formed by surrounding gate transistors and three-dimensional spontaneous polarization capacitors surrounds the bit line, and the memory unit is arranged into a cylindrical three-dimensional structure in the direction perpendicular to the surface of the wafer to realize high-density data storage. Structurally breaks through the limitation of the traditional two-dimensional structure, and realizes the stacking of the three-dimensional structure, thereby realizing the leap of storage density. The read-write speed is fast, can reach nanosecond level, and has high reliability and low power consumption. The biggest challenges of memory development today are solved, namely the combination of high performance of memory cells and high density of memory structures.

Description

Storage structure, storage module, storage system and preparation method

Technical Field

The invention relates to the technical field of semiconductors, in particular to a storage structure, a storage unit, a storage module, a storage system and a preparation method.

Background

With the rapid development of current technology, higher requirements are put on electronic products in domestic and foreign markets. Data storage is also facing new challenges as a critical device.

The volatile memory, including Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM), has a fast read-write speed up to nanosecond level, but has a disadvantage that information is easily lost under the condition of power failure, so that the plug-and-play is limited, data cannot be stored for a long time, the occupied area is large, the cost is high, and the memory density cannot be improved by making a 3D structure. While non-volatile memories such as FLASH memory (FLASH) can store data for a long time, have low cost and can be made into a 3D structure to realize high storage density, the writing speed is slow, even in millisecond level, the erasable times are small, and the requirements of high-speed, high-reliability writing and unlimited times erasing in a real-time processing system cannot be met.

The power consumption of the two traditional memories is also high, and the low power consumption requirement of future Internet of things application cannot be met.

Disclosure of Invention

This section is intended to outline some aspects of embodiments of the application and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section as well as in the description of the application and in the title of the application, which may not be used to limit the scope of the application.

The present invention has been made in view of the problems of the prior art.

It is therefore a first object of the present invention to provide a memory cell which is fast in read/write speed, can reach nanosecond level, and has high reliability and low power consumption. The second object of the present invention is to provide a storage structure, which adopts a three-dimensional structure, structurally breaks through the limitation of the traditional two-dimensional structure, and realizes the stacking of three-dimensional architecture, thereby realizing the leap of storage density. The combination of high performance of memory cells and high density of memory structures is the biggest challenge in the research and development of memories today, and therefore, it is a third object of the present invention to provide a manufacturing method for realizing data storage by means of surrounding gate transistors and three-dimensional spontaneous polarization capacitors, and such a memory system has excellent memory performance and extremely high data capacity.

In order to solve the technical problems, the invention provides the following technical scheme: a memory structure comprising, a memory element; a switching element; and a bit line, one pole of the switching element being connected to one electrode of the memory element, the other pole being connected to the bit line; the memory element and the adjacent switch element form a memory unit, and the memory element and the switch element are alternately arranged in the vertical direction of the wafer surface.

As a preferred embodiment of the storage structure according to the present invention, wherein: the memory element adopts a three-dimensional spontaneous polarization capacitor, and comprises a first electrode and a second electrode, wherein a spontaneous polarization high dielectric constant material is arranged between the first electrode and the second electrode.

As a preferred embodiment of the storage structure according to the present invention, wherein: the switching element adopts a surrounding grid transistor, and comprises a thin film channel; one end of the thin film channel is connected to the bit line, and the other end is connected to one electrode of the memory element.

In order to solve the technical problems, the invention provides the following technical scheme: the memory module further comprises word lines and plate lines; wherein one electrode of the memory element of the memory cell is connected to a corresponding plate line; the gate of the switching element of the memory cell is connected to a corresponding word line.

As a preferred embodiment of the memory module according to the invention, the memory module comprises: the memory cells share one bit line, the memory cells surround the bit line and are arranged into a cylindrical three-dimensional structure in the direction vertical to the surface of the wafer; the bit line is in a columnar or cylindrical structure.

As a preferred embodiment of the memory module according to the invention, the memory module comprises: the memory array comprises a plurality of groups of memory modules, wherein a plurality of memory cells of each group of memory modules share a bit line, and a plurality of memory cells of the same layer of memory modules of different groups share a word line and a plate line.

As a preferred embodiment of the memory module according to the invention, the memory module comprises: the device also comprises a step structure; the step structure is close to the edge of the storage array; the upper surfaces of every two adjacent steps in the step structure correspond to a word line and a plate line respectively; each layer of step in the step structure is stacked along the direction vertical to the surface of the wafer, and each layer of step is respectively connected with one metal contact.

As a preferred embodiment of the memory module according to the invention, the memory module comprises: the device also comprises a step structure; the step structure is close to the edge of the storage array and is divided into two areas; the upper surface of each step of the step structure in one area corresponds to one plate line respectively; the upper surface of each step of the step structure in the other area corresponds to one word line respectively; each layer of step in the step structure is stacked along the direction vertical to the surface of the wafer, and each layer of step is respectively connected with one metal contact.

In order to solve the technical problems, the invention provides the following technical scheme: the preparation method comprises depositing a barrier layer and multiple groups of composite film layers to form a three-dimensional stacked film layer; building holes in the three-dimensional stacked film layers, and arranging bit lines in the holes; constructing a step structure at the edge of the storage array; a surrounding gate transistor is disposed outside the bit line and forms a three-dimensional spontaneous polarization capacitor connected to the surrounding gate transistor.

As a preferred embodiment of the preparation process according to the invention, there is provided: the method for forming the three-dimensional stacked film layer comprises the steps of depositing a first barrier layer on a wafer with a peripheral circuit completed; repeatedly depositing a plurality of groups of composite film layers on the first barrier layer; and depositing a second barrier layer on the composite film layer, wherein the composite film layer is of a multi-layer structure and comprises a first sacrificial layer, a second sacrificial layer and a third sacrificial layer from bottom to top.

As a preferred embodiment of the preparation process according to the invention, there is provided: and the three-dimensional stacked film layer is provided with holes by dry etching, and the etching rate of the barrier layer is lower than half of the etching rate of the composite film layer.

As a preferred embodiment of the preparation process according to the invention, there is provided: the method of setting the bit line includes,

Sequentially depositing a bottom electrode and a bit line insulating layer on the inner wall of the hole by adopting an atomic deposition or chemical vapor deposition mode; and depositing bit line metal in the holes by chemical vapor deposition or ionized physical vapor deposition or other deposition modes with high step coverage rate until the whole holes are filled.

As a preferred embodiment of the preparation process according to the invention, there is provided: the method of constructing the step structure includes,

Using a photoetching mask to cover the storage array area and other areas needing protection with photoresist; carrying out sacrificial layer etching, wherein at least two high selectivity etching are adopted to match, wherein the etching rate of a second sacrificial layer in the high selectivity etching is two times greater than that of a third sacrificial layer, and the etching rate of the second sacrificial layer in the high selectivity etching is less than half of that of the third sacrificial layer; the photoresist is thinned by dry etching, and each thinning reduces the periphery of the photoresist film layer by one step width inwards on a plane parallel to the wafer.

As a preferred embodiment of the preparation process according to the invention, there is provided: a surrounding gate transistor is disposed on an outer side of the bit line and forms a three-dimensional spontaneous polarization capacitor connected to the surrounding gate transistor, including,

Forming a first barrier layer stopping the gap by dry etching;

Isotropic high-selectivity etching is carried out through the gaps, and the first sacrificial layer, the bottom electrode and the bit line insulating layer are sequentially removed;

Filling a third sacrificial layer material at the positions of the removed first sacrificial layer, the removed bottom electrode and the removed bit line insulating layer by adopting atomic deposition or chemical vapor deposition, and then removing the second sacrificial layer and the removed bottom electrode by isotropic high-selectivity etching;

performing isotropic high-selectivity etching to thin the third sacrificial layer, and exposing the bit line and a part of the bottom electrode;

Sequentially depositing a thin film channel material, a gate oxide layer and a word line material layer by an atomic layer deposition method;

removing the third sacrificial layer by isotropic high selectivity etching;

The spontaneous polarization high dielectric constant material, the top electrode and the plate wire material layer are sequentially deposited through atomic layer deposition or chemical vapor deposition.

The invention has the beneficial effects that: the memory unit is formed by surrounding the grid transistor and the three-dimensional spontaneous polarization capacitor and surrounds the bit line, and the memory unit is arranged into a cylindrical three-dimensional structure in the direction vertical to the surface of the wafer, so that high-density data storage is realized. Structurally breaks through the limitation of the traditional two-dimensional structure, and realizes the stacking of the three-dimensional structure, thereby realizing the leap of storage density. The read-write speed is fast, can reach nanosecond level, and has high reliability and low power consumption. The biggest challenges of memory development today are solved, namely the combination of high performance of memory cells and high density of memory structures.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:

FIG. 1 is a schematic cross-sectional view of a memory module according to the present invention.

FIG. 2 is a schematic cross-sectional view of a memory array according to the present invention

FIG. 3 is a schematic view of a three-dimensional stacked film layer according to the present invention.

FIG. 4 is a schematic diagram of a three-dimensional stacked film deposition hard mask and window according to the present invention.

FIG. 5 is a schematic cross-sectional view of a memory array of the present invention prior to formation of a hole.

FIG. 6 is a schematic diagram of filling a bottom electrode in a hole according to the present invention.

FIG. 7 is a schematic diagram of a bit line insulating layer deposited in a via in the present invention.

FIG. 8 is a schematic diagram of depositing bit line metal in holes and performing chemical mechanical polishing in accordance with the present invention.

FIG. 9 is a schematic cross-sectional view of a step structure in an area formed prior to the construction of a memory array in accordance with the present invention.

FIG. 10 is a schematic cross-sectional view of another in-region step structure formed prior to the construction of a memory array in accordance with the present invention.

FIG. 11 is a schematic diagram of a cross-sectional view of a build slot and a top view of a memory array in accordance with the present invention.

FIG. 12 is a schematic diagram of a process flow for fabricating a bit line contact in accordance with the present invention.

Fig. 13 is a schematic flow chart of a process for constructing a surrounding gate transistor in the present invention.

FIG. 14 is a schematic diagram of a process flow for constructing a three-dimensional spontaneous polarization capacitor in the present invention.

Fig. 15 is a schematic cross-sectional view of a step structure in one region formed after the memory array is constructed in accordance with the present invention.

Fig. 16 is a schematic cross-sectional view of another in-region step structure formed after the memory array is constructed in accordance with the present invention.

Detailed Description

The present invention provides a memory structure, a memory unit, a memory module, a memory system and a manufacturing method, and in order to make the above objects, features and advantages of the present invention more obvious and understood, the following detailed description of the embodiments of the present invention will be given with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail so as not to obscure the invention; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.

Further, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic can be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.

Example 1

Referring to fig. 1, a first embodiment of the present invention provides a memory structure.

Specifically, a memory structure includes a switching element 100; a memory element 200; bit line 401. One pole of the switching element 100 is connected to one electrode 201 of the memory element 200, and the other pole is connected to the bit line 401; the memory element 200 and the switching element 100 adjacent thereto constitute the memory cell 300, and the memory element 200 and the switching element 100 are alternately arranged in a direction perpendicular to the wafer surface, and the bit line 401 is surrounded by the bit line insulating layer 402.

Wherein the storage element 200 is used for storing information and the switching element 100 is used for controlling writing and reading of information. Unlike the related art, the memory cell 300 is formed by alternately stacking the switching element 100 and the memory element 200 in a direction perpendicular to the wafer surface. The memory cells 300 can be stacked all the way up in the vertical direction with the floor space being unchanged, and the number of stacked memory cells 300 can be hundreds of times, which greatly improves the data storage density relative to a two-dimensional memory structure. The switching element 100 and the memory element 200 are relatively independent, and can be respectively selected from high-performance devices and optimized in structure to improve performance without causing adverse effects, so that the combination of the methods can form the memory cell 300 with strong performance, and the three-dimensional structure can simultaneously meet the high performance of the memory cell and the high density of the memory structure.

Example 2

Referring to fig. 1, a second embodiment of the present invention is based on the previous embodiment, except that the memory element 200 selects a three-dimensional spontaneous polarization capacitance. For convenience of explanation, the reference numeral of the subsequent three-dimensional spontaneous polarization capacitor is also 200.

Specifically, the memory element 200 employs a three-dimensional spontaneous polarization capacitor 200, and the memory element 200 includes two electrodes 201 and 203, and a spontaneous polarization high dielectric constant material 202 is disposed between the two electrodes 201 and 203.

The use of the three-dimensional spontaneous polarization capacitor 200 as the memory element 200 allows such a memory structure to have nonvolatile memory characteristics, i.e., to retain stored information in the event of power failure or power failure, which means that data stored in the three-dimensional spontaneous polarization capacitor 200 is not lost even if the system is powered off or restarted, thereby providing reliable data storage.

In terms of the read speed, the three-dimensional spontaneous polarization capacitor 200 is nanosecond in read and write speed, and can read and write data in thousandth of a time or even less in comparison with the conventional flash memory having an erase and write delay of 5 to 10 ms.

In terms of density, the three-dimensional spontaneous polarization capacitor 200 can realize more data stored in a smaller physical size due to the characteristics of its three-dimensional structure, thereby providing a higher storage density.

In terms of lifetime, the three-dimensional spontaneous polarization capacitor 200 is capable of withstanding more than trillion erase cycles as compared to other memory technologies, while being capable of operating over a wider range of operating temperatures, thereby providing longer and reliable data storage.

In terms of power consumption, since the three-dimensional spontaneous polarization capacitor 200 requires only a low voltage when writing data, power consumption can be reduced and energy efficiency can be improved.

And the spontaneous polarization high dielectric constant material 202 is adopted as a capacitance medium, the following functions can be achieved:

the spontaneously polarized high dielectric constant material 202 has a higher dielectric constant and a spontaneous polarization effect in terms of storage capacity, which means that more charge and energy can be stored in the same-sized capacitor. Therefore, the use of the spontaneous polarization high dielectric constant material 202 as a capacitance medium can increase the storage capacity of the capacitor and increase the capacitance value of the capacitor.

The spontaneous polarization high dielectric constant material 202 has excellent electric field response speed in terms of electric field response speed. Due to the characteristics of the spontaneously polarized high dielectric constant material 202, the polarization state thereof can be rapidly changed when the electric field application direction is changed, thereby generating rapid charge and electric field change in the capacitor. This enables the capacitor to respond to the electric field change in a shorter time, improving the response speed of the capacitor.

In terms of power consumption and energy efficiency, the spontaneously polarized high dielectric constant material 202 requires a lower voltage and faster time when the polarization state changes, which means that its atomic displacement results in less energy being required for the polarization state change than other materials under the same electric field. Therefore, the use of the spontaneously polarized high dielectric constant material 202 can reduce the power consumption of the capacitor and improve the energy efficiency.

The spontaneously polarized high dielectric constant material 202 has good stability and long lifetime. The change in polarization state of the spontaneously polarized high dielectric constant material 202 is caused by the atomic displacement of its internal lattice, which is reversible, does not cause physical damage to the material itself, and can remain stable for a long period of time. This results in a longer lifetime and high reliability of a capacitor employing the spontaneously polarized high permittivity material 202 as a capacitive medium.

Example 3

Referring to fig. 1, a third embodiment of the present invention is based on the previous embodiment, except that a surrounding gate transistor is used for the switching element 100. For ease of description, the reference numeral surrounding the gate transistor is also 100.

Specifically, the switching element 100 employs a surrounding gate transistor 100, and the channel of the transistor employs a thin film channel 101 material, such as a silicon thin film, molybdenum disulfide, or the like.

In combination with the above embodiment, this results in a 1T1C structure formed by the memory structure, that is, a transistor plus a capacitor to realize the memory, and a plurality of 1T1C are stacked to obtain a memory cell 300.

The material of the thin film channel 101 of the transistor adopts molybdenum disulfide, for example, so that the following effects can be achieved:

1) High electron mobility: molybdenum disulfide has a higher electron mobility, which means that electrons are transported faster in the transistor channel. The high electron mobility helps to improve the switching speed and performance of the transistor.

2) Low power consumption: the low power consumption characteristics of molybdenum disulfide transistors make them an energy-efficient option. It can operate at low voltage, reduce power consumption, and can effectively reduce power consumption in standby mode.

3) High mechanical elasticity: the molybdenum disulfide has good mechanical elasticity and can adapt to micro-scale deformation and strain. This is very advantageous for manufacturing flexible electronic devices and bendable electronic equipment.

4) Two-dimensional material: molybdenum disulfide is a two-dimensional material with an extremely thin layered structure. This makes it a unique advantage in nanoelectronics, enabling higher integration and smaller size.

Example 4

Referring to fig. 1, a fourth embodiment of the present invention provides a memory module 400.

Specifically, the memory module 400 further includes a word line 103; a plate line 204; and a memory unit 300. One electrode 203 of the memory element 200 (i.e., the three-dimensional spontaneous polarization capacitor 200) of the memory cell 300 is connected to a corresponding plate line 204; the gate of the switching element 100 (i.e., surrounding the gate transistor 100) of the memory cell 300 is connected to a corresponding word line 103; one end of the thin film channel 101 is connected to the bit line to form a channel bit line contact 104, and the other end is connected to one electrode 201 of the memory element 200.

The memory module 400 is operated by reading and writing charges

Reading operation:

1) The word line 103 is activated to apply a voltage such that the gate of the surrounding gate transistor 100 is turned on.

2) A certain voltage is applied through the plate line 204.

3) If the polarization direction of the three-dimensional spontaneous polarization capacitor is opposite to the direction of the electric field applied by the plate line 204, the three-dimensional spontaneous polarization capacitor 200 is polarization flipped to release charge, the surrounding gate transistor 100 is turned on, and the voltage rise on the bit line 401 is captured by the sense amplifier to this signal, indicating that a logic "1" is read.

4) If the polarization direction of the three-dimensional spontaneous polarization capacitor 200 is the same as the direction of the electric field applied by the plate line 204, the three-dimensional spontaneous polarization capacitor 200 does not undergo polarization inversion, does not discharge charges, does not turn on around the gate transistor 100, and the voltage on the bit line 401 is unchanged, indicating that a logic "0" is read.

Write operation:

1) The word line 103 is activated to apply a voltage.

2) Depending on the logic value of the data to be written, different voltages are applied to bit line 401 and plate line 204 to create positive and negative voltage differentials, creating electric fields in different directions.

3) When the bit line 401 voltage is higher than the plate line 204 voltage, the surrounding gate transistor 100 is turned on and the electric field direction is directed from the bit line 401 to the plate line 204, so that the polarization direction of the three-dimensional spontaneous polarization capacitor 200 is the same as this electric field direction, indicating that a logic "1" is written.

4) When the bit line 401 voltage is lower than the plate line 204 voltage, the surrounding gate transistor 100 is not turned on, so that the polarization direction of the three-dimensional spontaneous polarization capacitor 200 is the same as the electric field direction, indicating that a logic "0" is written.

Example 5

Referring to fig. 2, a fifth embodiment of the present invention provides a storage system. The plurality of memory modules 400 are arranged in a pattern to form a memory array 900. The plurality of memory cells 300 of each group of memory modules 400 are surrounded by the bit lines 401, and share one bit line 401, and are arranged in a cylindrical three-dimensional structure in a direction perpendicular to the wafer surface, and the bit lines 401 have a columnar or cylindrical structure. The same layer of memory cells 300 of different groups of memory modules 400 share one word line 103 and one plate line 204.

Example 6

Referring to fig. 3 to 14, a sixth embodiment of the present invention provides a method for manufacturing a memory, which can be summarized as five parts, respectively, 1. Three-dimensional stacked film 700;2. bit line 401 fills; 3. constructing a step structure 800;4. building a surrounding gate transistor 100;5. a three-dimensional spontaneous polarization capacitor 200 is constructed.

Specifically, the preparation method comprises the steps of depositing a composite film layer 600 and forming a three-dimensional stacked film layer 700; building a hole 704 on the three-dimensional stacked film 700, and disposing a bit line 401 in the hole 704; building a step structure 800 at the edge of the memory array 900; outside the bit line 401, a surrounding gate transistor 100 is built and a three-dimensional spontaneous polarization capacitor 200 connected to the built surrounding gate transistor 100 is formed.

As shown in fig. 3, forming the three-dimensional stacked film 700 further includes depositing a first barrier layer 701 on the wafer 500 with the peripheral circuit completed, wherein the silicon substrate of the wafer 500 and the first barrier layer 701 may be separated by a substrate insulation layer 501 of a suitable thickness, and a preferred material is silicon oxide; repeatedly depositing a composite film layer 600 on the first barrier layer 701; depositing a second barrier layer 702 on the composite film 600; the composite film 600 has a multi-layer structure, and includes a first sacrificial layer 601, a second sacrificial layer 602, and a third sacrificial layer 603 from bottom to top.

Preferably, the material of the first sacrificial layer 601 is silicon oxide, the material of the second sacrificial layer 602 is polysilicon, the material of the third sacrificial layer 603 is silicon nitride, and the materials of the first barrier layer 701 and the second barrier layer 702 are aluminum oxide. The higher the number of accumulated layers, the more memory cells 300 can be stored per unit area, and the more data can be stored, but the higher the number of superimposed layers, the more difficult the multi-process is.

As shown in fig. 4 to 5, the method for constructing the hole 704 on the three-dimensional stacked film 700 includes depositing an organic carbon layer 703 on the second barrier layer 702 to obtain a hard mask, and transferring a pattern onto the hard mask by means of photolithography and dry etching; the composite film 600 is etched through by a hard mask in combination with dry etching and stopped in the first barrier layer 701, thereby obtaining holes 704. As shown in fig. 10, the pattern is generally circular holes arranged in an array.

Example 7

Referring to fig. 6 to 8, a seventh embodiment of the present invention is different from the above-described embodiment in that a manner of disposing the bit line 401 is provided in this embodiment.

Specifically, the method for disposing the bit line 401 in the hole 704 includes sequentially depositing the bottom electrode 201 and the bit line insulating layer 402 on the inner wall of the hole 704 by adopting an atomic deposition or chemical vapor deposition method; and depositing the metal of the bit line 401 in the hole 704 by a deposition mode with high step coverage rate such as chemical vapor deposition or ionized physical vapor deposition until the whole hole 704 is filled.

Preferably, the material of the bottom electrode 201 is titanium nitride, the material of the bit line insulating layer 402 is silicon oxide, and the material of the metal layer is tungsten. The deposition methods such as chemical vapor deposition and atomic deposition are well described in the prior art, and need not be described here.

Example 8

Referring to fig. 9 to 10, an eighth embodiment of the present invention is different from the above-described embodiment in that a manner of constructing the step structure 800 is provided in this embodiment.

Specifically, the method for constructing the step structure 800 includes the first step of using photoresist to cover the second barrier layer 702, and removing the memory array 900 and the portion outside the step structure 800 by photolithography. Step two, the second barrier layer 702 exposed outside the photoresist coverage is removed by dry etching and the etching of the third sacrificial layer 603 is continued until etching into the second sacrificial layer 602. Step three, the second sacrificial layer 602 and the first sacrificial layer 601 are removed using the high selectivity dry etch a, stopping on the third sacrificial layer 603. The etch rate of the second sacrificial layer 602 by the high selectivity dry etch a is much higher than the etch rate of the third sacrificial layer 603. And fourthly, thinning the photoresist to enable the coverage area of the photoresist to retract inwards by one step width. And repeating the second step to the fourth step until the topmost set of steps conforming to the film layer is constructed, wherein the dry etching time of the second step is shortened, and the second barrier layer 702 is only required to be removed, and the second step is stopped in the third sacrificial layer 603, so that the redundant photoresist is removed. In this way, a stepped structure 800 around the memory array 900 can be constructed.

The surface including the step structure 800 is covered with photoresist, and the region where the step structure 800 is located is divided into a photoresist covered region and a photoresist uncovered region by photolithography. The high selectivity dry etch B is performed on the area of the step structure 800 not covered by photoresist, removing the third sacrificial layer 603, stopping on the second sacrificial layer 602. The etch rate of the third sacrificial layer 603 for the high selectivity dry etch B is much higher than the etch rate of the second sacrificial layer 602. After the remaining photoresist is removed, two different regions of the step structure 800 may be formed. As shown in fig. 9, the upper surface of each step of the step structure 800 in one region is the third sacrificial layer 603. As shown in fig. 10, the upper surface of each step of the step structure 800 in one region is the second sacrificial layer 602. The step structure 800 may be filled with an insulating material 801, such as silicon dioxide, and polished flat by chemical mechanical polishing.

After the memory array 900 is built in a number of subsequent processes, the first, second and third sacrificial layers 603 are removed, and the plate line 204 is filled into the third sacrificial layer 603 and the word line 103 is filled into the second sacrificial layer 602. As shown in fig. 15-16, the step structures 800 in the two regions formed after the memory array 900 is built, the plate lines 204 and word lines 103 of different memory cells 300 are respectively connected out from the steps of different layers through metal contacts 802, and metal wiring interconnection is realized in the back-end process.

Example 9

Referring to fig. 11 to 14, a ninth embodiment of the present invention is different from the above-described embodiment in that a construction method of the memory cell 300 is provided in this embodiment.

Specifically, constructing the three-dimensional spontaneous polarization capacitor 200 surrounding the gate transistor 100 and connected to the transistor around the bit line 401 includes forming a slit 901 by dry etching to stop at the first barrier layer 701; isotropic high selectivity etching is performed through the slit 901 to sequentially remove the first sacrificial layer 601, the bottom electrode 201 and the bit line insulating layer 402; filling the third sacrificial layer 603 material at the removed positions of the first sacrificial layer 601, the bottom electrode 201 and the bit line insulating layer 402 by adopting atomic deposition or chemical vapor deposition, and then removing the second sacrificial layer 602 and the bottom electrode 201 by isotropic high selectivity etching; performing isotropic high selectivity etching to thin the third sacrificial layer 603, exposing the bit line 401 and a portion of the bottom electrode 201; sequentially depositing a thin film channel 101 material, a gate oxide layer 102 and a word line 103 material layer by an atomic layer deposition method; removing the third sacrificial layer 603 by isotropic high selectivity etching; the layers of spontaneously polarized high dielectric constant material 202, top electrode 204 material are deposited sequentially by atomic layer deposition or chemical vapor deposition.

If, as shown in fig. 13, a single layer of molybdenum disulfide is used as the material of the thin film channel 101, the band gap width is 1.8eV, which is higher than 1.2eV of silicon, and the pressure resistance is higher than that of silicon, the dielectric layer of the same pressure resistant device can be thinner, and the single layer of molybdenum disulfide can be used as an important substitute material of silicon for the thin film channel 101, thus having wide application space in the field of nano transistors.

It should be noted that, in the conventional 3D NAND memory, a charge pump is required to generate a high voltage by changing the voltage of the floating gate memory cell 300 to achieve the charge addition and the erase operation, so that a current is forced to pass through the gate oxide layer to achieve the erase function, and thus, a 5-10 ms erase delay is required. And high write power and long term write operations can damage floating gate memory cell 300, resulting in a limited number of erase and write operations.

The memory cell 300 in the present invention is a surrounding gate transistor 100 and a three-dimensional spontaneous polarization capacitor 200, the three-dimensional spontaneous polarization capacitor 200 stores by utilizing the characteristic that the polarization direction of the spontaneous polarization high dielectric constant material 202 changes along with the change of the direction of the electric field with sufficient intensity, the polarization inversion does not need particularly high electric field intensity, and the states of the memory cell 300 in "1" and "0" can be changed only by a lower working voltage, so the energy consumption is lower; the charge pump is not needed to generate high voltage for data erasure, so that the phenomenon of erasure delay is avoided, and the access speed is higher; the atomic displacement of the spontaneously polarized high dielectric constant material 202 results in less energy required to change polarization state than other materials. Therefore, the spontaneous polarization high dielectric constant material 202 can reduce the power consumption of the capacitor and improve the energy efficiency; the change in polarization state of the spontaneously polarized high dielectric constant material 202 is caused by the atomic displacement of its internal lattice, which is reversible, does not cause physical damage to the material itself, and can remain stable for a long period of time. This results in a longer lifetime and high reliability of a capacitor employing the spontaneous polarization high dielectric constant material 202 as the capacitive medium; the storage system provided by the invention adopts a three-dimensional structure, and the limitation of the traditional two-dimensional structure is broken through in the structure to realize the stacking of the three-dimensional structure, so that the leap of storage density is realized.

It is important to note that the construction and arrangement of the application as shown in the various exemplary embodiments is illustrative only. Although only a few embodiments have been described in detail in this disclosure, those skilled in the art who review this disclosure will readily appreciate that many modifications are possible (e.g., variations in sizes, dimensions, combinations, colors, orientations, etc.) without materially departing from the novel teachings and advantages of the subject matter described in this application. For example, elements shown as integrally formed may be constructed of multiple parts or elements, the position of elements may be reversed or otherwise varied, and the nature or number of discrete elements or positions may be altered or varied. Accordingly, all such modifications are intended to be included within the scope of present application. The order or sequence of any process or method steps may be varied or re-sequenced according to alternative embodiments. In the claims, any means-plus-function clause is intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Other substitutions, modifications, changes and omissions may be made in the design, operating conditions and arrangement of the exemplary embodiments without departing from the scope of the present applications. Therefore, the application is not limited to the specific embodiments, but extends to various modifications that nevertheless fall within the scope of the appended claims.

Furthermore, in an effort to provide a concise description of the exemplary embodiments, all features of an actual implementation may not be described (i.e., those not associated with the best mode presently contemplated for carrying out the invention, or those not associated with practicing the invention).

It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

It should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present invention may be modified or substituted without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered in the scope of the claims of the present invention.

Claims (14)

1. A memory structure, characterized in that: comprising the steps of (a) a step of,

A switching element (100);

A memory element (200); and

-A bit line (401), one pole of the switching element (100) being connected to one electrode of the memory element (200), the other pole being connected to the bit line (401); the memory element (200) and the adjacent switching element (100) form a memory cell (300), and the memory element (200) and the switching element (100) are alternately arranged in the vertical direction on the wafer surface.

2. The memory structure of claim 1, wherein: the memory element (200) adopts a three-dimensional spontaneous polarization capacitor, the memory element (200) comprises a first electrode (201) and a second electrode (203), and a spontaneous polarization high dielectric constant material (202) is arranged between the first electrode (201) and the second electrode (203).

3. The memory structure of claim 1, wherein: the switching element (100) is a surrounding gate transistor, and the switching element (100) comprises a thin film channel (101); one end of the thin film channel (101) is connected to the bit line (401), and the other end is connected to one electrode of the memory element (200).

4. A memory module comprising a memory structure as claimed in any one of claims 1 to 3, characterized in that: also included is a method of manufacturing a semiconductor device,

A word line (103); and

A plate line (204);

wherein one electrode of the memory element (200) of the memory cell (300) is connected to a corresponding plate line (204); the gate of the switching element (100) of the memory cell (300) is connected to a corresponding word line (103).

5. The memory module of claim 4, wherein: a plurality of memory cells (300) share one bit line (401), and the memory cells (300) are arranged around the bit line (401) in a cylindrical three-dimensional structure in a direction perpendicular to the surface of the wafer; the bit line (401) is in a columnar or cylindrical structure.

6. A memory system comprising the memory module of claim 4 or 5, wherein: the memory array (900) further comprises a plurality of groups of memory modules (400), wherein the memory cells (300) of each group of memory modules (400) share one bit line (401), and the memory cells (300) of the same layer of different groups of memory modules (400) share one word line (103) and one plate line (204).

7. The storage system of claim 6, wherein: also includes a step structure (800); the step structure (800) is near an edge of the memory array (900); the upper surfaces of every two adjacent steps in the step structure (800) correspond to the word line (103) and the plate line (204) respectively; each layer of step in the step structure (800) is stacked along the direction vertical to the surface of the wafer, and each layer of step is respectively connected with one metal contact (802).

8. The storage system of claim 6, wherein: also includes a step structure (800); the step structure (800) is close to the edge of the storage array (900) and is divided into two areas; the upper surface of each step of the step structure (800) in one of the areas corresponds to the plate line (204) respectively; the upper surface of each step of the step structure (800) in the other region corresponds to the word line (103); each step in the step structure (800) is stacked along the direction vertical to the surface of the wafer, and each step is respectively connected with one metal contact (802).

9. A method of manufacturing a storage system as claimed in any one of claims 6 to 8, wherein: comprises a plurality of steps of the method, including the steps of,

Depositing a barrier layer and a plurality of groups of composite film layers (600) to form a three-dimensional stacked film layer (700);

Building a hole (704) in the three-dimensional stacked film layer (700), and arranging a bit line (401) in the hole (704);

Building a step structure (800) at the edge of the storage array (900);

a surrounding gate transistor is provided outside a bit line (401) and a three-dimensional spontaneous polarization capacitor connected to the surrounding gate transistor is formed.

10. The method of preparing as claimed in claim 9, wherein: the method of forming a three-dimensional stacked film (700) includes,

Depositing a first barrier layer (701) on the wafer (500) having completed the peripheral circuitry;

repeatedly depositing a plurality of groups of composite film layers (600) on the first barrier layer (701);

Depositing a second barrier layer (702) on the composite film layer (600);

the composite film layer (600) is of a multi-layer structure and comprises a first sacrificial layer (601), a second sacrificial layer (602) and a third sacrificial layer (603) from bottom to top.

11. The method of manufacturing as claimed in claim 10, wherein: and the three-dimensional stacked film layer (700) is provided with a hole (704) by dry etching, and the etching rate of the barrier layer is lower than half of the etching rate of the composite film layer (600).

12. The method of manufacturing as claimed in claim 11, wherein: the method of setting the bit line (401) includes,

Sequentially depositing a bottom electrode and a bit line insulating layer (402) on the inner wall of the hole (704) by adopting an atomic deposition or chemical vapor deposition mode; and depositing the bit line (401) metal in the hole (704) by chemical vapor deposition or ionized physical vapor deposition or other deposition modes with high step coverage rate until the whole hole (704) is filled.

13. The method of preparing as claimed in claim 9, wherein: the method of constructing a step structure (800) includes,

Using a photolithographic mask to cover the memory array (900) area and other areas to be protected with photoresist; carrying out sacrificial layer etching, wherein at least two high selectivity etching are adopted to match, wherein the etching rate of a second sacrificial layer (602) in the high selectivity etching is two times greater than that of a third sacrificial layer (603), and the etching rate of the second sacrificial layer (602) in the high selectivity etching is less than half of that of the third sacrificial layer (603); the photoresist is thinned by dry etching, and each thinning reduces the periphery of the photoresist film layer by one step width inwards on a plane parallel to the wafer.

14. The method of preparing as claimed in claim 9, wherein: a surrounding gate transistor is provided outside the bit line (401) and a three-dimensional spontaneous polarization capacitor connected to the surrounding gate transistor is formed, comprising,

Forming a gap stop on the first barrier layer (701) by dry etching;

isotropic high selectivity etching is performed through the slit, and the first sacrificial layer (601), the bottom electrode and the bit line insulating layer (402) are sequentially removed;

Filling the positions of the removed first sacrificial layer (601), the removed bottom electrode and the removed bit line insulating layer (402) with a third sacrificial layer (603) material by adopting atomic deposition or chemical vapor deposition, and then removing the second sacrificial layer (602) and the removed bottom electrode by isotropic high selectivity etching;

performing isotropic high selectivity etching to thin the third sacrificial layer (603) to expose the bit line (401) and a portion of the bottom electrode;

Sequentially depositing a thin film channel (101) material, a gate oxide layer and a word line (103) material layer by an atomic layer deposition method;

Removing the third sacrificial layer (603) by isotropic high selectivity etching;

The layers of spontaneously polarized high dielectric constant material (202), top electrode (204) and plate line material are deposited sequentially by atomic layer deposition or chemical vapor deposition.