CN118349290A - Dual-memory chip start-up upgrade system, method, device, medium and product - Google Patents
Dual-memory chip start-up upgrade system, method, device, medium and product Download PDFInfo
- Publication number
- CN118349290A CN118349290A CN202410763765.4A CN202410763765A CN118349290A CN 118349290 A CN118349290 A CN 118349290A CN 202410763765 A CN202410763765 A CN 202410763765A CN 118349290 A CN118349290 A CN 118349290A
- Authority
- CN
- China
- Prior art keywords
- memory chip
- upgrading
- main memory
- firmware
- management controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 37
- 230000002093 peripheral effect Effects 0.000 claims abstract description 63
- 230000009977 dual effect Effects 0.000 claims abstract description 22
- 230000002159 abnormal effect Effects 0.000 claims description 30
- 238000004590 computer program Methods 0.000 claims description 20
- 238000005192 partition Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 101000823089 Equus caballus Alpha-1-antiproteinase 1 Proteins 0.000 description 2
- 101000651211 Homo sapiens Transcription factor PU.1 Proteins 0.000 description 2
- 102100027654 Transcription factor PU.1 Human genes 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000009877 rendering Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010801 machine learning Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Landscapes
- Hardware Redundancy (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention relates to the technical field of storage servers and discloses a system, a method, equipment, a medium and a product for starting and upgrading double storage chips. The baseboard management controller determines the starting position according to the respective zone bit of the main memory chip and the standby memory chip; when the starting position is the starting of the slave main memory chip, upgrading the main memory chip through a first serial peripheral interface, and upgrading the memory chip through a second serial peripheral interface; when the starting position is the starting of the slave storage chip, upgrading the slave storage chip through the first serial peripheral interface; and restarting after the upgrading is completed. The time taken for the dual memory chip upgrade is reduced.
Description
Technical Field
The invention relates to the technical field of storage servers, in particular to a system, a method, equipment, a medium and a product for starting and upgrading double storage chips.
Background
Baseboard management controllers (Baseboard Management Controller, BMC) have wide application in servers, and firmware of BMC is stored in a memory chip (flash). According to a traditional BMCflash scheme, a single flash chip is used, so that a main partition and a standby partition can be divided in the flash to realize a main and standby function, as shown in fig. 1, which is a schematic diagram of a BMCflash main and standby partition provided by the traditional technology, a memory chip of a baseboard management controller comprises a main partition and a standby partition, and the main partition and the standby partition have corresponding starting addresses and ending addresses respectively, such as a main partition starting address 0x00 and a main partition ending address 0x1000; the partition start address 0x2000 is prepared and the partition end address 0x3000 is prepared. When the storage system is started, the flash of the slave partition is started by default, and when the master partition is damaged or cannot be started normally, the slave partition is started.
When BMCflash is required to be upgraded, the flash of the main partition is required to be upgraded firstly, then the flash of the standby partition is required to be upgraded, and the upgrading time cannot be parallel. If BMCflash upgrades are damaged during the upgrade process, there may be situations where neither partition can be started properly.
With the improvement of the safety requirements of users, the storage server gradually develops from single BMC flash to double BMCflash, namely, the storage server comprises independent main flash and standby flash. The scene of the double BMC flash provides a self-remedy scheme for upgrade failure, and improves the safety of the system. However, the dual BMCflash upgrade scheme generally upgrades the main flash first, and upgrades the standby flash BMCflash after the main flash is upgraded and restarted, so that the whole implementation process needs to be upgraded twice and restarted twice, the upgrade time is long, and excessive upgrade time is occupied.
It can be seen that how to reduce the time spent on the dual memory chip upgrade is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The embodiment of the invention aims to provide a system, a method, equipment, a medium and a product for starting and upgrading double memory chips, which can solve the problem that the double memory chips take long time to upgrade.
In order to solve the technical problems, the embodiment of the invention provides a starting and upgrading system for double memory chips, which comprises a baseboard management controller, a complex programmable logic device, a switch component, a main memory chip and a standby memory chip; the baseboard management controller is connected with the main memory chip through a first serial peripheral interface, and is connected with the standby memory chip through a second serial peripheral interface; the switch component is respectively connected with the main memory chip and the standby memory chip;
The complex programmable logic device is respectively connected with the baseboard management controller and the switch component and is used for setting a flag bit for the main memory chip and the standby memory chip according to the working states of the main memory chip and the standby memory chip after the system is started; the flag bit comprises a normal start flag bit and an abnormal start flag bit;
The baseboard management controller is used for determining a starting position according to the respective zone bit of the main memory chip and the standby memory chip; under the condition that the starting position is started from the main memory chip, upgrading the main memory chip through the first serial peripheral interface and upgrading the standby memory chip through the second serial peripheral interface; upgrading the standby memory chip through the first serial peripheral interface under the condition that the starting position is started from the standby memory chip; and restarting after the upgrading is completed.
On one hand, the complex programmable logic device is used for judging whether the heartbeat signal transmitted by the baseboard management controller is received within a set time after the system is started; and setting a normal start flag bit for the main memory chip under the condition that the heartbeat signal transmitted by the baseboard management controller is received within a set time.
On the one hand, the complex programmable logic device is configured to set an abnormal start flag bit for the main memory chip and control the switch component to switch to the spare memory chip when the heartbeat signal transmitted by the baseboard management controller is not received within a set time, and restart the baseboard management controller and the spare memory chip; judging whether a heartbeat signal transmitted by the baseboard management controller is received within a set time; setting an abnormal starting zone bit for the standby memory chip under the condition that the heartbeat signal transmitted by the baseboard management controller is not received within a set time; and setting a normal start flag bit for the standby memory chip under the condition that the heartbeat signal transmitted by the baseboard management controller is received within a set time.
In one aspect, the complex programmable logic device is configured to switch, through a general-purpose input/output interface, a selection signal of the switching component to the spare memory chip, so that the baseboard management controller communicates with the spare memory chip through a first serial peripheral interface and the switching component.
In one aspect, the complex programmable logic device is configured to transmit a message for replacing a spare part to the baseboard management controller when the main memory chip and the spare memory chip are both set with an abnormal start flag bit.
In one aspect, the system further comprises a central processing unit;
The central processing unit is connected with the baseboard management controller and is used for detecting the firmware version number of the baseboard management controller under the condition that a firmware upgrading instruction of the baseboard management controller is received; issuing the firmware upgrading instruction to the baseboard management controller under the condition that the firmware version number is inconsistent with the version number carried in the firmware upgrading instruction;
and the baseboard management controller is used for executing the step of determining the starting position according to the respective flag bits of the main memory chip and the standby memory chip under the condition of receiving the firmware upgrading instruction issued by the central processing unit.
In one aspect, the baseboard management controller is configured to detect whether a firmware version number of the main memory chip is consistent with a version number carried in the firmware upgrade instruction and whether a firmware version number of the spare memory chip is consistent with a version number carried in the firmware upgrade instruction, respectively, when the starting position is that the main memory chip is started; under the condition that the firmware version number of the main memory chip is consistent with the version number carried in the firmware upgrading instruction, the upgrading operation of the main memory chip is not executed; upgrading the main memory chip through the first serial peripheral interface under the condition that the firmware version number of the main memory chip is inconsistent with the version number carried in the firmware upgrading instruction; under the condition that the firmware version number of the spare memory chip is consistent with the version number carried in the firmware upgrading instruction, the upgrading operation of the spare memory chip is not executed; and upgrading the standby memory chip through the second serial peripheral interface under the condition that the firmware version number of the standby memory chip is inconsistent with the version number carried in the firmware upgrading instruction.
In one aspect, the baseboard management controller is configured to detect whether a firmware version number of the spare memory chip is consistent with a version number carried in the firmware upgrade instruction when the starting position is that the spare memory chip is started; under the condition that the firmware version number of the spare memory chip is consistent with the version number carried in the firmware upgrading instruction, the upgrading operation of the spare memory chip is not executed; and upgrading the standby memory chip through the first serial peripheral interface under the condition that the firmware version number of the standby memory chip is inconsistent with the version number carried in the firmware upgrading instruction.
In one aspect, the baseboard management controller is configured to detect whether a firmware version number of the main memory chip is consistent with a version number carried in the firmware upgrade instruction; under the condition that the firmware version number of the main memory chip is consistent with the version number carried in the firmware upgrading instruction, the upgrading operation of the main memory chip is not executed; and upgrading the main memory chip through the first serial peripheral interface under the condition that the firmware version number of the main memory chip is inconsistent with the version number carried in the firmware upgrading instruction.
In one aspect, the baseboard management controller is configured to determine that a starting position is to be started from the main memory chip when a flag bit of the main memory chip is a normal starting flag bit; and under the condition that the flag bit of the main memory chip is an abnormal starting flag bit and the flag bit of the standby memory chip is a normal starting flag bit, determining the starting position to be started from the standby memory chip.
In one aspect, the baseboard management controller is configured to not execute the memory chip upgrade operation when the flag bit of the main memory chip is an abnormal start flag bit and the flag bit of the spare memory chip is an abnormal start flag bit.
The embodiment of the invention also provides a method for starting and upgrading the double memory chips, which is suitable for the baseboard management controller and comprises the following steps:
determining a starting position according to the respective flag bits of the main memory chip and the standby memory chip; the method comprises the steps that after a system is started up, the respective flag bits of a main memory chip and a standby memory chip are determined and obtained according to the working states of the main memory chip and the standby memory chip;
under the condition that the starting position is started from the main memory chip, upgrading the main memory chip through a first serial peripheral interface and upgrading the spare memory chip through a second serial peripheral interface;
Upgrading the standby memory chip through the first serial peripheral interface under the condition that the starting position is started from the standby memory chip;
And restarting after the upgrading is completed.
The embodiment of the invention also provides a device for starting and upgrading the double memory chips, which comprises:
a memory for storing a computer program;
and the processor is used for executing the computer program to realize the steps of the method for starting and upgrading the double memory chips.
The embodiment of the invention also provides a computer readable storage medium, wherein the computer readable storage medium is stored with a computer program, and the computer program realizes the steps of the method for starting and upgrading the double memory chips when being executed by a processor.
The embodiment of the invention also provides a computer program product, which comprises a computer program/instruction, wherein the computer program/instruction realizes the steps of the method for starting and upgrading the double memory chips when being executed by a processor.
According to the technical scheme, the starting and upgrading system of the double memory chips comprises a baseboard management controller, a complex programmable logic device, a switch component, a main memory chip and a standby memory chip; the substrate management controller is connected with the main memory chip through a first serial peripheral interface, and is connected with the memory chip through a second serial peripheral interface; the switch component is respectively connected with the main memory chip and the standby memory chip. The complex programmable logic device is respectively connected with the baseboard management controller and the switch component and is used for setting a flag bit for the main memory chip and the standby memory chip according to the working states of the main memory chip and the standby memory chip after the system is started; the flag bit comprises a normal start flag bit and an abnormal start flag bit; the substrate management controller is used for determining a starting position according to the respective zone bit of the main memory chip and the standby memory chip; under the condition that the starting position is the starting of the slave main memory chip, upgrading the main memory chip through a first serial peripheral interface, and upgrading the memory chip through a second serial peripheral interface; under the condition that the starting position is started from the spare memory chip, upgrading the spare memory chip through the first serial peripheral interface; and restarting after the upgrading is completed. The invention has the beneficial effects that the complex programmable logic device is connected with the main memory chip and the standby memory chip through the switch component, and the switching selection of the main memory chip and the standby memory chip can be realized. The two memory chips are independently connected through the two serial peripheral interfaces of the baseboard management controller, so that the simultaneous upgrading of the two memory chips can be realized, and the upgrading time is ensured to be consistent with the upgrading time of a single memory chip. Compared with the traditional double-memory chip upgrading mode, the scheme effectively reduces the time spent by double-memory chip upgrading.
Drawings
For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a schematic diagram of a BMCflash active-standby partition provided in the prior art;
FIG. 2 is a schematic diagram of a dual-memory-chip boot upgrade system according to an embodiment of the present invention;
FIG. 3 is a flowchart of a method for starting and upgrading a dual memory chip according to an embodiment of the present invention;
Fig. 4 is a block diagram of a dual-memory-chip boot upgrade apparatus according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present invention.
The terms "comprising" and "having" in the description of the invention and in the above-described figures, as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may include other steps or elements not expressly listed.
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.
In the conventional scheme, the upgrade scheme of the dual memory chip generally comprises the steps of firstly upgrading the main memory chip, restarting the main memory chip, and restarting the standby memory chip after the standby memory chip is upgraded. The whole implementation process needs to be subjected to two upgrades and restarted, the upgrade time is long, and excessive upgrade time can be occupied.
Therefore, the embodiment of the invention provides a system, a method, equipment, a medium and a product for starting and upgrading double memory chips, wherein a complex programmable logic device is connected with a main memory chip and a standby memory chip through a switch component, so that switching selection of the main memory chip and the standby memory chip can be realized, two memory chips are independently connected through two serial peripheral interfaces of a baseboard management controller, simultaneous upgrading of the two memory chips can be realized, upgrading time is ensured to be consistent with that of a single memory chip, and time spent for upgrading the double memory chips is effectively reduced.
Next, a system for starting and upgrading a dual memory chip provided by the embodiment of the invention is described in detail. Fig. 2 is a schematic structural diagram of a dual-memory-chip start-up upgrade system according to an embodiment of the present invention, where the system includes a baseboard management controller 11, a complex programmable logic device 12, a switch component 13, a main memory chip 14, and a spare memory chip 15; the baseboard management controller 11 is connected with the main memory chip 14 through a first serial peripheral interface, and the baseboard management controller 11 is connected with the memory chip 15 through a second serial peripheral interface; the switching members 13 are connected to the main memory chip 14 and the spare memory chip 15, respectively.
In an embodiment of the present invention, the baseboard management controller 11 can connect to different memory chips through different serial peripheral interfaces (SERIAL PERIPHERAL INTERFACE, SPI). For ease of description, SPI0 may be used to represent a first serial peripheral interface and SPI1 may be used to represent a second serial peripheral interface.
The complex programmable logic device 12 is respectively connected with the baseboard management controller 11 and the switch component 13, and is used for setting flag bits for the main memory chip 14 and the standby memory chip 15 according to the working states of the main memory chip 14 and the standby memory chip 15 after the system is started; the flag bit comprises a normal start flag bit and an abnormal start flag bit.
In practical applications, the complex programmable logic device 12 may identify whether the memory chip of the baseboard management controller 11 is operating normally by detecting the heartbeat signal of the baseboard management controller 11.
When the system is powered on and started, the baseboard management controller 11 is started from the main memory chip 14 by default, so that the complex programmable logic device 12 can judge whether a heartbeat signal transmitted by the baseboard management controller 11 is received within a set time after the system is started, so as to identify whether the main memory chip 14 works normally.
The value of the set time is not limited herein, and may be set to 30 seconds, for example.
To facilitate understanding of the memory chip from which the baseboard management controller 11 is started, a start flag bit may be set for whether each memory chip is operating properly.
In the case that the heartbeat signal transmitted by the baseboard management controller 11 is received within the set time, it is indicated that the main memory chip 14 can work normally, and the complex programmable logic device 12 can set a normal start flag bit for the main memory chip 14.
When the complex programmable logic device 12 does not receive the heartbeat signal transmitted by the baseboard management controller 11 within the set time, it indicates that the main memory chip 14 is abnormal, and at this time, an abnormal start flag bit may be set for the main memory chip 14, and the switch component 13 is controlled to switch to the spare memory chip 15, so that the baseboard management controller 11 and the spare memory chip 15 are restarted.
After switching to the standby memory chip 15 and restarting, the complex programmable logic device 12 can determine whether a heartbeat signal transmitted by the baseboard management controller 11 is received within a set time; if the heartbeat signal transmitted by the baseboard management controller 11 is not received within the set time, it indicates that the standby memory chip is abnormal, and at this time, an abnormal start flag bit may be set for the standby memory chip 15. When the heartbeat signal transmitted by the baseboard management controller 11 is received within the set time, it is indicated that the spare memory chip 15 can work normally, and at this time, a normal start flag bit can be set for the spare memory chip 15.
In the embodiment of the present invention, in the case that the flag bit of the main memory chip 14 is a normal start flag bit, the baseboard management controller 11 may determine that the start position is to be started from the main memory chip 14; in the case where the flag bit of the main memory chip 14 is an abnormal start flag bit and the flag bit of the standby memory chip 15 is a normal start flag bit, the baseboard management controller 11 may determine that the start position is to be started from the standby memory chip 15.
In the case where the flag bit of the main memory chip 14 is the abnormal start flag bit and the flag bit of the spare memory chip 15 is the abnormal start flag bit, it is indicated that both memory chips have problems, and the memory chip upgrade operation may not be performed at this time.
Considering that baseboard management controller 11 can only be powered on through SPI0, at power on, both from main memory chip 14 and from standby memory chip 15, the SPI0 channel connecting the memory chip to baseboard management controller 11 must be ensured. In the embodiment of the present invention, the purpose of selecting the switch component is also to ensure that the spare memory chip 15 can be connected to the SPI0 channel of the baseboard management controller 11 when the power is turned on.
In performing the switching of the spare memory chip 15, the complex programmable logic device 12 may switch the selection signal of the switch unit 13 to the spare memory chip 15 through a general purpose input/Output (General Purpose Input/Output, GPIO), so that the baseboard management controller 11 communicates with the spare memory chip 15 through the first serial peripheral interface and the switch unit 13. In fig. 2, the dotted line indicates the path between the baseboard management controller 11 and the spare memory chip 15.
The baseboard management controller 11 is configured to determine a starting position according to respective flag bits of the main memory chip 14 and the spare memory chip 15; under the condition that the starting position is the starting of the slave main memory chip 14, the main memory chip 14 is upgraded through a first serial peripheral interface, and the spare memory chip 15 is upgraded through a second serial peripheral interface; under the condition that the starting position is started from the equipment storage chip 15, upgrading the equipment storage chip 15 through a first serial peripheral interface; and restarting after the upgrading is completed.
Under the condition that the main memory chip 14 and the standby memory chip 15 are provided with the abnormal starting flag bit, it is indicated that the main memory chip 14 and the standby memory chip 15 are abnormal, and at this time, the complex programmable logic device 12 can transmit a spare part replacement message to the baseboard management controller 11, so that a manager can repair or replace the main memory chip 14 and the standby memory chip 15 in time.
In the embodiment of the present invention, firmware upgrade control of the baseboard management controller 11 may be implemented by a central processing unit. The central processing unit is connected with the baseboard management controller 11 and is used for detecting the firmware version number of the baseboard management controller 11 under the condition that a firmware upgrading instruction of the baseboard management controller 11 is received; and when the firmware version number is inconsistent with the version number carried in the firmware upgrading instruction, issuing the firmware upgrading instruction to the baseboard management controller 11. The firmware upgrade instruction may carry a firmware file.
The baseboard management controller 11 is configured to execute the step of determining the starting position according to the respective flag bits of the main memory chip 14 and the spare memory chip 15 when receiving the firmware upgrade instruction issued by the central processing unit.
When the firmware upgrade is executed, the firmware version numbers of the memory chips can be checked first to confirm whether the upgrade is needed.
In the case where the start position is the start from the main memory chip 14, it is indicated that the main memory chip 14 can operate normally, and at this time, the main memory chip 14 and the standby memory chip 15 can be upgraded at the same time. Considering that the firmware versions of the main memory chip 14 and the spare memory chip 15 may be different, the main memory chip 14 and the spare memory chip 15 may not both have firmware upgrade requirements, and thus the baseboard management controller 11 may detect whether the firmware version number of the main memory chip 14 is consistent with the version number carried in the firmware upgrade instruction, and whether the firmware version number of the spare memory chip 15 is consistent with the version number carried in the firmware upgrade instruction, respectively.
In the case where the firmware version number of the main memory chip 14 is identical to the version number carried in the firmware upgrade instruction, it is indicated that the main memory chip 14 does not have a firmware upgrade requirement, and at this time, the upgrade operation of the main memory chip 14 may not be performed.
In the case that the firmware version number of the main memory chip 14 is inconsistent with the version number carried in the firmware upgrade instruction, it is indicated that the main memory chip 14 has firmware upgrade requirements, and the baseboard management controller 11 can upgrade the main memory chip 14 through the first serial peripheral interface.
In the case where the firmware version number of the spare memory chip 15 is identical to the version number carried in the firmware upgrade instruction, it is indicated that the spare memory chip 15 does not have a firmware upgrade requirement, and at this time, the upgrade operation of the spare memory chip 15 may not be performed.
In the case that the firmware version number of the spare memory chip 15 is inconsistent with the version number carried in the firmware upgrade instruction, it is indicated that the spare memory chip 15 has firmware upgrade requirements, and the baseboard management controller 11 can upgrade the spare memory chip 15 through the second serial peripheral interface.
In the embodiment of the invention, when the starting position of the baseboard management controller 11 is the starting of the slave main memory chip 14, if the main memory chip 14 and the slave memory chip 15 both have firmware upgrading requirements, the firmware of the main memory chip 14 can be upgraded through the SPI0, and meanwhile, the firmware of the slave memory chip 15 can be upgraded through the SPI1, so that the simultaneous upgrading of the main memory chip 14 and the slave memory chip 15 is realized, and compared with the process that the firmware of the main memory chip 14 can be upgraded firstly and then the firmware of the slave memory node 15 is upgraded after restarting in the traditional mode, the scheme effectively saves the time spent for firmware upgrading.
When the starting position is the starting from the standby memory chip 15, it is indicated that the main memory chip 14 is abnormal, and at this time, the baseboard management controller 11 may only detect whether the firmware version number of the standby memory chip 15 is consistent with the version number carried in the firmware upgrade instruction. In the case where the firmware version number of the spare memory chip 15 is identical to the version number carried in the firmware upgrade instruction, it is indicated that the spare memory chip 15 does not have a firmware upgrade requirement, and at this time, the upgrade operation of the spare memory chip 15 may not be performed. Under the condition that the firmware version number of the spare memory chip 15 is inconsistent with the version number carried in the firmware upgrading instruction, the requirement that the spare memory chip 15 has firmware upgrading is indicated, and at the moment, the spare memory chip 15 can be upgraded through the first serial peripheral interface.
Considering that in practical applications, when the main memory chip 14 is abnormal, the firmware upgrading may solve the abnormal situation, so that the baseboard management controller 11 may also detect whether the firmware version number of the main memory chip 14 is consistent with the version number carried in the firmware upgrading instruction when the starting position is that the slave memory chip 15 is started. In the case where the firmware version number of the main memory chip 14 is identical to the version number carried in the firmware upgrade instruction, it is indicated that the main memory chip 14 does not have a firmware upgrade requirement, and at this time, the upgrade operation of the main memory chip 14 may not be performed. In the case where the firmware version number of the main memory chip 14 is inconsistent with the version number carried in the firmware upgrade instruction, the main memory chip 14 may be upgraded through the first serial peripheral interface.
After the upgrade is completed, the working state of the main memory chip 14 may be detected again, and if the main memory chip 14 is still abnormal, the baseboard management controller 11 may report an alarm message of the abnormality of the main memory chip 14 to the central processing unit.
In the embodiment of the present invention, in order to verify whether the firmware of the memory chip is successfully upgraded, the baseboard management controller 11 may verify the firmware content on each memory chip.
In practical applications, the checksum may be calculated using Message-Digest Algorithm 5 (MD5).
The cpu may carry the MD5 value corresponding to the firmware file when transmitting the firmware file to the baseboard management controller 11. Taking the firmware upgrade operation of the main memory chip 14 as an example, after the firmware upgrade operation of the main memory chip 14 is completed, the baseboard management controller 11 may read the firmware file on the main memory chip 14 and calculate the MD5 value of the firmware file. And judging whether the MD5 value is consistent with the MD5 value transmitted by the central processing unit, and if so, indicating that the firmware of the main memory chip 14 is successfully upgraded. Similarly, taking the firmware upgrade operation of the spare memory chip 15 as an example, after the firmware upgrade operation of the spare memory chip 15 is completed, the baseboard management controller 11 may read the firmware file on the spare memory chip 15 and calculate the MD5 value of the firmware file. And judging whether the MD5 value is consistent with the MD5 value transmitted by the central processing unit, and if so, judging that the firmware of the standby memory chip 15 is successfully upgraded.
In the embodiment of the invention, whether the firmware of the memory chip is successfully upgraded can be accurately identified by identifying whether the firmware file on the memory chip has the risk of data loss or tampering according to the MD5 value of the firmware file.
According to the technical scheme, the starting and upgrading system of the double memory chips comprises a baseboard management controller, a complex programmable logic device, a switch component, a main memory chip and a standby memory chip; the substrate management controller is connected with the main memory chip through a first serial peripheral interface, and is connected with the memory chip through a second serial peripheral interface; the switch component is respectively connected with the main memory chip and the standby memory chip. The complex programmable logic device is respectively connected with the baseboard management controller and the switch component and is used for setting a flag bit for the main memory chip and the standby memory chip according to the working states of the main memory chip and the standby memory chip after the system is started; the flag bit comprises a normal start flag bit and an abnormal start flag bit; the substrate management controller is used for determining a starting position according to the respective zone bit of the main memory chip and the standby memory chip; under the condition that the starting position is the starting of the slave main memory chip, upgrading the main memory chip through a first serial peripheral interface, and upgrading the memory chip through a second serial peripheral interface; under the condition that the starting position is started from the spare memory chip, upgrading the spare memory chip through the first serial peripheral interface; and restarting after the upgrading is completed. The invention has the beneficial effects that the complex programmable logic device is connected with the main memory chip and the standby memory chip through the switch component, and the switching selection of the main memory chip and the standby memory chip can be realized. The two memory chips are independently connected through the two serial peripheral interfaces of the baseboard management controller, so that the simultaneous upgrading of the two memory chips can be realized, and the upgrading time is ensured to be consistent with the upgrading time of a single memory chip. Compared with the traditional double-memory chip upgrading mode, the scheme effectively reduces the time spent by double-memory chip upgrading.
Fig. 3 is a flowchart of a method for starting and upgrading a dual memory chip, which is applicable to a baseboard management controller and includes:
s301: and determining the starting position according to the respective flag bits of the main memory chip and the standby memory chip.
The method comprises the steps that after a system is started up, the flag bits of each of a main memory chip and a standby memory chip are determined by a complex programmable logic device according to the working states of the main memory chip and the standby memory chip.
S302: and under the condition that the starting position is the starting of the slave main memory chip, upgrading the main memory chip through the first serial peripheral interface, and upgrading the memory chip through the second serial peripheral interface.
S303: and under the condition that the starting position is the starting from the spare memory chip, upgrading the spare memory chip through the first serial peripheral interface.
S304: and restarting after the upgrading is completed.
The description of the features in the embodiment corresponding to fig. 3 may be referred to the related description of the embodiment corresponding to fig. 2, which is not repeated here.
According to the technical scheme, the starting position is determined according to the respective flag bits of the main memory chip and the standby memory chip. The flag bits of the main memory chip and the standby memory chip can be determined by the complex programmable logic device according to the working states of the main memory chip and the standby memory chip after the system is started. And under the condition that the starting position is the starting of the slave main memory chip, upgrading the main memory chip through the first serial peripheral interface, and upgrading the memory chip through the second serial peripheral interface. And under the condition that the starting position is the starting from the spare memory chip, upgrading the spare memory chip through the first serial peripheral interface. And restarting after the upgrading is completed. The invention has the beneficial effects that the complex programmable logic device can realize the detection of the working states of the main memory chip and the standby memory chip, thereby controlling the switching selection of the main memory chip and the standby memory chip. The two memory chips are independently connected through the two serial peripheral interfaces of the baseboard management controller, so that the simultaneous upgrading of the two memory chips can be realized, and the upgrading time is ensured to be consistent with the upgrading time of a single memory chip. Compared with the traditional double-memory chip upgrading mode, the scheme effectively reduces the time spent by double-memory chip upgrading.
Fig. 4 is a block diagram of a dual-memory-chip startup upgrade apparatus according to an embodiment of the present invention, where, as shown in fig. 4, the dual-memory-chip startup upgrade apparatus includes: a memory 40 for storing a computer program;
a processor 41 for implementing the steps of the method for starting up the upgrade of the dual memory chip according to the above embodiment when executing the computer program.
The dual-storage-chip startup upgrading device provided in the embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.
Processor 41 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc., among others. The processor 41 may be implemented in at least one hardware form of Digital Signal Processing (DSP), field-Programmable gate array (fieldprogrammable GATE ARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 41 may also include a main processor and a coprocessor, the main processor being a processor for processing data in an awake state, also referred to as a central processor (Central Processing Unit, CPU); a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 41 may be integrated with an image processor (Graphics Processing Unit, GPU) for rendering and rendering of content to be displayed by the display screen. In some embodiments, the processor 41 may also include an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) processor for processing computing operations related to machine learning.
Memory 40 may include one or more computer-readable storage media, which may be non-transitory. Memory 40 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 40 is at least used for storing a computer program 401, where the computer program, after being loaded and executed by the processor 41, can implement the relevant steps of the dual memory chip boot upgrade method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 40 may further include an operating system 402, data 403, and the like, where the storage manner may be transient storage or permanent storage. Operating system 402 may include Windows, unix, linux, among other things. The data 403 may include, but is not limited to, flag bits of a main memory chip and a spare memory chip, etc.
In some embodiments, the dual memory chip boot upgrade apparatus may further include a display screen 42, an input/output interface 43, a communication interface 44, a power supply 45, and a communication bus 46.
Those skilled in the art will appreciate that the configuration shown in FIG. 4 does not constitute a limitation of a dual memory chip boot upgrade apparatus and may include more or fewer components than illustrated.
It will be appreciated that if the method of boot upgrade of the dual memory chip in the above embodiments is implemented in the form of a software functional unit and sold or used as a stand-alone product, it may be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in part or in whole or in part in the form of a software product stored in a storage medium for performing all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), an electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, a magnetic disk, or an optical disk, etc., which can store program codes.
Based on this, the embodiment of the invention also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the dual memory chip start-up upgrade method described above.
The embodiment of the invention also provides a computer program product, which comprises a computer program/instruction, wherein the computer program/instruction realizes the steps of the method for starting and upgrading the double memory chips when being executed by a processor.
The system, the method, the equipment, the medium and the product for starting and upgrading the double memory chips provided by the embodiment of the invention are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The system, the method, the equipment, the medium and the product for starting and upgrading the double memory chips provided by the invention are described in detail. The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present invention and its core ideas. It should be noted that it will be apparent to those skilled in the art that the present invention may be modified and practiced without departing from the spirit of the present invention.
Claims (15)
1. The starting and upgrading system of the double memory chips is characterized by comprising a baseboard management controller, a complex programmable logic device, a switch component, a main memory chip and a standby memory chip; the baseboard management controller is connected with the main memory chip through a first serial peripheral interface, and is connected with the standby memory chip through a second serial peripheral interface; the switch component is respectively connected with the main memory chip and the standby memory chip;
The complex programmable logic device is respectively connected with the baseboard management controller and the switch component and is used for setting a flag bit for the main memory chip and the standby memory chip according to the working states of the main memory chip and the standby memory chip after the system is started; the flag bit comprises a normal start flag bit and an abnormal start flag bit;
The baseboard management controller is used for determining a starting position according to the respective zone bit of the main memory chip and the standby memory chip; under the condition that the starting position is started from the main memory chip, upgrading the main memory chip through the first serial peripheral interface and upgrading the standby memory chip through the second serial peripheral interface; upgrading the standby memory chip through the first serial peripheral interface under the condition that the starting position is started from the standby memory chip; and restarting after the upgrading is completed.
2. The system for starting and upgrading double memory chips as defined in claim 1, wherein the complex programmable logic device is configured to determine whether a heartbeat signal transmitted by the baseboard management controller is received within a set time after the system is started; and setting a normal start flag bit for the main memory chip under the condition that the heartbeat signal transmitted by the baseboard management controller is received within a set time.
3. The dual-memory-chip start-up upgrade system according to claim 2, wherein the complex programmable logic device is configured to set an abnormal start flag bit for the main memory chip and control the switching element to switch to the spare memory chip, and restart the baseboard management controller and the spare memory chip if a heartbeat signal transmitted by the baseboard management controller is not received within a set time; judging whether a heartbeat signal transmitted by the baseboard management controller is received within a set time; setting an abnormal starting zone bit for the standby memory chip under the condition that the heartbeat signal transmitted by the baseboard management controller is not received within a set time; and setting a normal start flag bit for the standby memory chip under the condition that the heartbeat signal transmitted by the baseboard management controller is received within a set time.
4. The dual memory chip boot upgrade system according to claim 3, wherein the complex programmable logic device is configured to switch a selection signal of the switching unit to the spare memory chip through a general-purpose input/output interface, so that the baseboard management controller communicates with the spare memory chip through a first serial peripheral interface and the switching unit.
5. The dual memory chip boot upgrade system according to claim 3, wherein the complex programmable logic device is configured to transmit a spare part replacement message to the baseboard management controller when the main memory chip and the spare memory chip are both set with an abnormal boot flag bit.
6. The dual memory chip boot upgrade system according to claim 1, further comprising a central processing unit;
The central processing unit is connected with the baseboard management controller and is used for detecting the firmware version number of the baseboard management controller under the condition that a firmware upgrading instruction of the baseboard management controller is received; issuing the firmware upgrading instruction to the baseboard management controller under the condition that the firmware version number is inconsistent with the version number carried in the firmware upgrading instruction;
and the baseboard management controller is used for executing the step of determining the starting position according to the respective flag bits of the main memory chip and the standby memory chip under the condition of receiving the firmware upgrading instruction issued by the central processing unit.
7. The dual-memory chip boot upgrade system according to claim 6, wherein the baseboard management controller is configured to detect whether a firmware version number of the main memory chip is consistent with a version number carried in the firmware upgrade instruction and whether a firmware version number of the spare memory chip is consistent with a version number carried in the firmware upgrade instruction, respectively, when the boot position is a boot from the main memory chip; under the condition that the firmware version number of the main memory chip is consistent with the version number carried in the firmware upgrading instruction, the upgrading operation of the main memory chip is not executed; upgrading the main memory chip through the first serial peripheral interface under the condition that the firmware version number of the main memory chip is inconsistent with the version number carried in the firmware upgrading instruction; under the condition that the firmware version number of the spare memory chip is consistent with the version number carried in the firmware upgrading instruction, the upgrading operation of the spare memory chip is not executed; and upgrading the standby memory chip through the second serial peripheral interface under the condition that the firmware version number of the standby memory chip is inconsistent with the version number carried in the firmware upgrading instruction.
8. The dual-memory-chip boot upgrade system according to claim 6, wherein the baseboard management controller is configured to detect whether a firmware version number of the spare memory chip is consistent with a version number carried in the firmware upgrade instruction when the boot position is a boot from the spare memory chip; under the condition that the firmware version number of the spare memory chip is consistent with the version number carried in the firmware upgrading instruction, the upgrading operation of the spare memory chip is not executed; and upgrading the standby memory chip through the first serial peripheral interface under the condition that the firmware version number of the standby memory chip is inconsistent with the version number carried in the firmware upgrading instruction.
9. The dual-memory-chip start-up upgrade system according to claim 8, wherein the baseboard management controller is configured to detect whether a firmware version number of the main memory chip is consistent with a version number carried in the firmware upgrade instruction; under the condition that the firmware version number of the main memory chip is consistent with the version number carried in the firmware upgrading instruction, the upgrading operation of the main memory chip is not executed; and upgrading the main memory chip through the first serial peripheral interface under the condition that the firmware version number of the main memory chip is inconsistent with the version number carried in the firmware upgrading instruction.
10. The dual-memory-chip boot upgrade system according to any one of claims 1 to 9, wherein the baseboard management controller is configured to determine that a boot position is to be booted from the main memory chip if a flag bit of the main memory chip is a normal boot flag bit; and under the condition that the flag bit of the main memory chip is an abnormal starting flag bit and the flag bit of the standby memory chip is a normal starting flag bit, determining the starting position to be started from the standby memory chip.
11. The dual memory chip boot upgrade system according to claim 10, wherein the baseboard management controller is configured to not execute a memory chip upgrade operation in a case where a flag bit of the main memory chip is an abnormal boot flag bit and a flag bit of the spare memory chip is an abnormal boot flag bit.
12. A method for starting and upgrading a dual memory chip, which is suitable for a baseboard management controller, the method comprising:
determining a starting position according to the respective flag bits of the main memory chip and the standby memory chip; the method comprises the steps that after a system is started up, the respective flag bits of a main memory chip and a standby memory chip are determined and obtained according to the working states of the main memory chip and the standby memory chip;
under the condition that the starting position is started from the main memory chip, upgrading the main memory chip through a first serial peripheral interface and upgrading the spare memory chip through a second serial peripheral interface;
Upgrading the standby memory chip through the first serial peripheral interface under the condition that the starting position is started from the standby memory chip;
And restarting after the upgrading is completed.
13. A dual memory chip boot upgrade apparatus comprising:
a memory for storing a computer program;
A processor for executing the computer program to perform the steps of the dual memory chip boot upgrade method of claim 12.
14. A computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, which when executed by a processor, implements the steps of the dual memory chip boot upgrade method of claim 12.
15. A computer program product comprising computer programs/instructions which when executed by a processor implement the steps of the method for boot-up upgrade of dual memory chips of claim 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410763765.4A CN118349290B (en) | 2024-06-13 | 2024-06-13 | Dual-memory chip start-up upgrade system, method, device, medium and product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410763765.4A CN118349290B (en) | 2024-06-13 | 2024-06-13 | Dual-memory chip start-up upgrade system, method, device, medium and product |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118349290A true CN118349290A (en) | 2024-07-16 |
| CN118349290B CN118349290B (en) | 2024-09-17 |
Family
ID=91818367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410763765.4A Active CN118349290B (en) | 2024-06-13 | 2024-06-13 | Dual-memory chip start-up upgrade system, method, device, medium and product |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118349290B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106528097A (en) * | 2016-10-21 | 2017-03-22 | 浙江大华技术股份有限公司 | Version synchronization method for two pieces of BIOS (Basic Input/ Output System) firmware, and electronic equipment |
| CN112667462A (en) * | 2020-12-15 | 2021-04-16 | 苏州浪潮智能科技有限公司 | System, method and medium for monitoring double flash memory operation of server |
| CN114047958A (en) * | 2021-10-31 | 2022-02-15 | 山东云海国创云计算装备产业创新中心有限公司 | Starting method, equipment and medium for baseboard management controller of server |
| CN114860322A (en) * | 2022-04-20 | 2022-08-05 | 联想(北京)信息技术有限公司 | Substrate management controller, control method and electronic equipment |
| CN115129345A (en) * | 2022-07-01 | 2022-09-30 | 苏州浪潮智能科技有限公司 | Firmware upgrading method, device, equipment and storage medium |
| CN115589361A (en) * | 2022-09-28 | 2023-01-10 | 苏州浪潮智能科技有限公司 | Management equipment firmware updating method and device, electronic equipment and storage medium |
| CN115756648A (en) * | 2022-11-22 | 2023-03-07 | 加弘科技咨询(上海)有限公司 | Active recovery method and terminal for double-substrate management controller chip |
-
2024
- 2024-06-13 CN CN202410763765.4A patent/CN118349290B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106528097A (en) * | 2016-10-21 | 2017-03-22 | 浙江大华技术股份有限公司 | Version synchronization method for two pieces of BIOS (Basic Input/ Output System) firmware, and electronic equipment |
| CN112667462A (en) * | 2020-12-15 | 2021-04-16 | 苏州浪潮智能科技有限公司 | System, method and medium for monitoring double flash memory operation of server |
| CN114047958A (en) * | 2021-10-31 | 2022-02-15 | 山东云海国创云计算装备产业创新中心有限公司 | Starting method, equipment and medium for baseboard management controller of server |
| CN114860322A (en) * | 2022-04-20 | 2022-08-05 | 联想(北京)信息技术有限公司 | Substrate management controller, control method and electronic equipment |
| CN115129345A (en) * | 2022-07-01 | 2022-09-30 | 苏州浪潮智能科技有限公司 | Firmware upgrading method, device, equipment and storage medium |
| CN115589361A (en) * | 2022-09-28 | 2023-01-10 | 苏州浪潮智能科技有限公司 | Management equipment firmware updating method and device, electronic equipment and storage medium |
| CN115756648A (en) * | 2022-11-22 | 2023-03-07 | 加弘科技咨询(上海)有限公司 | Active recovery method and terminal for double-substrate management controller chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118349290B (en) | 2024-09-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10514930B2 (en) | Setting a startup parameter and controlling startup of a mainboard | |
| CN106257417B (en) | Boot program upgrading method, embedded equipment, control equipment and embedded system | |
| CN103365696A (en) | BIOS (Basic Input Output System) image file obtaining method and device | |
| US7194614B2 (en) | Boot swap method for multiple processor computer systems | |
| CN112506745B (en) | Memory temperature reading method and device and computer readable storage medium | |
| CN114138644A (en) | BMC (baseboard management controller) debugging method, monitoring method, system, device, equipment and medium | |
| CN110673867A (en) | CPLD online upgrading method, device and system | |
| CN111475175B (en) | Method, device and medium for installing and guiding operation system based on ARM server | |
| CN115113905A (en) | Firmware upgrading method and firmware upgrading device | |
| US20240264914A1 (en) | Method and device for recovering self-test exception of server component, system and medium | |
| CN114035831B (en) | CPLD upgrading method, system and computer readable storage medium | |
| CN114153477A (en) | Method, device, system, equipment and medium for upgrading firmware of PCIE (peripheral component interface express) driver card | |
| CN113641537A (en) | Starting system, method and medium for server | |
| CN118349290B (en) | Dual-memory chip start-up upgrade system, method, device, medium and product | |
| CN106484442B (en) | Server system and method for updating startup mapping file | |
| WO2022199622A1 (en) | Method for running startup program of electronic device, and electronic device | |
| CN114461286B (en) | Server starting method and device, electronic equipment and readable storage medium | |
| CN114461142B (en) | Method, system, device and medium for reading and writing Flash data | |
| CN113821265B (en) | Operating system control method and device, computer mainboard and readable storage medium | |
| CN115766410A (en) | Method, system, device and medium for switching working states of machine | |
| CN115658152A (en) | Firmware upgrading method, firmware, electronic device and computer readable storage medium | |
| CN114995854A (en) | Application program online upgrading method and device, terminal and operation machine | |
| CN113721992A (en) | BIOS starting method and related device of server | |
| CN111176735B (en) | Method for accelerating startup of electrocardiograph | |
| CN114139168B (en) | TPCM measuring method, device and medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |