CN118282358A

CN118282358A - Clock circuit, chip and clock synchronization system

Info

Publication number: CN118282358A
Application number: CN202211667991.XA
Authority: CN
Inventors: 罗祥; 刘维辉; 刘帅锋; 殷文杰
Original assignee: Hefei Chipsea Electronics Technology Co Ltd
Current assignee: Hefei Chipsea Electronics Technology Co Ltd
Priority date: 2022-12-23
Filing date: 2022-12-23
Publication date: 2024-07-02
Also published as: WO2024131950A1

Abstract

The embodiment of the application provides a clock circuit, a chip and a clock synchronization system, wherein the clock circuit comprises: the clock unit is used for generating a clock signal; the control unit is connected with the clock unit and is used for receiving the external clock control signal and generating a corresponding internal clock control signal based on the external clock control signal; the control unit is further used for adjusting the phase of the clock signal according to the internal clock control signal so as to keep the phase relation between the phase of the clock signal and the phase of the external clock control signal constant. By the mode, the asynchronous clock generated by the clock circuit can run synchronously.

Description

Clock circuit, chip and clock synchronization system

Technical Field

The application relates to the technical field of clock signal generation, in particular to a clock circuit, a chip and a clock synchronization system.

Background

The conventional clock circuit can only generate a single oscillation signal (clock signal) for other circuit modules, and if multiple clock signals are needed for multiple circuit modules, multiple clock circuits are generally utilized to generate multiple oscillation signals (asynchronous clocks) respectively. There is no relation between the plurality of oscillation signals, so that the plurality of circuit modules are difficult to integrate and uniformly control.

Disclosure of Invention

The embodiment of the application provides a clock circuit, a chip and a clock synchronization system, which aim to improve/solve the problem that clock signals generated by a plurality of clock circuits in the related art are difficult to synchronously operate.

The present application provides a clock circuit comprising: the clock unit is used for generating a clock signal; the control unit is connected with the clock unit and is used for receiving the external clock control signal and generating a corresponding internal clock control signal based on the external clock control signal; the control unit is further used for adjusting the phase of the clock signal according to the internal clock control signal so as to keep the phase relation between the phase of the clock signal and the phase of the external clock control signal constant.

In some embodiments, the control unit is configured to generate the internal clock control signal at a preset transition edge of the external clock control signal, and adjust a level of the clock signal within a preset delay based on the internal clock control signal.

In some embodiments, the clock unit includes at least one comparator, the clock unit is configured to generate a first intermediate signal and a second intermediate signal with opposite phases according to an output signal of the at least one comparator, and generate the clock signal based on the first intermediate signal and the second intermediate signal; the control unit is used for generating a first control signal and a second control signal at a preset jump edge of an external clock control signal, the first control signal is used for resetting the comparator, and the second control signal is used for pulling the level of the first intermediate signal and the second intermediate signal to a first level so that the clock signal output by the clock unit is of a preset level; the control unit is also used for releasing the clock unit after a preset time delay so as to make the clock signal oscillate again.

In some embodiments, the control unit comprises: the first trigger is used for inputting an external clock control signal, the first output end of the first trigger is used for outputting a first control signal, and the second output end of the first trigger is used for outputting a second control signal; the input end of the first delay module is connected with the first output end of the first trigger; and the output end of the first nor gate is connected with the reset end of the first trigger.

In some embodiments, the clock unit includes at least one comparator, the clock unit is configured to generate a first intermediate signal and a second intermediate signal with opposite phases according to an output signal of the at least one comparator, and generate the clock signal based on the first intermediate signal and the second intermediate signal; the control unit is used for generating a first control signal, a second control signal and a window signal at a preset jump edge of the external clock control signal, wherein the first control signal is used for resetting the comparator, the second control signal is used for pulling the levels of the first intermediate signal and the second intermediate signal to a first level so that the clock signal output by the clock unit is a preset level, and the window signal is used for prolonging the duration time of the current level of the clock signal after the preset jump edge of the external clock control signal arrives; the control unit is also used for releasing the clock unit after a preset time delay so as to make the clock signal oscillate again.

In some embodiments, the clock signal is generated based on an inverted signal of the second intermediate signal; the clock widening circuit includes: the second trigger receives the window signal and the second intermediate signal and outputs a first switch signal, wherein the first switch signal jumps to a second level after the rising edge of the window signal arrives and jumps to a first level after the falling edge of the second intermediate signal arrives; and the first latch is connected with the second trigger and the clock unit and is used for keeping the level of the clock signal output by the clock unit unchanged within the preset level duration time of the first switch signal.

In some embodiments, the clock signal is generated based on an inverted signal of the first intermediate signal; the clock widening circuit includes: the third trigger receives the window signal and the inverted signal of the first intermediate signal and outputs a second switching signal, wherein the second switching signal jumps to a second level after the rising edge of the window signal arrives and jumps to a first level after the falling edge of the inverted signal of the first intermediate signal arrives; and the second latch is connected with the third trigger and the clock unit and is used for keeping the level of the clock signal output by the clock unit unchanged within the preset level duration time of the second switch signal.

The application also provides a chip which comprises the clock circuit.

The application also provides a clock synchronization system, which comprises: a first clock circuit for generating an external clock control signal; and the second clock circuits are connected with the first clock circuit and used for generating corresponding clock signals under the control of external clock control signals, and the second clock circuits are the clock circuits.

The clock circuit provided by the embodiment of the application comprises: the clock unit is used for generating a clock signal; the control unit is connected with the clock unit and is used for receiving the external clock control signal and generating a corresponding internal clock control signal based on the external clock control signal; the control unit is further used for adjusting the phase of the clock signal according to the internal clock control signal so as to keep the phase relation between the phase of the clock signal and the phase of the external clock control signal constant. In this way, the phases of the control clock signal and the external clock control signal are kept constant, so that when the external clock control signal is used to control the plurality of clock circuits, the asynchronous clock signals generated by the plurality of clock circuits are kept constant with the phases of the external clock signals, and the phases of the plurality of clock signals are synchronous, that is, synchronous operation of the plurality of asynchronous clocks can be realized.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a clock circuit provided by the present application;

FIG. 2 is a schematic diagram of clock signal adjustment in one embodiment;

fig. 3 is a schematic structural view of a control unit in the first embodiment of the present application;

FIG. 4 is a schematic diagram of a clock unit according to a first embodiment of the present application;

FIG. 5 is a timing diagram corresponding to the first embodiment of the present application;

fig. 6 is another structural schematic diagram of the control unit in the first embodiment of the present application;

FIG. 7 is a schematic diagram of an embodiment of the generation module of FIG. 4;

FIG. 8 is a schematic diagram illustrating an embodiment of the reset control unit in FIG. 7;

FIG. 9 is a schematic diagram of an embodiment of the voltage generating unit in FIG. 7;

Fig. 10 is a schematic structural view of a control unit in a second embodiment of the present application;

Fig. 11 is another structural schematic diagram of the control unit in the second embodiment of the present application;

FIG. 12 is a schematic diagram of an embodiment of the clock widening circuit of FIG. 11;

FIG. 13 is a timing diagram corresponding to a second embodiment of the present application;

FIG. 14 is a schematic diagram showing the structure of a clock unit according to a third embodiment of the present application;

Fig. 15 is a schematic diagram of the structure of a clock widening circuit in a third embodiment of the present application;

FIG. 16 is a timing diagram corresponding to a third embodiment of the present application;

FIG. 17 is a schematic diagram of a chip according to an embodiment of the present application;

fig. 18 is a schematic structural diagram of an embodiment of a clock synchronization system provided by the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.

In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.

The use of "adapted" or "configured" in this disclosure is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps. In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

In the present application, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described as "exemplary" in this disclosure is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the application. In the following description, details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been described in detail so as not to obscure the description of the application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Referring to fig. 1, fig. 1 is a schematic diagram of a clock circuit according to an embodiment of the present application, and a clock circuit 100 includes a clock unit 10 and a control unit 20.

The clock unit 10 is used for generating a clock signal CLK, the control unit 20 is connected with the clock unit 10, and the control unit 20 is used for receiving an external clock control signal CS and generating a corresponding internal clock control signal based on the external clock control signal CS; and adjusting the phase of the clock signal CLK according to the internal clock control signal so that the phase relationship of the phase of the clock signal CLK and the phase of the external clock control signal CS remains constant.

Wherein, the phase relationship between the phase of the clock signal CLK and the phase of the external clock control signal CS is kept constant, which means that the time difference between the transition edge of the clock signal CLK and the transition edge of the external clock control signal CS is kept constant. For example, when the time corresponding to the transition edge of the external clock control signal CS is T1 and the time corresponding to one transition edge of the adjusted clock signal CLK is T2, then T2-t1=nt+Δt, where T is a half cycle of the clock signal CLK, Δt is a constant value, and n is an integer greater than or equal to 0.

It will be appreciated that if the clock signals CLK generated by the clock circuits 100 are adjusted by the same external clock control signal CS in the above manner, the phase relationship between the phases of the clock signals CLK and the phases of the external clock control signal CS is kept constant, and then the phases of the clock signals CLK are kept synchronous.

Optionally, in an embodiment, the control unit 20 is configured to generate the internal clock control signal at a preset transition edge of the external clock control signal CS, and adjust the level of the clock signal CLK within a preset delay based on the internal clock control signal.

For example, the control unit 20 generates the internal clock control signal at a preset transition edge of the external clock control signal CS, pulls the clock signal CLK down to a low level based on the internal clock control signal, keeps the level of the clock signal CLK low for a preset time delay, and resumes the clock signal CLK after the time delay is completed. As shown in fig. 2, fig. 2 is a schematic diagram illustrating the adjustment of clock signals in an embodiment, where clk_0 is a clock signal generated by the clock unit 10 without the adjustment of the control unit 20, and clk_1 is a clock signal generated by the clock unit 10 with the adjustment of the control unit 20.

When the external clock control signal CS reaches a preset transition edge, such as a falling edge (at time t 1), the clock signal is at a high level, clk_1 is pulled down to a low level at this time, clk_1 is kept at a low level continuously during a time delay period from t1 to t2, after the time delay is completed, the clock unit 10 resumes oscillation, clk_1 jumps to a high level at time t2, and then periodically jumps according to the natural frequency of the clock signal.

In this way, regardless of the phase of the original clock signal clk_0, the level of the clock signal is uniformly adjusted (pulled up or pulled down) when the set level transition is generated by the external clock control signal CS, and clock oscillation is recovered after a constant delay. Then, as long as the period of the clock is the same, from the start of the set level transition (time t 1) of the external clock control signal CS to the first level transition (time t 2) of the clock signal after the clock unit 10 resumes the clock oscillation, the time length (t 1 to t 2) therebetween is constant, i.e., the clock signal having a certain phase relationship with the external clock control signal CS can be generated under the control of the external clock control signal CS.

On this basis, if the clock circuits 100 are utilized, the clock circuits 100 are all under the control of the same external clock control signal CS, and the rising edges or the falling edges of the clock signals generated by the clock circuits 100 can be synchronized, so that the clock signals can be phase-synchronized, i.e. can run synchronously.

Unlike the related art, the clock circuit provided in this embodiment includes: the clock unit is used for generating a clock signal; the control unit is connected with the clock unit and is used for receiving the external clock control signal and generating a corresponding internal clock control signal based on the external clock control signal; the control unit is further used for adjusting the phase of the clock signal according to the internal clock control signal so as to keep the phase relation between the phase of the clock signal and the phase of the external clock control signal constant. In this way, the phases of the control clock signal and the external clock control signal are kept constant, so that when the external clock control signal is used to control the plurality of clock circuits, the asynchronous clock signals generated by the plurality of clock circuits are kept constant with the phases of the external clock signals, and the phases of the plurality of clock signals are synchronous, that is, synchronous operation of the plurality of asynchronous clocks can be realized.

The clock unit 10 and the control unit 20 are further described below. The clock unit 10 includes at least one comparator, the clock unit 10 is configured to generate a first intermediate signal G1 and a second intermediate signal G2 according to a signal output by the comparator, levels of the first intermediate signal G1 and the second intermediate signal G2 are inverted, and the clock signal CLK is generated based on one of the first intermediate signal G1 or the second intermediate signal G2; the control unit 20 generates a first control signal dff_1 for controlling the above-mentioned comparator reset and a second control signal dff_2 for pulling the levels of the first intermediate signal G1 and the second intermediate signal G2 to the first level based on the external clock control signal CS to make the clock signal CLK jump to a preset level; and releasing the clock unit 10 after a preset time delay to allow the clock signal CLK generated by the clock unit 10 to oscillate again.

As can be appreciated, in conjunction with the above-described fig. 2, if the clock signal CLK is generated based on the first intermediate signal G1 (the clock signal CLK is the same as the level of the first intermediate signal G1), at the falling edge of the external clock control signal CS (time t 1), the first control signal dff_1 controls the comparator to reset, and the second control signal dff_2 pulls the first intermediate signal G1 (the clock signal CLK) low so that the clock signal CLK is also pulled low. After a predetermined delay, the first control signal dff_1 releases the comparator, which regenerates the signal to cause the first intermediate signal G1 to jump to a high level at time t2 and to resume oscillation, whereupon the clock signal CLK resumes oscillation.

The clock unit 10 and the control unit 20 of the present application are described below by three embodiments:

first embodiment:

referring to fig. 3, fig. 3 is a schematic diagram of a control unit according to a first embodiment of the present application, and the control unit 20 includes a first flip-flop D1, a first delay module 21, and a first NOR gate nor_1.

First, an enable signal EN and a reset enable signal PDN are defined in the circuit, and the reset enable signal PDN may be obtained by inverting the enable signal EN, opposite to the level of the enable signal EN. As an example, the active level of the enable signal EN is high, i.e., the clock circuit is enabled and generates the clock signal CLK during the period when the enable signal EN is high. The active level of the reset enable signal PDN is low, i.e. during the period when the reset enable signal PDN is low, a normal reset of the first flip-flop D1 in the control unit 20 described below is ensured, and the reset control unit described below is able to normally generate a third control signal (as will be described in detail in the following embodiments).

The input end of the first trigger D1 is used for inputting an external clock control signal CS, the first output end of the first trigger D1 is used for outputting a first control signal dff_1, and the second output end of the first trigger D1 is used for outputting a second control signal dff_2; the input end of the first delay module 21 is connected with the first output end of the first trigger D1, the first input end of the first NOR gate NOR_1 is connected with the output end of the first delay module 21, the second input end of the first NOR gate NOR_1 is used for inputting a reset enabling signal PDN, the output end of the first NOR gate NOR_1 is connected with the reset end of the first trigger D1, and the output end of the first NOR gate NOR_1 outputs a reset signal dff_rst to the reset end of the first trigger D1. After the external clock control signal CS generates a preset time delay after the set level transitions, the reset signal dff_rst is turned to a level capable of resetting the first flip-flop D1, for example, a low level, so that the first flip-flop D1 is cleared and reset after the external clock control signal CS generates the preset time delay after the set level transitions.

In other embodiments, the first NOR gate nor_1 may be not added, but the input terminal of the first delay module 21 is connected to the second output terminal of the first flip-flop D1, and the output terminal of the first delay module 21 is directly connected to the reset terminal of the first flip-flop D1, that is, the reset of the first flip-flop D1 is controlled by the delayed second control signal dff_2.

The first flip-flop D1 is used for edge detection of the external clock control signal CS, and may be, for example, detecting a falling edge, and when the external clock control signal CS is detected to jump from a high level to a low level (falling edge), generating a high-level pulse signal, i.e., a first control signal dff_1, and a second control signal dff_2 opposite to the first control signal dff_1.

Referring to fig. 4, fig. 4 is a schematic diagram of a clock unit according to a first embodiment of the present application, and the clock unit 10 includes a generating module 11, a third NAND gate nand_3, a fourth NAND gate nand_4, and a second inverter N2.

Wherein the generating module 11 comprises at least one comparator and is used for generating an initial signal according to an output signal of the comparator, wherein the initial signal is a pulse signal with high and low levels alternating; the first input end of the third NAND gate NAND_3 is used for inputting an initial signal, the second input end of the third NAND gate NAND_3 is used for inputting a second control signal dff_2, and the output end of the third NAND gate NAND_3 is used for outputting a first intermediate signal G1; the first input end of the fourth NAND gate NAND_4 is connected with the output end of the third NAND gate NAND_3, the second input end of the fourth NAND gate NAND_4 is used for inputting a second control signal dff_2, and the output end of the fourth NAND gate NAND_4 is used for outputting a second intermediate signal G2; the input end of the second inverter N2 is connected to the output end of the fourth NAND gate nand_4, and the output end of the second inverter N2 is used for outputting the clock signal CLK. In the present embodiment, since the first intermediate signal G1 is obtained by processing the initial signal and the second control signal dff_2 through the third NAND gate nand_3, the first intermediate signal G1 is at a high level during the period when the second control signal dff_2 is at a low level; during the period when the two control signals dff_2 are at the high level, the first intermediate signal G1 is opposite in phase to the initial signal. Similarly, since the second intermediate signal G2 is obtained by processing the first intermediate signal G1 and the second control signal dff_2 by the fourth NAND gate nand_4, the second intermediate signal G2 is at a high level during the period when the second control signal dff_2 is at a low level; during the period when the second control signal dff_2 is at the high level, the second intermediate signal G2 is opposite to the first intermediate signal G1 in phase. In addition, since the second inverter N2 inverts the second intermediate signal G2 and outputs it as the clock signal CLK, the phase of the clock signal CLK is the same as that of the first intermediate signal G1, and the clock signal CLK is slightly delayed from the first intermediate signal G1 due to the delay of the inverter.

Referring to fig. 5, fig. 5 is a timing diagram corresponding to the first embodiment of the present application, and the principle of the above circuit is described below with reference to fig. 3 and fig. 4:

When the level of the external clock control signal CS transitions to a low level (falling edge, time t 1), the first control signal dff_1 generated by the first flip-flop D1 transitions to a high level, and the second control signal dff_2 transitions to a low level. The first control signal dff_1 resets the comparator in the generating module 11 during the high level, and the output of the comparator is maintained at the low level, so that the initial signal output by the generating module 11 is also maintained at the fixed level. Meanwhile, the second control signal dff_2 pulls the first intermediate signal G1 and the second intermediate signal G2 to a high level at the same time, and the clock signal CLK is pulled down to a low level since the second intermediate signal G2 is pulled up.

After the first control signal dff_1 passes through a delay (the delay length can be set according to the requirement) of the first delay module 21, a reset signal dff_rst is generated through the first NOR gate nor_1, when the reset signal dff_rst is at a low level, the first trigger D1 is cleared, the first control signal dff_1 output by the first trigger D1 is turned to a low level, and the second control signal dff_2 is turned to a high level. At this time, the comparator in the generating module 11 is no longer controlled by the high level and is released, the initial signal output by the generating module 11 resumes oscillation, the voltages of the first intermediate signal G1 and the second intermediate signal G2 show a high-low change, and the clock signal CLK of normal oscillation is regenerated.

The above signal change process is repeated when the next falling edge of the external clock control signal CS comes.

In fig. 5, t1 is the time when the falling edge of the external clock control signal CS arrives, the time difference from t1 to t2 is the delay length of the first delay module 21, t2 to t3 is the half period length of the normal clock signal, and the time difference (t 3-t 1) between the falling edge (t 1) of the external clock control signal CS and the next rising edge (t 3-t 1) of the clock signal CLK after recovery is constant, that is, the time period from the falling edge of the external clock control signal CS to the first rising edge of the clock signal CLK is ensured to be the same.

As shown in fig. 6, fig. 6 is another schematic structural diagram of the control unit in the first embodiment of the present application, and compared with the embodiment of fig. 3, the control unit 20 in the present embodiment further includes a switch module, an input end of the switch module is used for inputting the external clock control signal CS and the synchronization control enable signal control, and an output end of the switch module is connected to an input end of the first trigger D1. The switch module is configured to output an external clock control signal CS to an input terminal of the first flip-flop when the synchronization control enable signal control is at a first level.

Specifically, the switching module includes a first NAND gate nand_1 and a first inverter N1. The first input end of the first NAND gate NAND_1 is used for inputting an external clock control signal CS, and the second input end of the first NAND gate NAND_1 is used for inputting a synchronous control enabling signal control; the input end of the first inverter N1 is connected with the output end of the first NAND gate NAND_1, and the output end of the first inverter N1 is connected with the input end of the first trigger. Alternatively, the first level may be a high level or a low level. Taking the example that the first level is high level, when the synchronization control enable signal control is high level, if the external clock control signal CS is also high level, the first NAND gate nand_1 outputs low level, and outputs high level after passing through the first inverter N1; if the external clock control signal CS is at a low level, the first NAND gate nand_1 outputs a high level, and outputs a low level after passing through the first inverter N1, so that when the synchronization control enable signal control is at a high level, the output of the switch module follows the external clock control signal CS, and when the synchronization control enable signal control is at a first level, the external clock control signal CS is output to the input terminal of the first flip-flop.

The first output end of the first trigger D1 is used for outputting a first control signal dff_1, and the second output end of the first trigger D is used for outputting a second control signal dff_2; the input end of the first delay module 21 is connected to the first output end of the first trigger D1, the first input end of the first NOR gate nor_1 is connected to the output end of the first delay module 21, the second input end of the first NOR gate nor_1 is used for inputting a reset enable signal PDN, and the output end of the first NOR gate nor_1 is connected to the reset end of the first trigger. Assuming that the reset enable signal PDN is maintained at a high level during the operation of the clock circuit, when the first delay block 21 outputs a high level, the output terminal of the first NOR gate nor_1 outputs a low level reset signal dff_rst, and clears the first flip-flop D1.

Alternatively, the first delay module 21 may include a plurality of cascaded buffers, or an even number of inverters, and the specific number may be set according to the delay requirement.

Unlike the embodiment of fig. 3 described above, the present embodiment adds a synchronization control enable signal control and a switch module to control the enabling of the entire control unit 20, that is, when the synchronization control enable signal control is at a high level, the entire circuit performs clock synchronization adjustment, so that the synchronization function of the clock circuit can be flexibly turned on or off as required.

The generation module 11 will be described below on the basis of fig. 4.

As shown in fig. 7, fig. 7 is a schematic diagram of the structure of an embodiment of the generating module 11 in fig. 4, and the generating module 11 includes a voltage generating unit 111, a comparing unit 112, a reset control unit 113, and a latch unit 114.

Wherein the voltage generating unit 111 is configured to generate a first voltage signal V1 under control of the first intermediate signal G1 and generate a second voltage signal V2 under control of the second intermediate signal G2; the comparing unit 112 includes a first comparator Comp1 and a second comparator Comp2, wherein a first input terminal of the first comparator Comp1 is used for inputting a first voltage signal V1, a second input terminal of the first comparator Comp1 is used for inputting a reference voltage signal Vref, a first input terminal of the second comparator Comp2 is used for inputting a second voltage signal, and a second input terminal of the second comparator Comp2 is used for inputting the reference voltage signal Vref. The first comparator Comp1 compares the first voltage signal V1 with the reference voltage signal Vref and outputs a high level or a low level according to the comparison result; the second comparator Comp2 compares the second voltage signal V2 with the reference voltage signal Vref and outputs a high level or a low level according to the comparison result. With the variation of the first voltage signal V1 and the second voltage signal V2, the output signals of the first comparator Comp1 and the second comparator Comp2 each appear as a pulse signal alternating between high and low levels. A first input terminal of the latch unit 114 is connected to an output terminal of the first comparator Comp1, a second input terminal of the latch unit 114 is connected to an output terminal of the second comparator Comp2, and an output terminal of the latch unit 114 is used for outputting an initial signal. The latch unit 114 latches the pulse signals output from the two comparators and outputs an initial signal. The reset control unit 113 is connected to the comparing unit 112, and is configured to control the first comparator Comp1 and the second comparator Comp2 to reset at a preset transition edge of the external clock control signal CS under the action of the first control signal dff_1.

In combination with the above embodiment, in an alternative embodiment, the first control signal dff_1 or the third control signal dff_3 controls the comparator in the clock unit 10 (or the generating module 11) to reset, the first control signal dff_1 or the third control signal dff_3 may be input to the control terminals of the first comparator Comp1 and the second comparator Comp2, so that the first comparator Comp1 and the second comparator Comp2 are powered down to suspend operation. As can be appreciated, when the control terminals of the first and second comparators Comp1 and Comp2 input the high level signal, the output terminals of the first and second comparators Comp1 and Comp2 output the low level signal.

With further reference to fig. 8, fig. 8 is a schematic structural diagram of an embodiment of the reset control unit 113 in fig. 7, where the reset control unit 113 includes a second NAND gate nand_2 and an OR gate OR; wherein, the first input end of the second NAND gate NAND_2 is used for inputting a start enabling signal OK, and the second input end of the second NAND gate NAND_2 is used for inputting a reset enabling signal PDN; the first input end of the OR gate OR is connected to the output end of the second NAND gate nand_2, the second input end of the OR gate OR is used for inputting the first control signal dff_1, and the output end of the OR gate OR is used for outputting the third control signal dff_3.

Unlike the embodiment of fig. 3, the present embodiment adds control of the enable signal OK, and the third control signal dff_3 after the logic processing is performed on the enable signal OK and the first control signal dff_1 is used for resetting the comparator, so that the control is more flexible than the original control directly through the first control signal dff_1.

With further reference to fig. 9, fig. 9 is a schematic structural diagram of an embodiment of the voltage generating unit in fig. 7, where the voltage generating unit 111 includes a current mirror, a first switch T1, a second switch T2, a first capacitor C1 and a second capacitor C2.

The current mirror comprises a reference branch and a first branch and a second branch of the mirror reference branch, wherein a first end of a first capacitor C1 is connected with the first branch of the current mirror and outputs a first voltage signal V1, and a second end of the first capacitor C1 is grounded; a first end of the first switch T1 is connected with a first end of the first capacitor C1, a second end of the first switch T1 is grounded, and a control end of the first switch T1 is used for inputting a first intermediate signal G1; the first end of the second capacitor C2 is connected with the second branch of the current mirror and outputs a second voltage signal V2, and the second end of the second capacitor C2 is grounded; the first end of the second switch T2 is connected to the first end of the second capacitor C2, the second end of the second switch T2 is grounded, and the control end of the second switch T2 is used for inputting the second intermediate signal G2.

As an embodiment, the first switch T1 and the second switch T2 may be implemented by MOS transistors, for example, NMOS transistors as shown in fig. 9. The current mirror can be a P-type current mirror or an N-type current mirror, and the structure can adopt a basic current mirror structure or a cascode current mirror structure or other structures. Taking a P-type basic current mirror as an example, the reference branch comprises a third transistor T3, the first branch comprises a fourth transistor T4, the second branch comprises a fifth transistor T5, and the gate of the third transistor T3 is connected with the drain and the gate of the fourth transistor T4 and the gate of the fifth transistor T5 to form the basic current mirror. The third transistor T3 is a PMOS transistor, and a first end of the third transistor T3 is used for inputting the power voltage signal VDD; the fourth transistor T4 is a PMOS transistor, a first end of the fourth transistor T4 is used for inputting the power voltage signal VDD, and a second end of the fourth transistor T4 is connected to the first end of the first switch T1; the fifth transistor T5 is a PMOS transistor, a first terminal of the fifth transistor T5 is configured to input the power voltage signal VDD, and a second terminal of the fifth transistor T5 is connected to the first terminal of the second switch T2. In addition, the voltage generating unit 111 may further include a current source through which a current is supplied to the reference branch. As an example, the current source may be a sixth transistor T6 as shown in fig. 9, the sixth transistor T6 may be an NMOS transistor, a first terminal of the sixth transistor T6 is connected to the control terminal and the second terminal of the third transistor T3, a control terminal of the fourth transistor T4, a control terminal of the fifth transistor T5, a second terminal of the sixth transistor T6 is grounded, and a control terminal of the sixth transistor T6 is used for inputting the bias voltage signal v_bias. The bias voltage signal v_bias causes a current to flow between the source and the drain of the sixth transistor T6, and since the third transistor T3 and the sixth transistor T6 are connected in series, the current flows through the third transistor T3 and is mirrored by the fourth transistor T4 and the fifth transistor T5 to obtain two mirror currents, the two mirror currents charge the first capacitor C1 and the second capacitor C2 respectively to generate the first voltage signal V1 and the second voltage signal V2, and then the first voltage signal V1 and the second voltage signal V2 are input to the input terminals of the two comparators (COMP 1 and COMP 2) and are compared with the reference voltage Vref respectively. When the reference voltage Vref is higher than V1 (V2), the corresponding comparator output COMP_OT1 (COMP_OIT 2) is high, and vice versa is low.

Because the first intermediate signal G1 and the second intermediate signal G2 are opposite, one side of the first voltage signal V1 and the second voltage signal V2 is larger, and the other side is smaller, and the first voltage signal V1 and the second voltage signal V2 are compared by the comparator, so that the voltages of the initial signal, the first intermediate signal G1 and the second intermediate signal G2 are inverted again, and a clock signal with a varying level is generated.

In some embodiments, to avoid clock glitches due to transitions of the external control signal CS and the internal control signal, the time taken for the synchronization process, i.e., the time period from the preset transition edge of the external clock control signal to the release of the clock element, may also be extended. The second embodiment and the third embodiment will be described in detail below.

Second embodiment:

The second embodiment is the same as the clock unit 10 of the first embodiment, except that the control unit 20 is configured to generate a first control signal dff_1, a second control signal dff_2 and a window signal Switch at a preset transition edge of the external clock control signal CS, the first control signal dff_1 is configured to reset a comparator in the clock unit 10, the second control signal dff_2 is configured to pull the levels of the first intermediate signal G1 and the second intermediate signal G2 to the first level, so that the clock signal CLK output by the clock unit 10 is at the preset level, and the window signal Switch is configured to extend the duration of the current level of the clock signal CLK after the preset transition edge of the external clock control signal CS arrives; the control unit 20 is further configured to release the clock unit 10 after a preset delay to allow the clock signal CLK to oscillate again.

Referring to fig. 10, fig. 10 is a schematic diagram of a control unit according to a second embodiment of the present application, and the control unit 20 includes a first flip-flop D1, a first delay module 21, a second delay module 22, and a first NOR gate nor_1.

The input end of the first trigger D1 is used for inputting an external clock control signal CS, the first output end of the first trigger D1 is used for outputting a first control signal dff_1, and the second output end of the first trigger D1 is used for outputting a second control signal dff_2; the input end of the first delay module 21 is connected with the first output end of the first trigger D1; the input end of the second delay module 22 is connected with the output end of the first delay module 21; the first input end of the first NOR gate nor_1 is connected to the output end of the second delay module 22, the second input end of the first NOR gate nor_1 is used for inputting a reset enable signal PDN (low level in operation) in operation, the output end of the first NOR gate nor_1 is connected to the reset end of the first flip-flop D1, and the output end of the first NOR gate nor_1 outputs a reset signal dff_rst to the reset end of the first flip-flop D1. After the external clock control signal CS generates a preset time delay after the set level transitions, the reset signal dff_rst is turned to a level capable of resetting the first flip-flop D1, for example, a low level, so that the first flip-flop D1 is cleared and reset after the external clock control signal CS generates the preset time delay after the set level transitions.

With further reference to fig. 11, fig. 11 is another schematic structural diagram of a control unit according to a second embodiment of the present application, and the control unit 20 further includes a control window generating circuit 23 and a clock widening circuit 24.

The input end of the control window generating circuit 23 is used for inputting an external clock control signal CS, and is used for generating a window signal cs_rst after a preset jump edge of the external clock control signal CS arrives; the clock widening circuit 24 is connected to the control window generating circuit 23, and is configured to extend the duration of the current level of the clock signal according to the window signal cs_rst, that is, to widen the first clock signal CLK1 output by the clock unit 10 into the second clock signal CLK2.

Alternatively, as shown in fig. 12, fig. 12 is a schematic diagram of an embodiment of the clock widening circuit in fig. 11, and the clock widening circuit 24 includes a second flip-flop D2 and a first latch S1.

The second flip-flop D2 receives the window signal cs_rst and the second intermediate signal G2, and outputs the first Switch signal switch_1, and the first latch S1 connects the second flip-flop G2 and the clock unit 10, so as to keep the level of the clock signal CLK1 output by the clock unit 10 unchanged during the preset level duration of the first Switch signal switch_1. The preset level of the first Switch signal switch_1 may be a first level or a second level, taking the second level as an example, the first Switch signal switch_1 jumps to the second level after the rising edge of the window signal cs_rst arrives, and jumps to the first level after the falling edge of the second intermediate signal G2 arrives; the first latch S1 keeps the level of the clock signal CLK1 unchanged after the first Switch signal switch_1 transitions to the second level until the first Switch signal switch_1 transitions to the first level again. Wherein the first level may be a high level and the second level may be a low level.

Referring to fig. 13, fig. 13 is a timing diagram corresponding to the second embodiment of the present application, and the principle of the circuit is described below with reference to fig. 4, fig. 7, fig. 10, fig. 11 and fig. 12, which are also shown in the following description:

when the level of the external clock control signal CS transitions to a low level (falling edge, time t 1), the first control signal dff_1 generated by the first flip-flop D1 transitions to a high level, and the second control signal dff_2 transitions to a low level. The first control signal dff_1 resets the comparator in the generating module 11 during the high level, and the output of the comparator is maintained at the low level, so that the initial signal output by the generating module 11 is also maintained at the fixed level. Meanwhile, the second control signal dff_2 pulls the first intermediate signal G1 and the second intermediate signal G2 to high level at the same time, and the clock signals CLK (CLK 1 and CLK 2) are pulled down to low level since the second intermediate signal G2 is pulled up.

After the first control signal dff_1 passes through a delay (delay length may be set according to the requirement) of the first delay module 21 (delay to time t 3) and the second delay module 22 (delay to time t 4), a reset signal dff_rst is generated through the first NOR gate nor_1, and when the reset signal dff_rst is at a low level, the first trigger D1 is cleared, the first control signal dff_1 output by the first trigger D1 is turned to a low level, and the second control signal dff_2 is turned to a high level. At this time, the comparator in the generating module 11 is released, the comparator in the generating module 11 is no longer controlled by the high level, the initial signal output by the generating module 11 resumes oscillation, the voltages of the first intermediate signal G1 and the second intermediate signal G2 show a high-low variation, and the clock signal CLK of normal oscillation is regenerated.

Further, the window signal cs_rst is generated based on the external clock control signal CS, and the first switching signal switch_1 is generated based on the rising edge of the window signal cs_rst and the falling edge of the second intermediate signal G2 such that the first switching signal switch_1 has a wide low level section in which the level of the output second clock signal CLK2 is maintained (i.e., the low level is maintained) regardless of the level of the first clock signal CLK 1.

Third embodiment:

The clock unit 10 of the third embodiment differs from the first embodiment in the manner of generating the clock signal, and the control unit 20 differs from the second embodiment in the manner of generating the switching signal Switch.

Specifically, the control unit 20 is configured to generate, at a preset transition edge of the external clock control signal CS, a first control signal dff_1, a second control signal dff_2, and a window signal Switch, where the first control signal dff_1 is configured to reset a comparator in the clock unit 10, the second control signal dff_2 is configured to pull levels of the first intermediate signal G1 and the second intermediate signal G2 to a first level, so that the clock signal CLK output by the clock unit 10 is at a preset level, and the window signal Switch is configured to extend a duration of a current level of the clock signal CLK after the preset transition edge of the external clock control signal CS arrives; the control unit 20 is further configured to release the clock unit 10 after a preset delay to allow the clock signal CLK to oscillate again.

Referring to fig. 14, fig. 14 is a schematic diagram of a clock unit according to a third embodiment of the present application, and the clock unit 10 includes a generating module 11, a third NAND gate nand_3, a fourth NAND gate nand_4, and a third inverter N3.

Wherein the generating module 11 comprises at least one comparator and is configured to generate an initial signal based on an output signal of the comparator; the first input end of the third NAND gate NAND_3 is used for inputting an initial signal, the second input end of the third NAND gate NAND_3 is used for inputting a second control signal dff_2, and the output end of the third NAND gate NAND_3 is used for outputting a first intermediate signal G1; the first input end of the fourth NAND gate NAND_4 is connected with the output end of the third NAND gate NAND_3, the second input end of the fourth NAND gate NAND_4 is used for inputting a second control signal dff_2, and the output end of the fourth NAND gate NAND_4 is used for outputting a second intermediate signal G2; the input end of the third inverter N3 is connected to the output end of the third NAND gate nand_3, and the output end of the third inverter N3 is configured to output the first clock signal CLK1.

Referring to fig. 11 in combination with the second embodiment, fig. 15 is a schematic diagram of a clock widening circuit 24 according to a third embodiment of the present application, where the clock widening circuit 24 includes a second flip-flop D2 and a first latch S1.

The second flip-flop D2 receives the window signal cs_rst and the inverted signal g1_n of the first intermediate signal, and outputs a second Switch signal switch_2, where the second Switch signal switch_2 transitions to the second level after the rising edge of the window signal cs_rst arrives, and transitions to the first level after the falling edge of the inverted signal g1_n of the first intermediate signal arrives; the first latch S1 is connected to the second flip-flop G2 and the clock unit 10, and is configured to maintain the level of the clock signal CLK1 outputted from the clock unit 10 unchanged during the preset level duration of the second Switch signal switch_2.

Referring now to fig. 16, fig. 16 is a timing diagram corresponding to a third embodiment of the present application, and the principle of the circuit is described below with reference to fig. 3, 6, 7, 11, 14 and 15:

When the level of the external clock control signal CS transitions to a low level (falling edge, time t 1), the first control signal dff_1 generated by the first flip-flop D1 transitions to a high level, and the second control signal dff_2 transitions to a low level. The first control signal dff_1 resets the comparator in the generating module 11 during the high level, and the output of the comparator is maintained at the low level, so that the initial signal output by the generating module 11 is also maintained at the fixed level. Meanwhile, the second control signal dff_2 pulls the first intermediate signal G1 and the second intermediate signal G2 to high level at the same time, and the clock signal CLK (CLK 1 and CLK 2) is pulled down to low level since the first intermediate signal G1 is pulled up and the inverted signal g1_n of the first intermediate signal is pulled down.

After the first control signal dff_1 passes through a delay (the delay length can be set according to the requirement) of the first delay module 21 (the delay time reaches the time t 3), a reset signal dff_rst is generated through the first NOR gate nor_1, when the reset signal dff_rst is at a low level, the first trigger D1 is cleared, the first control signal dff_1 output by the first trigger D1 is turned to a low level, and the second control signal dff_2 is turned to a high level. At this time, the comparator in the generating module 11 is no longer controlled by the high level and is released, the initial signal output by the generating module 11 resumes oscillation, the voltages of the first intermediate signal G1 and the second intermediate signal G2 show a high-low change, and the clock signal CLK of normal oscillation is regenerated.

Further, the window signal cs_rst is generated based on the external clock control signal CS, and the second switching signal switch_2 is generated based on the rising edge of the window signal cs_rst and the falling edge of the inverted signal g1_n of the first intermediate signal G1, so that the second switching signal switch_2 has a wide low level section in which the level of the output second clock signal CLK2 is maintained constant (i.e., maintains a low level) regardless of the level of the first clock signal CLK 1.

As can be appreciated, the clock widening circuits added to the above second and third embodiments can ensure that glitches generated by transitions of the external control signal CS and the internal control signals (dff_1, dff_2, dff_rst, etc.) are avoided during clock output, since the level of the clock signal is kept constant by the first latch S1 in the clock widening circuit.

Referring to fig. 17, fig. 17 is a schematic structural diagram of an embodiment of a chip provided by the present application, in which a clock circuit 100 is integrated in the chip 200, and the clock circuit 100 is a clock circuit as described in the above embodiment, which is not described herein again.

As an embodiment, the chip 200 may further include one or more operation circuits, each of which is connected to the clock circuit 100 and operates according to a clock signal provided by the clock circuit 100. When the chips respectively receive the same external clock control signal and adjust the clock phase based on the same external clock control signal, the clocks of the chips can be synchronized, so that the running circuits in the chips run synchronously.

Alternatively, the operating circuit may be any circuit that needs to operate according to a clock, including but not limited to an analog-to-digital converter, a communication interface, a Microcontroller (MCU), etc.

The chip 200 may be embodied in the form of a wafer, a dicing die, or a packaging sheet, which is not limited in this embodiment.

Referring to fig. 18, fig. 18 is a schematic diagram of a clock synchronization system according to an embodiment of the present application, and the clock synchronization system 300 includes a first clock circuit 301 and a plurality of second clock circuits 302.

Wherein the first clock circuit 301 is configured to generate an external clock control signal CS; each second clock circuit 302 is connected to the first clock circuit 301 for generating a corresponding clock signal CLK under the control of an external clock control signal CS.

The first clock circuit 301 may be a conventional clock circuit, for example, may include a crystal oscillator, a crystal oscillator control chip, and a capacitor, and the second clock circuit 302 is a clock circuit or chip described in the above embodiments.

Alternatively, the plurality of second clock circuits 302 may be provided inside the same electronic device or may be provided in different electronic devices. The first clock circuit 301 and any one of the second clock circuits 302 may be provided in the same electronic device, or may be provided in different electronic devices.

It will be appreciated that since the clock signals of the plurality of clock circuits 302 are each capable of maintaining a constant phase relationship with the external clock control signal CS under the control of the external clock control signal CS, as described in the previous embodiments, the length of time between the first rising edge of the clock signal generated by the clock circuits and the falling edge of the external clock control signal CS is constant, so that the plurality of asynchronous clock signals can run synchronously.

The foregoing has outlined rather broadly the more detailed description of embodiments of the application, wherein the principles and embodiments of the application are explained in detail using specific examples, the above examples being provided solely to facilitate the understanding of the method and core concepts of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.

Claims

1. A clock circuit, the clock circuit comprising:

The clock unit is used for generating a clock signal;

The control unit is connected with the clock unit and is used for receiving an external clock control signal and generating a corresponding internal clock control signal based on the external clock control signal;

The control unit is further configured to adjust a phase of the clock signal according to the internal clock control signal, so that a phase relationship between the phase of the clock signal and the phase of the external clock control signal is kept constant.

2. The clock circuit of claim 1, wherein the clock circuit comprises a plurality of clock circuits,

The control unit is used for generating the internal clock control signal at a preset jump edge of the external clock control signal and adjusting the level of the clock signal within a preset time delay based on the internal clock control signal.

3. The clock circuit of claim 2, wherein the clock circuit comprises a clock circuit,

The clock unit comprises at least one comparator, and is used for generating a first intermediate signal and a second intermediate signal with opposite phases according to the output signal of the at least one comparator, and generating the clock signal based on the first intermediate signal and the second intermediate signal;

The control unit is used for generating a first control signal and a second control signal at a preset jump edge of the external clock control signal, the first control signal is used for resetting the comparator, and the second control signal is used for pulling the levels of the first intermediate signal and the second intermediate signal to a first level so as to enable the clock signal output by the clock unit to be at a preset level;

the control unit is also used for releasing the clock unit after a preset time delay so as to enable the clock signal to oscillate again.

4. The clock circuit of claim 3, wherein the clock circuit comprises a clock circuit,

The control unit includes:

The input end of the first trigger is used for inputting the external clock control signal, the first output end of the first trigger is used for outputting the first control signal, and the second output end of the first trigger is used for outputting the second control signal;

the input end of the first delay module is connected with the first output end of the first trigger;

The first input end of the first NOR gate is connected with the output end of the first delay module, the second input end of the first NOR gate is used for inputting a reset enabling signal, and the 5 output end of the first NOR gate is connected with the reset end of the first trigger.

5. The clock circuit of claim 4, wherein the clock circuit comprises a clock circuit,

The control unit further comprises a switch module, wherein the input end of the switch module is used for inputting the external clock control signal and the synchronous control enabling signal, and the output end of the switch module is connected with the input end of the first trigger;

And 0, wherein the switch module is used for outputting the external clock control signal to the input end of the first trigger when the synchronous control enabling signal is at a first level.

6. The clock circuit of claim 5, wherein the clock circuit comprises a clock circuit,

The switch module includes:

the first input end of the first NAND gate is used for inputting the external clock control signal 5, and the second input end of the first NAND gate is used for inputting the synchronous control enabling signal;

The input end of the first inverter is connected with the output end of the first NAND gate, and the output end of the first inverter is connected with the input end of the first trigger.

7. The clock circuit of claim 2, wherein the clock circuit comprises a clock circuit,

The clock unit comprises at least one comparator, and is used for generating a first intermediate signal and a second intermediate signal with opposite phases according to an output signal of the at least one comparator 0, and generating the clock signal based on the first intermediate signal and the second intermediate signal;

The control unit is used for generating a first control signal, a second control signal and a window signal at a preset jump edge of the external clock control signal, wherein the first control signal is used for resetting the comparator, the second control signal is used for pulling the levels of the first intermediate signal and the second intermediate signal to a first 5 level so that the clock signal output by the clock unit is at the preset level, and the window signal is used for prolonging the duration time of the current level of the clock signal after the preset jump edge of the external clock control signal arrives;

8. The clock circuit of claim 7, wherein the clock circuit comprises a plurality of clock circuits,

The control unit includes:

The input end of the second delay module is connected with the output end of the first delay module;

The first input end of the first NOR gate is connected with the output end of the second delay module, the second input end of the first NOR gate is used for inputting a reset enabling signal, and the output end of the first NOR gate is connected with the reset end of the first trigger.

9. The clock circuit of claim 7, wherein the clock circuit comprises a plurality of clock circuits,

The control unit includes:

The input end of the control window generation circuit is used for inputting the external clock control signal and generating the window signal after the preset jump edge of the external clock control signal arrives;

and the clock widening circuit is connected with the control window generating circuit and used for prolonging the duration time of the current level of the clock signal according to the window signal.

10. The clock circuit of claim 9, wherein the clock circuit comprises a plurality of clock circuits,

The clock signal is generated based on an inverted signal of the second intermediate signal;

the clock widening circuit includes:

The second trigger receives the window signal and the second intermediate signal and outputs a first switch signal, wherein the first switch signal jumps to a second level after the rising edge of the window signal arrives and jumps to a first level after the falling edge of the second intermediate signal arrives;

And the first latch is connected with the second trigger and the clock unit and is used for keeping the level of the clock signal output by the clock unit unchanged within the preset level duration time of the first switch signal.

11. The clock circuit of claim 9, wherein the clock circuit comprises a clock circuit,

The clock signal is generated based on an inverted signal of the first intermediate signal;

the clock widening circuit includes:

A third flip-flop that receives the window signal and an inverted signal of the first intermediate signal and outputs a second switching signal that transitions to a second level after a rising edge of the window signal arrives and transitions to a first level after a falling edge of the inverted signal of the first intermediate signal arrives;

And the second latch is connected with the third trigger and the clock unit and is used for keeping the level of the clock signal output by the clock unit unchanged within the preset level duration time of the second switch signal.

12. A clock circuit as claimed in claim 3 or 10, wherein,

The clock unit includes:

A generation module comprising the at least one comparator and configured to generate an initial signal according to an output signal of the comparator;

The first input end of the third NAND gate is used for inputting the initial signal, the second input end of the third NAND gate is used for inputting the second control signal, and the output end of the third NAND gate is used for outputting the first intermediate signal;

The first input end of the fourth NAND gate is connected with the output end of the third NAND gate, the second input end of the fourth NAND gate is used for inputting the second control signal, and the output end of the fourth NAND gate is used for outputting the second intermediate signal;

And the input end of the second inverter is connected with the output end of the fourth NAND gate, and the output end of the second inverter is used for outputting the clock signal.

13. The clock circuit of claim 11, wherein the clock circuit comprises a clock circuit,

The clock unit includes:

and the input end of the third inverter is connected with the output end of the third NAND gate, and the output end of the third inverter is used for outputting the clock signal.

14. A clock circuit as claimed in claim 12 or 13, wherein,

The generation module comprises:

A voltage generating unit for generating a first voltage signal under control of the first intermediate signal and a second voltage signal under control of the second intermediate signal;

The comparison unit comprises a first comparator and a second comparator, wherein the positive end of the first comparator is used for inputting the first voltage signal, the negative end of the first comparator is used for inputting a reference voltage signal, the positive end of the second comparator is used for inputting the second voltage signal, and the negative end of the second comparator is used for inputting the reference voltage signal;

The reset control unit is connected with the comparison unit and used for controlling the first comparator and the second comparator to reset at the preset jump edge of the external clock control signal under the action of the first control signal;

The first input end of the latch unit is connected with the output end of the first comparator, the second input end of the latch unit is connected with the output end of the second comparator, and the output end of the latch unit is used for outputting the initial signal.

15. The clock circuit of claim 14, wherein the clock circuit comprises a clock circuit,

The voltage generation unit includes:

the current mirror comprises a reference branch, a first branch and a second branch, wherein the first branch and the second branch are used for mirroring the reference branch;

The first end of the first capacitor is connected with the first branch of the current mirror and outputs the first voltage signal, and the second end of the first capacitor is grounded;

The first end of the first switch is connected with the first end of the first capacitor, the second end of the first switch is grounded, and the control end of the first switch is used for inputting the first intermediate signal;

The first end of the second capacitor is connected with the second branch of the current mirror and outputs the second voltage signal, and the second end of the second capacitor is grounded;

And the first end of the second switch is connected with the first end of the second capacitor, the second end of the second switch is grounded, and the control end of the second switch is used for inputting the second intermediate signal.

16. The clock circuit of claim 14, wherein the clock circuit comprises a clock circuit,

The reset control unit further includes:

the first input end of the second NAND gate is used for inputting a start enabling signal, and the second input end of the second NAND gate is used for inputting a reset enabling signal;

the first input end of the OR gate is connected with the output end of the second NAND gate, the second input end of the OR gate is used for inputting the first control signal, and the output end of the OR gate is connected with the control ends of the first comparator and the second comparator.

17. A chip comprising a clock circuit as claimed in any one of claims 1 to 16.

18. A clock synchronization system, the clock synchronization system comprising:

a first clock circuit for generating an external clock control signal;

A plurality of second clock circuits, each of the second clock circuits being connected to the first clock circuit for generating a corresponding clock signal under control of the external clock control signal, the second clock circuits being clock circuits as claimed in any one of claims 1 to 16.