CN217307668U - Clock generation circuit and image sensor - Google Patents
Clock generation circuit and image sensor Download PDFInfo
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- CN217307668U CN217307668U CN202221116178.9U CN202221116178U CN217307668U CN 217307668 U CN217307668 U CN 217307668U CN 202221116178 U CN202221116178 U CN 202221116178U CN 217307668 U CN217307668 U CN 217307668U
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Abstract
The application provides a clock generating circuit and an image sensor, wherein the frequency and the phase of a received input clock signal are tracked through a phase-locked loop circuit so as to output a first output clock signal, and a second output clock signal is fed back to the input end of the phase-locked loop circuit; the delay circuit delays the first output clock signal to output a delayed clock signal; the detection circuit receives an external input reference clock signal and a delay clock signal and outputs a detection signal based on the frequency and/or the phase of the external input reference clock signal and the delay clock signal; the delay circuit adjusts the delay time of the first output clock signal based on the detection signal, and establishes an internal clock signal with the same phase as the second output clock signal based on the delay clock signal and the delay time; the selection circuit selects and outputs an external input reference clock signal or an internal clock signal to the phase-locked loop circuit based on the detection signal; according to the method and the device, the interface is not required to be occupied to input the external input reference clock signal, and the data transmission efficiency is improved.
Description
Technical Field
The application belongs to the technical field of electronic circuits, and particularly relates to a clock generation circuit and an image sensor.
Background
The miniature camera module has the characteristics of small volume and simple structure, and an Inter-Integrated Circuit (I2C) interface is usually adopted for data transmission. If one port is always occupied for clock signal input, the operation is troublesome and the data transmission efficiency is low, so that when the miniature camera module adopts a four-port structure, the port cannot be distributed to provide a reference clock signal for a phase-locked loop in the module, and at the moment, the clock signal needs to be completely generated through an internal circuit of the module. However, the frequency generated by the oscillator has a large deviation with factors such as the process, and the application requirements are difficult to meet.
SUMMERY OF THE UTILITY MODEL
The present application provides a clock generation circuit and an image sensor, which are used to solve the problem that the clock generation circuit cannot generate a clock signal through a module internal circuit.
An embodiment of the present application provides a clock generation circuit, including: the phase-locked loop circuit, the delay circuit, the selection circuit and the detection circuit;
the phase-locked loop circuit is configured to track the frequency and phase of an input clock signal received by the phase-locked loop circuit, so as to output a first output clock signal to the delay circuit and feed back a second output clock signal to the input end of the phase-locked loop circuit;
the delay circuit is configured to delay the first output clock signal to output a delayed clock signal;
the detection circuit is configured to receive an externally input reference clock signal and the delayed clock signal and output a detection signal based on the frequency and/or phase of the two;
the delay circuit adjusts the delay time of the first output clock signal based on the detection signal, and establishes an internal clock signal based on the delay clock signal and the delay time, wherein the phase of the internal clock signal is the same as that of the second output clock signal;
the selection circuit is configured to receive the external input reference clock signal and the internal clock signal, and to selectively output the external input reference clock signal or the internal clock signal to the phase-locked loop circuit based on the detection signal.
The embodiment of the utility model provides a still provide an image sensor, image sensor includes foretell clock generation circuit.
Compared with the prior art, the embodiment of the utility model beneficial effect who exists is: because the internal clock signal is used as the reference clock after the internal clock signal is aligned with the external input reference clock signal, the clock terminal SCL of the external interface is not required to access the external input reference clock signal, and at the moment, the clock terminal SCL can be used for transmitting data, thereby improving the data transmission efficiency.
Drawings
In order to more clearly illustrate the technical utility model in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a clock generation circuit according to an embodiment of the present application;
fig. 2 is a schematic diagram of another structure of a clock generation circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a logic circuit in a clock generation circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a phase-locked loop circuit in a clock generation circuit according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a delay circuit in a clock generation circuit according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of another structure of a phase-locked loop circuit in a clock generation circuit according to an embodiment of the present disclosure;
FIG. 7 is a partial schematic circuit diagram of a clock generation circuit according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram of an output waveform of a voltage controlled oscillator in a clock generation circuit according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a key waveform of a clock generation circuit according to an embodiment of the present application;
FIG. 10 is a schematic diagram of another key waveform of a clock generation circuit according to an embodiment of the present application;
fig. 11 is a schematic diagram of a four-port structure of a miniature camera module.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings to facilitate the description of the application and to simplify the description, and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed in a particular orientation, and be constructed in operation as a limitation of the application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Fig. 1 shows a schematic structural diagram of a clock generation circuit provided in a preferred embodiment of the present application, and for convenience of description, only the parts related to this embodiment are shown, and the details are as follows:
the clock generation circuit includes a phase-locked loop circuit 12, a delay circuit 13, a selection circuit 11, and a detection circuit 15.
The pll circuit 12 is configured to track the frequency and phase of the input clock signal it receives, to output a first output clock signal to the delay circuit 13, and to feed back a second output clock signal to the input of the pll circuit 12.
The delay circuit 13 is configured to delay the first output clock signal to output a delayed clock signal.
The detection circuit 15 is configured to receive an externally input reference clock signal and a delayed clock signal and output a detection signal based on the frequency and/or phase of both.
The delay circuit 13 adjusts a delay time for the first output clock signal based on the detection signal, and establishes an internal clock signal based on the delay clock signal and the delay time, the internal clock signal having the same phase as the second output clock signal.
The selection circuit 11 is configured to receive an externally input reference clock signal and an internal clock signal, and selectively output the externally input reference clock signal or the internal clock signal to the phase-locked loop circuit 12 based on the detection signal.
Wherein, at different stages, the input clock signal is an external input reference clock signal or an internal clock signal.
The working process of the clock generation circuit is divided into the following three stages:
1. phase-locked loop establishing phase. At this time, the external input reference clock signal is input from the clock terminal SCL of the I2C interface, and the selection circuit 11 accesses the external input reference clock signal to the phase-locked loop circuit 12 as the reference clock, i.e. the input clock signal received by the phase-locked loop circuit 12 at this stage is the external input reference clock signal.
2. A self-calibration signal generation phase. After a certain time, the pll circuit locks, and the pll circuit 12 outputs two paths of signals (a first output clock signal and a second output clock signal) with a phase difference. The delay length of the first output clock signal is adjusted by the delay circuit 13, the detection circuit 15 compares the adjusted first output clock signal with an external input reference clock, and finally, the two input signals (the adjusted first output clock signal and the external input reference clock signal) of the detection circuit 15 have no phase difference, and the delay circuit 13 outputs the adjusted first output clock signal without the phase difference as an internal clock signal.
3. And a phase-locked loop stable output stage. When the internal clock signal is aligned with the external input reference clock signal, the detection signal output by the detection circuit 15 is inverted, so as to trigger the selection circuit 11 to access the internal clock signal into the phase-locked loop circuit 12 as the reference clock, i.e. the input clock signal received by the phase-locked loop circuit 12 at this stage is the internal clock signal, and then the phase-locked loop circuit 12 outputs a stable frequency and does not rely on the clock terminal SCL to access the external input reference clock signal.
Through the three stages, the internal clock signal is established by utilizing the external input reference clock signal accessed by the clock terminal SCL of the external interface, when the internal clock signal is aligned with the external input reference clock signal, the internal clock signal is used as the reference clock, the clock terminal SCL is not required to be accessed to the external input reference clock signal, and at the moment, the clock terminal SCL can be used for transmitting data, so that the data transmission efficiency is improved.
As shown in fig. 2, the clock generation circuit further includes a logic circuit 16.
And the logic circuit 16 is electrically connected with the detection circuit 15 and the delay circuit 13 and is configured to output a delay control signal to the delay circuit 13 according to the detection signal so as to control the delay time of the delay circuit 13.
The delay circuit 13 is specifically configured to delay the first output clock signal according to the delay control signal to output the internal clock signal; when the delay control signal is locked, the phase of the internal clock signal is the same as that of the second output clock signal.
As shown in fig. 3, the logic circuit 16 includes a judgment circuit 161, a counter 162, and a digital circuit 163.
The determination circuit 161 is connected to the detection circuit 15, and configured to output the trigger signal and maintain or disconnect the output of the trigger signal based on the detection signal.
And a counter 162 connected to the determination circuit 161 and configured to count to output a count result when the trigger signal is received and stop counting to lock the count result when the trigger signal is turned off.
And a digital circuit 163 connected to the counter 162 and the delay circuit 13, and configured to output a delay control signal according to the counting result.
Since the counter 162 counts to output a count result when receiving the trigger signal, and the digital circuit 163 outputs the delay control signal according to the count result; therefore, the delay control signal is gradually adjusted when the internal clock signal is not aligned with the external input reference clock signal. Since the judgment circuit 161 turns off the output of the trigger signal when receiving the detection signal, the counter 162 stops counting to lock the counting result when the trigger signal is turned off; therefore, the delay control signal is locked when the internal clock signal is aligned with the external input reference clock signal.
As shown in fig. 4, the phase-locked loop circuit 12 includes a phase frequency detector 121, a charge pump 122, a main loop filter 123, and a voltage-controlled oscillator 124.
The phase frequency detector 121 is connected to the selection circuit 11, and configured to detect a phase difference between the input clock signal and the second output clock signal and generate a first control signal.
It will be appreciated that at different stages, the input clock signal is either an externally input reference clock signal or an internal clock signal.
The charge pump 122 is connected to the phase frequency detector 121 and configured to charge and discharge according to the first control signal to output a first control voltage.
A main loop filter 123, connected to the charge pump 122, configured to filter the first control voltage to generate a modulation voltage.
And a voltage controlled oscillator 124 connected to the main loop filter 123 and the delay circuit 13, and configured to output a first output clock signal and a second output clock signal having frequencies proportional to the modulation voltage.
As shown in fig. 5, the delay circuit 13 includes a first frequency divider 132 and a variable delay module 131, and the variable delay module 131 delays the first output clock signal based on the detection signal and outputs the delayed clock signal to the first frequency divider 132 to expand the frequency range of the delayed clock signal; as shown in fig. 6, the phase-locked loop circuit 12 further includes a second frequency divider 125, and the second frequency divider 125 is connected to the voltage-controlled oscillator 124 and the phase frequency detector 121, and configured to divide the frequency of the second output clock signal to output the divided frequency of the second output clock signal to an input of the phase frequency detector 121.
Wherein the dividing ratios of the first frequency divider 132 and the second frequency divider 125 are the same.
When the frequency of the output clock signal of the phase-locked loop circuit 12 is too high, the output signal needs to be decreased from high to low by the frequency divider because the phase frequency detector 121 has a certain upper limit.
The present application also provides a control method of the clock generation circuit, where the clock generation circuit includes a clock signal establishment state and a clock signal stable output state; in the clock signal establishing state, an external input reference clock signal is accessed to the detection circuit 15 and the selection circuit 11, and the selection circuit 11 outputs the external input reference clock signal to the phase-locked loop circuit 12 to be used as an input clock signal of the phase-locked loop circuit 12; the phase-locked loop circuit 12 outputs a first output clock signal and a second output clock signal having a constant phase difference based on an externally input reference clock signal; the delay circuit 13 delays the first output clock signal and outputs a delayed clock signal; the detection circuit 15 compares the frequency and the phase of the externally input reference clock signal and the delayed clock signal, and outputs a detection signal; the delay circuit 13 adjusts a delay time based on the detection signal to output an internal clock signal having the same frequency and phase as the second output clock signal.
In the stable output state of the clock signal, the connection of the external input reference clock signal is disconnected, and the selection circuit 11 outputs the internal clock signal to the phase-locked loop circuit 12 as the input clock signal of the phase-locked loop circuit 12.
In combination with the three phases of the working process of the clock generation circuit, the clock signal establishment state of the present embodiment includes a phase-locked loop establishment phase and a self-calibration signal generation phase, and the stable clock signal output state is the phase-locked loop stable output phase.
Fig. 7 shows a partial example circuit structure of a clock generation circuit provided in an embodiment of the present invention, and for convenience of description, only the portions related to the embodiment of the present invention are shown, and detailed descriptions are as follows:
the voltage controlled oscillator 124 includes an operational amplifier U1, a first inverter U2, a second inverter U3, and a third inverter U4.
The non-inverting input terminal of the operational amplifier U1 is used as the modulation voltage input terminal of the voltage controlled oscillator 124, and is connected to the main loop filter 123 to receive the modulation voltage; the inverting input terminal of the operational amplifier U1 is connected to the output terminal of the operational amplifier U1, the power supply terminal of the first inverter U2, the power supply terminal of the second inverter U3 and the power supply terminal of the third inverter U4; the input end of the first inverter U2 and the output end of the third inverter U4 are used together as a first output clock signal output end of the voltage-controlled oscillator 124, and are connected with the delay circuit 13 to output a first output clock signal; the output end of the second inverter U3 and the input end of the third inverter U4 are used together as a second output clock signal output end of the voltage-controlled oscillator 124, and are connected to the second frequency divider 125 to output a second output clock signal; the output of the first inverter U2 is connected to the input of the second inverter U3.
The voltage-controlled oscillator 124 is implemented by three-level ring oscillation, and a modulation voltage is applied to a power supply terminal of the inverter through an operational amplifier U1 (the operational amplifier U1 is used for preventing the ring oscillator from shaking) to control the ring oscillation frequency, where the ring oscillator may be formed by connecting 3 inverters with each other, or may be formed by connecting 5 inverters with each other, and the number of the inverters is an odd number greater than 2 and forms a loop.
Fig. 8 is an output waveform of the three-stage ring oscillator, where VX and VZ are the first output clock signal and the second output clock signal, respectively, and it can be seen from the figure that the first output clock signal is delayed by 2 pi/3 cycles, i.e. the first output clock signal coincides with the waveform of the second output clock signal, so that the circuit delay time is 2 pi/3 cycles at this time.
As shown in fig. 7, the variable delay module 131 includes a first fet M1, a second fet M2, a third fet M3, a fourth fet M4, a fifth fet M5, a sixth fet M6, n capacitors Ci, and n switching transistors Ki; wherein n is a natural number greater than 0, and i is a positive integer less than or equal to n.
The drain of the first fet M1 and the drain of the fifth fet M5 are commonly connected to the first power supply VAA, and the gate of the first fet M1 serves as the first bias signal input terminal of the variable delay module 131 to receive the first bias signal; the source of the first field effect transistor M1 is connected to the drain of the second field effect transistor M2, and the gate of the second field effect transistor M2 and the gate of the third field effect transistor M3 are used together as the first output clock signal input terminal of the variable delay module 131, and are connected to the phase-locked loop circuit 12 to access the first output clock signal; the source of the second fet M2 is connected to the drain of the third fet M3, the first input/output terminals of the n switching transistors Ki, the gate of the fifth fet M5, and the gate of the sixth fet M6, the second input/output terminal of the ith switching transistor Ki is connected to the first terminal of the ith capacitor Ci, the second terminals of the n capacitors Ci, the source of the fourth fet M4, and the source of the sixth fet M6 are commonly connected to the power ground, the source of the third fet M3 is connected to the drain of the fourth fet M4, and the gate of the fourth fet M4 is used as the second bias signal input terminal of the variable delay module 131 to receive the second bias signal; the source of the fifth fet M5 and the drain of the sixth fet M6 are used together as the delay clock signal output terminal of the variable delay module 131, and are connected to the first frequency divider 132 to output a delay clock signal; the control ends of the n switching tubes Ki are used as the input end of the delay control signal of the variable delay module 131 together to access the delay control signal.
The variable delay module 131 changes the size of the capacitor in the access circuit by turning on the switching tube, so as to adjust the delay time of the circuit, and the more the capacitors are connected in parallel, the longer the delay time is. The first field effect transistor M1 and the fourth field effect transistor M4 determine the charging and discharging current of the circuit, and can be adjusted by the first bias signal and the second bias signal. It should be emphasized that, in the present application, the variable delay module 131 can be implemented without providing the first bias signal and the second bias signal, but to further improve the flexibility of circuit adjustment, the first bias signal and the second bias signal can be set, and the control of the charging and discharging current can be implemented according to the requirement of circuit design.
With continued reference to fig. 7, the detection circuit 15 includes a D flip-flop U5.
The data input end of the D flip-flop U5 is used as the external input reference clock signal input end of the detection circuit 15 to access the external input reference clock signal; the clock end of the D flip-flop U5 is used as the internal clock signal input end of the detection circuit 15, and is connected to the delay circuit 13 to access the internal clock signal; the data output terminal of the D flip-flop U5 and the reset terminal of the D flip-flop U5 are connected to the selection circuit 11 as the detection signal output terminal of the delay circuit 13, so as to output a detection signal.
In the detection circuit 15, the data input terminal of the D flip-flop U5 is connected to an external input reference clock signal, the clock terminal of the D flip-flop U5 is connected to an internal clock signal, and the data output terminal of the D flip-flop U5 is the output terminal of the detection circuit 15 and is connected to the reset terminal of the D flip-flop U5, so that when the signal output by the D flip-flop U5 changes, i.e., when the reset terminal changes from low to high, setting occurs, and the output state of the detection circuit 15 is locked.
The selection circuit 11 includes a first transmission gate U6, a second transmission gate U7, a fourth inverter U8, and a fifth inverter U9.
The input end of the first transmission gate U6 is used as the internal clock signal input end of the selection circuit 11, and is connected with the delay circuit 13 to access the internal clock signal; an input end of the second transmission gate U7 is used as an external input reference clock signal input end of the selection circuit 11 to access an external input reference clock signal; the input end of the fourth inverter U8 is used as the detection signal input end of the selection circuit 11, and is connected with the detection circuit 15 to access the detection signal; the output end of the fourth inverter U8 is connected to the input end of the fifth inverter U9, the non-inverting control end of the first transmission gate U6 and the inverting control end of the second transmission gate U7; the output terminal of the fifth inverter U9 is connected to the inverting control terminal of the first transmission gate U6 and the non-inverting control terminal of the second transmission gate U7. An output terminal of the first transmission gate U6 and an output terminal of the second transmission gate U7, which are commonly used as an internal clock signal output terminal or an external input reference clock signal output terminal of the selection circuit 11, are connected to the phase-locked loop circuit 12 to output an internal clock signal or an external input reference clock signal.
The description of fig. 7 is further described below in conjunction with the working principle:
the working process of the clock generation circuit is divided into the following three stages:
1. and a phase-locked loop establishing stage. At this time, the external input reference clock signal is input to the input terminal of the second transmission gate U7 from the clock terminal SCL of the I2C interface, the data input terminal of the D flip-flop U5 is connected to the external input reference clock signal, the clock terminal of the D flip-flop U5 is not connected to the internal clock signal, and the detection circuit 15 does not output a detection signal, that is: the detection circuit 15 outputs a low-level signal; the eighth inverter U8 and the ninth inverter U9 invert the low level signal output by the detection circuit 15 to obtain a pair of first transmission control signals with opposite polarities, and the second transmission gate U7 couples the externally input reference clock signal to the phase-locked loop circuit 12 as the reference clock according to the first transmission control signal with opposite polarities.
2. A self-calibration signal generation phase. The phase-locked loop circuit 12 (including the phase frequency detector 121, the charge pump 122, the main loop filter 123 and the voltage-controlled oscillator 124) tracks the frequency and the phase of the externally input reference clock signal received by the phase-locked loop circuit to output a first output clock signal to the delay circuit 13, and feeds back a second output clock signal to the input terminal of the phase-locked loop circuit 12; it should be noted that the phase frequency detector 121 detects a phase difference between the externally input reference clock signal and the second output clock signal, and generates the first control signal. The charge pump 122 charges and discharges according to the first control signal to output a first control voltage. The main loop filter 123 filters the first control voltage to generate a modulation voltage. A modulation voltage is applied to power supply terminals of the 3 inverters through the operational amplifier U1 to control the ring oscillation frequency, wherein an output terminal of the third inverter U4 outputs a first output clock signal and an output terminal of the second inverter U3 outputs a second output clock signal. After a certain time, the pll circuit 12 locks, and at this time, the pll circuit 12 outputs two paths of signals (a first output clock signal and a second output clock signal) with a phase difference.
The judgment circuit 161 outputs a trigger signal; the counter 162 counts to output a count result when receiving the trigger signal; the digital circuit 163 outputs a delay control signal according to the counting result.
The first output clock signal is input to the gate of the second field-effect transistor M2 and the gate of the third field-effect transistor M3, the delay control signal is input to the control ends of the n switching tubes Ki, the size of a capacitor in the access circuit is changed by turning on the switching tubes Ki, so that the delay time of the circuit is adjusted, the delay clock signal is output from the source electrode of the fifth field-effect transistor M5 and the drain electrode of the sixth field-effect transistor M6, and the first frequency divider 132 divides the delay clock signal.
3. And a phase-locked loop stable output stage. In the detection circuit 15, the data input end of the D flip-flop U5 is connected to an external input reference clock signal, the clock end of the D flip-flop U5 is connected to a delayed clock signal after frequency division, when the phases of the external input reference clock signal and the delayed clock signal are the same, and the reset end is changed from low to high, setting occurs, and the detection circuit 15 outputs a detection signal with a locked state and outputs a high level.
The judgment circuit 161 turns off the output of the trigger signal when receiving the detection signal of high level. The counter 162 stops counting to lock the counting result when the trigger signal is turned off. The digital circuit 163 outputs a locked delay control signal according to the locking of the count result. At this time, the delay circuit 13 establishes an internal clock signal having the same phase as the second output clock signal.
At this time, the eighth inverter U8 and the ninth inverter U9 invert the high-level detection signal outputted from the detection circuit 15 to obtain a pair of second transmission control signals with opposite polarities, and the first transmission gate U6 switches the internal clock signal into the phase-locked loop circuit 12 as the reference clock according to the second transmission control signal with opposite polarities. Then, the output frequency of the phase-locked loop circuit 12 is stable and no longer depends on the clock terminal SCL to access the external input reference clock signal.
The waveforms of the key nodes of the clock generation circuit are shown in fig. 9. In the figure, the first output clock signal a and the second output clock signal B have been stably established, but the internal clock signals have not been completely established. At this time, the phase difference between the first output clock signal A and the second output clock signal B is determined (2 π/3 for the third-order ringing in FIG. 8). The delayed clock signal a _ delay is a waveform of the first output clock signal a delayed by the delay circuit 13, and the second output clock signal B and the delayed clock signal a _ delay generate the divided second output clock signal clk _ fb and the internal clock signal after passing through the frequency dividers with the same division ratio, respectively. At this time, the reference clock clk _ ref of the phase-locked loop is the external input reference clock, and the first output clock signal a and the second output clock signal B are already stably established, so that there is no phase difference between the divided second output clock signal clk _ fb and the external input reference clock. As can be seen, the output of the detection circuit 15 is low at this time, indicating that the delay time is insufficient, so that the delay circuit 13 increases the delay time.
When the delayed clock signal a _ delay is made equal to the second output clock signal B by adding the delay of the delay circuit 13, the circuit key node waveforms at this time are as shown in fig. 10. At this time, there is no phase difference between the internal clock signal and the external input reference clock, which indicates that the internal self-calibration clock is completely established, the output of the detection circuit 15 goes to high level, and the state of the output of the detection circuit 15 is locked, and the state of the delay circuit 13 is also locked, so that the delay time from the first output clock signal a to a _ delay is determined. The reference clock selection circuit 11 switches in the internal clock signal as the reference clock of the phase locked loop circuit, so far, the clock generation circuit does not need to provide the reference clock externally.
After the self-calibration clock is established, if the output frequency of the phase-locked loop circuit is shifted, the frequencies of the first output clock signal a and the second output clock signal B change synchronously, but the delay from the first output clock signal a to the delayed clock signal a _ delay is fixed, so that a phase difference is generated between the internal clock signal and the divided second output clock signal clk _ fb, thereby adjusting the frequency of the voltage-controlled oscillator 124 to return to the self-calibrated circuit state, and thus achieving the stability of the output frequency of the phase-locked loop.
Fig. 11 is a schematic diagram illustrating a four-port structure of a miniature camera module. It has 4 interfaces, which are power terminal VDD, clock terminal SCL, data terminal SDA and ground terminal VSS respectively.
The embodiment of the utility model provides a still provide an image sensor, this image sensor includes foretell clock generation circuit.
The embodiment of the utility model provides a track its frequency and phase place of receiving input clock signal through phase-locked loop circuit to output first output clock signal to delay circuit, and feed back second output clock signal to phase-locked loop circuit's input; the delay circuit delays the first output clock signal to output a delay clock signal; the detection circuit receives an external input reference clock signal and a delay clock signal and outputs a detection signal based on the frequency and/or the phase of the external input reference clock signal and the delay clock signal; the delay circuit adjusts the delay time of the first output clock signal based on the detection signal, and establishes an internal clock signal based on the delay clock signal and the delay time, wherein the phase of the internal clock signal is the same as that of the second output clock signal; the selection circuit receives an external input reference clock signal and an internal clock signal and selectively outputs the external input reference clock signal or the internal clock signal to the phase-locked loop circuit based on the detection signal; therefore, when the internal clock signal is aligned with the external input reference clock signal, the internal clock signal is used as the reference clock, and the clock terminal SCL is not required to access the external input reference clock signal any more, and at the moment, the clock terminal SCL can be used for transmitting data, so that the data transmission efficiency is improved.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
The above-mentioned embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (9)
1. A clock generation circuit, comprising: the phase-locked loop circuit, the delay circuit, the selection circuit and the detection circuit;
the phase-locked loop circuit is configured to track the frequency and phase of an input clock signal received by the phase-locked loop circuit, so as to output a first output clock signal to the delay circuit and feed back a second output clock signal to the input end of the phase-locked loop circuit;
the delay circuit is configured to delay the first output clock signal to output a delayed clock signal;
the detection circuit is configured to receive an external input reference clock signal and the delayed clock signal and output a detection signal based on the frequency and/or phase of the two;
the delay circuit adjusts the delay time of the first output clock signal based on the detection signal, and establishes an internal clock signal based on the delay clock signal and the delay time, wherein the internal clock signal has the same phase as the second output clock signal;
the selection circuit is configured to receive the external input reference clock signal and the internal clock signal, and to selectively output the external input reference clock signal or the internal clock signal to the phase-locked loop circuit based on the detection signal.
2. The clock generation circuit of claim 1, further comprising:
the logic circuit is electrically connected with the detection circuit and the delay circuit and is configured to output a delay control signal to the delay circuit according to the detection signal so as to control the delay time of the delay circuit;
the logic circuit includes:
a judgment circuit connected to the detection circuit, configured to output a trigger signal, and to maintain or disconnect the output of the trigger signal based on the detection signal;
the counter is connected with the judging circuit and is configured to count to output a counting result when the triggering signal is received and stop counting to lock the counting result when the triggering signal is disconnected;
and the digital circuit is connected with the counter and the delay circuit and is configured to output the delay control signal according to the counting result.
3. The clock generation circuit of claim 1, wherein the phase-locked loop circuit comprises:
a phase frequency detector connected to the selection circuit and configured to detect a phase difference between the input clock signal and the second output clock signal and generate a first control signal;
the charge pump is connected with the phase frequency detector and configured to be charged and discharged according to the first control signal so as to output a first control voltage;
a main loop filter coupled to the charge pump and configured to filter the first control voltage to generate a modulation voltage;
a voltage controlled oscillator coupled to the main loop filter and the delay circuit and configured to output the first output clock signal and the second output clock signal having frequencies proportional to a modulation voltage.
4. The clock generation circuit of claim 3, wherein the delay circuit comprises a first frequency divider and a variable delay module that delays the first output clock signal based on a detection signal and outputs a delayed clock signal to the first frequency divider to extend a frequency range of the delayed clock signal;
the phase-locked loop circuit further comprises a second frequency divider, the second frequency divider is connected with the voltage-controlled oscillator and the phase frequency detector, and is configured to divide the frequency of the second output clock signal to output the divided second output clock signal to the input end of the phase frequency detector;
wherein the frequency division ratios of the first frequency divider and the second frequency divider are the same.
5. The clock generation circuit of claim 4, wherein the voltage controlled oscillator comprises an operational amplifier, a first inverter, a second inverter, and a third inverter;
a positive phase input end of the operational amplifier is used as a modulation voltage input end of the voltage-controlled oscillator and is connected with the main loop filter so as to be connected with the modulation voltage;
the inverting input end of the operational amplifier is connected with the output end of the operational amplifier, the power end of the first inverter, the power end of the second inverter and the power end of the third inverter;
the input end of the first inverter and the output end of the third inverter are jointly used as a first output clock signal output end of the voltage-controlled oscillator, and the first output clock signal output end is connected with the delay circuit to output the first output clock signal;
the output end of the second inverter and the input end of the third inverter are jointly used as a second output clock signal output end of the voltage-controlled oscillator, and the second output clock signal output end is connected with the second frequency divider to output the second output clock signal;
and the output end of the first phase inverter is connected with the input end of the second phase inverter.
6. The clock generation circuit of claim 4, wherein the variable delay module comprises a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, n capacitors, and n switching transistors; wherein n is a natural number greater than 0, and i is a positive integer less than or equal to n;
the drain electrode of the first field effect transistor and the drain electrode of the fifth field effect transistor are connected to a first power supply in a shared mode, and the grid electrode of the first field effect transistor serves as a first bias signal input end of the variable delay module to be connected with a first bias signal; the source electrode of the first field effect transistor is connected with the drain electrode of the second field effect transistor, and the grid electrode of the second field effect transistor and the grid electrode of the third field effect transistor are jointly used as a first output clock signal input end of the variable delay module and connected with the phase-locked loop circuit so as to access the first output clock signal; the source electrode of the second field effect transistor is connected with the drain electrode of the third field effect transistor, the first input/output ends of the n switch transistors, the grid electrode of the fifth field effect transistor and the grid electrode of the sixth field effect transistor, the second input/output end of the ith switch transistor is connected with the first end of the ith capacitor, the second ends of the n capacitors, the source electrode of the fourth field effect transistor and the source electrode of the sixth field effect transistor are connected to a power ground in common, the source electrode of the third field effect transistor is connected with the drain electrode of the fourth field effect transistor, and the grid electrode of the fourth field effect transistor is used as a second bias signal input end of the variable delay module to access a second bias signal; a source electrode of the fifth field effect transistor and a drain electrode of the sixth field effect transistor are jointly used as a delay clock signal output end of the variable delay module, and are connected with the first frequency divider to output the delay clock signal; and the control ends of the n switching tubes are jointly used as the input end of the delay control signal of the variable delay module so as to access the delay control signal.
7. The clock generation circuit of claim 1, wherein the detection circuit comprises a D flip-flop;
the data input end of the D trigger is used as the external input reference clock signal input end of the detection circuit so as to access the external input reference clock signal; the clock end of the D trigger is used as the input end of the internal clock signal of the detection circuit and is connected with the delay circuit so as to access the internal clock signal; and the data output end of the D trigger and the reset end of the D trigger are jointly used as the detection signal output end of the delay circuit and are connected with the selection circuit so as to output the detection signal.
8. The clock generation circuit of claim 1, wherein the selection circuit comprises a first transmission gate, a second transmission gate, a fourth inverter, and a fifth inverter;
the input end of the first transmission gate is used as the input end of the internal clock signal of the selection circuit, and is connected with the delay circuit so as to access the internal clock signal;
the input end of the second transmission gate is used as the external input reference clock signal input end of the selection circuit so as to access the external input reference clock signal;
the input end of the fourth inverter is used as the detection signal input end of the selection circuit and is connected with the detection circuit so as to access the detection signal;
the output end of the fourth inverter is connected with the input end of the fifth inverter, the positive phase control end of the first transmission gate and the negative phase control end of the second transmission gate;
the output end of the fifth inverter is connected with the inverting control end of the first transmission gate and the non-inverting control end of the second transmission gate;
the output end of the first transmission gate and the output end of the second transmission gate are jointly used as the output end of the internal clock signal or the output end of the external input reference clock signal of the selection circuit, and are connected with the phase-locked loop circuit to output the internal clock signal or the external input reference clock signal.
9. An image sensor comprising the clock generation circuit of any one of claims 1 to 8.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117478134A (en) * | 2023-12-25 | 2024-01-30 | 深圳大学 | Variable delay clock circuit, single-bit ADC chip and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117478134A (en) * | 2023-12-25 | 2024-01-30 | 深圳大学 | Variable delay clock circuit, single-bit ADC chip and electronic equipment |
| CN117478134B (en) * | 2023-12-25 | 2024-05-31 | 深圳大学 | Variable delay clock circuit, single-bit ADC chip and electronic equipment |
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