CN117478134A - Variable delay clock circuit, single-bit ADC chip and electronic equipment - Google Patents
Variable delay clock circuit, single-bit ADC chip and electronic equipment Download PDFInfo
- Publication number
- CN117478134A CN117478134A CN202311790918.6A CN202311790918A CN117478134A CN 117478134 A CN117478134 A CN 117478134A CN 202311790918 A CN202311790918 A CN 202311790918A CN 117478134 A CN117478134 A CN 117478134A
- Authority
- CN
- China
- Prior art keywords
- ith
- circuit
- nand gate
- output
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims abstract description 51
- 239000003990 capacitor Substances 0.000 claims description 36
- 230000005669 field effect Effects 0.000 claims description 28
- 239000000872 buffer Substances 0.000 claims description 17
- 238000010586 diagram Methods 0.000 description 7
- 235000008429 bread Nutrition 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000005070 sampling Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000875 corresponding effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
Abstract
A variable delay clock circuit, a single-bit ADC chip and an electronic device belong to the technical field of electronic circuits and comprise a clock distribution circuit, n detection circuits, n counters, n comparison circuits and n logic circuits; the ith detection circuit outputs a trigger signal when the ith clock signal and the (i+1) th clock signal have different voltage polarities; the ith counter counts the trigger signals output by the ith detection circuit; when the count value of any counter reaches a preset value, the ith comparison circuit compares the count value of the ith counter with the count value of the (i+1) th counter and outputs an ith comparison signal according to the comparison result; the ith logic circuit updates the ith control word according to the ith comparison signal; the clock distribution circuit outputs n clock signals according to the updated control word; the uniformity of the phase difference of each adjacent clock signal is improved.
Description
Technical Field
The application belongs to the technical field of electronic circuits, and particularly relates to a variable delay clock circuit, a single-bit ADC chip and electronic equipment.
Background
In analog-to-digital sampling of the time interleaving technology, clock deviation is caused by uneven phase difference of sampling clocks among different channels, and mainly results from mismatch of an input buffer, unequal signal wiring, inconsistent sampling and the like, and the clock deviation appears as spurious at a specific position on an output frequency spectrum. The time offset is due to sampling edge misalignment in each sub-analog-to-digital converter, which can create spurs and reduce the signal-to-noise ratio of the analog-to-digital converter, especially in high frequency applications.
Therefore, it is desirable to provide a variable delay clock circuit to improve the uniformity of the phase difference between adjacent clock signals.
Disclosure of Invention
The invention aims to provide a variable delay clock circuit, a single-bit ADC chip and electronic equipment, and aims to solve the problem that the phase difference uniformity of adjacent clock signals output by related variable delay clock circuits is poor.
The embodiment of the application provides a variable delay clock circuit, which comprises a clock distribution circuit, n detection circuits, n counters, n comparison circuits and n logic circuits;
the ith logic circuit is configured to output a control signal carrying a preset ith control word;
the clock distribution circuit is connected with the n logic circuits and is configured to output n clock signals according to control signals carrying n preset control words;
an ith detection circuit connected to the clock distribution circuit and configured to output a trigger signal when the ith clock signal and the (i+1) th clock signals have different voltage polarities; an ith counter connected to the ith detection circuit and configured to count the trigger signals output by the ith detection circuit;
the ith comparison circuit is connected with the ith counter and the (i+1) th counter, and is configured to compare the count value of the ith counter with the count value of the (i+1) th counter when the count value of any one of the (n) th counters reaches a preset value, and output an ith comparison signal according to the comparison result;
the ith logic circuit is further connected with the ith comparison circuit and is further configured to update the ith control word according to the ith comparison signal and output the ith control signal according to the updated ith control word;
the clock distribution circuit is further configured to output n clock signals according to a control signal carrying n updated control words;
n is a positive integer greater than 2, and i is a positive integer less than or equal to n.
In one embodiment, the ith comparison circuit is specifically configured to output the ith comparison signal of the first level when the count value of any one of the n counters reaches a preset value, and output the ith comparison signal of the second level when the count value of the ith counter is greater than or equal to the count value of the (i+1) th counter and the count value of the ith counter is less than the count value of the (i+1) th counter; the first level and the second level are of opposite polarity.
In one embodiment, the ith logic circuit is specifically configured to take the difference between the control word and 1 as a new ith control word according to the ith comparison signal of the second level, take the sum of the control word and 1 as a new ith control word according to the ith comparison signal of the first level, and output the ith control signal according to the updated ith control word.
In one embodiment, the clock distribution circuit includes:
the device comprises N first buffers which are sequentially connected in series and N capacitor components which are connected with the output ends of the N first buffers in parallel one by one.
In one embodiment, the control word has K bits; the capacitive assembly comprises 2 K A variable capacitor; k is a positive integer;
the clock distribution circuit further comprises n decoding switch circuits;
the ith decoding switch circuit is connected with the ith logic circuit and the ith capacitor component, and is configured to obtain the ith control word according to the ith control signal, convert the ith control word into decimal to obtain the number of effective capacitors, connect the variable capacitors of the number of effective capacitors in the ith capacitor component with a first power supply, and output the ith clock signal.
In one embodiment, the method further comprises:
a self-oscillating circuit connected to the n detection circuits and configured to output a reference clock signal based on a reference voltage;
the ith detection circuit is specifically configured to output the trigger signal according to the reference clock signal in a case where the ith clock signal and the (i+1) th clock signal have different voltage polarities.
In one embodiment, the self-oscillating circuit includes a first nand gate, a second nand gate, a third nand gate, a fourth nand gate, a fifth nand gate, a sixth nand gate, a seventh nand gate, and a second buffer;
the first input end of the first NAND gate is connected with the output end of the seventh NAND gate and the input end of the second buffer, the output end of the first NAND gate is connected with the first input end of the second NAND gate, the output end of the second NAND gate is connected with the first input end of the third NAND gate, the output end of the third NAND gate is connected with the first input end of the fourth NAND gate, the output end of the fifth NAND gate is connected with the first input end of the sixth NAND gate, the output end of the sixth NAND gate is connected with the first input end of the seventh NAND gate, the second input end of the first NAND gate, the second input end of the second NAND gate, the second input end of the third NAND gate, the second input end of the fourth NAND gate, the second input end of the fifth NAND gate, the second input end of the sixth NAND gate and the second input end of the seventh NAND gate are used as reference voltages for the self-oscillation circuit; the output end of the second buffer is used as a reference clock signal output end of the self-oscillating circuit and is connected with the detection circuit so as to output the reference clock signal.
In one embodiment, the ith detection circuit includes a first comparator, a second comparator, an exclusive-or gate, a first field effect transistor, and a second field effect transistor;
the drain electrode of the first field effect transistor and the drain electrode of the second field effect transistor are used as a reference clock signal input end of the ith detection circuit together and are connected with the self-oscillating circuit so as to be connected with the reference clock signal;
the grid electrode of the first field effect transistor is used as an ith clock signal input end of the ith detection circuit and is connected with the clock distribution circuit so as to be connected with the ith clock signal;
the grid electrode of the second field effect tube is used as the (i+1) th clock signal input end of the (i+1) th detection circuit and is connected with the clock distribution circuit so as to be connected with the (i+1) th clock signal;
the source electrode of the first field effect transistor is connected with the non-inverting input end of the first comparator, the source electrode of the second field effect transistor is connected with the non-inverting input end of the second comparator, the output end of the first comparator is connected with the first input end of the exclusive-OR gate, and the output end of the second comparator is connected with the first input end of the exclusive-OR gate;
the output end of the exclusive-OR gate is used as a trigger signal output end of the ith detection circuit and is connected with the ith counter so as to output the trigger signal.
The embodiment of the invention also provides a single-bit ADC chip, which comprises the variable delay clock circuit.
The embodiment of the invention also provides electronic equipment which comprises the variable delay clock circuit.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: since the i-th detection circuit outputs the trigger signal in the case where the i-th clock signal and the i+1-th clock signal have different voltage polarities; the ith counter counts the trigger signals output by the ith detection circuit; the phase difference between the i-th clock signal and the i+1-th clock signal is positively correlated with the trigger probability (the count value of the i-th counter); when the count value of any one of the n counters reaches a preset value, comparing the count value of the i counter with the count value of the i+1th counter through an i comparison circuit, and outputting an i comparison signal according to a comparison result; the ith logic circuit updates the ith control word according to the ith comparison signal and outputs the ith control signal according to the updated ith control word; the clock distribution circuit is further configured to output n clock signals according to a control signal carrying n updated control words; so that the correlation and feedback between the phase difference of the ith clock signal and the (i+1) th clock signal and the count value of the ith counter are realized; in summary, the uniformity of the phase difference of each adjacent clock signal is improved.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it will be apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a schematic diagram of a variable delay clock circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of another configuration of a clock distribution circuit in a variable delay clock circuit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of another configuration of a clock distribution circuit in a variable delay clock circuit according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of another configuration of a variable delay clock circuit according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of an exemplary circuit of a self-oscillating circuit in a variable delay clock circuit according to one embodiment of the present application;
fig. 6 is a schematic circuit diagram of an example of an ith detection circuit in a variable delay clock circuit according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved by the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the present application and simplify description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and therefore should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Fig. 1 shows a schematic diagram of a variable delay clock circuit according to a preferred embodiment of the present application, and for convenience of explanation, only the parts related to the present embodiment are shown, which are described in detail below:
the variable delay clock circuit comprises a clock distribution circuit 01, n detection circuits 02, n counters 03, n comparison circuits 04 and n logic circuits 05;
the i-th logic circuit 05 is configured to output a control signal carrying a preset i-th control word.
The clock distribution circuit 01, connected to the n logic circuits 05, is configured to output n clock signals according to control signals carrying n preset control words.
The i-th detection circuit 02 is connected to the clock distribution circuit 01 and configured to output a trigger signal when the i-th clock signal and the i+1-th clock signal have different voltage polarities.
The i-th counter 03 is connected to the i-th detection circuit 02 and configured to count the trigger signals output from the i-th detection circuit 02.
An ith comparing circuit 04 connected to the ith counter 03 and the (i+1) th counter 03 and configured to compare the count value of the ith counter 03 with the count value of the (i+1) th counter 03 when the count value of any one of the (n) th counters 03 reaches a preset value, and output an ith comparison signal according to the comparison result.
The ith logic circuit 05 is further connected to the ith comparing circuit 04, and is further configured to update the ith control word according to the ith comparing signal, and output the ith control signal according to the updated ith control word.
The clock distribution circuit 01 is further configured to output n clock signals in dependence of a control signal carrying n updated control words.
Wherein n is a positive integer greater than 2, and i is a positive integer less than or equal to n.
When i+1 is n+1, the 1 st clock signal is the n+1 th clock signal, and the 1 st counter 03 is the n+1 th counter 03.
The i-th comparing circuit 04 is specifically configured to output the i-th comparing signal of the first level when the count value of any one counter 03 among the n-th counters 03 reaches a preset value, and output the i-th comparing signal of the second level when the count value of the i-th counter 03 is equal to or greater than the count value of the i+1th counter 03 and when the count value of the i-th counter 03 is less than the count value of the i+1th counter 03; the first level and the second level are of opposite polarity.
In a specific implementation, the first level may be a high level, and the second level may be a low level.
In the case where the count value of the i-th counter 03 is equal to or greater than the count value of the i+1th counter 03, the i-th comparison signal of the first level is output, it is understood that at this time, the phase difference between the i-th clock signal and the i+1th clock signal is equal to or greater than the phase difference between the i+1th clock signal and the i+2th clock signal.
Outputting the i-th comparison signal of the second level in the case where the count value of the i-th counter 03 is smaller than the count value of the i+1th counter 03; it is understood that at this time, the phase difference between the i-th clock signal and the i+1-th clock signal is smaller than the phase difference between the i+1-th clock signal and the i+2-th clock signal.
By comparing the count value of the i-th counter 03 with the count value of the i+1th counter 03 to output the i-th comparison signal of the corresponding level, the i-th comparison signal can indicate the magnitude relation between the adjacent phase differences.
By way of example and not limitation, the ith logic circuit 05 is specifically configured to take the difference between the control word and 1 as a new ith control word according to the ith comparison signal of the second level, take the sum of the control word and 1 as a new ith control word according to the ith comparison signal of the first level, and output the ith control signal according to the updated ith control word.
As will be appreciated from the difference between the control word and 1 as the new control word in the ith comparison signal of the second level, at this time, the phase difference between the ith clock signal and the i+1th clock signal is smaller than the phase difference between the i+1th clock signal and the i+2th clock signal, so that the phase between the i+1th clock signal and the i+2th clock signal needs to be reduced, and the control word carried by the ith control signal needs to be stepped down.
The sum of the control word and 1 is taken as a new control word according to the i-th comparison signal of the first level, and it can be understood that at this time, the phase difference between the i-th clock signal and the i+1-th clock signal is greater than or equal to the phase difference between the i+1-th clock signal and the i+2-th clock signal, so that the phase between the i+1-th clock signal and the i+2-th clock signal needs to be increased, and the control word carried by the i-th control signal needs to be increased step by step.
The control word carried by the ith control signal is updated by the ith comparison signal indicating the magnitude relationship between adjacent phase differences so that the control word can indicate the phase difference of each adjacent clock signal.
As shown in fig. 2, the clock distribution circuit 01 includes: n first buffers 11 connected in series in turn and n capacitor elements 12 connected in parallel one by one with the output terminals of the n first buffers 11.
With the above-described structure of the clock distribution circuit 01, it is achieved that n clock signals are output from the output terminals of the n first buffers 11, respectively.
By way of example and not limitation, a control word has K bits; capacitor assembly 12 includes 2 K A variable capacitor; k is a positive integer.
As shown in fig. 3, the clock distribution circuit 01 further includes n decoding switch circuits 13.
The ith decoding switch circuit 13 is connected to the ith logic circuit 05 and the ith capacitor assembly 12, and is configured to obtain the ith control word according to the ith control signal, convert the ith control word into decimal to obtain the number of effective capacitors, connect the variable capacitors of the number of effective capacitors in the ith capacitor assembly 12 to the first power supply, and output the ith clock signal.
The effective capacitance number of each capacitor assembly 12 is obtained by decoding each control word indicating the phase difference of each adjacent clock signal, the variable capacitance corresponding to the effective capacitance number of each capacitor assembly 12 is connected with a first power supply, and each clock signal is output, so that the phase difference of each adjacent clock signal is adjusted, and the uniformity of the phase difference of each adjacent clock signal is improved.
As shown in fig. 4, the variable delay clock circuit further includes a self-oscillating circuit 90.
A self-oscillating circuit 90 connected to the n detection circuits 02 and configured to output a reference clock signal based on a reference voltage;
the i-th detection circuit 02 is specifically configured to output a trigger signal according to the reference clock signal in the case where the i-th clock signal and the i+1-th clock signal have different voltage polarities.
By providing the same reference clock signal for each detection circuit 02, the uniformity of the phase difference of each adjacent clock signal is further improved.
Fig. 5 shows a partial example circuit structure of a self-oscillating circuit 90 in a variable delay clock circuit according to an embodiment of the present invention, fig. 6 shows a partial example circuit structure of an ith detection circuit 02 in a variable delay clock circuit according to an embodiment of the present invention, and for convenience of explanation, only the parts related to the embodiment of the present invention are shown, and the details are as follows:
as shown in fig. 5, the self-oscillating circuit 90 includes a first nand gate U1, a second nand gate U2, a third nand gate U3, a fourth nand gate U4, a fifth nand gate U5, a sixth nand gate U6, a seventh nand gate U7, and a second buffer U8;
the first input end of the first NAND gate U1 is connected with the output end of the seventh NAND gate U7 and the input end of the second buffer U8, the output end of the first NAND gate U1 is connected with the first input end of the second NAND gate U2, the output end of the second NAND gate U2 is connected with the first input end of the third NAND gate U3, the output end of the third NAND gate U3 is connected with the first input end of the fourth NAND gate U4, the output end of the fifth NAND gate U5 is connected with the first input end of the sixth NAND gate U6, the output end of the sixth NAND gate U6 is connected with the first input end of the seventh NAND gate U2, the second input end of the first NAND gate U1, the second input end of the second NAND gate U2, the second input end of the third NAND gate U3, the second input end of the fourth NAND gate U4, the second input end of the fifth NAND gate U5, the second input end of the sixth NAND gate U6 and the second input end of the seventh NAND gate U7 are used as reference voltages to be accessed together; the output terminal of the second buffer U8 is connected to the detection circuit 02 as a reference clock signal output terminal of the self-oscillating circuit 90 to output a reference clock signal X (t).
As shown in fig. 6, the i-th detection circuit 02 includes a first comparator U9, a second comparator U10, an exclusive or gate U11, a first fet M1, and a second fet M2;
the drain electrode of the first field effect transistor M1 and the drain electrode of the second field effect transistor M2 are used as the reference clock signal input end of the i-th detection circuit 02 together and are connected with the self-oscillating circuit 90 so as to be connected with the reference clock signal X (t);
the grid electrode of the first field effect transistor M1 is used as an ith clock signal input end of an ith detection circuit 02 and is connected with the clock distribution circuit 01 so as to be connected with an ith clock signal phi;
the grid electrode of the second field effect transistor M2 is used as the (i+1) th clock signal input end of the (i+1) th detection circuit 02 and is connected with the clock distribution circuit 01 so as to be connected with the (i+1) th clock signal phi i+1;
the source electrode of the first field effect transistor M1 is connected with the non-inverting input end of the first comparator U9, the source electrode of the second field effect transistor M2 is connected with the non-inverting input end of the second comparator U10, the output end of the first comparator U9 is connected with the first input end of the exclusive-OR gate U11, and the output end of the second comparator U10 is connected with the first input end of the exclusive-OR gate U11;
the output terminal of the exclusive or gate U11 is connected to the i-th counter 03 as a trigger signal output terminal of the i-th detection circuit 02 to output a trigger signal TRIGi.
The following further describes the operation of the device shown in fig. 1 to 6 in conjunction with the following principle:
the variable delay clock circuit will be described below by taking n as 3 as an example. Each logic circuit 05 outputs a control signal carrying a preset ith control word (for example, 1000); the clock distribution circuit 01 outputs n clock signals according to a control signal carrying n-1 preset control words.
Each detection circuit 02 outputs a trigger signal in the case where each adjacent clock signal has a different voltage polarity; that is, the i-th detection circuit 02 outputs a trigger signal in the case where the i-th clock signal and the i+1-th clock signal have different voltage polarities; in specific implementation, the first to seventh nand gates U1 to U7 output reference clock signals to the drain of the first field effect transistor M1 and the drain of the second field effect transistor M2 in each detection circuit 02 according to the reference voltage, and meanwhile, the gate of the first field effect transistor M1 and the gate of the second field effect transistor M2 are respectively connected to the ith clock signal and the (i+1) th clock signal, the source of the first field effect transistor M1 and the source of the second field effect transistor M2 respectively output a first steamed bread wave and a second steamed bread wave, the first steamed bread wave and the second steamed bread wave are respectively connected to the non-inverting input terminal of the first comparator U9 and the non-inverting input terminal of the second comparator U10 for analog-digital conversion, and the first digital signal output by the output terminal of the first comparator U9 and the second digital signal output by the output terminal of the second comparator U10 are xored, so as to output the trigger signal according to the reference clock signal when the ith clock signal and the (i+1) th clock signal have different voltage polarities.
When the count value of any counter 03 in the n counters 03 reaches a preset value, each comparator compares the count values of adjacent counters 03 and outputs each comparison signal according to the comparison result; each logic circuit 05 updates each control word according to each comparison signal and outputs each control signal according to each updated control word; for example, the 1 st counter 03 reaches a preset value 512, the count value of the 2 nd counter 03 is 510, and the count value of the 3 rd counter 03 is 511; since the count value of the 1 st counter 03 is larger than the count value of the 2 nd counter 03, the 1 st comparator outputs the 1 st comparison signal of the high level; by analogy, the 2 nd comparator outputs the 2 nd comparison signal of the low level, and the 3 rd comparator outputs the 3 rd comparison signal of the low level.
The 1 st logic circuit 05 adds 1 to the 1 st control word as a new 1 st control word (1001) according to the 1 st comparison signal of the high level and outputs the 1 st control signal; and so on, the new 2 nd control word is 0111, and the new 3 rd control word is 0111.
The 1 st decoding switch circuit 13 obtains the 1 st control word 1001 according to the 1 st control signal, converts the control word into decimal to obtain the number of effective capacitors 17, connects the variable capacitors of the number of effective capacitors 17 in the 1 st capacitor assembly 12 to the first power supply, and outputs the 1 st clock signal. By analogy, the 2 nd decoding switch circuit 13 obtains the 2 nd control word 0111 according to the 2 nd control signal, converts the control word into decimal to obtain the number 15 of effective capacitors, connects the variable capacitors of the number 15 of the effective capacitors in the 2 nd capacitor assembly 12 with the first power supply, and outputs the 2 nd clock signal; the 3 rd decoding switch circuit 13 obtains the 3 rd control word 0111 according to the 3 rd control signal, converts the control word into decimal to obtain the number of effective capacitors 15, connects the variable capacitors of the number of effective capacitors 15 in the 3 rd capacitor assembly 12 with the first power supply, and outputs the 3 rd clock signal.
Then, the steps of outputting the trigger signal by each detection circuit 02 in the case where each adjacent clock signal has a different voltage polarity are continuously performed in a loop until the count value of each counter 03 reaches a preset value at the same time.
The embodiment of the invention also provides a single-bit analog-to-digital converter (ADC) chip, which comprises the variable delay clock circuit.
The embodiment of the invention also provides electronic equipment which comprises the variable delay clock circuit.
The embodiment of the invention comprises a clock distribution circuit, n detection circuits, n counters, n comparison circuits and n logic circuits; the ith detection circuit outputs a trigger signal under the condition that the ith clock signal and the (i+1) th clock signal have different voltage polarities; the ith counter counts the trigger signals output by the ith detection circuit; when the count value of any one of the n counters reaches a preset value, the ith comparison circuit compares the count value of the ith counter with the count value of the (i+1) th counter and outputs an ith comparison signal according to the comparison result; the ith logic circuit updates the ith control word according to the ith comparison signal and outputs the ith control signal according to the updated ith control word; the clock distribution circuit outputs n clock signals according to the control signals carrying n updated control words; the uniformity of the phase difference of each adjacent clock signal is improved.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. The variable delay clock circuit is characterized by comprising a clock distribution circuit, n detection circuits, n counters, n comparison circuits and n logic circuits;
the ith logic circuit is configured to output a control signal carrying a preset ith control word;
the clock distribution circuit is connected with the n logic circuits and is configured to output n clock signals according to control signals carrying n preset control words;
an ith detection circuit connected to the clock distribution circuit and configured to output a trigger signal when the ith clock signal and the (i+1) th clock signals have different voltage polarities; an ith counter connected to the ith detection circuit and configured to count the trigger signals output by the ith detection circuit;
the ith comparison circuit is connected with the ith counter and the (i+1) th counter, and is configured to compare the count value of the ith counter with the count value of the (i+1) th counter when the count value of any one of the (n) th counters reaches a preset value, and output an ith comparison signal according to the comparison result;
the ith logic circuit is further connected with the ith comparison circuit and is further configured to update the ith control word according to the ith comparison signal and output the ith control signal according to the updated ith control word;
the clock distribution circuit is further configured to output n clock signals according to a control signal carrying n updated control words;
wherein n is a positive integer greater than 2, and i is a positive integer less than or equal to n.
2. The variable delay clock circuit of claim 1, wherein the ith comparison circuit is specifically configured to output the ith comparison signal of the first level when a count value of any one of the n counters reaches a preset value, and output the ith comparison signal of the second level when the count value of the ith counter is equal to or greater than a count value of the (i+1) th counter and when the count value of the (i) th counter is less than a count value of the (i+1) th counter; the first level and the second level are of opposite polarity.
3. The variable delay clock circuit of claim 2, wherein the ith said logic circuit is specifically configured to take the difference of the control word and 1 as a new ith said control word according to the ith said comparison signal of the second level, take the sum of the control word and 1 as a new ith said control word according to the ith said comparison signal of the first level, and output the ith control signal according to the updated ith said control word.
4. A variable delay clock circuit as claimed in any one of claims 1 to 3, wherein the clock distribution circuit comprises:
the device comprises N first buffers which are sequentially connected in series and N capacitor components which are connected with the output ends of the N first buffers in parallel one by one.
5. The variable delay clock circuit of claim 4, wherein the control word has K bits; the capacitive assembly comprises 2 K A variable capacitor; k is a positive integer;
the clock distribution circuit further comprises n decoding switch circuits;
the ith decoding switch circuit is connected with the ith logic circuit and the ith capacitor component, and is configured to obtain the ith control word according to the ith control signal, convert the ith control word into decimal to obtain the number of effective capacitors, connect the variable capacitors of the number of effective capacitors in the ith capacitor component with a first power supply, and output the ith clock signal.
6. A variable delay clock circuit as claimed in any one of claims 1 to 3, further comprising:
a self-oscillating circuit connected to the n detection circuits and configured to output a reference clock signal based on a reference voltage;
the ith detection circuit is specifically configured to output the trigger signal according to the reference clock signal in a case where the ith clock signal and the (i+1) th clock signal have different voltage polarities.
7. The variable delay clock circuit of claim 6, wherein the self-oscillating circuit comprises a first nand gate, a second nand gate, a third nand gate, a fourth nand gate, a fifth nand gate, a sixth nand gate, a seventh nand gate, and a second buffer;
the first input end of the first NAND gate is connected with the output end of the seventh NAND gate and the input end of the second buffer, the output end of the first NAND gate is connected with the first input end of the second NAND gate, the output end of the second NAND gate is connected with the first input end of the third NAND gate, the output end of the third NAND gate is connected with the first input end of the fourth NAND gate, the output end of the fifth NAND gate is connected with the first input end of the sixth NAND gate, the output end of the sixth NAND gate is connected with the first input end of the seventh NAND gate, the second input end of the first NAND gate, the second input end of the second NAND gate, the second input end of the third NAND gate, the second input end of the fourth NAND gate, the second input end of the fifth NAND gate, the second input end of the sixth NAND gate and the second input end of the seventh NAND gate are used as reference voltages for the self-oscillation circuit; the output end of the second buffer is used as a reference clock signal output end of the self-oscillating circuit and is connected with the detection circuit so as to output the reference clock signal.
8. The variable delay clock circuit of claim 6, wherein the ith detection circuit comprises a first comparator, a second comparator, an exclusive-or gate, a first field effect transistor, and a second field effect transistor;
the drain electrode of the first field effect transistor and the drain electrode of the second field effect transistor are used as a reference clock signal input end of the ith detection circuit together and are connected with the self-oscillating circuit so as to be connected with the reference clock signal;
the grid electrode of the first field effect transistor is used as an ith clock signal input end of the ith detection circuit and is connected with the clock distribution circuit so as to be connected with the ith clock signal;
the grid electrode of the second field effect tube is used as the (i+1) th clock signal input end of the (i+1) th detection circuit and is connected with the clock distribution circuit so as to be connected with the (i+1) th clock signal;
the source electrode of the first field effect transistor is connected with the non-inverting input end of the first comparator, the source electrode of the second field effect transistor is connected with the non-inverting input end of the second comparator, the output end of the first comparator is connected with the first input end of the exclusive-OR gate, and the output end of the second comparator is connected with the first input end of the exclusive-OR gate;
the output end of the exclusive-OR gate is used as a trigger signal output end of the ith detection circuit and is connected with the ith counter so as to output the trigger signal.
9. A single bit ADC chip, characterized in that it comprises a variable delay clock circuit according to any one of claims 1 to 8.
10. An electronic device comprising a variable delay clock circuit as claimed in any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311790918.6A CN117478134A (en) | 2023-12-25 | 2023-12-25 | Variable delay clock circuit, single-bit ADC chip and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311790918.6A CN117478134A (en) | 2023-12-25 | 2023-12-25 | Variable delay clock circuit, single-bit ADC chip and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117478134A true CN117478134A (en) | 2024-01-30 |
Family
ID=89634983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311790918.6A Pending CN117478134A (en) | 2023-12-25 | 2023-12-25 | Variable delay clock circuit, single-bit ADC chip and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117478134A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101478240A (en) * | 2008-10-09 | 2009-07-08 | 天津大学 | Digital DC-DC voltage boosting converter |
| CN102035514A (en) * | 2010-11-11 | 2011-04-27 | 东南大学 | Control method for digital pulse width modulation (DPWM) circuit |
| CN214177280U (en) * | 2021-02-04 | 2021-09-10 | 保定华仿科技股份有限公司 | Digital three-phase inversion phase-shifting trigger circuit of cascade speed regulation device |
| CN113741619A (en) * | 2020-05-27 | 2021-12-03 | 安徽寒武纪信息科技有限公司 | Clock control device and related product |
| CN217307668U (en) * | 2022-04-29 | 2022-08-26 | 思特威(上海)电子科技股份有限公司 | Clock generation circuit and image sensor |
| CN117238338A (en) * | 2022-06-06 | 2023-12-15 | 长鑫存储技术有限公司 | Phase adjustment circuit, delay locking circuit and memory |
-
2023
- 2023-12-25 CN CN202311790918.6A patent/CN117478134A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101478240A (en) * | 2008-10-09 | 2009-07-08 | 天津大学 | Digital DC-DC voltage boosting converter |
| CN102035514A (en) * | 2010-11-11 | 2011-04-27 | 东南大学 | Control method for digital pulse width modulation (DPWM) circuit |
| CN113741619A (en) * | 2020-05-27 | 2021-12-03 | 安徽寒武纪信息科技有限公司 | Clock control device and related product |
| CN214177280U (en) * | 2021-02-04 | 2021-09-10 | 保定华仿科技股份有限公司 | Digital three-phase inversion phase-shifting trigger circuit of cascade speed regulation device |
| CN217307668U (en) * | 2022-04-29 | 2022-08-26 | 思特威(上海)电子科技股份有限公司 | Clock generation circuit and image sensor |
| CN117238338A (en) * | 2022-06-06 | 2023-12-15 | 长鑫存储技术有限公司 | Phase adjustment circuit, delay locking circuit and memory |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9608652B2 (en) | Methods and apparatus for reducing timing-skew errors in time-interleaved analog-to-digital converters | |
| Song et al. | A 10-b 800-MS/s time-interleaved SAR ADC with fast variance-based timing-skew calibration | |
| US9148166B2 (en) | Adding predefined offset to coarse ADC residue output to SAR | |
| US9071265B1 (en) | Successive approximation analog-to-digital converter with linearity error correction | |
| US8325076B2 (en) | Time-to-digital converter | |
| Jiang et al. | Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS | |
| US10084470B2 (en) | Analogue-digital converter of non-binary capacitor array with redundant bit and its chip | |
| US8912942B2 (en) | Successive-approximation-register analog-to-digital converter (SAR ADC) and method thereof | |
| CN110672943B (en) | Aging detection sensor based on voltage comparator | |
| US10367517B2 (en) | Analog to digital conversion apparatus and analog to digital converter calibration method of the same | |
| US10230383B2 (en) | Time-to-digital converter and digital phase locked loop | |
| WO2019173540A1 (en) | Chopping switch time-skew calibration in time-interleaved analog-to-digital converters | |
| TW201408065A (en) | Image sensor and column analog to digital converter | |
| CN114050827B (en) | Digital calibration method applied to capacitor three-section successive approximation analog-to-digital converter | |
| CN117478134A (en) | Variable delay clock circuit, single-bit ADC chip and electronic equipment | |
| Xu et al. | A linearity-improved 8-bit 320-MS/s SAR ADC with metastability immunity technique | |
| US20210328596A1 (en) | Digital slope analog to digital converter device and signal conversion method | |
| Liu et al. | Accuracy-enhanced variance-based time-skew calibration using SAR as window detector | |
| US8860598B2 (en) | Bit error rate timer for a dynamic latch | |
| CN114448441B (en) | Clock calibration method, device and equipment | |
| US20200350922A1 (en) | Analog to digital converting device and capacitor adjusting method thereof | |
| US11133813B2 (en) | Analog to digital converter device and noise shaping digital slope analog to digital converter circuitry | |
| US11095301B1 (en) | Flash-successive approximation register (SAR) hybrid analog-to-digital converter (ADC) | |
| CN110311678A (en) | A kind of time mismatch correcting circuit suitable for time-interleaved analog-digital converter | |
| CN109756229B (en) | Configurable sigma delta ADC modulator suitable for wireless communication system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |