CN118265306A

CN118265306A - Memory array, preparation method, memory and electronic equipment

Info

Publication number: CN118265306A
Application number: CN202211678416.XA
Authority: CN
Inventors: 林琪; 陈华威; 卜思童; 丁士成; 方亦陈; 徐亮; 许俊豪
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-12-26
Filing date: 2022-12-26
Publication date: 2024-06-28
Also published as: WO2024139645A1

Abstract

The embodiment of the application discloses a memory array, a preparation method, a memory and electronic equipment, wherein the memory array comprises the following components: a substrate, and a plurality of stacked structures disposed on the substrate; a storage region and a first step region corresponding to the storage region, which are sequentially arranged along a first direction; wherein the storage area comprises a plurality of storage units; the first step region includes a plurality of first step groups arranged in a second direction, each of the first step groups including a plurality of steps; each of the steps extending in the second direction; wherein the first direction and the second direction are perpendicular and parallel to the substrate. Thus, the first step structure includes a plurality of step groups, and the steps of each step group extend in the direction of the step group adjacent to the step group, so that the plurality of step groups have a plurality of steps with the same height, the number of steps with the same height is increased, and the storage density is improved.

Description

Memory array, preparation method, memory and electronic equipment

Technical Field

The embodiment of the application relates to the technical field of semiconductor design and manufacture, in particular to a memory array, a preparation method, a memory and electronic equipment.

Background

In the prior art, the three-dimensional storage array adopts a flat plate stacking integration scheme, so that the process difficulty can be effectively reduced, and the storage density can be improved. In the plate stacking scheme, each layer of plates is led out of the contact hole through a step structure and then connected to a plate driving circuit of a front channel through a metal wire.

Fig. 5 is a schematic structural diagram of a laminated structure according to the prior art. As shown in fig. 5, the laminated structure 01 includes a plurality of laminated layers 011 and wiring layers 012 sequentially provided along the Z-axis.

Wherein the plurality of stacks 011 includes a plurality of insulating layers and a plurality of conductive layers alternately arranged.

The laminated structure 01 includes: a storage region 013 and a step structure 014 arranged in the second direction.

The step structure 014 includes a plurality of steps 015, each step 015 including a step extending in the Y direction, wherein a step surface of each step is an exposed conductive layer, and the steps 015 are connected to the wiring layer 012 through the electrical connection 016.

The wiring layer 012 includes: a plurality of connection lines 0121, the connection lines 0121 are opposite to the steps 015 one by one, and each step 015 is connected with one connection line 0121 through a plurality of electric connectors 016.

However, as the number of layers of the plurality of stacked layers 011 increases, the land occupied area of the step structure 014 increases significantly, limiting the increase in storage density.

Disclosure of Invention

The embodiment of the application provides a memory array, a preparation method, a memory and electronic equipment, and solves the problem of low memory density of a laminated structure.

In order to achieve the above purpose, the embodiment of the application adopts the following technical scheme:

In a first aspect of an embodiment of the present application, there is provided a memory array, including: a substrate, and a plurality of stacked structures disposed on the substrate; each of the laminated structures includes: a storage region and a first step region corresponding to the storage region, which are sequentially arranged along a first direction; wherein the storage area comprises a plurality of storage units; the first step region includes a plurality of first step groups arranged in a second direction, each of the first step groups including a plurality of steps; each of the steps extending in the second direction; wherein the first direction and the second direction are perpendicular and parallel to the substrate. Therefore, each first step area comprises a plurality of step groups, and the steps of each step group extend towards the direction of the step group adjacent to the step group, and therefore, the step groups have a plurality of steps with the same height.

In an alternative implementation manner, projections of two adjacent first step groups arranged along the second direction on the second wiring layer are arranged in an axisymmetric manner. Therefore, the steps of the adjacent step groups are opposite to each other, and wiring is more convenient.

In an alternative implementation, the stacked structure further includes: a second step region corresponding to the storage region, the second step region being located at a side of the storage region away from the first step region; the second step region includes a plurality of second step groups arranged along the second direction, each of the second step groups including a plurality of steps, a direction of each of the steps extending along the second direction. Therefore, the second step area is arranged on the other side of the storage area, so that the number of step groups can be further increased, the number of steps with the same height is further increased, the occupied area of the step structure is effectively reduced under the condition that extra cost is not increased, and the miniaturization design and the high-density storage design of the storage array are facilitated.

In an alternative implementation, the laminate structure includes a plurality of laminates arranged in a stack along a third direction; the third direction is perpendicular to the substrate, and a plurality of the step sets include: the first type step group and the second type step group, a part of the lamination layer in the lamination structure is connected with the first type step group, another part of the lamination layer in the lamination structure is connected with the second type step group, and the height of the first type step group is different from the height of the second type step group. Therefore, by arranging the step groups with a plurality of heights, compared with the step group with only one height, the occupied area of the step structure is effectively reduced under the condition of not increasing extra cost, the area of a core area is conveniently increased, and the three-dimensional storage array is beneficial to the structure miniaturization design and the storage high-density design.

In an alternative implementation, the bottom surface of the first type of step set is higher than or equal to the top surface of the second type of step set. Therefore, the two step groups are staggered in the height direction, and the storage density is improved.

In an alternative implementation, the first step region includes: a plurality of first class step sets, the second step region comprising: a plurality of second class step sets, or, the first step region comprising: a plurality of second class step sets, the second step regions comprising: a plurality of first class step sets. Therefore, the two step groups are staggered in the height direction, and the storage density is improved.

In an alternative implementation, the first step region includes: at least one first class of step sets and at least one second class of step sets. Therefore, the two step groups are staggered in the height direction, and the storage density is improved.

In an alternative implementation, the second step region includes: at least one first class of step sets and at least one second class of step sets. Therefore, the two step groups are staggered in the height direction, and the storage density is improved.

In an alternative implementation, the stacked structure includes a plurality of insulating layers and a plurality of conductive layers alternately arranged along the first direction. Therefore, the conductive layer can be used as an electrode and electrically connected with the driving circuit to realize the storage function of the storage array.

In an alternative implementation, the stacked structure further includes: a first wiring layer and a second wiring layer stacked in the first direction, wherein the first wiring layer is disposed on a side of the stacked structure away from the substrate, and the second wiring layer is disposed on a side of the first wiring layer away from the stacked structure; the first wiring layer includes: a plurality of first connection lines; the second wiring layer includes: a plurality of second connection lines; the electrical connector includes: a first electrical connector and a second electrical connector; each of the steps is connected to a first connecting line by a first electrical connection; and the first connecting wire connected with the steps with the same height in the step groups is connected with the same second connecting wire through the second electric connecting piece. Therefore, by arranging the first wiring layer and the second wiring layer, the wiring does not occupy additional area outside the array, and the storage density is improved. Meanwhile, compared with the direct connection through the electric connecting piece, the length of the electric connecting piece is reduced by arranging the wiring layer, the occupied metal wiring resources are few, the winding is avoided, the wiring difficulty is reduced, and the time delay is reduced.

In an alternative implementation manner, a plurality of the first connection lines are sequentially arranged along the second direction; the second connecting lines are sequentially arranged along the third direction. Therefore, the wiring difficulty is further reduced.

In an alternative implementation, the first electrical connector is perpendicular to the first connection line, and the second electrical connector is perpendicular to the second connection line. Therefore, the length of the electric connecting piece is reduced, the wiring difficulty is reduced, and the time delay is reduced.

In an alternative implementation, the wiring layer further includes: a third wiring layer disposed on a side of the stacked structure away from the second wiring layer, the first wiring layer further comprising: the second wiring layers are connected with the third connecting wires through third electric connecting pieces, the third connecting wires are connected with the third wiring layers through fourth connecting pieces, and the third wiring layers are used for being connected with the front driving circuit. Thereby, the third wiring layer is made closer to the driving circuit, and the time delay is reduced.

In an alternative implementation, a gap is provided between adjacent step sets, and the fourth electrical connection is provided in the gap. Thereby, the occupation of space by the fourth electrical connector can be reduced.

In an alternative implementation, the conductive layer is a plate line, and the stacked structure further includes: and a word line and a bit line disposed on a side of the stacked structure away from the second wiring layer, the word line and the bit line extending in a direction perpendicular to each other. Therefore, the word line, the bit line and the third wiring layer (the conductive layer is a plate line, and the plate line is connected with the driving circuit through the third wiring layer) are arranged on the same side of the laminated structure, and when the plate line is connected with the driving circuit, the wiring is shortest, so that the time delay is reduced.

In a second aspect of the embodiment of the present application, there is provided a method for manufacturing a memory array, including: forming a plurality of stacked structures on a substrate; wherein the laminated structure comprises in a first direction: a storage region and a first step region corresponding to the storage region; wherein the storage area comprises a plurality of storage units; forming a plurality of first step groups arranged in a second direction in the first step region; wherein each first step group includes a plurality of steps; each of the steps extending in the second direction; the first direction and the second direction are perpendicular and parallel to the substrate.

In an alternative implementation, the forming a plurality of first step groups arranged along the second direction in the first step region includes: forming a plurality of patterns of the first step group on the surface of the first step region; and carrying out layered etching on the area, where the pattern is not arranged, of the first step area to obtain a plurality of layers of steps, and forming a plurality of first step groups.

In an alternative implementation, the stacked structure further includes, in the second direction: a second step region located on a side of the storage region remote from the first step region, the method further comprising: a plurality of second step groups arranged in a second direction are formed in the second step region.

In an alternative implementation, the preparation method further includes: forming a first dielectric layer on the laminated structure; etching the first dielectric layer to obtain a plurality of first contact holes; filling the first contact hole to obtain a first electric connecting piece; forming a first wiring layer on the first dielectric layer; wherein the first wiring layer includes: a plurality of first connection lines, each of the steps being connected to one of the first connection lines through a first electrical connection; forming a second dielectric layer on the first wiring layer; etching the second dielectric layer to obtain a plurality of second contact holes; filling the second contact hole to obtain a second electric connecting piece; forming a second wiring layer on the surface of the second dielectric layer; wherein the second wiring layer includes: a plurality of second connection lines; the first connecting lines connected with the steps with the same height in the step groups are connected with the same second connecting line through the second electric connecting piece.

In an alternative implementation, the forming a plurality of stacked structures on a substrate includes: forming a plurality of third dielectric layers on the substrate; forming a third wiring layer on the third dielectric layer; forming a plurality of the stacked structures on the third wiring layer; wherein the first wiring layer further includes: a plurality of third connection lines; the first dielectric layer also comprises a fourth electric connecting piece, the third connecting wire is connected with the third wiring layer through the fourth connecting piece, the second dielectric layer also comprises a third electric connecting piece, and the second wiring layer is connected with the third connecting wire through the third electric connecting piece; the third wiring layer is used for connecting with the front driving circuit

In a third aspect of an embodiment of the present application, there is provided a memory array, including: a substrate, and a plurality of stacked structures disposed on the substrate; a first wiring layer and a second wiring layer; the first wiring layer is arranged on one side of the laminated structure far away from the substrate, and the second wiring layer is arranged on one side of the first wiring layer far away from the laminated structure; the first wiring layer includes: a plurality of first connection lines; the second wiring layer includes: a plurality of second connection lines; each of the laminated structures includes: a storage region and a step structure disposed along a first direction; the step structure comprises a plurality of step groups, each step group comprises a plurality of steps; the memory array further includes: a first electrical connector and a second electrical connector; each step is connected with one first connecting wire through a first electric connecting piece; the second connecting wires connected with the steps with the same height in the step groups are connected with the same second connecting wire through the second electric connecting piece; wherein the first direction is parallel to the substrate.

In an alternative implementation manner, each step extends along a second direction, and a plurality of the first connecting lines are sequentially arranged along the second direction; the second connecting lines are sequentially arranged along the first direction, and the first direction and the second direction intersect and are parallel to the substrate.

In an alternative implementation, the first electrical connector is perpendicular to the first connection line, and the second electrical connector is perpendicular to the second connection line.

In an alternative implementation, the wiring layer further includes: a third wiring layer disposed on a side of the stacked structure away from the second wiring layer, the first wiring layer further comprising: the second wiring layers are connected with the third connecting wires through third electric connecting pieces, the third connecting wires are connected with the third wiring layers through fourth connecting pieces, and the third wiring layers are used for being connected with the front driving circuit.

In a fourth aspect of an embodiment of the present application, there is provided a memory including: the controller and the storage array are electrically connected.

In a fifth aspect of an embodiment of the present application, there is provided a chip package structure, including: packaging a substrate; and the memory is arranged on the packaging substrate.

A sixth aspect of an embodiment of the present application provides an electronic device, including: a main board; and the chip packaging structure is arranged on the main board and is electrically connected with the main board.

Drawings

Fig. 1 is a schematic diagram of a disassembled structure of an electronic device according to an embodiment of the present application;

Fig. 2 is a schematic diagram of a chip package structure according to an embodiment of the present application;

FIG. 3 is a perspective view of the chip package structure of FIG. 2;

FIG. 4 is a schematic diagram of a memory array according to an embodiment of the present application;

FIG. 5 is a schematic view of a laminated structure according to the prior art;

Fig. 6 is a schematic structural diagram of a laminated structure according to an embodiment of the present application;

FIG. 7 is a flowchart of a method for fabricating a laminated structure according to an embodiment of the present application;

fig. 8 and 9 are schematic diagrams of the product structure obtained after each step in fig. 7 is performed;

FIG. 10 is a flowchart of another method for manufacturing a laminated structure according to an embodiment of the present application;

FIG. 11 is a schematic diagram of the structure of the product obtained after the steps of FIG. 10 are performed;

FIG. 12 is a flowchart of another method for manufacturing a laminated structure according to an embodiment of the present application;

fig. 13 is a schematic diagram of the structure of the product obtained after the steps in fig. 12 are performed.

Fig. 14 is a schematic structural view of a first step region in a laminated structure provided in example one;

Fig. 15 is a schematic structural view of a second step region in the laminated structure provided in example one;

FIG. 16 is a flow chart illustrating a method of fabricating a laminated structure;

fig. 17, 18, 19 and 20 are schematic views of the product structure obtained after each step in fig. 16 is performed;

Fig. 21 is a schematic structural view of a first step region in a stacked structure provided in example two;

fig. 22 is a schematic structural view of a second step region in the laminated structure provided in example two;

FIG. 23 is a schematic diagram of another memory array according to an embodiment of the present application;

FIG. 24 is a schematic diagram of a memory array according to another embodiment of the present application;

FIG. 25 is a flowchart of a method for fabricating an electrical connector and a wiring layer according to an embodiment of the present application;

fig. 26, 27, 28, 29, 30 and 31 are schematic views of the product structure obtained after each step in fig. 25 is performed;

FIG. 32 is a schematic view of a second electrical connection on a second wiring layer;

FIG. 33 is a flowchart of another method for fabricating an electrical connector and wiring layer according to an embodiment of the present application;

fig. 34 and 35 are schematic structural diagrams of the product obtained after each step in fig. 33 is performed;

Fig. 36 is a schematic diagram of a driving circuit of a memory array according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings.

Hereinafter, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

Furthermore, in the present application, directional terms "upper", "lower", etc. are defined with respect to the orientation in which the components are schematically disposed in the drawings, and it should be understood that these directional terms are relative concepts, which are used for description and clarity with respect thereto, and which may be changed accordingly in accordance with the change in the orientation in which the components are disposed in the drawings.

The present application provides an electronic device, which may include a mobile phone, a tablet computer (tablet personal computer), a laptop computer (laptop), a Personal Digital Assistant (PDA), a camera, a personal computer, a notebook computer, a vehicle-mounted device, a wearable device, an augmented reality (augmented reality) glasses, an AR helmet, a Virtual Reality (VR) glasses, or a VR helmet, etc. that needs to store data. The embodiment of the application does not limit the specific form of the electronic device. For convenience of explanation, the electronic device is exemplified by a mobile phone as shown in fig. 1.

Referring to fig. 1, fig. 1 is a schematic diagram illustrating a disassembled structure of an electronic device according to some embodiments of the present application, in this embodiment, as shown in fig. 1, the electronic device 1 includes a display screen 2, a middle frame 3, a housing (or called a battery cover, a rear case) 4, a cover plate 5, and a main board 31 fixed on the middle frame 3.

It will be appreciated that fig. 1 only schematically shows some components comprised by the electronic device 1, the actual shape, the actual size, the actual position and the actual configuration of which are not limited by fig. 1 and 2.

In some embodiments of the present application, the electronic device 1 may further comprise a chip package structure 30 as shown in fig. 2. The chip package structure 30 is disposed on the motherboard 31 and electrically connected to the motherboard 31. For example, the chip package structure 30 may be electrically connected to the motherboard 31 through a ball grid array (ball GRID ARRAY, BGA), or a plurality of copper pillar bumps (copper pillar bump, CPB) arranged in an array, so that the chip package structure 30 can implement signal transmission with other chips or chip stack structures on the motherboard 31.

It should be noted that the main board 31 may be a printed circuit board (printed circuit board, PCB).

The number of the chip package structures 30 on the motherboard 31 is not limited in the present application, and may be one, two or more.

The structure of the above-described chip package structure 30 is exemplified below. Referring to fig. 3, the chip package structure 30 may include a package Substrate (SUB) 301, a chip 302 disposed on the package substrate 301, and a molding compound (molding) 303 for molding the chip 302. The chip 302 may be a bare chip (i.e., bare die) or a chip stack structure (i.e., a stack of a plurality of bare die).

The number of chips 302 packaged in the chip package structure 30 is not limited, and may be one, two, or more than two.

In some embodiments, the chip 302 in the chip package structure 30 may be a chip having at least a memory function, and the chip may include a three-dimensional memory array. The chip with the three-dimensional memory array and the processing chip can be electrically connected with the package substrate 301, so that the chip with the three-dimensional memory array and the processing chip can perform data transmission through the package substrate 301.

It should be noted that a chip having at least a memory function means that the chip may have only a memory function. At this time, the chip is a memory chip. Or the chip may have a memory function and other functions, such as a data processing function, and in this case, the chip is a multifunctional integrated chip.

The three-dimensional memory array may be a ferroelectric memory array (Ferroelectric Random Access Memory, feRAM), a dynamic random access memory array (Dynamic Random Access Memory, DRAM), a phase change memory array (PHASE CHANGE Random Access Memory, PCRAM), a resistive memory array (RESISTIVE RANDOM ACCESS MEMORY, reRAM), a magnetic memory array (Magnetoresistive Random Access Memory, MRAM).

The structure of the three-dimensional memory array is further described below. The three-dimensional memory array 10 shown in fig. 4 includes a substrate 101 and a memory array layer 102, the memory array layer 102 including a plurality of stacked structures 1001. The substrate 101 may be located below the storage array layer 102 and used to carry the storage array layer 102.

By way of example, the substrate 101 may be of a single layer structure. In this case, the material constituting the substrate 101 may include a semiconductor material such as silicon, germanium, gallium arsenide, indium phosphide, or the like. Or the material of the substrate 101 may comprise a non-conductive material such as glass, plastic, or sapphire, etc. As another example, the substrate 101 may have a multi-layered structure. One layer furthest from the memory array layer 102 may be made of the semiconductor material or the non-conductive material, and the remaining film layers may be patterned as needed to form other circuit structures.

It should be noted that the patterning process may include a photolithography process, or include a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, ink-jet, and the like. The corresponding patterning process may be selected according to the structures formed in embodiments of the present application. The photolithography process refers to a process of forming a pattern using photoresist, a mask plate, an exposure machine, etc., including processes of film formation, exposure, development, etc.

For convenience of description below, X, Y, Z coordinate systems may be established in some of the figures. The plane of the substrate 101 shown in fig. 4 may be an XY plane, and taking the substrate 101 shown in fig. 8 as a rectangle for example, the X axis may be the length direction of the substrate 101, the Y axis may be the width direction of the substrate 101, and the Z axis may be a direction perpendicular or approximately perpendicular to the substrate 101 within manufacturing tolerances. It is understood that the width of the substrate 101 is smaller in size than the length of the substrate 101.

To this end, embodiments of the present application provide an improved laminate structure.

Fig. 6 is a schematic perspective view of a stacked structure according to an embodiment of the present application. As shown in fig. 6, the laminated structure 1001 includes: the stacked layers are stacked one on top of the other in the first direction (Z direction in fig. 6).

Wherein the stacked structure 1001 includes a plurality of insulating layers and a plurality of conductive layers alternately arranged in the first direction, the conductive layers being for connection with a driving circuit of the stacked structure. (in fig. 6, the black laminate is an insulating layer, and the white laminate is a conductive layer).

In some embodiments, the conductive layer is made of a conductive material, including but not limited to tungsten, cobalt, copper, aluminum, doped silicon, and/or silicide. The insulating layer is made of an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

Laminate structure 1001 further includes: a storage region 10011 sequentially arranged in the second direction (Y direction in fig. 6), and a first step region 10012 corresponding to the storage region 10011.

The storage area 10011 includes a plurality of storage units 100110.

As shown in fig. 6, the memory region 10011 includes a plurality of conductive layers and a plurality of insulating layers (black lamination is an insulating layer and white lamination is a conductive layer in fig. 6), and each conductive layer includes a plurality of electrodes 100110 thereon, and the electrodes 100110 are electrically connected to the first electrode of the transistor.

The location where the electrode 100110 and the conductive layer are connected includes the memory cells 100111, the plurality of memory cells 100111 form a two-dimensional memory array, and the plurality of conductive layers form a three-dimensional memory array.

The embodiment of the application does not limit the electric connection structure of the storage area. In some embodiments of the present application, the stacked structure includes a transistor, which may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET).

Wherein the transistor includes: a first pole, a second pole and a gate. In this stacked structure, a first electrode of the transistor is electrically connected to the electrode 100110, a second electrode of the transistor is electrically connected to the bit line BL, and a control terminal of the transistor Tr is electrically connected to the word line WL.

In the present application, one of the drain (drain) or source (source) of the transistor Tr is referred to as a first pole, the other pole is referred to as a second pole, and the control terminal of the transistor Tr is a gate. The drain and source of the transistor Tr may be determined according to the flow direction of the current.

The first step region 10012 includes a plurality of step groups arranged in the third direction (X direction in fig. 6).

Wherein the first direction (Z direction in fig. 6) is perpendicular to the substrate, the second direction (Y direction in fig. 6) and the third direction (X direction in fig. 6) are perpendicular and parallel to the substrate.

The embodiment of the application does not limit the number of the step groups. By way of example, there are four step sets in FIG. 6: step set 10012a, step set 10012b, step set 10012c, and step set 10012d.

The embodiment of the application does not limit the number of the step groups and can be set according to the needs.

The embodiment of the application does not limit the structure of the step group. In some embodiments of the present application, each step set includes a plurality of steps, each step extending in a third direction (X-direction in fig. 6).

Wherein each step comprises: at least one of the step surfaces 10010, the step surface 10010 is formed to protrude in the third direction (X direction in fig. 6) relative to the lamination of the steps.

As shown in fig. 6, each step has a step surface 10010, and the step surface 10010 is the conductive layer of the above-described laminated structure.

The extending direction of the steps in each step group is not limited in the embodiment of the present application, and in some embodiments of the present application, the steps of the step group are formed by extending the stack of the step groups in the +x direction.

In other embodiments of the present example, the steps of the step group are formed by the stack of step groups protruding in the-X direction.

In other embodiments of the present example, the steps of each step group are formed by stacking the step groups protruding in the direction of the adjacent step group, so that the projected patterns of the adjacent two step groups on the substrate are arranged in an axisymmetric manner.

As illustrated in fig. 6, the stack of steps 10012a extends in the direction of the step set 10012b to form a step, and the stack of steps 10012b extends in the direction of the step set 10012a to form a step, with the steps of the step set 10012a and the step set 10012b being arranged face to face.

The stack of step set 10012c extends in the direction of step set 10012d to form a step, the steps of step set 10012b and step set 10012c are arranged back-to-back, the stack of step set 10012d extends in the direction of step set 10012c to form a step, and the steps of step set 10012c and step set 10012d are arranged face-to-face.

Therefore, each first step area comprises a plurality of step groups, and the steps of each step group extend towards the direction of the step group adjacent to the step group, and therefore, the step groups have a plurality of steps with the same height.

The embodiment of the application also provides a preparation method of the laminated structure, as shown in fig. 7, the method comprises the following steps:

S101. as shown in fig. 8, a stacked structure is formed on a substrate (not shown in the drawing) along a first direction.

Wherein the stacked structure may be divided into a first step region 1001A and a storage region 1001B in the second direction, the first step region 1001A being used to form a first step group, the storage region 1001B including a plurality of memory cells.

S102. as shown in fig. 9, a plurality of first step groups are formed in the first step region 1001A of the stacked structure.

Wherein the first step region includes a plurality of first step groups arranged in the third direction, each first step group including a plurality of steps; each step includes: at least one step surface, the step surface is formed by stretching out of the lamination of the steps along a third direction; wherein the first direction is perpendicular to the substrate, and the second direction and the third direction are perpendicular and parallel to the substrate.

In some embodiments of the present application, as shown in fig. 10, forming a plurality of first step groups in a first step region 1001A of a stacked structure includes:

s1021. as shown in fig. 11, a pattern of a plurality of first step groups is formed on the surface of the first step region 1001A of the laminated structure.

The patterns of the plurality of first step groups can be formed on the surface of the first step region of the laminated structure in a photoetching mode.

For example, the first step region 1001A may be covered with the mask 001, and the surface of the storage region 1001B may be covered with the barrier adhesive 002. The mask 001 includes a plurality of patterns of the first step group, and the patterns of the mask 001 can be transferred to the first step region 1001A of the stacked structure. The barrier glue can be used for protecting the storage area and avoiding the influence on the lamination of the storage area when the first structure is etched.

S1022. as shown in fig. 9, the stacked structure is subjected to layered etching according to the patterns of the plurality of first step groups, so as to form the plurality of first step groups.

The laminated structure can be subjected to layered etching according to the patterns transferred to the laminated structure by the mask 001, so that the first step region is obtained.

In some embodiments of the present application, referring next to fig. 7 and 8, the laminated structure 1001 further includes: second step region 10013, second step region 10013 being located on a side of storage region 10011 remote from first step region 10012.

In addition, as shown in fig. 12, the manufacturing method of the laminated structure further includes:

S103. as shown in fig. 13, a plurality of second step groups are formed in the second step region 1001C of the stacked structure.

The preparation method of the second step set may refer to the preparation method of the first step set, and will not be described again.

As shown in fig. 6, the second step region 10013 includes a plurality of step groups arranged in the third direction (X direction in fig. 6), each step group including a plurality of steps.

Therefore, a plurality of first step groups are formed on one side of the storage area 10011, a plurality of second step groups are formed on one side of the storage area 10011 far away from the first step areas, so that the first step structure is only arranged on one side of the storage area 10011, and the second step structure is only arranged on the other side of the storage area 10011.

In some embodiments of the present application, as shown in fig. 14, 15, 21, 22, the plurality of step groups include: a first type step set 10041 and a second type step set 10042, a part of the stack in the stack structure 1001 is connected to the first type step set 10041, another part of the stack in the stack structure 1001 is connected to the second type step set 10042, and the height of the first type step set 10041 is different from the height of the second type step set 10042.

In some embodiments of the application, the height of the first type of step set 10041 is greater than or equal to the height of the second type of step set 10042.

The first type step set 10041 and the second type step set 10042 are staggered in the Z axis direction, and after the second type step set 10042 is translated along the Z axis, the first type step set 10041 and the second type step set 10042 may be symmetrical about the Z axis.

Wherein the height of the first step set 10041 is higher than or equal to the height of the second step set 10042, which means that the minimum height of the first step set 10041 is higher than or equal to the maximum height of the second step set 10042. The minimum height of the first step set 10041 may be the height of the bottom surface of the first step set 10041 from the substrate, and the maximum height of the second step set 10042 may be the height of the top surface of the second step set 10042 from the substrate.

The embodiments of the present application do not limit the distribution of the first type of step set 10041 and the second type of step set 10042 in the first step region 10012 and the second step region 10013.

In some embodiments of the present application, laminate structure 1001 includes: a storage region 10011 and a first step region 10012. The first step region 10012 includes: at least one first class of step set 10041 and at least one second class of step set 10042.

In other embodiments of the present application, laminate structure 1001 includes: a storage region 10011, a first step region 10012, and a second step region 10013.

In some embodiments, the first step region 10012 comprises: a plurality of first class step sets 10041, the second step region 10013 comprising: a plurality of second class step sets 10042.

In other embodiments, as shown in fig. 14 and 15, the first step region 10012 includes: a plurality of second class of step sets 10042, the second step region 10013 comprising: a plurality of first class step sets 10041.

In other embodiments, the first step region 10012 comprises: at least one first class of step set 10041 and at least one second class of step set 10042. And, the second step region 10013 includes: at least one first class of step set 10041 and at least one second class of step set 10042.

Or the first step region 10012 includes: one type of step set (a plurality of second type of step sets 10042, or a plurality of first type of step sets 10041), the second step region 10013 includes: at least one first class of step set 10041 and at least one second class of step set 10042.

Or the second step region 10013 includes: one type of step set (a plurality of second type of step sets 10042, or a plurality of first type of step sets 10041), the first step region 10012 comprises: at least one first class of step set 10041 and at least one second class of step set 10042.

The embodiment of the application does not limit the types of the step groups. In other embodiments of the present example, the plurality of step sets further includes: a third step group, wherein the height of the third step group is higher than the height of the first step group 10042 and is smaller than the height of the first step group 10041, and the third step group may be disposed in the first step region 10012 or the second step region 10013.

Of course, the types of the step groups in the application are not limited to two or three types, and only the corresponding step surfaces are required to be arranged on each conductive layer in the laminated structure, so that the step groups can be selected by a person skilled in the art according to the needs, and the step groups belong to the protection scope of the application.

Therefore, by arranging the step groups with a plurality of heights, compared with the step group with only one height in the related art, the occupied area of the step structure is effectively reduced under the condition of not increasing extra cost, the area of a core area is conveniently increased, and the three-dimensional storage array is beneficial to the structure miniaturization design and the storage high-density design. Meanwhile, the occupied area of the step structure is reduced, so that the dielectric layer structure covered on the step structure is correspondingly reduced, the stress of the step structure on the dielectric layer structure is reduced, and the stability of the step structure is improved.

The following describes the arrangement and preparation process of two types of step groups in the laminated structure in the embodiment of the present application with reference to example one and example two.

Example one:

Fig. 14 is a schematic structural view of a first step region 10012 in a stacked structure as provided in example one. Fig. 15 is a schematic structural view of a second step region 10013 in the laminated structure provided in example one.

As shown in fig. 14 and 15, the laminated structure includes: the laminated structure 1001 is laminated in this order along the first direction (Z direction in fig. 14 and 15).

Wherein the stacked structure 1001 includes a plurality of insulating layers and a plurality of conductive layers alternately arranged in the first direction, the conductive layers being for connection with a driving circuit of the stacked structure. (in fig. 14 and 15, the black laminate is an insulating layer, and the white laminate is a conductive layer).

Laminate structure 1001 further includes: a first step region 10012, a storage region 10011, and a second step region 10013 disposed in the second direction (Y direction in fig. 14, 15).

The present example does not limit the number of step groups that the first step region 10012 and the second step region 10013 include.

In some embodiments of the examples, as shown in fig. 14, the first step region 10012 includes four first step groups arranged in the X direction: step set 10012a, step set 10012b, step set 10012c, and step set 10012d.

The second step region 10013 includes four second step groups arranged in the X direction: step set 10013a, step set 10013b, step set 10013c, and step set 10013d.

Wherein the first direction (Z direction in fig. 14, 15) is perpendicular to the substrate, and the second direction (Y direction in fig. 14, 15) and the third direction (X direction in fig. 14, 15) are perpendicular and parallel to the substrate.

The present example does not limit the structure of the step group. In some embodiments of the present example, each step set includes a plurality of steps, each step including: at least one step surface which is a conductive layer of the laminated structure.

The present example does not limit the extending direction of the steps in each step group, and in some embodiments of the present example, the steps of each step group are formed by extending the stack of step groups in the +.x direction.

In other embodiments of the present example, the steps of each step group are formed by a stack of step groups protruding in the-X direction.

In other embodiments of the present example, the steps of each step group are formed by extending the stack of step groups in the direction of the adjacent step group, and the projected patterns of the adjacent two step groups on the substrate are arranged in an axisymmetric manner.

As illustrated in fig. 14, the stack of the step group 10012a protrudes in the direction of the step group 10012b to form a step, and the stack of the step group 10012b protrudes in the direction of the step group 10012a to form a step, and the steps of the step group 10012a and the step group 10012b are arranged face to face.

As shown in fig. 15, the stack of the step group 10013a protrudes in the direction of the step group 10013b to form a step, and the stack of the step group 10013b protrudes in the direction of the step group 10013a to form a step, and the steps of the step group 10013a and the step group 10013b are arranged face to face.

The stack of the step group 10013c extends in the direction of the step group 10013d to form a step, the steps of the step group 10013b and the step group 10013c are arranged back to back, the stack of the step group 10013d extends in the direction of the step group 10013c to form a step, and the steps of the step group 10013c and the step group 10013d are arranged face to face.

Therefore, a plurality of step groups are arranged in each laminated structure, and the steps of each step group are formed by extending from the laminated layers of the steps to the direction of the step group adjacent to the step group, so that the space on the side edge of the storage area can be fully utilized, the arrangement density of the electric connecting pieces is improved, and the occupied area of the step structure can be effectively reduced under the condition of not increasing extra cost.

In this example, the step group may be divided into: a first type of step set 10041 and a second type of step set 10042.

In some embodiments of the present example, the height of the first type of step set 10041 is greater than or equal to the height of the second type of step set 10042.

The height of the first class of step set 10041 being greater than or equal to the height of the second class of step set 10042 means that the minimum height of the first class of step set 10041 is greater than or equal to the maximum height of the second class of step set 10042. The minimum height of the first step group 10041 may be the height of the step region of the first step group 10041 from the substrate, and the maximum height of the second step group 10042 may be the height of the step region of the second step group 10042 from the substrate.

The height of the first step region 10012 and the second step region 10013 is not limited in this embodiment, in some embodiments of the present example, as shown in fig. 14, the first step region 10012 employs the second step group 10042, as shown in fig. 15, and the second step region 10013 employs the first step group 10041.

In other embodiments of the present example, the first step region 10012 employs a first type of step set 10041 and the second step region 10013 employs a second type of step set 10042. This structure is not shown in the drawings, and reference is made to the structures of fig. 14 and 15.

By way of example, the laminate structure has a total of 8 layers, each comprising a conductive layer and an insulating layer. In fig. 14 and 15, the black layer is an insulating layer, and the white layer is a conductive layer.

As shown in fig. 14, the second-type step group 10042 has 4-layer stacks, and the stacks of the second-type step group 10042 are the same height as the portions of the lower 4 layers (1-4 layers in the Z direction) of the storage region 10011 that pass through the second-type step group 10042 in the Y direction.

Wherein the stack of the second type step group 10042 is "the same height" as the portion of the storage region passing through the second type step group 10042 in the Y direction, which means that, in the adjacent step structure and storage region 1011, the first type step group 10041 of the step structure and any corresponding position in the storage region 1011 passing through the first type step group 10041 have the same height.

As illustrated in fig. 14, taking the second step group 10042 as an example, in the Z direction, the heights of the steps included in the second step group 10042 gradually increase, the heights of the stacks included in the portion passing through the second step group 10042 in the storage area 1011 also gradually increase, the height of the leftmost stack of the portion passing through the second step group 10042 in the storage area 1011 coincides with the height of the leftmost step of the second step group 10042, the height of the rightmost stack of the portion passing through the second step group 10042 in the storage area 1011 coincides with the height of the rightmost step of the second step group 10042, and in other positions, for example, one of the steps in the step group indicated by four arrows in fig. 14 and one of the stacks in the storage area 1011, the steps and the stacks correspond in the Y direction, and the stacks have the same height.

As shown in fig. 15, the first type step group 10041 has 8 layers of stacked layers, which may be a step region 10041A and a stacked region 10041B, wherein the stacked layers of the step region 10041A of the first type step group 10041 are the same height as the upper 4 layers (5-8 layers in the + Z direction) of the storage region passing through the first type step group 10041 in the Y direction, and the stacked layers of the stacked region 10041B of the first type step group 10041 are the same height as the lower 4 layers (1-4 layers in the + Z direction) of the storage region passing through the first type step group 10041 in the Y direction.

In some embodiments of the present example, the dimension of the stacking region 10041B in the X direction is consistent with the dimension of the bottommost layer of the step region 10041A. The first type of step set 10041 may be prepared by etching only a portion of the stack of upper step regions 10041A.

As illustrated in fig. 15, taking the first type step group 10041 as an example, in the Z direction, the heights of the steps included in the first type step group 10041 gradually increase, the heights of the stacks included in the portion passing through the first type step group 10041 in the storage area 1011 also gradually increase, the height of the leftmost stack of the portion passing through the first type step group 10041 in the storage area 1011 coincides with the height of the leftmost step of the first type step group 10041, the height of the rightmost stack of the portion passing through the first type step group 10041 in the storage area 1011 coincides with the height of the rightmost step of the first type step group 10041, and in other positions, for example, one of the steps in the step group indicated by four arrows in fig. 15 and one of the stacks in the storage area 1011, the steps and the stacks correspond in the Y direction, and the steps and the stacks have the same height.

The present example also provides a method for manufacturing a laminated structure, as shown in fig. 16, including:

s201. as shown in fig. 17, a stacked structure is formed on a substrate (not shown in the drawing) along a first direction.

Wherein the laminated structure comprises in a second direction: a first step region 1001A, a storage region 1001B, and a second step region 1001C, the first step region 1001A being used to form a first step region, the storage region 1001B being a storage region, and the second step region 1001C being used to form a second step region.

S202. as shown in fig. 18, the stacked structure of the upper layer of the first step region 1001A is removed.

For example, referring to fig. 18, the stack 1001 has 8 layers in total, and the upper 4 layers of the stack at the first step region 1001A can be removed.

S203. as shown in fig. 19, a plurality of patterns of the first step group are formed in the first step region, and a plurality of patterns of the second step group are formed in the second step region.

For example, the surfaces of the first step region 1001A and the second step region 1001C may be covered with the mask 001, and the surface of the storage region 1001B may be covered with the barrier adhesive 002.

The mask 001 of the first step region 1001A includes a pattern of the first step region, and the pattern of the mask 001 of the first step region 1001A may be transferred to the first step region 1001A of the stacked structure.

The mask 001 of the second step region 1001C includes a pattern of the second step region, and the pattern of the mask 001 of the second step region 1001C may be transferred to the surface of the second step region 1001C of the stacked structure.

The barrier glue 002 may be used to protect the storage area from the effects of etching the first mesa structure and the second mesa region to the stack of storage areas.

S204, as shown in fig. 20, performing layered etching on the laminated structure according to the patterns of the first step group and the patterns of the second step group to obtain the first step group and the second step group.

And carrying out layered etching on the laminated structure according to the patterns transferred to the laminated structure by the mask 001 to obtain the first step region and the second step region.

In addition, after the first step region and the second step region are prepared, the preparation method further includes: and removing the mask 001 and the blocking adhesive 002 on the surface of the laminated structure to obtain the laminated structure shown in fig. 14 and 15.

Example two:

Fig. 21 is a schematic structural view of a first step region 10012 in a stacked structure provided in example two. Fig. 22 is a schematic structural view of a second step region 10013 in the stacked structure provided in example two.

As shown in fig. 21 and 22, the laminated structure includes: the laminated structure 1001 is laminated in this order in the first direction (Z direction in fig. 21 and 22).

Wherein the stacked structure 1001 includes a plurality of insulating layers and a plurality of conductive layers alternately arranged in the first direction, the conductive layers being for connection with a driving circuit of the stacked structure. (in fig. 21 and 22, the black laminate is an insulating layer, and the white laminate is a conductive layer).

Laminate structure 1001 further includes: a first step region 10012, a storage region 10011, and a second step region 10013 disposed in the second direction (Y direction in fig. 21, 22).

In some embodiments of the examples, as shown in fig. 21, the first step region 10012 includes four first step groups arranged in the X direction: step set 10012a, step set 10012b, step set 10012c, and step set 10012d.

Four second step groups of the second step regions 10013 are arranged in the X direction: step set 10013a, step set 10013b, step set 10013c, and step set 10013d.

Wherein the first direction (Z direction in fig. 21, 22) is perpendicular to the substrate, and the second direction (Y direction in fig. 21, 22) and the third direction (X direction in fig. 21, 22) are perpendicular and parallel to the substrate.

As illustrated in fig. 21, the stack of the step group 10012a protrudes in the direction of the step group 10012b to form a step, and the stack of the step group 10012b protrudes in the direction of the step group 10012a to form a step, and the steps of the step group 10012a and the step group 10012b are arranged face to face.

As shown in fig. 22, the stack of the step group 10013a protrudes in the direction of the step group 10013b to form a step, and the stack of the step group 10013b protrudes in the direction of the step group 10013a to form a step, and the steps of the step group 10013a and the step group 10013b are arranged face to face.

The height of the first step region 10012 and the second step region 10013 is not limited in this embodiment, and in some embodiments of this example, as shown in fig. 21, the step group 10012a and the step group 10012d employ the first type step group 10041.

The step set 10012b and the step set 10012c employ a second type of step set 10041.

As shown in fig. 22, the step set 10013a and the step set 10013d employ a second type of step set 10042.

The step set 10013b and the step set 10013c employ a first type of step set 10041.

By way of example, the laminate structure has a total of 8 layers, each comprising a conductive layer and an insulating layer. In fig. 21 and 22, the black layer is an insulating layer, and the white layer is a conductive layer.

As shown in fig. 21 and 22, the second step group 10042 has 4 stacked layers, and the stacked layers of the second step group 10042 are the same height as the portions of the lower 4 layers (1-4 layers in the Z direction) of the storage region 1011 passing through the second step group 10042 in the Y direction.

As illustrated in fig. 21 and 22, taking the second step group 10042 as an example, the height of the plurality of steps included in the second step group 10042 gradually increases in the Z direction, the height of the plurality of stacked layers included in the portion passing through the second step group 10042 in the storage region 1011 also gradually increases, the height of the leftmost stacked layer in the portion passing through the second step group 10042 in the storage region 1011 coincides with the height of the leftmost step in the second step group 10042, the height of the rightmost stacked layer in the portion passing through the second step group 10042 in the storage region 1011 coincides with the height of the rightmost step in the second step group 10042, and in other positions, for example, one of the steps in the step group indicated by four arrows in fig. 21 and one of the stacked layers in the storage region 1011, the steps and the stacked layers correspond in the Y direction, and the stacked layers all have the same height.

The first type of step set 10041 has 8 layers of stacked layers, which may be a step region 10041A and a stacked region 10041B, wherein the stacked layer of the step region 10041 of the first type of step set 10041 is the same in height as the portion of the upper 4 layers (5-8 layers in the + Z direction) of the storage region passing through the first type of step set 10041 in the Y direction, and the stacked layer of the stacked region 10041B of the first type of step set 10041 is the same in height as the portion of the lower 4 layers (1-4 layers in the + Z direction) of the storage region passing through the first type of step set 10041 in the Y direction.

As illustrated in fig. 21 and 22, taking the first type step group 10041 as an example, in the Z direction, the heights of the steps included in the first type step group 10041 gradually increase, the heights of the stacks included in the portion passing through the first type step group 10041 in the storage region 1011 also gradually increase, the height of the leftmost stack of the portion passing through the first type step group 10041 in the storage region 1011 coincides with the height of the leftmost step of the first type step group 10041, the height of the rightmost stack of the portion passing through the first type step group 10041 in the storage region 1011 coincides with the height of the rightmost step of the first type step group 10041, and in other positions, for example, one of the steps in the step group indicated by four arrows in fig. 22 and one of the stacks in the storage region 1011, the steps and the stacks correspond in the Y direction, and the steps and the stacks have the same height.

The present example also provides a method for manufacturing a laminated structure, which can refer to example one and will not be described herein.

The conductive layers in the above-described stacked structure need to be connected to the driving circuit, and in some embodiments of the present application, the step surface 10010 of each step may be connected to the wiring layer through an electrical connector, and then the wiring layer is electrically connected to the driving circuit.

Compared with the related art, the laminated structure provided by the application has the advantages that more step surfaces 10010 are added, each step surface 10010 is connected with the driving circuit, so that the wiring of the laminated structure is more complex, if the wiring mode in the prior art shown in fig. 5 is adopted, the time delay is easy to generate, and in order to reduce the wiring difficulty of the laminated structure, the embodiment of the application also provides an improved laminated structure.

As shown in fig. 23, the laminated structure further includes: a first wiring layer 10021 and a second wiring layer 10022. The first wiring layer 10021 is disposed near the stacked structure 1001, and the second wiring layer 10022 is located on a side of the first wiring layer 10021 away from the stacked structure 1001.

As illustrated in fig. 23, the first wiring layer 10021 includes: a plurality of first connection lines (e.g., first connection lines 10021a, 10021 b). The second wiring layer 10022 includes: a plurality of second connection lines (e.g., second connection line 10022a, second connection line 10022 b).

Referring next to fig. 23, the laminated structure 100 further includes: electrical connector 1003.

As shown in fig. 24, the electrical connector 1003 includes: the step surface 10010 is connected to the first wiring layer 10021 by the first electrical connectors 1003 and the second electrical connectors 10032, and the first wiring layer 10021 is connected to the second wiring layer 10022 by the second electrical connectors 10032.

The structure of the first electrical connector 1003 is not limited in the embodiment of the present application. In some embodiments of the present application, the first electrical connector 1003 employs through silicon vias (Through Silicon Via, TSV), comprising: a contact hole, and a conductive material filled in the contact hole.

The steps with the same height in each step group are connected with the same first connecting wire through a first electric connecting piece 10031, and the first connecting wire connected with the steps with the same height in a plurality of step groups is connected with the same second connecting wire through a second electric connecting piece 10032.

The embodiment of the application does not limit the arrangement mode of the first connecting wire and the second connecting wire. In some embodiments, the plurality of first connection lines are sequentially arranged in the second direction (Y direction in fig. 6). The plurality of second connection lines are sequentially arranged along the third direction (X direction in fig. 6).

In some embodiments, the first connection lines are in one-to-one opposition to the step face 10010. The first connecting line includes: opposite first and second ends, wherein the first end of the first connecting wire is connected to the first electrical connector 10031 and the other end of the first connecting wire is connected to the second electrical connector 10032.

As an example, as shown in fig. 24, one step 10010a of the first step group 10012a is the same height as one step 10010b of the second step group 10012b, the step 10010a is connected to one first connecting line 10021a through two first electric connectors 10031a, the step 10010b is connected to the other first connecting line 10021b through two first electric connectors 10031b, the first connecting line 10021a is connected to one second connecting line 10022a through one second electric connector 10032a, and the first connecting line 10021b is connected to one second connecting line 10022a through the other second electric connector 10032 b.

In some embodiments, a dielectric layer is disposed on the laminate structure, and the first and second electrical connectors 10031, 10032 are formed in the dielectric layer, and the first and second wiring layers 10021, 10022 are formed on the dielectric layer, for example.

It should be noted that, in the embodiment of the present application, the first wiring layer 10021, the second wiring layer 10022, and the first electrical connector 10031 and the second electrical connector 10032 may be used not only for the stacked structure shown in fig. 6, 14, etc., but also for other stacked structures, including but not limited to the stacked structure in the related art shown in fig. 5.

The embodiment of the application also provides a preparation method of the electric connector and the wiring layer. Wherein the fabrication of the electrical connection and wiring layers is performed taking the stacked structure shown in fig. 14 as an example. As shown in fig. 25, the method includes:

S301. as shown in fig. 26, a first dielectric layer 0001 is formed on the stacked structure.

S302. as shown in fig. 27, a first electrical connector 10031 is formed in the first dielectric layer 0001.

Wherein forming the first electrical connection 10031 in the first dielectric layer 0001 includes:

Etching the first dielectric layer 0001 to obtain a plurality of first contact holes.

Filling the first contact hole to obtain the first electrical connector 10031.

S303. as shown in fig. 28, a first wiring layer 10021 is formed on the first dielectric layer 0001.

Wherein, the first wiring layer 10021 includes: and a plurality of first connecting lines, each step being connected to one of the first connecting lines through a first electrical connector.

S304. as shown in fig. 29, a second dielectric layer 0002 is formed on the first wiring layer 10021.

S305. as shown in fig. 30, a second electrical connector 10032 is formed in the second dielectric layer 0002.

Wherein forming the second electrical connector 10032 in the second dielectric layer 0002 comprises:

And etching the second dielectric layer 0002 to obtain a plurality of second contact holes.

And then filling the second contact hole to obtain a second electric connector 10032.

S306. as shown in fig. 31, a second wiring layer 10022 is formed on the second dielectric layer 0002.

Wherein the second wiring layer 10022 includes: a plurality of second connecting lines. Wherein, the first connection line connected with the steps with the same height in the step groups is connected with the same second connection line through the second electric connector 10032.

Therefore, by arranging the first wiring layer and the second wiring layer, the wiring does not occupy additional area outside the array, and the storage density is improved. Meanwhile, compared with the direct connection through the electric connecting piece, the length of the electric connecting piece is reduced by arranging the wiring layer, wiring difficulty is reduced, and time delay is reduced.

In addition, in some embodiments of the present application, as shown in fig. 32, projections of the second electrical connectors 10032 corresponding to two adjacent step groups on the second wiring layer are arranged in an axisymmetric manner.

For example, referring to fig. 32, the projections of the second electrical connectors 10032 corresponding to the first step group 10012a on the second wiring layer 10022 are 4, the projections of the second electrical connectors 10032 corresponding to the second step group 10012b on the second wiring layer 10022 are 4, the projections of the second electrical connectors 10032 corresponding to the first step group 10012a on the second wiring layer 10022 are arranged from the left upper corner to the right upper corner, and the projections of the second electrical connectors 10032 corresponding to the second step group 10012a on the second wiring layer 10022 and the projections of the second electrical connectors 10032 corresponding to the second step group 10012b on the second wiring layer 10022 are arranged in an axisymmetric manner.

Therefore, the second electric connecting piece adopts the arrangement mode, the wiring difficulty is reduced, the wiring length is reduced, and the time delay can be reduced.

In some embodiments, referring next to fig. 23 and 24, the routing layer further includes: the third wiring layer 10023, the third wiring layer 10023 is provided on the side of the stacked structure 1001 away from the second wiring layer 10022.

The electrical connector 1003 further includes: third electrical connector 10032.

As shown in fig. 24, the first wiring layer 10021 further includes: the plurality of third connection lines 10021c, the second wiring layer 10022 is connected to the third connection lines 10021c through third electrical connectors 10032c, the third connection lines are connected to the third wiring layer 10023 through fourth connectors 10031c, and the third wiring layer 10023 is used for connection to the previous driving circuit.

In order to shorten the routing distance, a gap is provided between adjacent step groups, and the fourth electrical connector 10032c is disposed in the gap.

For example, referring to fig. 24, a gap is provided between the first step set 10012a and the second step set 10012b, and a fourth electrical connector 10032c is provided in the gap of the first step set 10012a and the second step set 10012 b.

It should be noted that the above-mentioned wiring layer and electrical connection structure may be used not only in the stacked structure provided in the embodiment of the present application to interconnect the step surface 10010 and the driving circuit, but also in other stacked structures, including but not limited to those in the related art.

In addition, in the case where the number of layers of the stacked structure 1001 continues to increase, the connection lines in the second wiring layer 10022 may be divided into a plurality of segments, each of which is used to connect the first wiring layer 10021 of one conductive layer and each of which is connected to the third wiring layer 10023, and the occupied area may be further reduced.

Correspondingly, the embodiment of the application also provides a preparation method of the third wiring layer and the electric connecting piece. The third wiring layer is provided on the substrate 101, for example. As shown in fig. 33, forming the stacked structure on the substrate in the above step S101 may include:

s401. as shown in fig. 34, a third dielectric layer 0003 is formed on the substrate 101.

S402. as shown in fig. 35, a third wiring layer 10023 is formed on the third dielectric layer 0003.

S403. a plurality of stacked structures are formed over the third wiring layer 10023, resulting in a stacked structure (substrate not shown) as shown in fig. 24.

Wherein, the first wiring layer 10021 further includes: the plurality of third connection lines 10021c further includes a third electrical connector 10032c in the second dielectric layer 0002, the second wiring layer 10022 is connected to the third connection line 10021c through the third electrical connector 10032c, the first dielectric layer 0001 further includes a fourth connector 10031c, the third connection line is connected to the third wiring layer 10023 through the fourth connector 10031c, and the third wiring layer 10023 is used for connecting to a previous driving circuit.

In some embodiments of the present application, the conductive layer in the stacked structure 1001 may be a plate line (PLATE LINE, PL). Each plate line is connected to the third wiring layer 10023, respectively, and is connected to the driving circuit through the third wiring layer 10023.

As shown in fig. 24, the laminated structure further includes: a plurality of Word Lines (WL) and a plurality of Bit Lines (BL), the word lines WL and the bit lines BL being disposed on a side of the stacked structure 1001 remote from the second wiring layer 10022, the extending directions of the word lines WL and the bit lines BL being perpendicular.

Thus, the word line WL, the bit line BL, and the third wiring layer 10023 are all located on the side of the stacked structure 1001 away from the second wiring layer 10022, and the word line WL, the bit line BL, and the third wiring layer 10023 are disposed on the same side of the stacked structure, so that the wiring is shortest when connected to the driving circuit, and the delay can be reduced.

In fig. 24, the third wiring layer 10023 includes two connection lines: the connection lines 1023a and 1023b, wherein the connection lines 1023a and 1023b and the bit lines BL are arranged in the same layer, and the connection lines 1023a and 1023b and the bit lines BL run the same.

In some embodiments, the connection lines 1023a and 1023b are disposed in the gaps of the bit lines BL, and the connection lines 1023a and 1023b occupy only 2 bit lines BL, which is advantageous for improving the memory density.

In some embodiments of the present application, as shown in fig. 26, a front driving circuit of a memory array is arranged below the array, and the front driving circuit includes: a plate drive circuit (PL driver), a bit line BL drive circuit (BL driver) and a word line WL drive circuit (WL driver).

Wherein, the panel driving circuit (PL driver) includes: the first panel driving circuit PL1 driver, the second panel driving circuit PL2 driver, the third panel driving circuit PL3 driver, the fourth panel driving circuit PL4 driver, the fifth panel driving circuit PL5 driver, the sixth panel driving circuit PL6 driver, the seventh panel driving circuit PL7 driver, and the eighth panel driving circuit PL8 driver.

In the above embodiment, as shown in fig. 23, each laminated structure 100 has 8 conductive layers in total: first conductive layer 1001a, second conductive layer 1001b, third conductive layer 1001c, fourth conductive layer 1001d, fifth conductive layer 1001e, sixth conductive layer 1001f, seventh conductive layer 1001g, and eighth conductive layer 1001h. These conductive layers may be plate lines (PLATE LINE, PL).

The first conductive layer 1001a is electrically connected to the first panel driving circuit PL1 driver, the second conductive layer 1001b is electrically connected to the second panel driving circuit PL2 driver, the third conductive layer 1001c is electrically connected to the third panel driving circuit PL3 driver, the fourth conductive layer 1001d is electrically connected to the fourth panel driving circuit PL4 driver, the fifth conductive layer 1001e is electrically connected to the fifth panel driving circuit PL5 driver, the sixth conductive layer 1001f is electrically connected to the sixth panel driving circuit PL6 driver, the seventh conductive layer 1001g is electrically connected to the seventh panel driving circuit PL7 driver, and the eighth conductive layer 1001g is electrically connected to the eighth panel driving circuit PL8 driver.

Each of the conductive layers is connected to the third wiring layer 10023, respectively, and is electrically connected to the panel driving circuit PL driver through the third wiring layer 10023.

The panel driving circuits PL driver are distributed beside the corresponding tracks of each conductive layer, for example. The steps corresponding to each conductive layer are connected with the eight panel driving circuits PLdriver one by one through the electric connection piece and the wiring layer.

In some embodiments of the present application, referring next to fig. 23 and 24, the conductive layers of the first and second step regions 10012 and 10013 that are symmetrical about the memory region 10011 after being translated in the Z-direction are connected down to a drive-occupying common bit line drive circuit (BL driver).

For example, the first conductive layer 1001a is connected to the first panel driver circuit PL1 driver, the fifth conductive layer 1001e is connected to the fifth panel driver circuit PL5 driver, and the first conductive layer 1001a and the fifth conductive layer 1001e are symmetrical with respect to the storage region 10011 after being translated along the Z direction, and the first panel driver circuit PL1 driver and the fifth panel driver circuit PL5 driver share the same bit line driver circuit (BL driver).

As shown in fig. 36, bit line BL driving circuits (BL drivers) are arranged in the middle of the array in the Y direction, distributed perpendicular to the direction of the bit line BL routing, and the bit lines BL in the stacked structure may be connected to the bit line BL driving circuits (BLdriver) in-situ down-lead.

The word line WL driver circuits (WL drivers) are arranged in the middle of the array along the X direction, are distributed perpendicular to the line direction of the word lines WL, and the word lines WL in the stacked structure can be connected to the word line WL driver circuits (WLdriver) in-situ.

Thus, the wiring paths of the conductive layer to the flat panel drive circuit (PL driver), the bit line BL to the bit line drive circuit BL driver, and the word line WL to the word line drive circuit (WLdriver) can be made shortest, and the drive delay can be reduced.

Meanwhile, each layer of flat plate is provided with a plurality of electric connectors connected to a front circuit, so that the driving delay can be reduced.

In addition, the bit line BL, the bit line driving circuit BL driver and the switching circuit can be shared by the plurality of laminated structures, and the plurality of laminated structures in the memory array are only required to be switched by the switching circuit when in read-write operation each time, so that the memory density is improved, and the panel power consumption of single operation is reduced.

The present application is not limited to the above embodiments, and any changes or substitutions within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims

1. A memory array, comprising:

The substrate is provided with a plurality of holes,

And a plurality of stacked structures disposed on the substrate;

Each of the laminated structures includes: a storage region and a first step region corresponding to the storage region, which are sequentially arranged along a first direction; wherein the storage area includes a plurality of storage units;

The first step region includes a plurality of first step groups arranged in a second direction, each of the first step groups including a plurality of steps; each of the steps extending in the second direction;

wherein the first direction and the second direction are perpendicular and parallel to the substrate.

2. The memory array of claim 1, wherein projections of adjacent two of the first step groups arranged in the second direction on the substrate are arranged axisymmetrically.

3. The memory array of claim 1 or 2, wherein the stacked structure further comprises: the second step area corresponds to the storage area and is positioned at one side of the storage area away from the first step area;

the second step region includes a plurality of second step groups arranged in the second direction, each of the second step groups including a plurality of steps, a direction of each of the steps extending in the second direction.

4. A memory array according to any of claims 1-3, wherein the stacked structure comprises a plurality of stacks stacked in a third direction; the third direction is perpendicular to the substrate;

The plurality of step groups include: the storage area comprises a first type step group and a second type step group, wherein part of the storage area is connected with the first type step group, the other part of the storage area is connected with the second type step group, and the height of the first type step group is different from the height of the second type step group.

5. The memory array of any of claims 1-4, wherein the stacked structure further comprises: a first wiring layer and a second wiring layer which are stacked, wherein the first wiring layer is arranged on one side of the stacked structure far away from the substrate, and the second wiring layer is arranged on one side of the first wiring layer far away from the stacked structure;

The first wiring layer includes: a plurality of first connection lines;

The second wiring layer includes: a plurality of second connection lines;

The memory array further includes: a plurality of first electrical connectors and a plurality of second electrical connectors;

Each step is connected with a first connecting wire through a first electric connecting piece; and the first connecting wires connected with the steps with the same height in the step groups are connected with the same second connecting wire through the second electric connecting piece.

6. The memory array of claim 5, wherein a plurality of the first connection lines are sequentially arranged along the second direction; the plurality of second connecting lines are sequentially arranged along the first direction.

7. The memory array of claim 5 or 6, wherein the first electrical connection is perpendicular to the first connection line and the second electrical connection is perpendicular to the second connection line.

8. The memory array of any of claims 5-7, wherein the stacked structure further comprises: a third wiring layer provided on a side of the laminated structure away from the second wiring layer, the first wiring layer further comprising: the second wiring layers are connected with the third connecting wires through third electric connecting pieces, the third connecting wires are connected with the third wiring layers through fourth connecting pieces, and the third wiring layers are used for being connected with a front driving circuit.

9. The memory array of claim 8, wherein gaps are provided between adjacent step sets, the fourth electrical connection being disposed in the gaps.

10. The memory array of any of claims 1-9, wherein the stacked structure comprises a plurality of insulating layers and a plurality of conductive layers alternating along a third direction.

11. The memory array of claim 10, wherein the conductive layer is a plate line, the memory array further comprising: and the word line and the bit line are arranged on one side of the laminated structure far away from the second wiring layer, and the extending direction of the word line and the bit line is vertical.

12. A memory array according to claim 10 or 11, wherein a plurality of memory cells arranged in an array are provided on each of the conductive layers of the memory region.

13. A memory array, comprising:

The substrate is provided with a plurality of holes,

And a plurality of stacked structures disposed on the substrate;

A first wiring layer and a second wiring layer; the first wiring layer is arranged on one side of the laminated structure far away from the substrate, and the second wiring layer is arranged on one side of the first wiring layer far away from the laminated structure;

The first wiring layer includes: a plurality of first connection lines;

The second wiring layer includes: a plurality of second connection lines;

Each of the laminated structures includes: a storage region and a step region disposed along a first direction;

The step area comprises a plurality of step groups, and each step group comprises a plurality of steps;

The memory array further includes: a plurality of first electrical connectors and a plurality of second electrical connectors; each step is connected with one first connecting wire through the first electric connecting piece; the second connecting wires connected with the steps with the same height in the step groups are connected with the same second connecting wire through the second electric connecting piece;

wherein the first direction is parallel to the substrate.

14. The memory array of claim 13, wherein each of the steps extends in a second direction, and a plurality of the first connection lines are sequentially arranged in the second direction; the second connecting lines are sequentially arranged along the first direction, and the first direction and the second direction intersect and are parallel to the substrate.

15. The memory array of claim 13 or 14, wherein the first electrical connection is perpendicular to the first connection line and the second electrical connection is perpendicular to the second connection line.

16. The memory array of any of claims 13-15, wherein the routing layer further comprises: a third wiring layer provided on a side of the laminated structure away from the second wiring layer, the first wiring layer further comprising: the second wiring layers are connected with the third connecting wires through third electric connecting pieces, the third connecting wires are connected with the third wiring layers through fourth connecting pieces, and the third wiring layers are used for being connected with a front driving circuit.

17. A memory, comprising: a controller, and a memory array according to any one of claims 1-16, the controller being electrically connected to the memory array.

18. A chip package structure, comprising:

Packaging a substrate;

and the memory of claim 17 disposed on the package substrate.

19. An electronic device, comprising: comprising the following steps: a main board; the chip package structure of claim 18, wherein the chip package structure is disposed on the motherboard and electrically connected to the motherboard.

20. A method of manufacturing a memory array, the method comprising:

Forming a plurality of stacked structures on a substrate; wherein the laminated structure includes in a first direction: a storage region and a first step region corresponding to the storage region; wherein the storage area includes a plurality of storage units;

Forming a plurality of first step groups in the first step region; wherein a plurality of the first step groups are arranged along a second direction, each of the first step groups including a plurality of steps; each of the steps extending in the second direction; the first direction and the second direction are perpendicular and parallel to the substrate.

21. The method of manufacturing a memory array according to claim 20, wherein forming a plurality of first step groups arranged in the second direction in the first step region comprises:

forming a plurality of patterns of the first step groups on the surface of the first step region;

And carrying out layered etching on the area, where the pattern is not arranged, of the first step area to obtain a plurality of layers of steps, and forming a plurality of first step groups.

22. The method of claim 20 or 21, wherein the stacked structure further comprises, in a second direction: a second step region located on a side of the storage region remote from the first step region, the method further comprising:

Forming a plurality of second step groups in the second step region; wherein a plurality of the second step groups are arranged along a second direction.

23. The method of any one of claims 20-22, further comprising: forming a first dielectric layer on the laminated structure;

forming a plurality of first electrical connectors in the first dielectric layer;

Forming a first wiring layer on the first dielectric layer; wherein the first wiring layer includes: a plurality of first connection lines, each of the steps being connected to one of the first connection lines through the first electrical connection member;

forming a second dielectric layer on the first wiring layer;

forming a plurality of second electrical connectors in the second dielectric layer;

forming a second wiring layer on the surface of the second dielectric layer; wherein the second wiring layer includes: a plurality of second connection lines; the first connecting lines connected with the steps with the same height in the step groups are connected with the same second connecting line through the second electric connecting piece.

24. The method of claim 23, wherein forming a plurality of stacked structures on the substrate comprises:

Forming a third dielectric layer on the substrate;

forming a third wiring layer on the third dielectric layer;

Forming a plurality of the stacked structures on the third wiring layer; wherein the first wiring layer further includes: a plurality of third connection lines; a fourth electric connecting piece is further formed in the first dielectric layer, the third connecting wire is connected with the third wiring layer through the fourth connecting piece, a third electric connecting piece is further formed in the second dielectric layer, and the second wiring layer is connected with the third connecting wire through the third electric connecting piece; the third wiring layer is used for being connected with the front driving circuit.