CN112289796B - Manufacturing method of three-dimensional memory and three-dimensional memory - Google Patents
Manufacturing method of three-dimensional memory and three-dimensional memory Download PDFInfo
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- CN112289796B CN112289796B CN202011169455.8A CN202011169455A CN112289796B CN 112289796 B CN112289796 B CN 112289796B CN 202011169455 A CN202011169455 A CN 202011169455A CN 112289796 B CN112289796 B CN 112289796B
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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Abstract
The invention provides a manufacturing method of a three-dimensional memory and the three-dimensional memory, wherein in the manufacturing method of the three-dimensional memory, a plurality of first virtual metal contact structures are formed around a first metal contact structure in an array chip to share and drain static electricity caused by subsequent etching; in addition, in the circuit chip, add the static elimination circuit who is connected with first virtual metal contact structure electricity, in order to catch or eliminate the static that first virtual metal contact structure is gone up through static elimination circuit and accumulate, further strengthen the sharing drainage effect to static, thereby can greatly reduced through the static volume in first metal contact structure and the conduction of second metal contact structure to the control circuit on the circuit chip, the damage of static that can effectively avoid the sculpture to cause to control circuit, control circuit's structural stability and reliability on the circuit chip have been strengthened.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a three-dimensional memory and the three-dimensional memory.
Background
The three-dimensional memory is a technology for stacking data units, can realize the stacking of 32 layers or more of data units at present, overcomes the limitation of the practical expansion limit of a plane memory, further improves the storage capacity, reduces the storage cost of each data bit, and reduces the energy consumption.
However, in the current method for manufacturing the three-dimensional memory, after the array chip and the circuit chip are bonded, the substrate of the array chip needs to be etched, and the metal interconnection structure is led out from the back surface of the array chip, which requires plasma etching and deposition processes, wherein ions generated by the plasma etching carry a large amount of static electricity, and the static electricity is transmitted to each control circuit in the circuit chip along the metal interconnection structure, so that the structure of the control circuit is damaged, and the reliability of the three-dimensional memory is reduced.
Therefore, how to effectively reduce the damage of the etching deposition and other processes after the array chip and the circuit chip are bonded to the control circuit structure in the circuit chip is a problem to be solved at present.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a method for manufacturing a three-dimensional memory capable of shunting and dissipating static electricity, which solves the above-mentioned problems.
To achieve the above and other related objects, the present invention provides a method for manufacturing a three-dimensional memory, including:
providing an array chip having a first substrate with a front side and a back side which are oppositely arranged, wherein the front side of the first substrate comprises a core array area and an edge connection area, the array chip comprises a storage array structure arranged on the core array area, a first metal contact structure arranged on the edge connection area and a first dummy metal contact structure arranged on the edge connection area and arranged around the first metal contact structure;
providing a circuit chip with a second substrate, wherein the circuit chip comprises a control circuit, an electrostatic elimination circuit, a second metal contact structure and a second virtual metal contact structure, the control circuit, the electrostatic elimination circuit and the second virtual metal contact structure are arranged on the second substrate, the second metal contact structure is electrically connected with the control circuit, and the second virtual metal contact structure is electrically connected with the electrostatic elimination circuit;
bonding the array chip and the circuit chip so that the first metal contact structure is electrically connected with the second metal contact structure and the first virtual metal contact structure is electrically connected with the second virtual metal contact structure;
and etching the back surface of the first substrate, and forming a contact hole on the first substrate, wherein the contact hole exposes the first metal contact structure.
Optionally, the step of forming the array chip comprises:
forming a stacked structure on the core array region, and forming a first dielectric structure on the edge connection region;
forming the memory array structure in the stacked structure, and forming a plurality of the first metal contact structures and a plurality of the first dummy metal contact structures in the first dielectric structure.
Optionally, a plurality of the first dummy metal contact structures are disposed around at least one of the first metal contact structures, or one of the first dummy metal contact structures is disposed around one of the first metal contact structures.
Optionally, the step of forming the circuit chip includes:
forming a plurality of mutually independent control circuits and static elimination circuits in the second substrate;
forming a second dielectric structure on the second substrate, and forming the second metal contact structure and the second dummy metal contact structure in the second dielectric structure.
Optionally, the plurality of second dummy metal contact structures correspond to and are electrically connected to the plurality of static elimination circuits one to one.
Optionally, the step of bonding the array chip and the circuit chip includes:
forming a first pad electrically connected to the first metal contact structure and a second pad electrically connected to the first dummy metal contact structure on a surface of the first dielectric structure;
forming a third pad electrically connected to the second metal contact structure and a fourth pad electrically connected to the second dummy metal contact structure on a surface of the second dielectric structure;
bonding the first bonding pad and the third bonding pad to realize the electrical connection of the first metal contact structure and the second metal contact structure; and bonding the second bonding pad and the fourth bonding pad to realize the electrical connection of the first virtual metal contact structure and the second virtual metal contact structure.
Optionally, the first metal contact structure is electrically connected to the first pad through a first interconnect layer, the first dummy metal contact structure is electrically connected to the second pad through a first dummy interconnect layer, the second metal contact structure is electrically connected to the third pad through a second interconnect layer, and the second dummy metal contact structure is electrically connected to the fourth pad through a second dummy interconnect layer.
Optionally, the method for manufacturing the three-dimensional memory further includes:
and filling the contact hole to form a third metal contact structure, wherein the third metal contact structure is electrically connected with the first metal contact structure.
Further, to achieve the above and other related objects, the present invention provides a three-dimensional memory including:
the array chip comprises a storage array structure, a first metal contact structure and a first virtual metal contact structure arranged around the first metal contact structure;
the circuit chip comprises a control circuit, a second metal contact structure electrically connected with the control circuit, a static elimination circuit and a second virtual metal contact structure electrically connected with the static elimination circuit;
the array chip and the circuit chip are bonded together, the first metal contact structure is electrically connected with the second metal contact structure, and the first virtual metal contact structure is electrically connected with the second virtual metal contact structure.
Optionally, in the array chip, a plurality of the first dummy metal contact structures are arranged around at least one of the first metal contact structures, or one first dummy metal contact structure is arranged around one first metal contact structure; in the circuit chip, the second dummy metal contact structures correspond to and are electrically connected with the static elimination circuits one by one.
Optionally, the static elimination circuit includes at least: a PN junction.
Optionally, a first pad and a second pad are formed on the surface of the array chip, the first pad is electrically connected to the first metal contact structure, and the second pad is electrically connected to the first dummy metal contact structure; a third bonding pad and a fourth bonding pad are formed on the surface of the circuit chip, the third bonding pad is electrically connected with the second metal contact structure, and the fourth bonding pad is electrically connected with the second virtual metal contact structure; the first bonding pad is bonded with the third bonding pad, so that the first metal contact structure is electrically connected with the second metal contact structure; the second pad is in bonding connection with the fourth pad such that the first dummy metal contact structure is electrically connected with the second dummy metal contact structure.
Optionally, the substrate of the array chip includes a front surface and a back surface that are arranged oppositely, the storage array structure, the first metal contact structure and the first dummy metal contact structure are arranged on the front surface of the substrate of the array chip, a third metal contact structure penetrating through the substrate of the array chip is further formed on the array chip, and the third metal contact structure electrically leads the first metal contact structure out from the back surface of the substrate of the array chip.
As described above, the method for manufacturing a three-dimensional memory according to the present invention has the following advantages:
in the array chip, a first virtual metal contact structure is arranged around the first metal contact structure, and when the first substrate is etched subsequently to lead out the first metal contact structure, the first virtual metal contact structure can share and drain static electricity brought by etching ions, so that the static electricity accumulated on the first metal contact structure is effectively reduced; simultaneously, still be provided with the static elimination circuit of being connected with first virtual metal contact structure electricity in the circuit chip, can eliminate or save the static of first virtual metal contact structure upper accumulation, further strengthened the sharing drainage effect of first virtual metal contact structure to static for from the static greatly reduced in the control circuit on the first metal contact structure reaches the circuit chip, can effectively avoid great static to the damage of control circuit's structure, the structural stability and the reliability of control circuit have been strengthened.
Drawings
Fig. 1 is a process flow diagram of a method for manufacturing a three-dimensional memory.
FIG. 2 is a schematic diagram showing a method for fabricating a three-dimensional memory according to the present invention.
Fig. 3-19 are process flow diagrams illustrating a method of fabricating a three-dimensional memory according to the present invention.
Description of the reference numerals
1-array chip, 2-circuit chip, 3-bonding connection of array chip 1 and circuit chip 2, 10-first substrate, 10 a-front side of first substrate 10, 10B-back side of first substrate 10, 101, 103-edge connection region of front side 10a of first substrate 10, 102-core array region of front side 10a of first substrate 10, 1A-stack structure, 1B-first dielectric structure, 11-first metal contact structure, 12-first dummy metal contact structure, 20-second substrate, 20 a-front side of second substrate 20, 20B-back side of second substrate 20, 2B-second dielectric structure, 21-control circuit, 22-isolation structure, 23-second metal contact structure, 24-static elimination circuit, 25-second dummy metal contact structure, 31-first pad, 32-second pad, 33-third pad, 34-fourth pad, 3B-third dielectric structure, 41-third metal contact structure.
Detailed Description
The inventor researches and discovers that in the current manufacturing process of the three-dimensional memory, as shown in fig. 1, after an array chip (i.e., a memory array wafer) 1 and a circuit chip (i.e., a CMOS circuit wafer) 2 are bonded through a bonding connection part 3, it is further required to etch a substrate 10 of the array chip 1 and lead a first metal contact structure 11 out from the back of the array chip 1, which requires plasma etching, ions of the plasma etching carry static electricity (a "+" sign in fig. 1), and the static electricity is conducted to a control circuit 21 on the circuit chip 2 along the first metal contact structure 11, a first bonding pad 31, a third bonding pad 33 and a second metal contact structure 23, and a large amount of static electricity is accumulated to cause structural damage of the control circuit 21, which leads to a decrease in reliability of the three-dimensional memory.
Therefore, the invention provides a manufacturing method of a three-dimensional memory based on a design principle of electrostatic guiding shunting and storing or eliminating, which comprises the following steps: in the array chip 1, when the first metal contact structure 11 is formed, a first dummy metal contact structure arranged around the first metal contact structure 11 is simultaneously formed around the first metal contact structure 11, so that static electricity is drained and shared; in addition, in the circuit chip 2, a static elimination circuit independent from the control circuit 21 is additionally provided, and the static elimination circuit is electrically connected to the first dummy metal contact structure, so that static electricity accumulated on the first dummy metal contact structure is eliminated or stored by the static elimination circuit, and the sharing and drainage effect of the static electricity is enhanced.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2 to fig. 19. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. The structures, proportions, sizes, and other dimensions shown in the drawings and described in the specification are for understanding and reading the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined in the claims, and are not essential to the art, and any structural modifications, changes in proportions, or adjustments in size, which do not affect the efficacy and attainment of the same are intended to fall within the scope of the present disclosure. Meanwhile, the terms such as "upper", "lower", "middle", "front", "back" and "first" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship may be made without substantial technical changes and modifications.
As shown in fig. 2, the present invention provides a method for manufacturing a three-dimensional memory, which comprises the steps of:
s1, providing an array chip 1 having a first substrate 10, the first substrate 10 having a front side 10a and a back side 10b oppositely disposed, the front side 10a of the first substrate 10 including a core array region 102 and edge connection regions 101, 103, the array chip 1 including a memory array structure disposed on the core array region 102, a first metal contact structure 11 disposed on the edge connection regions 101, 103, and a first dummy metal contact structure 12 disposed on the edge connection regions 101, 103 and disposed around the first metal contact structure 11;
s2, providing the circuit chip 2 having the second substrate 20, the circuit chip 2 including a control circuit 21 disposed on the second substrate 20, a static elimination circuit 24, a second metal contact structure 23 electrically connected to the control circuit 21, and a second dummy metal contact structure 25 electrically connected to the static elimination circuit 24;
s3, bonding the array chip 1 and the circuit chip 2, such that the first metal contact structure 11 is electrically connected to the second metal contact structure 23, and the first dummy metal contact structure 12 is electrically connected to the second dummy metal contact structure 25;
s4, etching the back surface 10b of the first substrate 10, and forming a contact hole on the first substrate 10, wherein the contact hole exposes the first metal contact structure 11.
In detail, as shown in fig. 3, in step S1, the array chip 1 is provided with a first substrate 10, a stacked structure 1A and a first dielectric structure 1B are formed on the substrate 10, a memory array structure (not shown) is formed in the stacked structure 1A, and a first metal contact structure 11 and a first dummy metal contact structure 12 disposed around the first metal contact structure 11 are formed in the first dielectric structure 1B.
In more detail, as shown in fig. 4, the first substrate 10 has a front surface 10a and a back surface 10b disposed oppositely, and the front surface 10a of the first substrate 10 includes a core array region 102 and edge connection regions 101, 103, the core array region 102 being located between the edge connection region 101 and the edge connection region 103; the first substrate 10 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI substrate, a GOI substrate, or the like, and an appropriate semiconductor material may be selected according to actual requirements of devices, which is not limited herein.
In detail, as shown in fig. 5 to 7, the step S1 of forming the array chip 1 having the first substrate 10 further includes:
s11, as shown in fig. 5, forming a stacked structure 1A on the core array region 102 and a first dielectric structure 1B on the edge connection regions 101, 103;
s12, as shown in fig. 6-7, a memory array structure (not shown) is formed in the stacked structure 1A, and a plurality of first metal contact structures 11 and a plurality of first dummy metal contact structures 12 are formed in the first dielectric structure 1B.
The stacking structure 1A comprises a plurality of pseudo gate layers and dielectric layers which are alternately stacked, wherein one dielectric layer and an adjacent pseudo gate layer form a composite layer, and the number of layers of the composite layer in the stacking structure can be flexibly designed; the detailed process steps for forming the memory array sub-structure in the stacked structure 1A, such as forming the conductive channel structure, and forming the gate layer instead, can refer to the prior art, and are not described herein again.
In more detail, as shown in fig. 7, taking the first dielectric structure 1B on the edge connection region 103 as an example for description, a plurality of first metal contact structures 11 and a plurality of first dummy metal contact structures 12 are formed in the first dielectric structure 1B, and the first dummy metal contact structures 12 are disposed around the first metal contact structures 11; alternatively, a plurality of first dummy metal contact structures 12 are disposed around at least one first metal contact structure 11, or one first dummy metal contact structure 12 is disposed around one first metal contact structure 11, and exactly one first dummy metal contact structure 12 is disposed between two adjacent first metal contact structures 11 as shown in fig. 6.
Wherein the ellipses in fig. 3, 6-7 indicate corresponding extensions of the first metal contact structures 11 and the first dummy metal contact structures 12, which are not fully shown; optionally, a first interconnection layer (not shown) is further formed on the top of the first metal contact structure 11 for external electrical connection, and a first dummy interconnection layer (not shown) is further formed on the top of the first dummy metal contact structure 12 for external electrical connection.
It will be appreciated that there are many possible situations regarding the positional relationship between the first metal contact structure 11 and the first dummy metal contact structure 12: it is possible that one first dummy metal contact structure 12 is correspondingly disposed around one first metal contact structure 11, and it is also possible that a plurality of first dummy metal contact structures 12 are disposed around one or more first metal contact structures 11 (for example, in the case that the first metal contact structures 11 are relatively dense, there is no space between two first metal contact structures 11 to dispose the first dummy metal contact structures 12), as long as the shunting function is performed.
Finally, the array chip 1 shown in FIG. 6 is obtained, and only the portion on the edge connection region 103 is shown in FIG. 7.
In detail, as shown in fig. 8, in step S2, a circuit chip 2 having a second substrate 20 is provided, a second dielectric structure 2B is formed on the second substrate 20, the circuit chip 2 includes a control circuit 21, an isolation structure 22 and an electrostatic elimination circuit 24 disposed in the second substrate 20, and the circuit chip 2 further includes a second metal contact structure 23 disposed on the second dielectric structure 2B and electrically connected to the control circuit 21 and a second dummy metal contact structure 25 electrically connected to the electrostatic elimination circuit 24.
In more detail, as shown in fig. 9, the second substrate 20 has a front surface 20a and a back surface 20b oppositely disposed; the second substrate 20 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI substrate, a GOI substrate, or the like, and an appropriate semiconductor material may be selected according to actual requirements of the device, which is not limited herein.
In detail, as shown in fig. 10 to 14, the step S2 of forming the circuit chip 2 having the second substrate 20 further includes:
s21, as shown in fig. 10 to 13, forming a plurality of independent control circuits 21 and static elimination circuits 24 in the second substrate 20;
s22, as shown in fig. 11-14, a second dielectric structure 2B is formed on the second substrate 20, and a second metal contact structure 23 and a second dummy metal contact structure 25 are formed in the second dielectric structure 2B. In more detail, in step S21, as shown in fig. 10 to 13, a plurality of mutually independent control circuits 21, isolation structures 22 and static electricity elimination circuits 24 are formed in the second substrate 20, the control circuits 21 may be logic device structures such as switches, and the isolation structures (or guard rings) 22 are provided around the control circuits 21 to physically isolate and protect the control circuits 21; as shown in fig. 10-14, the static elimination circuit 24 may be a simplest PN junction to store static electricity capture, and it is understood that the static elimination circuit 24 may also be other storage circuits or ground discharge circuits, which are not described herein again.
Wherein, the plurality of static elimination circuits 24 correspond to the plurality of second dummy metal contact structures 12 one by one, for example, at least one static elimination circuit 24 is disposed between two adjacent control circuits 21 and corresponds to the first dummy metal contact structure 12 on the first substrate 10; alternatively, as shown in fig. 10 to 13, exactly one static elimination circuit 24 is provided between two adjacent control circuits 21.
In detail, in step S22, as shown in fig. 11 to 14, the second metal contact structure 23 and the second dummy metal contact structure 25 are formed in the second dielectric structure 2B, the second metal contact structure 23 is electrically connected to the control circuit 21, and the second dummy metal contact structure 25 is electrically connected to the static electricity elimination circuit 24. Finally, the circuit chip 2 shown in fig. 12 is obtained, and only a portion corresponding to the edge connection region 103 is shown in fig. 13.
Wherein the ellipses in fig. 8, 12-13 represent corresponding extensions of the second metal contact structures 23 and the second dummy metal contact structures 25, which are not fully shown; optionally, a second interconnect layer (not shown) is further formed on the top of the second metal contact structure 23 for external electrical connection, and a second dummy interconnect layer (not shown) is further formed on the top of the second dummy metal contact structure 25 for external electrical connection.
In detail, as shown in fig. 15 to 17, the step S3 of bonding the array chip 1 and the circuit chip 2 further includes:
s31, as shown in fig. 15, forming a first pad 31 electrically connected to the first metal contact structure 11 and a second pad 32 electrically connected to the first dummy metal contact structure 12 on the surface of the first dielectric structure 1B;
s32, as shown in fig. 16, forming a third pad 33 electrically connected to the second metal contact structure 23 and a fourth pad 34 electrically connected to the second dummy metal contact structure 25 on the surface of the second dielectric structure 2B;
s33, as shown in fig. 17, bonding the first pad 31 and the third pad 33 to electrically connect the first metal contact structure 11 and the second metal contact structure 23; the second pad 32 and the fourth pad 34 are bonded to electrically connect the first dummy metal contact structure 12 and the second dummy metal contact structure 25.
The first metal contact structure 11 is electrically connected to the first pad 31 through a first interconnection layer (not shown), the first dummy metal contact structure 12 is electrically connected to the second pad 32 through a first dummy interconnection layer (not shown), the second metal contact structure 23 is electrically connected to the third pad 33 through a second interconnection layer (not shown), and the second dummy metal contact structure 25 is electrically connected to the fourth pad 34 through a second dummy interconnection layer (not shown).
It is understood that the first interconnect layer and the second interconnect layer respectively comprise one or more metal layers to electrically connect the first metal contact structure 11 and the second metal contact structure 23; likewise, the first and second dummy interconnection layers include one or more metal layers, respectively, to electrically connect the first and second dummy metal contact structures 12 and 25.
Alternatively, as shown in fig. 18 to 19, after the array chip 1 and the circuit chip 2 are bonded, the method for manufacturing the three-dimensional memory further includes the steps of:
s4, forming a third dielectric structure 3B on the back surface 10B of the first substrate 10, etching the third dielectric structure 3B and the first substrate 10 from the back surface 10B of the first substrate 10, and forming a contact hole on the third dielectric structure 3B and the first substrate 10, wherein the contact hole exposes the first metal contact structure 11;
s5, filling the contact holes to form a third metal contact structure 41 (i.e. a pad), where the third metal contact structure 41 is electrically connected to the first metal contact structure 11, and the third metal contact structure 41 is mainly used for electrically connecting the three-dimensional memory to the outside.
In detail, in step S4, since the array chip 1 is formed with a plurality of first dummy metal contact structures 12 disposed around the first metal contact structure 11, the static electricity caused by etching can be distributed; in addition, in the circuit chip 2, the static elimination circuit 24 electrically connected with the first dummy metal contact structure 12 is additionally arranged, static electricity accumulated on the first dummy metal contact structure 12 can be captured or eliminated through the static elimination circuit 24, and the sharing and drainage effect on the static electricity is further strengthened, so that the quantity of the static electricity conducted to the control circuit 21 through the first metal contact structure 11 and the second metal contact structure 23 can be greatly reduced, and the damage of the static electricity caused by etching to the control circuit 21 can be effectively avoided.
Finally, a three-dimensional memory as shown in fig. 19 is obtained, which includes:
an array chip 1 including a memory array structure (not shown), a first metal contact structure 11, and a first dummy metal contact structure 12 disposed around the first metal contact structure 11;
a circuit chip 2 including a control circuit 21, a second metal contact structure 23 electrically connected to the control circuit 21, a static elimination circuit 24, and a second dummy metal contact structure 25 electrically connected to the static elimination circuit 24;
the array chip 1 and the circuit chip 2 are bonded together, the first metal contact structure 11 is electrically connected with the second metal contact structure 23, and the first dummy metal contact structure 12 is electrically connected with the second dummy metal contact structure 25.
Alternatively, in the array chip 1, a plurality of first dummy metal contact structures 12 are disposed around at least one first metal contact structure 11, or one first dummy metal contact structure 12 is disposed around one first metal contact structure 11, not limited to the illustration in fig. 19; in the circuit chip 2, the plurality of second dummy metal contact structures 25 correspond to and are electrically connected to the plurality of static elimination circuits 24 one by one, and are not limited to those shown in fig. 19. The static elimination circuit 24 at least includes: a PN junction.
In detail, as shown in fig. 19, a first pad 31 and a second pad 32 are formed on the surface of the array chip 1, the first pad 31 is electrically connected to the first metal contact structure 11, and the second pad 32 is electrically connected to the first dummy metal contact structure 12; a third bonding pad 33 and a fourth bonding pad 34 are formed on the surface of the circuit chip 2, the third bonding pad 33 is electrically connected with the second metal contact structure 23, and the fourth bonding pad 34 is electrically connected with the second dummy metal contact structure 25; the first pad 31 is bonded to the third pad 33 such that the first metal contact structure 11 is electrically connected to the second metal contact structure 23; the second pad 32 is bonded to the fourth pad 34 such that the first dummy metal contact structure 12 is electrically connected to the second dummy metal contact structure 25.
Optionally, the base (i.e., the first substrate 10) of the array chip 1 includes a front surface 10a and a back surface 10b that are oppositely disposed, the memory array structure, the first metal contact structure 11, and the first dummy metal contact structure 12 are disposed on the front surface 10a of the base of the array chip 1, a third metal contact structure 41 penetrating through the base of the array chip 1 is further formed on the array chip 1, and the third metal contact structure 41 electrically leads the first metal contact structure 11 from the direction of the back surface 10b of the base of the array chip 1.
In summary, in the manufacturing method of the three-dimensional memory and the three-dimensional memory provided by the invention, because the plurality of first dummy metal contact structures arranged around the first metal contact structure are formed in the array chip, static electricity caused by etching can be distributed and drained; in addition, in the circuit chip, add the electrostatic elimination circuit who is connected with first virtual metal contact structure electricity, in order to catch or eliminate the static that first virtual metal contact structure is gone up through electrostatic elimination circuit and accumulate, further strengthened the sharing drainage effect to static, thereby can greatly reduced through the static volume in first metal contact structure and the conduction of second metal contact structure to the control circuit on the circuit chip, the damage of static that can effectively avoid the sculpture to cause to control circuit, control circuit's structural stability and reliability on the circuit chip have been strengthened.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (13)
1. A method of fabricating a three-dimensional memory, comprising:
providing an array chip having a first substrate with a front side and a back side which are oppositely arranged, wherein the front side of the first substrate comprises a core array area and an edge connection area, the array chip comprises a storage array structure arranged on the core array area, a first metal contact structure arranged on the edge connection area and a first dummy metal contact structure arranged on the edge connection area and arranged around the first metal contact structure;
providing a circuit chip with a second substrate, wherein the circuit chip comprises a control circuit, an electrostatic elimination circuit, a second metal contact structure and a second virtual metal contact structure, the control circuit, the electrostatic elimination circuit and the second virtual metal contact structure are arranged on the second substrate, the second metal contact structure is electrically connected with the control circuit, and the second virtual metal contact structure is electrically connected with the electrostatic elimination circuit;
bonding the array chip and the circuit chip so that the first metal contact structure is electrically connected with the second metal contact structure and the first virtual metal contact structure is electrically connected with the second virtual metal contact structure;
and etching the back surface of the first substrate, and forming a contact hole on the first substrate, wherein the contact hole exposes the first metal contact structure.
2. The method of claim 1, wherein the step of forming the array chip comprises:
forming a stacked structure on the core array region, and forming a first dielectric structure on the edge connection region;
forming the memory array structure in the stacked structure, and forming a plurality of the first metal contact structures and a plurality of the first dummy metal contact structures in the first dielectric structure.
3. The method of claim 2, wherein a plurality of the first dummy metal contact structures are disposed around at least one of the first metal contact structures, or one of the first dummy metal contact structures is disposed around one of the first metal contact structures.
4. The method of claim 2, wherein the step of forming the circuit chip comprises:
forming a plurality of mutually independent control circuits and static elimination circuits in the second substrate;
forming a second dielectric structure on the second substrate, and forming the second metal contact structure and the second dummy metal contact structure in the second dielectric structure.
5. The method of claim 4, wherein the second dummy metal contact structures are in one-to-one correspondence with and electrically connected to the static elimination circuits.
6. The method of claim 5, wherein the step of bonding the array chip and the circuit chip comprises:
forming a first pad electrically connected to the first metal contact structure and a second pad electrically connected to the first dummy metal contact structure on a surface of the first dielectric structure;
forming a third pad electrically connected to the second metal contact structure and a fourth pad electrically connected to the second dummy metal contact structure on a surface of the second dielectric structure;
bonding the first bonding pad and the third bonding pad to realize the electrical connection of the first metal contact structure and the second metal contact structure; and bonding the second bonding pad and the fourth bonding pad to realize the electrical connection of the first virtual metal contact structure and the second virtual metal contact structure.
7. The method of claim 6, wherein the first metal contact structure is electrically connected to the first pad through a first interconnect layer, the first dummy metal contact structure is electrically connected to the second pad through a first dummy interconnect layer, the second metal contact structure is electrically connected to the third pad through a second interconnect layer, and the second dummy metal contact structure is electrically connected to the fourth pad through a second dummy interconnect layer.
8. The method of manufacturing a three-dimensional memory according to claim 1 or 7, further comprising:
and filling the contact hole to form a third metal contact structure, wherein the third metal contact structure is electrically connected with the first metal contact structure.
9. A three-dimensional memory, comprising:
the array chip comprises a storage array structure, a first metal contact structure and a first virtual metal contact structure arranged around the first metal contact structure;
the circuit chip comprises a control circuit, a second metal contact structure electrically connected with the control circuit, a static elimination circuit and a second virtual metal contact structure electrically connected with the static elimination circuit;
the array chip and the circuit chip are bonded together, the first metal contact structure is electrically connected with the second metal contact structure, and the first virtual metal contact structure is electrically connected with the second virtual metal contact structure.
10. The three-dimensional memory according to claim 9, wherein a plurality of the first dummy metal contact structures are disposed around at least one of the first metal contact structures or one of the first dummy metal contact structures is disposed around one of the first metal contact structures in the array chip; in the circuit chip, the second dummy metal contact structures correspond to and are electrically connected with the static elimination circuits one by one.
11. The three-dimensional memory according to claim 10, wherein the static elimination circuit comprises at least: a PN junction.
12. The three-dimensional memory according to claim 9 or 11, wherein a first pad and a second pad are formed on the surface of the array chip, the first pad is electrically connected with the first metal contact structure, and the second pad is electrically connected with the first dummy metal contact structure; a third bonding pad and a fourth bonding pad are formed on the surface of the circuit chip, the third bonding pad is electrically connected with the second metal contact structure, and the fourth bonding pad is electrically connected with the second virtual metal contact structure; the first bonding pad is bonded with the third bonding pad, so that the first metal contact structure is electrically connected with the second metal contact structure; the second pad is in bonding connection with the fourth pad such that the first dummy metal contact structure is electrically connected with the second dummy metal contact structure.
13. The three-dimensional memory according to claim 12, wherein the substrate of the array chip comprises a front surface and a back surface which are oppositely arranged, the memory array structure, the first metal contact structure and the first dummy metal contact structure are arranged on the front surface of the substrate of the array chip, and a third metal contact structure penetrating through the substrate of the array chip is further formed on the array chip and electrically leads the first metal contact structure out of the back surface of the substrate of the array chip.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10181442B1 (en) * | 2017-11-30 | 2019-01-15 | Sandisk Technologies Llc | Three-dimensional memory device having L-shaped word lines and methods of making the same |
| CN109817626A (en) * | 2017-11-21 | 2019-05-28 | 三星电子株式会社 | Three-dimensional semiconductor memory device |
| CN110808248A (en) * | 2018-08-06 | 2020-02-18 | 三星电子株式会社 | Semiconductor device including through wiring region |
| CN110993606A (en) * | 2018-10-02 | 2020-04-10 | 三星电子株式会社 | Three-dimensional semiconductor memory device |
| CN111788697A (en) * | 2018-03-06 | 2020-10-16 | 株式会社半导体能源研究所 | Semiconductor device with a plurality of semiconductor chips |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109817626A (en) * | 2017-11-21 | 2019-05-28 | 三星电子株式会社 | Three-dimensional semiconductor memory device |
| US10181442B1 (en) * | 2017-11-30 | 2019-01-15 | Sandisk Technologies Llc | Three-dimensional memory device having L-shaped word lines and methods of making the same |
| CN111788697A (en) * | 2018-03-06 | 2020-10-16 | 株式会社半导体能源研究所 | Semiconductor device with a plurality of semiconductor chips |
| CN110808248A (en) * | 2018-08-06 | 2020-02-18 | 三星电子株式会社 | Semiconductor device including through wiring region |
| CN110993606A (en) * | 2018-10-02 | 2020-04-10 | 三星电子株式会社 | Three-dimensional semiconductor memory device |
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