CN118259717A

CN118259717A - Switching control method, system, chip, electronic device and storage medium of system clock

Info

Publication number: CN118259717A
Application number: CN202211686781.5A
Authority: CN
Inventors: 段思邈; 岳虎; 潘宇; 施惠丰; 王勇
Original assignee: Juquan Microelectronics Shanghai Co ltd
Current assignee: Juquan Microelectronics Shanghai Co ltd
Priority date: 2022-12-26
Filing date: 2022-12-26
Publication date: 2024-06-28

Abstract

The application discloses a switching control method, a switching control system, a switching control chip, electronic equipment and a storage medium of a system clock. The switching control method comprises the steps that a clock signal sent by the first clock source meets a first preset condition, a vibration stopping signal is sent out, and the clock source of the system clock is switched from the first clock source to the second clock source; determining a clock signal sent by a second clock source as a current clock signal of a system clock; filtering the current clock signal to obtain a filtered clock signal; the filtered clock signal is determined as a system clock signal of the system clock.

Description

Switching control method, system, chip, electronic device and storage medium of system clock

Technical Field

The technical scheme of the application relates to the technical field of system clock control in integrated circuits, in particular to a switching control method, a switching control system, a switching control chip, an electronic device and a storage medium of a system clock.

Background

In integrated circuit systems such as microcontrollers or system-on-chip SOC (system on a chip), the system clock is the basis for the orderly operation of the integrated circuit system, and the clock signal generated by the system clock is the operation reference of the digital logic of the integrated circuit.

The clock system is a circuit composed of an oscillator, a timing wake-up device, a frequency divider, clock switching and the like. In the running process of the system clock, the possibility of unstable oscillation, stop oscillation and the like exists. Therefore, in order to ensure safe and stable operation of integrated circuit systems such as a system on chip, in a switching control strategy of a system clock, problems possibly occurring in an oscillator (particularly, the oscillation stop of the oscillator) need to be taken into consideration.

In some current system clock switching control strategies, for example, a clock signal interlocking synchronous switching technology can synchronously switch an original clock domain to a target clock domain, so that switching of clock signal sources is completed.

The inventor of the present application found that the current system clock switching control strategy still has the following problems:

1. Because the original clock domain and the target clock domain of the system clock are required to be synchronized in the respective clock domains, if the oscillator is completely stopped, synchronization cannot be realized, and the system clock can stop running;

2. Because of the problem 1, when the oscillator stops vibrating, the clock needs to be switched in an asynchronous mode, but when the oscillator stops vibrating but does not stop vibrating completely (i.e. low-frequency vibration condition), burrs can be introduced in asynchronous switching, and the burr signals can interfere and affect the normal operation of the system clock.

Disclosure of Invention

One aspect of the present application provides a method for controlling switching of a system clock. The switching control method comprises the following steps: determining that the clock signal sent by the first clock source meets a first preset condition, sending out a vibration stopping signal, and switching the clock source of the system clock from the first clock source to the second clock source; determining a clock signal sent by a second clock source as a current clock signal of a system clock; filtering the current clock signal to obtain a filtered clock signal; the filtered clock signal is determined as a system clock signal of the system clock.

According to some embodiments of the present application, determining that the clock signal sent by the first clock source meets the first preset condition may include: detecting the oscillation frequency of a clock signal sent by a first clock source by adopting an analog circuit; if the oscillation frequency is lower than the first threshold value, determining that the clock signal meets a first preset condition;

According to some embodiments of the present application, determining that the clock signal sent by the first clock source meets the first preset condition may further include: and if the frequency counting proportion deviation of the clock signal sent by the first clock source and the reference clock signal is larger than the second threshold value, determining that the clock signal meets the first preset condition.

According to some embodiments of the application, the system clock further includes a third clock source, and after determining the filtered clock signal as the system clock signal of the system clock, the switching control method may further include: the clock source of the system clock is synchronously and interlockingly switched from the second clock source to the third clock source; and determining the clock signal sent out by the third clock source as a system clock signal of the system clock.

Another aspect of the present application provides a system clock switching control system. The system clock comprises a first clock source and a second clock source, and the switching control system comprises: the vibration stopping detection unit is used for sending out a vibration stopping signal under the condition that the clock signal sent out by the first clock source is detected to be in accordance with a first preset condition; the second clock source starting unit is used for starting the second clock source according to the vibration stopping signal; the clock source selection unit is used for switching the clock source of the system clock from the first clock source to the second clock source and determining the clock signal sent by the second clock source as the current clock signal of the system clock; the filtering unit is used for filtering the current clock signal to obtain a filtered clock signal; and the system clock selection unit is used for determining the filtered clock signal as a system clock signal of the system clock.

According to some embodiments of the application, the oscillation stop detection unit detects an oscillation frequency of a clock signal sent by the first clock source by using an analog circuit, and if the oscillation frequency is detected to be lower than a first threshold value, determines that the clock signal meets a first preset condition.

According to some embodiments of the present application, when the oscillation stop detection unit detects that the frequency count ratio deviation of the clock signal sent by the first clock source and the reference clock signal is greater than the second threshold, it is determined that the clock signal meets the first preset condition.

According to some embodiments of the application, the system clock further comprises a third clock source; the system clock selection unit is further used for synchronously and interlockingly switching the clock source of the system clock from the second clock source to the third clock source and determining the clock signal sent by the third clock source as the system clock signal of the system clock.

Yet another aspect of the application provides a chip comprising a switching control system for a system clock as described above.

Still another aspect of the application provides an electronic device comprising a chip as described above.

The application further provides electronic equipment. The electronic device includes one or more processors and a storage device for storing one or more programs. The one or more programs, when executed by the one or more processors, enable the one or more processors to implement the handoff control method as described above.

According to yet another aspect of the present application, there is also provided a non-volatile computer-readable storage medium. The storage medium has stored thereon a computer program enabling the implementation of the handover control method as described above.

According to the technical scheme, after the clock signal sent by the first clock source meets the first preset condition, the vibration stopping signal is sent. And switching the clock source of the system clock from the first clock source to the second clock source according to the sent vibration stopping signal, filtering the clock signal sent by the second clock source to obtain an impurity-free clock signal, and determining the filtered clock signal as the system clock signal of the system clock. According to the technical scheme, when the current clock source of the system clock stops vibrating, the asynchronous switching of the target clock source can be performed, and signal burrs generated in the asynchronous switching can be eliminated.

Drawings

In order to more clearly describe the technical scheme in the embodiment of the present application, the following will describe the embodiment

The drawings that are required for the description are briefly introduced and it is apparent that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 is a schematic flow chart of a handover control method according to an exemplary embodiment of the present application;

Fig. 2 shows another flow diagram of a handover control method according to an example embodiment of the application;

Fig. 3 shows a schematic configuration diagram of a handover control system according to an exemplary embodiment of the present application;

Fig. 4 shows a clock signal comparison diagram of an exemplary embodiment of the present application.

Reference numerals illustrate:

A switching control system 1 of a system clock; a first clock source 10; a second clock source 11; a vibration stop detection unit 12; a second clock source start unit 13; a clock source selection unit 14; a filtering unit 15; a system clock selection unit 16; and a third clock source 17.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the disclosed aspects may be practiced without one or more of the specific details, or with other methods, components, materials, apparatus, etc. In these instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail.

Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order.

The following description of the embodiments of the present application will be made more complete and clear by reference to the accompanying drawings of embodiments of the present application, wherein it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The clock system is a core component of an embedded system (such as a chip) and is a digital reference of operation logic of a kernel and peripheral components in the embedded system. The kernel completes the actions of instruction, state conversion and the like under the driving of the clock signal sent by the system clock, and the peripheral component completes the actions of data transmission, A/D conversion, timer counting and the like under the driving of the clock signal sent by the system clock.

Clock sources for clock systems include RC oscillators, external crystal oscillators, and the like. The inventor of the present application has found that the external oscillator may suffer from problems such as non-start-up, unstable oscillation, stop of oscillation, etc. at any time due to its own characteristics. And after the external oscillator is abnormal, the output frequency is uncertain, and the external oscillator can stop vibrating completely or vibrate at a low frequency.

Therefore, in the switching control strategy of the system clock, the inventor considers that the problem of complete oscillation stop of the external oscillator in the switching of the system clock is considered, and also considers that the problem of signal burr is generated in the asynchronous switching when the external oscillator is not completely stopped in the oscillation stop process.

Based on this, an aspect of the present application provides a switching control method of a system clock, where the switching control method may perform asynchronous switching of a target clock source when it is determined that a current clock source of the system clock is stopped, and may eliminate signal glitches generated by switching the clock when a failure clock source is not completely stopped.

The technical scheme of the application will be described in detail below with reference to the accompanying drawings.

Fig. 1 shows a flow diagram of a handover control method according to an exemplary embodiment of the present application. As shown in fig. 1, the handover control method includes steps S100 to S400. According to an example embodiment, the switching control method is performed by a switching control device of a system clock.

According to an example embodiment, a system clock according to the present application includes a first clock source and a second clock source. The first clock source and the second clock source provide clock signals for the system clock to drive the system clock to normally and orderly run.

Optionally, in a state of normal operation of the system clock, the first clock source provides a clock signal to the system clock, and the system clock uses the clock signal provided by the first clock source as the system clock signal. And in the state of normal operation of the system clock, the second clock source is in a closed state so as to save the energy consumption of the system clock.

For example, the first clock source is an external Oscillator (OSC) and the second clock source is an RC oscillator. The frequency output by the RC oscillator is fixed, the RC system clock formed by the RC oscillator is a reliable internal RC clock, the RC clock cannot stop vibrating, and the frequency of the RC oscillator can be any preset frequency.

In the following description, the technical solution of the present application is described by taking the first clock source as an external oscillator and the second clock source as an RC oscillator as an example, but it is obvious that the present application is not limited thereto.

In step S100, the switching control device determines that the clock signal sent by the first clock source meets the first preset condition, and sends out a vibration stopping signal to switch the clock source of the system clock from the first clock source to the second clock source.

For example, the switching control device performs stop-vibration detection on a clock signal emitted from the external oscillator. When the switching control device judges that the clock signal sent by the external oscillator meets a first preset condition, the external oscillator is determined to stop vibrating, and a vibration stopping signal is sent out. The first preset condition is preset by a user according to actual conditions, and the first preset condition is a threshold value condition for representing the vibration stopping of the external oscillator.

Alternatively, the switching control means may issue the vibration stop signal at an arbitrary phase.

The switching control device switches the clock source of the system clock to the RC oscillator according to the vibration stopping signal. Namely, under the condition that the external oscillator stops vibrating, the RC oscillating circuit where the RC oscillator is forcedly started.

According to an exemplary embodiment, the output frequency of the RC oscillator may be any preset frequency, and in the on state, the RC oscillator may not stop vibrating, which is a reliable internal clock source.

After the RC oscillator is forcibly turned on, the switching control device takes the clock signal sent by the RC oscillator as the clock signal of the system clock and performs subsequent signal processing.

In step S200, the switching control device determines the clock signal sent by the second clock source as the current clock signal of the system clock.

For example, after the switching control device switches the clock source of the system clock from the external oscillator to the internal RC oscillator, the switching control device selects the clock signal sent by the RC oscillator as the current clock signal, so that the internal clock source in the system can be switched in time when the external oscillator has a problem.

In step S300, the switching control device performs filtering processing on the current clock signal to obtain a filtered clock signal.

For example, the switching control device performs filtering processing on the clock signal of the system clock to filter out other high-frequency frequencies of the frequency bands of the non-RC oscillator and the external oscillator.

Because the external oscillator and the RC oscillator are switched asynchronously, signal burrs can be generated in the system clock in the switching process, so that the stability of the system clock is affected. The switching control device can filter clock signals of an unwanted frequency band by filtering the clock signals of the system clock, so that the situation of signal burrs can be avoided.

In step S400, the switching control device determines the filtered clock signal as the current clock signal of the system clock.

For example, the switching control device determines the filtered clock signal as the current clock signal of the system clock after switching, and drives the normal operation of the system clock with the clock signal as a reference.

Through the above example embodiments, according to the technical solution of the present application, after determining that the clock signal sent by the first clock source meets the first preset condition, the oscillation stop signal is sent. And switching the clock source of the system clock from the first clock source to the second clock source according to the sent vibration stopping signal, filtering the clock signal sent by the second clock source to obtain an impurity-free clock signal, and determining the filtered clock signal as the system clock signal of the system clock. According to the technical scheme, when the current clock source of the system clock stops vibrating, the asynchronous switching of the target clock source can be performed, and signal burrs generated when the current clock source does not stop vibrating completely can be eliminated.

Optionally, in step S100, the switching control device may determine whether the clock signal sent by the first clock source meets the first preset condition by setting the analog circuit.

According to an example embodiment, the switching control means detects an operating frequency of the clock signal issued by the first clock source. When the switching control device judges that the operation frequency is lower than the first threshold value, the clock signal is determined to accord with a first preset condition.

For example, the first preset condition is that when the running frequency of the clock signal sent by the first clock source is lower than the first threshold value, which is preset by the user according to the actual situation, the switching control device judges that the first clock source stops vibrating. For example, the first threshold may be 10Khz to 20Khz, but the present application is not limited thereto.

Optionally, in step S100, the switching control device may perform the determination of whether the clock signal sent by the first clock source meets the first preset condition by setting the digital circuit.

According to an example embodiment, if the switching control device determines that the frequency count ratio deviation of the clock signal sent by the first clock source and the reference clock signal is greater than the second threshold, the switching control device determines that the clock signal meets the first preset condition.

For example, the first preset condition is that when the frequency count proportion deviation of the clock signal sent by the first clock source and the reference clock signal preset by the user according to the actual situation is greater than the second threshold, the switching control device judges that the first clock source is out of vibration.

The reference clock signal and the initial frequency of the first clock source are the same, and the switching control device detects the deviation of the frequency count of the clock signal sent by the first clock source and the reference clock signal under the same frequency. When the frequency count deviation is greater than the second threshold, for example, the second threshold may be 50% (the application is not limited thereto), the switching control device determines that the first clock source has stopped vibrating.

Through the above example embodiments, the present application may detect the state of the first clock source in time by performing the vibration-stopping detection of the first clock source by setting an analog circuit or a digital circuit. The detection method ensures that other software configuration is not required to be arranged between the external oscillator and the RC oscillator, and ensures that the oscillators are switched more conveniently and rapidly.

Optionally, the system clock further comprises a third clock source. Fig. 2 shows another flow chart of a handover control method according to an exemplary embodiment of the present application, and the handover control method further includes steps S500-S600 as shown in fig. 2.

Steps S100-S400 in fig. 2 are described in detail above, and the present application will not be repeated.

In step S500, the switching control device switches the clock source of the system clock from the second clock source to the third clock source in a synchronous interlocking manner, and determines the clock signal sent by the third clock source as the current clock signal of the system clock.

In step S600, the switching control device determines the clock signal sent from the third clock source as the system clock signal of the system clock.

According to an example embodiment, the third clock source may be a PLL clock source.

For example, an RC clock formed by an RC oscillator has the characteristics of stable frequency and no stop oscillation, but the oscillation frequency of the RC clock may not necessarily be the operation frequency required by the system clock, which may make the operation of the system clock slow.

For example, after the external oscillator stops vibrating and the system clock is switched to the RC clock, the system clock can be switched back to the external oscillator clock after the external oscillator is recovered to be normal; or after the system clock is switched to the RC clock, the system clock can be switched to other non-vibration-stopping clock sources (such as a PLL clock source) again, so as to ensure that the current system clock has higher vibration frequency.

Therefore, when the external oscillator fails to stop vibrating or does not stop vibrating completely, the switching control device switches the clock source to an internal reliable RC clock source through asynchronous switching. After the system clock is stable, the user can decide to switch the RC clock source to other clock sources, such as a third clock source (such as a PLL clock source), so that the reliable and stable operation of the system clock can be ensured.

Another aspect of the present application provides a switching control system for a system clock, where the switching control system may perform asynchronous switching of a target clock source when a current clock source of the system clock is stopped, and may eliminate signal glitches generated by performing asynchronous switching when a failure clock source is not completely stopped.

Fig. 3 shows a schematic configuration diagram of a handover control system according to an exemplary embodiment of the present application. As shown in fig. 3, the switching control system 1 for system clock includes at least a first clock source 10, a second clock source 11, a stop-oscillation detecting unit 12, a second clock source starting unit 13, a clock source selecting unit 14, a filtering unit 15, and a system clock selecting unit 16.

According to an example embodiment, the first clock source 10 and the second clock source 11 provide clock signals for the system clock to drive the system clock to operate normally in order.

In a state of normal operation of the system clock, the first clock source 10 provides a clock signal for the system clock, and the system clock uses the clock signal provided by the first clock source 10 as a current clock signal. And in the state of normal operation of the system clock, the second clock source is in a closed state so as to save the energy consumption of the system clock.

For example, the first clock source 10 is an external Oscillator (OSC), and the second clock source 11 is an RC oscillator. Because the frequency output by the RC oscillator is fixed, the RC system clock formed by the RC oscillator is a reliable internal RC clock, the RC clock cannot stop vibrating, and the frequency of the RC oscillator can be any preset frequency as the reliable system clock.

In the following description, the first clock source 10 is taken as an external oscillator, and the second clock source 11 is taken as an RC oscillator as an example to describe the technical solution of the present application, but it is obvious that the present application is not limited thereto.

According to an exemplary embodiment, the vibration stopping detection unit 12 is configured to issue a vibration stopping signal if it is detected that the clock signal issued by the first clock source meets a first preset condition.

For example, the oscillation stop detection unit 12 performs oscillation stop detection on a clock signal emitted from an external oscillator. When the oscillation stop detection unit 12 determines that the clock signal sent by the external oscillator meets the first preset condition, it determines that the external oscillator has stopped oscillating, and sends out an oscillation stop signal. The first preset condition is preset by a user according to actual conditions, and the first preset condition is a threshold value condition for representing the vibration stopping of the external oscillator.

Alternatively, the vibration stop detection unit 12 may issue the vibration stop signal at an arbitrary phase.

According to an exemplary embodiment, the second clock source start unit 13 is configured to start the second clock source according to the vibration stop signal.

For example, the second clock source start unit 13 switches the clock source of the system clock to the RC oscillator according to the stop oscillation signal. Namely, under the condition that the external oscillator stops vibrating, the RC oscillating circuit where the RC oscillator is forcedly started.

According to an exemplary embodiment, the clock source selection unit 14 is configured to switch the clock source of the system clock from the first clock source 10 to the second clock source 12, and determine the clock signal sent by the second clock source 12 as the current clock signal of the system clock.

For example, when the external oscillator is in a state of normal operation, the clock source selection unit 14 determines the external oscillator as the current clock source of the system clock, and determines the clock signal (OSC CLK shown in fig. 3) emitted by the external oscillator as the current clock signal of the system clock.

When the oscillation stop detection unit 12 detects that the external oscillator stops oscillating, the clock source selection unit 14 receives the oscillation stop signal from the oscillation stop detection unit 12, and the clock source selection unit 14 determines the RC oscillator as the current clock source of the system clock and determines the clock signal (RC CLK as shown in fig. 3) sent by the RC oscillator as the current clock signal of the system clock, so that the internal clock source in the system can be switched in time when the external oscillator has a problem.

According to an exemplary embodiment, the filtering unit 15 is configured to perform a filtering process on the current clock signal to obtain a filtered clock signal.

For example, the clock source selecting unit 14 performs filtering processing on the clock signal of the system clock, filtering out other high-frequency frequencies than the RC oscillator and the external oscillator frequency band, to obtain a filtered clock signal (LF CLK as shown in fig. 3).

Because the external oscillator and the RC oscillator are switched asynchronously, signal burrs can be generated in the system clock in the switching process, so that the stability of the system clock is affected. The filtering unit 15 can filter the clock signal of the unwanted frequency band by performing filtering processing on the clock signal of the system clock, so that the situation of signal glitch can be avoided.

According to an exemplary embodiment, the system clock selection unit 16 is configured to determine the filtered clock signal as a system clock signal of the system clock.

For example, the system clock selection unit 16 determines the filtered clock signal as a system clock signal (SYS CLK shown in fig. 3) of the system clock after switching, and drives normal operation of the system clock with the clock signal as a reference.

Alternatively, the vibration stopping detection unit 12 may perform the determination of whether the clock signal sent by the first clock source meets the first preset condition by setting the analog circuit.

According to an exemplary embodiment, the de-ringing detection unit 12 detects the operating frequency of the clock signal emitted by the first clock source. When the vibration stopping detection unit 12 determines that the operation frequency is lower than the first threshold value, it is determined that the clock signal meets the first preset condition.

For example, the first preset condition is that the oscillation stop detection unit 12 determines that the oscillation stop of the first clock source occurs when the operation frequency of the clock signal sent by the first clock source 10 is lower than the first threshold value, which is preset by the user according to the actual situation. For example, the first threshold may be 10Khz to 20Khz, but the present application is not limited thereto.

Optionally, the vibration stopping detection unit 12 may further perform a determination on whether the clock signal sent by the first clock source meets the first preset condition by setting the digital circuit.

According to an exemplary embodiment, when the oscillation stop detection unit 12 determines that the frequency count ratio deviation of the clock signal sent by the first clock source 10 and the reference clock signal is greater than the second threshold, the oscillation stop detection unit 12 determines that the clock signal meets the first preset condition.

For example, the first preset condition is that when the frequency count ratio deviation of the clock signal sent by the first clock source 10 and the reference clock signal, preset by the user according to the actual situation, is greater than the second threshold, it can be determined that the first clock source 10 is out of vibration.

The reference clock signal is identical to the initial frequency of the first clock source 10, and the stop-ringing detection unit 12 detects a deviation of the frequency count of the clock signal emitted from the first clock source at the same frequency from the reference clock signal. When the frequency count deviation is greater than the second threshold, for example, the second threshold may be 50% (the present application is not limited thereto), the oscillation stop detection unit 12 may determine that the oscillation stop of the first clock source 10 has occurred.

Optionally, as shown in fig. 3, the system clock further comprises a third clock source 17. According to an example embodiment, the third clock source 17 may be a PLL clock source.

The system clock selection unit 16 is further configured to switch the clock source of the system clock from the second clock source 11 to the third clock source 17 in a synchronous interlocking manner, and determine a clock signal (PLL CLK shown in fig. 3) sent out by the third clock source 17 as a system clock signal of the system clock.

Therefore, when a failure such as a stop or an incomplete stop of the external oscillator occurs, the clock source selecting unit 14 switches the clock source to an internally reliable RC clock source by asynchronous switching. After the system clock is stable, the user can decide to switch the RC clock source to another clock source, such as the third clock source 17 (e.g., PLL clock source), so as to ensure reliable and stable operation of the system clock.

Fig. 4 shows a clock signal comparison diagram of an exemplary embodiment of the present application. Fig. 4 shows a comparison of the clock signals after switching of the system clock is completed in the event of a stop oscillation of a first clock source 10.

As shown in fig. 4, when the first clock source 10 is stopped at a certain time, the switching control system 1 switches the clock source of the system clock from the first clock source 10 to the second clock source 11, and as can be seen from fig. 4, the clock signal (RC CLK) sent out by the second clock source 11 is a stable and reliable clock signal. And after the clock signals are switched within a certain time, the current clock signal (SW CLK), the filtered clock signal (LF CLK) and the system clock signal (SYS CLK) are recovered to be normal after being temporarily abnormal, so that the safe and stable operation of the system clock is ensured.

Finally, it should be noted that the foregoing description is only a preferred embodiment of the present application, and is not intended to limit the application, but rather the detailed description of the present application is given with reference to the foregoing embodiment, and those skilled in the art can modify the technical solution of each embodiment or make equivalent substitutions for some technical features thereof. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. The switching control method of the system clock is characterized in that the system clock comprises a first clock source and a second clock source, and the switching control method comprises the following steps:

Determining that the clock signal sent by the first clock source meets a first preset condition, sending a vibration stopping signal, and switching the clock source of the system clock from the first clock source to the second clock source;

determining a clock signal sent by the second clock source as a current clock signal of the system clock;

Filtering the current clock signal to obtain a filtered clock signal;

And determining the filtered clock signal as a system clock signal of the system clock.

2. The method of claim 1, wherein determining that the clock signal sent by the first clock source meets a first preset condition comprises:

detecting the oscillation frequency of a clock signal sent by the first clock source by adopting an analog circuit;

If the oscillation frequency is lower than a first threshold value, determining that the clock signal meets the first preset condition;

Or alternatively

And if the frequency counting proportion deviation of the clock signal sent by the first clock source and the reference clock signal is larger than a second threshold value, determining that the clock signal meets the first preset condition.

3. The switching control method according to claim 2, wherein the system clock further includes a third clock source, and after determining the filtered clock signal as the system clock signal of the system clock, the switching control method further includes:

synchronously interlocking and switching the clock source of the system clock from the second clock source to the third clock source;

And determining the clock signal sent out by the third clock source as the system clock signal of the system clock.

4. A switching control system of a system clock, wherein the system clock includes a first clock source and a second clock source, the switching control system comprising:

The vibration stopping detection unit is used for sending out a vibration stopping signal under the condition that the clock signal sent out by the first clock source is detected to be in accordance with a first preset condition;

The second clock source starting unit is used for starting the second clock source according to the vibration stopping signal;

a clock source selecting unit, configured to switch a clock source of the system clock from the first clock source to the second clock source, and determine a clock signal sent by the second clock source as a current clock signal of the system clock;

The filtering unit is used for carrying out filtering processing on the current clock signal to obtain a filtered clock signal;

and the system clock selection unit is used for determining the filtered clock signal as a system clock signal of the system clock.

5. The switching control system according to claim 4, wherein the oscillation stop detection unit detects an oscillation frequency of a clock signal emitted from the first clock source using an analog circuit, and determines that the clock signal meets the first preset condition if the oscillation frequency is detected to be lower than a first threshold;

Or alternatively

And if the vibration stopping detection unit detects that the frequency counting proportion deviation of the clock signal sent by the first clock source and the reference clock signal is larger than a second threshold value, determining that the clock signal accords with the first preset condition.

6. The handover control system of claim 5, wherein the system clock further comprises a third clock source;

The system clock selection unit is further configured to switch a clock source of the system clock from the second clock source to the third clock source in a synchronous interlocking manner, and determine a clock signal sent by the third clock source as a system clock signal of the system clock.

7. A chip comprising a switching control system of a system clock as claimed in any one of claims 4-6.

8. An electronic device comprising the chip of claim 7.

9. An electronic device, comprising:

One or more processors;

A storage means for storing one or more programs;

the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the handover control method of any of claims 1-3.

10. A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that the computer program implements the handover control method according to any one of claims 1-3.