CN1182576C

CN1182576C - Dual-mask CMP technology for eliminating influence of silicon cone phenomenon

Info

Publication number: CN1182576C
Application number: CNB021121478A
Authority: CN
Inventors: 虎金; 金虎; 张征
Original assignee: Shanghai Huahong Group Co Ltd
Current assignee: Shanghai Huahong Group Co Ltd; Shanghai Integrated Circuit Research and Development Center Co Ltd
Priority date: 2002-06-20
Filing date: 2002-06-20
Publication date: 2004-12-29
Anticipated expiration: 2022-06-20
Also published as: CN1396645A

Abstract

The present invention relates to dual hard mask CMP technology for eliminating the influence of a silicon cone phenomenon. The shallow grooved-isolation technology (STI) is new field isolation technology which is generated along with the technology development of a deep submicron integrated circuit. The technique has the characteristics of small dimension, high integration degree and high isolation effect, and simultaneously has the problems of complex process and difficult control. The problems of dishing and erosion in the CMP technology are outstanding. Thereby, the developed field protecting hard mask technology effectively solves the two problems. However, a new problem that a silicon cone phenomenon is generated in the step of etching technology, and the CMP technology can not be corrected effectively because of the protection of hard mask appears. The present invention refers to a method of a hard mask with a false structure, and the correction of the silicon cone phenomenon is raised under the condition without losing the protection effect of the hard mask.

Description

A kind of dual-mask CMP technology of eliminating the silicon cone phenomenon influence

Technical field

The invention belongs to the integrated circuit processing technique field, be specifically related to a kind of dual-mask CMP technology of eliminating the silicon cone phenomenon influence.

Background technology

In semiconductor integrated circuit technique, traditional isolation technology is an autoregistration field oxidation isolation technology, promptly shelters active area with hard mask, with the substrate silicon exposure of place, uses the method for thermal oxidation then, produces the isolated area silica.This method is simple, and productivity is strong, and used mature production technology, shortcoming are to form ' beak ' district on the active area border, becomes the bottleneck that improves the collection degree in the development of deep submicron process as shown in Figure 1.

In the practice, the size of ' beak ' is difficult to reduce to below the 0.1 μ m.Therefore, when the characteristic size of microelectronic technique is reduced to 0.35 μ m, an oxidation technology is replaced by shallow-trench isolation technology (STI) technology gradually.With the protection active area of hard mask, with the place cutting, the method with CVD forms spacer medium in groove again, and the advantage of STI technology is significantly as shown in Figure 2, can the most effective live width of utilizing active area, improve the collection degree.STI technology in conjunction with CMP (Chemical Mechanical Polishing) process can be accomplished high flattening surface, increases the number of plies of road, back wiring.But also there is complex process in STI technology, uppity problem.Common has, and the STI silica crosses grinding (Dishing) and the hard mask of active area is crossed grinding (Erosion).

The STI silica is crossed grinding (Dishing) problem: because the influence of pattern density, CMP technology is in the removal rates difference in different graphic zone, and in the zone less with respect to density, the bigger zone of active area pattern density, grinding speed is lower.Therefore when the lower zone of active area pattern density, the grinding of shallow-trench isolation silica is finished on the active area, but the higher zone of pattern density will have silica residual.In order to remove residual silica, the grinding excessively of CMP (chemico-mechanical polishing) arts demand certain hour.This grinding meeting excessively causes the silica loss in the isolation channel, and groove width increases, and this phenomenon is serious more, makes the silica plane be lower than the active area plane.Phenomenon that Here it is ' Dising '.

The hard mask of STI active area is crossed grinding (Erosion) problem: unaffected for the protection active area in CMP technology, need at active area deposit hard mask layer.Though the slurry that adopts in the technology is selective to hard mask, because the mechanism in the technical process, hard mask layer also has the grinding phenomenon, particularly aforesaid grinding excessively.Need support the whole grinding process of crossing because of hard mask layer, lose comparatively seriously that especially in the low zone of active area pattern density, thereby the active area edge might be ground to some problem of appearance that causes device.Phenomenon that Here it is ' Erosion '.

These two kinds of phenomenons all will cause the silica in the isolation channel to reduce, and cause the active area edge to expose, and gate voltage reduces, and electric leakage increases, and promptly causes so-called ' Hump ' effect.As shown in Figure 3.

Be control ' Dishing ' and ' Erosion ' phenomenon, isolation channel protects hard masking process to be introduced in the shallow-trench isolation technology as Fig. 4.After promptly dielectric material was grown in isolation channel, the deposit hard mask layer kept sipes hard mask partly then, and remainder is removed with the method for etching.In the middle of CMP technology, a hard mask of protection can play the loss that stops dielectric material in the wide isolation channel, and owing to adjusted the density of hard mask pattern, the Erosion phenomenon has been played good inhibition effect like this.

In the technology that isolation channel forms, being divided into for two steps carries out, i.e. the etching of hard mask and the etching of silicon groove.In the technological process as Fig. 4 reflection, promptly in the hard mask process of etching, if hard mask particle residue is arranged at silicon face, will produce silicon in follow-up silicon groove etching process in groove and bore, this is that isotropic character by dry etching causes.After filling isolation dielectric, at groove district dielectric surface, the shape of silicon awl will be retained; and owing to protect the existence of hard mask in field, sipes district; in the CMP technical process, can't carry out effective planarization to the silicon awl, remaining silicon awl will impact follow-up polysilicon wire technology.

Summary of the invention

The objective of the invention is to propose a kind of dual-mask CMP technology of eliminating the silicon cone phenomenon influence.

Protect in the hard masking process in the etching field,, stoped the planarization effect of CMP technology the silicon awl because a hard mask of protection is that monoblock is stayed on the isolated area.Therefore, the structure that rehearses on the hard mask of the present invention's protection on the scene both reticulated structure or island structure with hard mask design, to be reduced in the defect concentration that the film shallow slot is left over behind the CMP of field.The hard mask of this band false knot structure can reduce the possibility of dielectric peak hard masking film of quilt in CMP technology of silicon taper one-tenth, and the hard mask layer of not overslaugh simultaneously is to the protective effect of isolation channel silica.

Revise the mask of photoetching field protection hard mask layer processing step among the present invention, adopt the method legal or photoetching of anti-version, in the sipes structure, form the hard mask pattern of netted or island, as shown in Figure 7 dummy pattern.

Among the present invention, hard mask material can silicon nitride, silicon oxynitride, carborundum material.

Among the present invention, the network interface size 0.4 μ m-1.1 μ m in the hard mask network structure of monoblock, the network interface spacing is 0.4 μ m-1.1 μ m.

Among the present invention, the size of the hard mask island structure of monoblock is 0.1 μ m-0.4 μ m, and distance is 0.4 μ m-1.1 μ m between the island.

The present invention is by the simple change of hard mask layer structural design, can eliminate the influence of silicon cone phenomenon to the shallow grooved-isolation technique technology fairly simplely, improve the rate of finished products of polycrystalline wiring, also eliminated because silicon cone phenomenon and might producing, the influence of phenomenons such as transistor leakage puncture.While is the netted or hard mask pattern density of island comparatively uniformly, helps the control and the effect of flatening process.

Description of drawings

Fig. 1 is an autoregistration field oxidation technology schematic diagram

Fig. 2 is a shallow-trench isolation technology schematic diagram

Fig. 3 a is the physical structure schematic diagram at active area edge

Fig. 3 b is the influence schematic diagram of active area edge parasitic transistor to the transistor electrical property

Fig. 4 is a protection silicon nitride techniqueflow schematic diagram

Fig. 5 is that silicon cone phenomenon influences schematic diagram in technical process

Fig. 6 is that hard mask pattern correction schematic diagram is protected in the sipes midfield

Fig. 7 is the pictorial diagram of reticle at the place, place

Drawing reference numeral: 1 is the isolated area of an oxidation technology; 2 is ' beak ' phenomenon of an oxidation technology; 3 is the field silica of shallow-trench isolation technology; 4 is the parasitic transistor at active area edge; 5 is the gate oxidation silicon of marginal zone; 6 is the field protection silicon nitride in order to the erosion of the dishing that stops the isolation oxidation silicon in the sipes and little active area; 7 is the presentation surface particle; 8 are the silicon awl; the hard mask etching processing step of 9 expressions; 10 expression isolation channel etching technics steps; 11 expression isolation channel dielectric substance deposition process steps; a 12 expressions protection hard mask material deposition process steps; a 13 expressions hard mask etching processing step of protection; 14 expression CMP processing steps; 15 expression hard mask materials are removed processing step.

Embodiment

Implementation step of the present invention is as follows:

1, with dry oxidation deposit resilient coating silica; Low pressure chemical vapor deposition method deposit silicon nitride;

2, lithography step, the hard mask etching of the first step, silicon groove etching.

3, high density plasma CVD method is filled the isolation channel dielectric.

4, secondary silicon nitride deposition.

5, a hard mask lithography of protection, etching adopts to have cancellated mask; Produce last cancellated the hard mask of protection in isolation channel zone.

6, silica CMP technology.

7, the hard mask of wet etching.

Claims

1, a kind of CMP technology of dual-mask shallow-trench isolation; for protecting the dielectric hard mask of not impaired deposit monoblock in technical process in the wide isolation channel; it is characterized in that the hard mask of above-mentioned monoblock produces network structure or island structure by adopting the method legal or photoetching of anti-version, to be reduced in the defect concentration that the film shallow slot is left over behind the CMP of field.

2, CMP technology according to claim 1 is characterized in that described monoblock hard mask material adopts silicon nitride, silicon oxynitride, carborundum.

3, CMP technology according to claim 1 is characterized in that the network interface size in the described network structure is 0.4～1.1 μ m, network interface spacing 0.4～1.1 μ m.