CN118231378A - Test structure, forming method thereof and test method - Google Patents
Test structure, forming method thereof and test method Download PDFInfo
- Publication number
- CN118231378A CN118231378A CN202211630533.9A CN202211630533A CN118231378A CN 118231378 A CN118231378 A CN 118231378A CN 202211630533 A CN202211630533 A CN 202211630533A CN 118231378 A CN118231378 A CN 118231378A
- Authority
- CN
- China
- Prior art keywords
- test
- region
- substrate
- test signal
- signal loading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 470
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000010998 test method Methods 0.000 title claims description 13
- 239000010410 layer Substances 0.000 claims abstract description 238
- 229910052751 metal Inorganic materials 0.000 claims abstract description 150
- 239000002184 metal Substances 0.000 claims abstract description 150
- 239000000758 substrate Substances 0.000 claims abstract description 143
- 239000011229 interlayer Substances 0.000 claims abstract description 67
- 229910021332 silicide Inorganic materials 0.000 claims description 51
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 51
- 230000000903 blocking effect Effects 0.000 claims description 29
- 230000000149 penetrating effect Effects 0.000 claims description 7
- 238000001514 detection method Methods 0.000 abstract description 18
- 230000009286 beneficial effect Effects 0.000 abstract description 7
- 239000000463 material Substances 0.000 description 26
- 230000008569 process Effects 0.000 description 23
- 150000002500 ions Chemical class 0.000 description 16
- 239000004065 semiconductor Substances 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 230000005684 electric field Effects 0.000 description 9
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 8
- 210000000746 body region Anatomy 0.000 description 8
- 229910017052 cobalt Inorganic materials 0.000 description 8
- 239000010941 cobalt Substances 0.000 description 8
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 8
- 229910052707 ruthenium Inorganic materials 0.000 description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 8
- 229910052721 tungsten Inorganic materials 0.000 description 8
- 239000010937 tungsten Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000011112 process operation Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
A test structure, a forming method and a testing method thereof, the structure comprises: the substrate comprises a channel region, a drain region adjacent to the channel region is formed in the substrate on one side of the channel region, a source region adjacent to the channel region is formed in the substrate on the other side of the channel region, the drain region is used as a first test signal loading end, and the source region is used as a second test signal loading end; an interlayer dielectric layer covering the substrate; the metal layer is positioned on the interlayer dielectric layer above the channel region, the projection of the metal layer on the surface of the substrate covers the channel region, and the metal layer is used as a third test signal loading end. The invention adopts a simpler and easy-to-implement test structure, realizes the detection of the CMOS structure in a specific working environment, and is beneficial to the detection of the CMOS structure.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a test structure, a forming method thereof and a testing method thereof.
Background
The integrated circuit BCD (Bipolar-complementary metal oxide semiconductor-double diffused metal oxide semiconductor, bipolarcmos-DMOS) product is a semiconductor chip integrating three devices, bipolar transistor (Bipolar), complementary metal oxide semiconductor field effect transistor (CMOS) and double diffused metal oxide semiconductor field effect transistor (DMOS).
In the design of BCD products, CMOS or DMOS is usually located under the wiring of the Metal layer (Metal), and since DMOS is usually required to withstand high voltages from tens of volts to more than tens of volts, when the semiconductor device is in operation, the Metal layer is correspondingly required to withstand high voltages, the CMOS under the Metal layer is affected by the electric field of the Metal layer, resulting in a change in threshold voltage (Threshold Voltage, VT), so that it is important to detect whether the VT of the CMOS has an effect when a larger current passes through the Metal layer.
Disclosure of Invention
The embodiment of the invention provides a test structure, a forming method thereof and a testing method thereof, which can improve the testing accuracy of the test structure.
To solve the above problems, an embodiment of the present invention provides a test structure, including: the substrate comprises a channel region, a drain region adjacent to the channel region is formed in the substrate on one side of the channel region, a source region adjacent to the channel region is formed in the substrate on the other side of the channel region, the drain region is used as a first test signal loading end, and the source region is used as a second test signal loading end; an interlayer dielectric layer covering the substrate; the metal layer is positioned on the interlayer dielectric layer above the channel region, the projection of the metal layer on the surface of the substrate covers the channel region, and the metal layer is used as a third test signal loading end.
Correspondingly, the embodiment of the invention also provides a method for forming the test structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a channel region, a drain region adjacent to the channel region is formed in the substrate on one side of the channel region, a source region adjacent to the channel region is formed in the substrate on the other side of the channel region, the drain region is used as a first test signal loading end, and the source region is used as a second test signal loading end; forming an interlayer dielectric layer covering the substrate; and forming a metal layer on the interlayer dielectric layer above the channel region, wherein the projection of the metal layer on the surface of the substrate covers the channel region, and the metal layer is used as a third test signal loading end.
Correspondingly, the embodiment of the invention also provides a testing method, which comprises the following steps: providing a test structure; loading corresponding test signals on the first test signal loading end and the second test signal loading end, wherein the test signals are used for enabling the substrate between the drain region and the source region to form a test passage; performing one or more circuit tests, the circuit tests including: loading a corresponding test signal to the third test signal loading end, wherein the test signal loading end is used for loading the test signal to a test channel formed by the substrate between the drain region and the source region; detecting an electrical signal of a test path formed by the substrate between the drain region and the source region; when the electric signal is smaller than a preset electric signal threshold value, increasing the test signal corresponding to the third test signal loading end, and returning to execute the loading of the test signal corresponding to the third test signal loading end until the test signal corresponding to the third test signal loading end reaches the preset test signal threshold value in the current circuit test, so as to complete the circuit test; and when the electric signal is greater than or equal to a preset electric signal threshold value, the circuit test is not passed, and the circuit test is ended.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
In the test structure provided by the embodiment of the invention, the drain region is used as a first test signal loading end, the source region is used as a second test signal loading end, the interlayer dielectric layer covers the substrate, the metal layer is positioned on the interlayer dielectric layer above the channel region, the projection of the metal layer on the surface of the substrate covers the channel region, and the metal layer is used as a third test signal loading end; in the embodiment of the invention, the interlayer dielectric layer is used as the insulating layer, the metal layer, the interlayer dielectric layer and the substrate of the channel region form the metal-oxide-semiconductor device to simulate the CMOS structure, and the metal layer is used as the third test signal loading end, so that the working environment of the CMOS structure can be simulated by applying an electric signal (for example, higher voltage) on the metal layer, and the performance (for example, threshold voltage) of the corresponding CMOS structure under a specific working environment (for example, high-voltage working environment) can be obtained by detecting the test structure, so that a simpler and easy-to-implement test structure can be adopted, the detection of the CMOS structure under the specific working environment can be realized, and the detection of the CMOS structure can be realized advantageously.
In the test method provided by the embodiment of the invention, the interlayer dielectric layer is adopted as the insulating layer, the metal layer, the interlayer dielectric layer and the substrate of the channel region form the metal-oxide-semiconductor device to simulate the CMOS structure, the metal layer is used as the third test signal loading end, the working environment of the CMOS structure can be simulated by applying an electric signal (for example, higher voltage) on the metal layer, the performance (for example, threshold voltage) of the corresponding CMOS structure in a specific working environment (for example, high-voltage working environment) is obtained by detecting the electric signal of the test channel formed by the substrate between the drain region and the source region, when the circuit test fails, the CMOS structure is represented to fail the test, when the circuit test is normally completed, the CMOS structure is represented to pass the test, so that the test structure which is simpler and easy to implement can be adopted to realize the detection of the CMOS structure in the specific working environment, and the detection of the CMOS structure is facilitated.
Drawings
FIG. 1 is a schematic diagram of one embodiment of a test structure according to the present invention;
FIGS. 2-5 are schematic diagrams illustrating steps of a method for forming a test structure according to an embodiment of the present invention;
FIG. 6 is a flow chart of steps of an embodiment of a testing method of the present invention;
FIG. 7 is a schematic diagram of a testing method according to an embodiment of the present invention;
FIG. 8 is a circuit diagram corresponding to an embodiment of the testing method of the present invention.
Detailed Description
As known from the background art, in the BCD product, under the wiring of the Metal, there is usually a CMOS or DMOS condition, and since the DMOS is usually required to bear a high voltage of tens of volts to more than tens of volts, when the semiconductor device is in operation, the Metal is correspondingly required to bear a high voltage, and the CMOS under the Metal is affected by the Metal electric field, which easily causes a change of the threshold voltage (Threshold Voltage, VT), which affects the performance of the BCD product, so that the CMOS affected by the Metal electric field needs to be tested.
In order to solve the technical problem, an embodiment of the present invention provides a test structure, including: the substrate comprises a channel region, a drain region adjacent to the channel region is formed in the substrate on one side of the channel region, a source region adjacent to the channel region is formed in the substrate on the other side of the channel region, the drain region is used as a first test signal loading end, and the source region is used as a second test signal loading end; an interlayer dielectric layer covering the substrate; the metal layer is positioned on the interlayer dielectric layer above the channel region, the projection of the metal layer on the surface of the substrate covers the channel region, and the metal layer is used as a third test signal loading end.
In the test structure provided by the embodiment of the invention, the drain region is used as a first test signal loading end, the source region is used as a second test signal loading end, the interlayer dielectric layer covers the substrate, the metal layer is positioned on the interlayer dielectric layer above the channel region, the projection of the metal layer on the surface of the substrate covers the channel region, and the metal layer is used as a third test signal loading end; in the embodiment of the invention, the interlayer dielectric layer is used as the insulating layer, the metal layer, the interlayer dielectric layer and the substrate of the channel region form the metal-oxide-semiconductor device to simulate the CMOS structure, and the metal layer is used as the third test signal loading end, so that the working environment of the CMOS structure can be simulated by applying an electric signal (for example, higher voltage) on the metal layer, and the performance (for example, threshold voltage) of the corresponding CMOS structure under a specific working environment (for example, high-voltage working environment) can be obtained by detecting the test structure, so that a simpler and easy-to-implement test structure can be adopted, the detection of the CMOS structure under the specific working environment can be realized, and the detection of the CMOS structure can be realized advantageously.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
FIG. 1 is a schematic diagram of a test structure according to an embodiment of the present invention.
The test structure comprises: a substrate 100 including a channel region 100c, a drain region 120 formed in the substrate 100 at one side of the channel region 100c and adjacent to the channel region 100c, a source region 130 formed in the substrate 100 at the other side of the channel region 100c and adjacent to the channel region 100c, the drain region 120 serving as a first test signal loading terminal, and the source region 130 serving as a second test signal loading terminal; an interlayer dielectric layer 200 covering the substrate 100; the metal layer 300 is located on the interlayer dielectric layer 200 above the channel region 100c, the projection of the metal layer 300 on the surface of the substrate 100 covers the channel region 100c, and the metal layer 300 is used as a third test signal loading end.
In this embodiment, the test structure is used to simulate the CMOS structure for testing.
The substrate 100 provides a process operation basis for the test structure formation process. Specifically, the substrate 100 is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.
In this embodiment, the substrate 100 includes a channel region 100c, and the channel region 100c is used as a channel of a test structure to simulate a channel of a CMOS structure.
In this embodiment, the substrate 100 has a well region 110.
Well region 110 is used to provide the N-type or P-type substrate required for the test structure to operate and to achieve electrical isolation between adjacent devices.
Well 110 has well ions therein, which have a conductivity type opposite to the channel conductivity type of the corresponding test structure. That is, the well ions in the well 110 corresponding to the N-type test structure are P-type ions, and the well ions in the well 110 corresponding to the P-type test structure are N-type ions.
In this embodiment, taking the test structure as an N-type test structure as an example, the well ions in the well 110 are P-type ions.
The drain region 120 is configured to act as a drain for the test structure, and the drain region 120 is configured to provide a source of carriers when the test structure is in operation.
The source region 130 is used as a source for the test structure, and the source region 130 is used to provide a source of carriers during operation of the test structure.
In this embodiment, the drain region 120 is used as a first test signal loading end, the source region 130 is used as a second test signal loading end, and the potential from the drain to the source gradually decreases during the operation of the CMOS structure, so in this embodiment, the first test signal loading end is used for loading a positive potential, and the second test signal loading end is used for loading a zero potential.
In this embodiment, the test structure further includes: and a body contact region 140, in the substrate 100 on a side of the source region 130 facing away from the channel region 100c, the body contact region 140 serving as a fourth signal loading terminal.
The body contact region 140 is used as a signal contact for a body region (not shown) to enable electrical connection between the body region and an external circuit or other interconnect structure.
In this embodiment, the sidewalls of the body contact regions 140 are in contact with the sidewalls of the source regions 130.
The doping type of the body contact region 140 is the same as that of the body region, and the doping ion concentration of the body contact region 140 is greater than that of the body region, so that the resistance of the body contact region 140 is smaller.
In this embodiment, the fourth test signal loading end is used to load zero potential, so as to facilitate reducing the probability of leakage of the substrate 100, and further reduce the influence on the test result.
In this embodiment, the test structure further includes: a metal silicide layer 150 is located on top of the substrate 100 of the drain region 120 and the source region 130.
The metal silicide layer 150 is used to improve adhesion between the contact plug corresponding to the source region 130 and the source region 130, and between the contact plug corresponding to the drain region 120 and the drain region 120, and to reduce contact resistance between the contact plug corresponding to the source region 130 and the source region 130, and between the contact plug corresponding to the drain region 120 and the drain region 120.
In this embodiment, the metal silicide layer 150 is also located on top of the body contact region 140.
Correspondingly, the metal silicide layer 150 is further used for improving the adhesion between the contact plug corresponding to the body contact region 140 and the contact lifting region 140 and reducing the contact resistance between the contact plug corresponding to the contact region 140 and the contact lifting region 140.
In this embodiment, the test structure further includes: a silicide blocking layer 160 covers the surface of the substrate 100 of the channel region 100 c.
A silicide blocking layer (SAB) 160 is used as a barrier layer between the metal layer and silicon in a metal silicide process, thereby blocking the growth of a metal silicide (Salicide) layer. Specifically, in the present embodiment, the metal silicide layer 150 needs to be formed on top of the source region 130 and the drain region 120, but the metal silicide layer 150 cannot be formed in the channel region 100c, so that the silicide blocking layer 160 should be covered on the channel region 100c before the metal silicide layer 150 is formed, for blocking the formation of the metal silicide in the channel region 100c when the metal silicide layer 150 is formed.
In this embodiment, the silicide blocking layer 160 is also used to simulate a gate oxide layer in a CMOS structure along with the interlayer dielectric layer 200.
The material of the silicide blocking layer 160 is a dielectric material, so that the silicide blocking layer 160 can isolate the metal layer from the silicon in the metal silicide process. The material of the silicide blocking layer 160 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the material of the silicide blocking layer 160 is silicon oxide.
The interlayer dielectric layer 200 is used to achieve electrical isolation between plugs, and the interlayer dielectric layer 200 is also used to achieve electrical isolation between adjacent devices, in this embodiment, the interlayer dielectric layer 200 is also used to simulate a gate oxide layer in a CMOS structure along with the silicide blocking layer 160.
The material of the interlayer dielectric layer 200 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 200 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may be silicon nitride or silicon oxynitride or other dielectric materials.
In this embodiment, the test structure further includes: a drain region plug 210 located on top of the drain region 120 and penetrating the interlayer dielectric layer 200 on top of the drain region 120.
The drain plug 210 is for electrically connecting with the outside to apply an electrical signal to the drain 120, and accordingly, the drain plug 210 is for acting as a first test signal loading terminal.
In this embodiment, the drain plug 210 is made of tungsten. In other embodiments, the drain plug material may also be cobalt or ruthenium.
In this embodiment, the test structure further includes: source plug 220 is located on top of source 130 and extends through interlayer dielectric layer 200 on top of source 130.
The source plug 220 is used to be electrically connected to the outside so as to apply an electrical signal to the source 130, and accordingly, the source plug 220 is used as a second test signal loading terminal.
In this embodiment, the source plug 220 is made of tungsten. In other embodiments, the source plug material may also be cobalt or ruthenium.
In this embodiment, the test structure further includes: and a body contact plug 230 located on top of the body contact region 140 and penetrating the interlayer dielectric layer 200 on top of the body contact region 140.
The body contact plug 230 is for electrical connection with the outside to apply an electrical signal to the body contact region 140, and accordingly, the body contact plug 230 is for use as a fourth test signal loading terminal.
In this embodiment, the material of the body contact plug 230 is tungsten. In other embodiments, the material of the body contact plug may also be cobalt or ruthenium.
The metal layer 300 is used to simulate the gate layer in a CMOS structure, and the metal layer 300 is also used to apply a higher voltage to the test structure, thereby simulating the situation where the CMOS structure is in a high voltage operating state.
In this embodiment, by using the interlayer dielectric layer 200 as an insulating layer, the metal layer 300, the interlayer dielectric layer 200 and the substrate 100 of the channel region 100c form a metal-oxide-semiconductor device to simulate a CMOS structure, and the metal layer 300 is used as a third test signal loading end, the working environment of the CMOS structure can be simulated by applying an electrical signal (e.g., a higher voltage) on the metal layer 300, and the performance (e.g., a threshold voltage) of the corresponding CMOS structure under a specific working environment (e.g., a high-voltage working environment) can be obtained by detecting the test structure, so that a simpler and easy-to-implement test structure can be used to realize the detection of the CMOS structure under the specific working environment, and the detection of the CMOS structure can be facilitated.
In this embodiment, the metal layer 300 is used as the third test signal loading terminal, and a higher voltage needs to be applied to the metal layer 300 to test whether the threshold Voltage (VT) of the channel region 100c from the drain region 120 to the source region 130 is changed during the test, so that the third test signal loading terminal is used to load a positive potential.
In this embodiment, the projection of the metal layer 300 on the surface of the substrate 100 covers the channel region 100c, and then a voltage is applied to the metal layer 300 during the operation of the test structure, so that the whole channel region 100c can sense the electric field of the metal layer 300, and thus, during the test, the channel region 100c from the drain region 120 to the source region 130 can be tested, which is beneficial to ensuring the smooth performance of the test, and if the channel region 100c from the drain region 120 to the source region 130 is not covered by the projection of the metal layer 300, and a part of the channel region 100c cannot sense the electric field of the metal layer 300, the channel region 100c from the drain region 120 to the source region 130 cannot form a channel, and during the test, when the voltage applied to the metal layer 300 makes the channel region 100c sufficiently conducted, the channel region 100c from the drain region 120 to the source region 130 cannot be detected because of not forming a channel, thereby affecting the test accuracy of the test structure.
Correspondingly, in the present embodiment, along the direction from the drain region 120 to the source region 130, the dimension d1 of the metal layer 300 is greater than the dimension d2 of the metal silicide blocking layer 160, so that the projection of the metal layer 300 on the surface of the substrate 100 covers the channel region 100c, which is beneficial to ensuring that the test of the test structure is performed smoothly.
In this embodiment, the test structure further includes: a metal layer plug 310 is located on top of the metal layer 300 and electrically connected to the metal layer plug 310.
The metal layer plug 310 is used to be electrically connected to the outside so as to apply an electrical signal to the metal layer 300, and accordingly, the metal layer plug 310 is used as a fourth test signal loading terminal.
In this embodiment, the material of the metal layer plug 310 is tungsten. In other embodiments, the material of the metal layer plug may also be cobalt or ruthenium.
In this embodiment, the test structure is disposed on the wafer, the wafer includes the dicing street, the test structure is located in the dicing street, thereby the procedure of forming the device product on the wafer can be adopted, and meanwhile, the test structure is formed on the wafer, the process flow is simplified, the process efficiency is improved, the process cost is saved, meanwhile, the on-line test can be realized, the test time is saved, the process cost is further saved, and the consistency of the test structure and the device product is also guaranteed, in addition, the test structure is located in the dicing street, after the test is performed, the test structure can be cut and removed through the dicing street, and thus the device product on the wafer can be directly obtained.
Correspondingly, the invention further provides a forming method of the test structure. Fig. 2 to 5 are schematic structural views illustrating steps of a method for forming a test structure according to an embodiment of the present invention.
Referring to fig. 2, a substrate 100 is provided, including a channel region 100c, a drain region 120 adjacent to the channel region 100c is formed in the substrate 100 on one side of the channel region 100c, a source region 130 adjacent to the channel region 100c is formed in the substrate 100 on the other side of the channel region 100c, the drain region 120 serves as a first test signal loading terminal, and the source region 130 serves as a second test signal loading terminal.
In this embodiment, the test structure is used to simulate the CMOS structure for testing.
The substrate 100 provides a process operation basis for the test structure formation process. Specifically, the substrate 100 is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.
In this embodiment, the substrate 100 includes a channel region 100c, and the channel region 100c is used as a channel of a test structure to simulate a channel of a CMOS structure.
In this embodiment, the substrate 100 has a well region 110.
Well region 110 is used to provide the N-type or P-type substrate required for the test structure to operate and to achieve electrical isolation between adjacent devices.
Well 110 has well ions therein, which have a conductivity type opposite to the channel conductivity type of the corresponding test structure. That is, the well ions in the well 110 corresponding to the N-type test structure are P-type ions, and the well ions in the well 110 corresponding to the P-type test structure are N-type ions.
In this embodiment, taking the test structure as an N-type test structure as an example, the well ions in the well 110 are P-type ions.
The drain region 120 is configured to act as a drain for the test structure, and the drain region 120 is configured to provide a source of carriers when the test structure is in operation.
The source region 130 is used as a source for the test structure, and the source region 130 is used to provide a source of carriers during operation of the test structure.
In this embodiment, the drain region 120 is used as a first test signal loading end, the source region 130 is used as a second test signal loading end, and the potential from the drain to the source gradually decreases during the operation of the CMOS structure, so in this embodiment, the first test signal loading end is used for loading a positive potential, and the second test signal loading end is used for loading a zero potential.
In the step of providing the substrate 100 in this embodiment, the body contact region 130 is formed in the substrate 100 on the side of the source region 130 facing away from the channel region 100c, and the body contact region 140 is used as the fourth signal loading end.
The body contact region 140 is used as a signal contact for a body region (not shown) to enable electrical connection between the body region and an external circuit or other interconnect structure.
In this embodiment, the sidewalls of the body contact regions 140 are in contact with the sidewalls of the source regions 130.
The doping type of the body contact region 140 is the same as that of the body region, and the doping ion concentration of the body contact region 140 is greater than that of the body region, so that the resistance of the body contact region 140 is smaller.
In this embodiment, the fourth test signal loading end is used to load zero potential, so as to facilitate reducing the probability of leakage of the substrate 100, and further reduce the influence on the test result.
Referring to fig. 3, before the interlayer dielectric layer covering the substrate 100 is subsequently formed, the forming method further includes: a metal silicide blocking layer 160 is formed to cover the surface of the substrate 100 of the channel region 100 c.
A silicide blocking layer (SAB) 160 is used as a barrier layer between the metal layer and silicon in a metal silicide process, thereby blocking the growth of a metal silicide (Salicide) layer. Specifically, in this embodiment, a metal silicide layer needs to be formed on top of the source region 130 and the drain region 120, but a metal silicide layer cannot be formed in the channel region 100c, so that the channel region 100c should be covered with the silicide blocking layer 160 before the metal silicide layer is subsequently formed, for blocking the formation of the metal silicide in the channel region 100c when the metal silicide layer is subsequently formed.
In this embodiment, the silicide blocking layer 160 is also used to simulate a gate oxide layer in a CMOS structure together with an interlayer dielectric layer formed later.
The material of the silicide blocking layer 160 is a dielectric material, so that the silicide blocking layer 160 can isolate the metal layer from the silicon in the metal silicide process. The material of the silicide blocking layer 160 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the material of the silicide blocking layer 160 is silicon oxide.
With continued reference to fig. 3, after forming the metal silicide blocking layer 160, a metal silicide layer 150 is formed on top of the substrate 100 of the drain region 120 and the source region 130.
The metal silicide layer 150 serves to improve adhesion between the contact plug corresponding to the source region 130 and the source region 130, and between the contact plug corresponding to the drain region 120 and the drain region 120, and to reduce contact resistance between the contact plug corresponding to the source region 130 and the source region 130, and between the contact plug corresponding to the drain region 120 and the drain region 120.
In this embodiment, the metal silicide layer 150 is also formed on top of the body contact region 140.
Correspondingly, the metal silicide layer 150 is further used for improving the adhesion between the contact plug corresponding to the body contact region 140 and the contact lifting region 140 and reducing the contact resistance between the contact plug corresponding to the contact region 140 and the contact lifting region 140.
Referring to fig. 4, an interlayer dielectric layer 200 is formed to cover the substrate 100.
The interlayer dielectric layer 200 is used to achieve electrical isolation between plugs, and the interlayer dielectric layer 200 is also used to achieve electrical isolation between adjacent devices, in this embodiment, the interlayer dielectric layer 200 is also used to simulate a gate oxide layer in a CMOS structure along with the silicide blocking layer 160.
The material of the interlayer dielectric layer 200 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 200 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may be silicon nitride or silicon oxynitride or other dielectric materials.
With continued reference to fig. 4, prior to forming a metal layer on the interlayer dielectric layer 200 above the channel region 100c, the forming method further includes: a drain plug 210 penetrating the interlayer dielectric layer 200 on top of the drain region 120 is formed on top of the drain region 120.
The drain plug 210 is for electrically connecting with the outside to apply an electrical signal to the drain 120, and accordingly, the drain plug 210 is for acting as a first test signal loading terminal.
In this embodiment, the drain plug 210 is made of tungsten. In other embodiments, the drain plug material may also be cobalt or ruthenium.
In this embodiment, a source plug 220 is formed on top of the source 130, penetrating the interlayer dielectric layer 200 on top of the source 130.
The source plug 220 is used to be electrically connected to the outside so as to apply an electrical signal to the source 130, and accordingly, the source plug 220 is used as a second test signal loading terminal.
In this embodiment, the source plug 220 is made of tungsten. In other embodiments, the source plug material may also be cobalt or ruthenium.
In this embodiment, before the metal layer is formed on the interlayer dielectric layer 200 above the channel region 100c, the forming method further includes: a body contact plug 230 is formed on top of the body contact region 140 through the interlayer dielectric layer 200 on top of the body contact region 140.
The body contact plug 230 is for electrical connection with the outside to apply an electrical signal to the body contact region 140, and accordingly, the body contact plug 230 is for use as a fourth test signal loading terminal.
In this embodiment, the material of the body contact plug 230 is tungsten. In other embodiments, the material of the body contact plug may also be cobalt or ruthenium.
In this embodiment, the drain region plug 210, the source region plug 220 and the body contact plug 230 are formed in the same step, which is beneficial to saving the process cost and improving the process efficiency.
Referring to fig. 5, a metal layer 300 is formed on the interlayer dielectric layer 200 above the channel region 100c, a projection of the metal layer 300 on the surface of the substrate 100 covers the channel region 100c, and the metal layer 300 is used as a third test signal loading terminal.
The metal layer 300 is used to simulate the gate layer in a CMOS structure, and the metal layer 300 is also used to apply a higher voltage to the test structure, thereby simulating the situation where the CMOS structure is in a high voltage operating state.
In this embodiment, by using the interlayer dielectric layer 200 as an insulating layer, the metal layer 300, the interlayer dielectric layer 200 and the substrate 100 of the channel region 100c form a metal-oxide-semiconductor device to simulate a CMOS structure, and the metal layer 300 is used as a third test signal loading end, the working environment of the CMOS structure can be simulated by applying an electrical signal (e.g., a higher voltage) on the metal layer 300, and the performance (e.g., a threshold voltage) of the corresponding CMOS structure under a specific working environment (e.g., a high-voltage working environment) can be obtained by detecting the test structure, so that a simpler and easy-to-implement test structure can be used to realize the detection of the CMOS structure under the specific working environment, and the detection of the CMOS structure can be facilitated.
In this embodiment, the metal layer 300 is used as the third test signal loading terminal, and a higher voltage needs to be applied to the metal layer 300 to test whether the threshold Voltage (VT) of the channel region 100c from the drain region 120 to the source region 130 is changed during the test, so that the third test signal loading terminal is used to load a positive potential.
In this embodiment, the projection of the metal layer 300 on the surface of the substrate 100 covers the channel region 100c, and then a voltage is applied to the metal layer 300 during the operation of the test structure, so that the whole channel region 100c can sense the electric field of the metal layer 300, and thus, during the test, the channel region 100c from the drain region 120 to the source region 130 can be tested, which is beneficial to ensuring the smooth performance of the test, and if the channel region 100c from the drain region 120 to the source region 130 is not covered by the projection of the metal layer 300, and a part of the channel region 100c cannot sense the electric field of the metal layer 300, the channel region 100c from the drain region 120 to the source region 130 cannot form a channel, and during the test, when the voltage applied to the metal layer 300 makes the channel region 100c sufficiently conducted, the channel region 100c from the drain region 120 to the source region 130 cannot be detected because of not forming a channel, thereby affecting the test accuracy of the test structure.
Correspondingly, in the present embodiment, along the direction from the drain region 120 to the source region 130, the dimension d1 of the metal layer 300 is greater than the dimension d2 of the metal silicide blocking layer 160, so that the projection of the metal layer 300 on the surface of the substrate 100 covers the channel region 100c, which is beneficial to ensuring that the test of the test structure is performed smoothly.
In this embodiment, after forming the metal layer 300, the forming method further includes: a metal layer plug 310 electrically connected to the metal layer plug 310 is formed on top of the metal layer 300.
The metal layer plug 310 is used to be electrically connected to the outside so as to apply an electrical signal to the metal layer 300, and accordingly, the metal layer plug 310 is used as a fourth test signal loading terminal.
In this embodiment, the material of the metal layer plug 310 is tungsten. In other embodiments, the material of the metal layer plug may also be cobalt or ruthenium.
In this embodiment, the test structure is formed on the wafer, the wafer includes the dicing street, the test structure is located in the dicing street, so that a process of forming a device product on the wafer can be adopted, and meanwhile, the test structure is formed on the wafer, so that a process flow is simplified, a process efficiency is improved, a process cost is saved, meanwhile, an on-line test can be realized, a test time is saved, a process cost is further saved, and further, the consistency of the test structure and the device product is guaranteed.
Correspondingly, the invention further provides a testing method. Fig. 6 is a flowchart of an embodiment of the testing method of the present invention, fig. 7 is a schematic structural diagram corresponding to an embodiment of the testing method of the present invention, and fig. 8 is a circuit diagram corresponding to an embodiment of the testing method of the present invention.
In this embodiment, the test method includes the following basic steps:
Step S1: a test structure of the foregoing inventive embodiment is provided.
Step S2: and loading corresponding test signals on the first test signal loading end and the second test signal loading end, wherein the test signals are used for enabling the substrate between the drain region and the source region to form a test passage.
Step S3: performing one or more circuit tests, the circuit tests including: loading a corresponding test signal to the third test signal loading end, wherein the test signal loading end is used for loading the test signal to a test channel formed by the substrate between the drain region and the source region; detecting an electrical signal of a test path formed by the substrate between the drain region and the source region; when the electric signal is smaller than a preset electric signal threshold value, increasing the test signal corresponding to the third test signal loading end, and returning to execute the loading of the test signal corresponding to the third test signal loading end until the test signal corresponding to the third test signal loading end reaches the preset test signal threshold value in the current circuit test, so as to complete the circuit test; and when the electric signal is greater than or equal to a preset electric signal threshold value, the circuit test is not passed, and the circuit test is ended.
In the test method provided by the embodiment of the invention, the interlayer dielectric layer is adopted as the insulating layer, the metal layer, the interlayer dielectric layer and the substrate of the channel region form the metal-oxide-semiconductor device to simulate the CMOS structure, the metal layer is used as the third test signal loading end, the working environment of the CMOS structure can be simulated by applying an electric signal (for example, higher voltage) on the metal layer, the performance (for example, threshold voltage) of the corresponding CMOS structure in a specific working environment (for example, high-voltage working environment) is obtained by detecting the electric signal of the test channel formed by the substrate between the drain region and the source region, when the circuit test fails, the CMOS structure is represented to fail the test, when the circuit test is normally completed, the CMOS structure is represented to pass the test, so that the test structure which is simpler and easy to implement can be adopted to realize the detection of the CMOS structure in the specific working environment, and the detection of the CMOS structure is facilitated.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, the following detailed description of the embodiments of the present invention refers to fig. 7 and 8.
Referring to fig. 7, step S1 is performed: a test structure of the foregoing inventive embodiment is provided.
In this embodiment, in the step of providing the test structure, the test structure further includes: and a body contact region 140, in the substrate 100 on a side of the source region 130 facing away from the channel region 100c, the body contact region 140 serving as a fourth signal loading terminal.
The detailed description of the foregoing embodiments of the invention refers to the description of the test structure, and is not repeated herein.
Referring to fig. 7 and 8, step S2 is performed: corresponding test signals are loaded to the first test signal loading terminal D and the second test signal loading terminal S for forming a test path of the substrate 100 between the drain region 120 and the source region 130.
In this embodiment, by loading corresponding test signals to the first test signal loading end D and the second test signal loading end S, the substrate 100 between the drain region 120 and the source region 130 forms a test path, so as to detect whether the test path between the drain region 120 and the source region 130 is turned on in a subsequent test process.
In this embodiment, by using the interlayer dielectric layer 200 as an insulating layer, the metal layer 300, the interlayer dielectric layer 200, and the substrate 100 of the channel region 100c constitute a metal-oxide-semiconductor device to simulate a CMOS structure, and the metal layer 300 is used as a third test signal loading end, then the working environment of the CMOS structure can be simulated by applying an electrical signal (e.g., a higher voltage) on the metal layer 300, and by detecting the electrical signal of the test path formed by the substrate 100 between the drain region 120 and the source region 130, the performance (e.g., threshold voltage) of the corresponding CMOS structure in a specific working environment (e.g., a high-voltage working environment) is obtained, when the circuit test fails, the CMOS structure is characterized as failing the test, and when the circuit test is completed normally, the CMOS structure is characterized as passing the test, so that a simpler and easy-to-implement test structure can be used to realize the detection of the CMOS structure in the specific working environment, which is beneficial to realize the detection of the CMOS structure.
In this embodiment, in the step of loading the corresponding test signals on the first test signal loading terminal D and the second test signal loading terminal S, the positive potential is loaded on the first test signal loading terminal D, and the zero potential is loaded on the second test signal loading terminal S.
In this embodiment, during the operation of the CMOS structure, the potential from the drain to the source gradually decreases, so in this embodiment, the first test signal loading terminal D is used to load a positive potential, and the second test signal loading terminal S is used to load a zero potential, so as to apply the operating bias Vd to the substrate 100 between the drain region 120 and the source region 130 forming the test path.
In this embodiment, in the step of loading the positive potential on the first test signal loading terminal D, the positive potential on the first test signal loading terminal D should not be too large or too small. If the positive potential loaded on the first test signal loading end D is too large, the interlayer dielectric layer 200 is easy to leak electricity to influence the test result; if the positive potential loaded on the first test signal loading end D is too small, the current of the test path is easy to be too low, and the preset electric signal threshold value is difficult to be reached, so that the accuracy of the test result is affected. For this, in the step of loading the first test signal loading terminal D with a positive potential, the positive potential loaded on the first test signal loading terminal D is 0.1V to 5V.
In this embodiment, before performing one or more subsequent circuit tests, the test method further includes: and loading a corresponding test signal on the fourth signal loading end B.
In the step of loading the corresponding test signal to the fourth signal loading terminal B, the zero potential is loaded to the fourth signal loading terminal B, so that the probability of leakage of the substrate 100 is reduced, and the influence on the test result is reduced.
Step S3 is executed: performing one or more circuit tests, the circuit tests including: loading a corresponding test signal to the third test signal loading terminal G for loading the test signal to the test path formed by the substrate 100 between the drain region 120 and the source region 130; detecting an electrical signal of a test path formed by the substrate 100 between the drain region 120 and the source region 130; when the electric signal is smaller than a preset electric signal threshold value, increasing the test signal corresponding to the third test signal loading end G, and returning to execute the loading of the test signal corresponding to the third test signal loading end G until the test signal corresponding to the third test signal loading end G reaches the preset test signal threshold value in the current circuit test, so as to complete the circuit test; and when the electric signal is greater than or equal to a preset electric signal threshold value, the circuit test is not passed, and the circuit test is ended.
In this embodiment, a smaller working bias Vd is loaded to the drain region 120, and the source region 130 is grounded, so that the substrate 100 between the drain region 120 and the source region 130 forms a test path, and a corresponding test signal is loaded to the third test signal loading end G, so that the test path formed by the substrate 100 between the drain region 120 and the source region 130 can induce an electric field caused by the test signal of the metal layer 300.
In the present embodiment, in the step of loading the third test signal loading terminal G with the corresponding test signal, a positive potential is applied to the third test signal loading terminal G, and during the test, a higher voltage needs to be applied to the metal layer 300 to test whether the threshold Voltage (VT) of the channel region 100c from the drain region 120 to the source region 130 is changed, so the third test signal loading terminal G is used to load the positive potential, that is, the voltage Vg is applied to the third test signal loading terminal G.
It should be noted that, when the device is changed from depletion to inversion, a state is to be experienced in which the electron concentration of the Si surface is equal to the hole concentration, and the device is in a critical on state, the gate voltage of the device is defined as a threshold Voltage (VT), in this embodiment, when the threshold Voltage (VT) is the critical on state of the test path formed by the substrate 100 between the drain region 120 and the source region 130, the voltage Vg applied by the metal layer 300 is the threshold Voltage (VT), and during the test, that is, when the test path formed by the substrate 100 between the drain region 120 and the source region 130 appears above the preset test signal threshold, that is, it is determined that the test path formed by the substrate 100 between the drain region 120 and the source region 130 is on, and then the voltage Vg applied by the metal layer 300 is the threshold Voltage (VT).
Specifically, the present embodiment determines whether the threshold Voltage (VT) of the substrate 100 between the drain region 120 and the source region 130 is changed by testing whether the voltage value applied by the metal layer 300 does not reach the preset threshold voltage when the test path formed by the substrate 100 between the drain region 120 and the source region 130 is turned on.
In this embodiment, after loading the corresponding test signal to the third test signal loading end G, an electrical signal of a test path formed by the substrate 100 between the drain region 120 and the source region 130 is detected, specifically, a current Id of the test path formed by the substrate 100 between the drain region 120 and the source region 130 is detected, and when the current Id of the test path reaches a preset current threshold, it is characterized that the substrate 100 between the drain region 120 and the source region 130 is turned on.
It should be noted that, in the embodiment, the preset electrical signal threshold is not too large or too small in the step of performing one or more circuit tests. If the preset electrical signal threshold is too large, the detection condition of the test path is too loose, which easily results in that the test path is actually turned on when the current of the test path does not reach the preset electrical signal threshold, that is, the threshold Voltage (VT) of the substrate 100 between the drain region 120 and the source region 130 is actually changed, but the test process does not detect the threshold voltage, thereby affecting the accuracy of the test; if the preset electrical signal threshold is too small, the detection condition of the test path is too harsh, which easily causes that when the current of the test path reaches the preset electrical signal threshold, the threshold Voltage (VT) of the substrate 100 between the drain region 120 and the source region 130 cannot be actually represented to change, so that misjudgment that the circuit test fails occurs, unnecessary waste is caused, and the test result is affected. For this reason, in the step of detecting the electric signal of the test path constituted by the substrate 100 between the drain region 120 and the source region 130 in this embodiment, the preset electric signal threshold value is 10E-6A.
Specifically, in this embodiment, when the electrical signal of the test path is smaller than the preset electrical signal threshold, the test signal corresponding to the third test signal loading end G is increased, and the test signal corresponding to the third test signal loading end G is returned to be executed until the test signal corresponding to the third test signal loading end G reaches the preset test signal threshold in the current circuit test, so as to complete the circuit test.
That is, in this embodiment, when the current Id of the test path is smaller than the preset current threshold, it is indicated that the substrate 100 between the drain region 120 and the source region 130 is not turned on yet, the voltage Vg applied by the third test signal loading terminal G is increased, and the test path for detecting the substrate 100 between the drain region 120 and the source region 130 is returned, and the cycle is repeated until the test signal corresponding to the third test signal loading terminal G reaches the preset test signal threshold in the present circuit test, which is indicated that the voltage Vg applied by the third test signal loading terminal G has reached the actual operating voltage requirement, and the substrate 100 between the drain region 120 and the source region 130 is still not turned on, the threshold Voltage (VT) of the substrate 100 between the drain region 120 and the source region 130 is unchanged, accordingly, the threshold Voltage (VT) of the CMOS structure simulated by the test structure is unchanged, and the operating performance of the CMOS structure passes the test.
As an example, in BCD products, DMOS is usually required to bear a higher operating voltage, so when the semiconductor device is in operation, the Metal is correspondingly required to bear a high voltage, the CMOS under the Metal is affected by the Metal electric field, then the preset test signal threshold corresponding to the third test signal loading end G is set to be the upper operating voltage limit of the BCD product, during the test, circuit tests are repeated until the test signal corresponding to the third test signal loading end G reaches the upper operating voltage limit of the BCD product, the substrate 100 between the drain region 120 and the source region 130 is still not turned on, which indicates that the threshold Voltage (VT) of the CMOS structure is not affected by the higher operating voltage during the operation of the BCD product, and the operation performance of the CMOS structure passes the test.
Specifically, in this embodiment, when the electrical signal of the test path is smaller than the preset electrical signal threshold, in the step of increasing the test signal corresponding to the third test signal loading end G, in each circuit test, the difference between the test signal corresponding to the third test signal loading end G increases progressively, so that the regularity and the uniformity of the test process are better, and the steps of the test method are simplified.
As an example, in BCD products, the upper limit of the working voltage is 35V, the test signal corresponding to the third test signal loading end G in the first circuit test is set to 0V, and the test signals corresponding to the third test signal loading end G in the plurality of circuit tests are set to test according to the rule of increasing 1V from 0V to 35V each time.
In this embodiment, when the electrical signal is greater than or equal to the preset electrical signal threshold, the circuit test is failed, and the circuit test is ended.
That is, in this embodiment, when the current Id of the test path is greater than or equal to the preset current threshold, it is indicated that the substrate 100 between the drain region 120 and the source region 130 is turned on, and then it is indicated that the voltage Vg applied by the third test signal loading terminal G has not reached the actual operating voltage requirement, and the substrate 100 between the drain region 120 and the source region 130 is turned on, then the threshold Voltage (VT) of the substrate 100 between the drain region 120 and the source region 130 is changed, and accordingly, the threshold Voltage (VT) of the CMOS structure simulated by the test structure is changed, and the operating performance of the CMOS structure fails the test.
As an example, during the test, the test signal corresponding to the third test signal loading terminal G has not reached the upper operating voltage limit of the BCD product, and the substrate 100 between the drain region 120 and the source region 130 has been turned on, which indicates that the threshold Voltage (VT) of the CMOS structure is affected by the higher operating voltage during the operation of the BCD product, and the operation performance of the CMOS structure fails the test.
It should be noted that, in the embodiment, the preset test signal threshold is not too large or too small in the step of performing one or more circuit tests. If the preset test signal threshold is too large, the number of circuit tests which are easy to circulate is too large, the test process is too long, the time cost and the test cost are increased, and unnecessary waste is caused; if the preset test signal threshold is too small, it is easy to cause that for a test structure which does not meet the actual working requirement, when the test signal corresponding to the third test signal loading end G still reaches the test signal threshold, the situation that the electrical signal of the test path of the substrate 100 between the drain region 120 and the source region 130 is greater than or equal to the preset electrical signal threshold does not occur, that is, in the actual working process, the threshold Voltage (VT) of the substrate 100 between the drain region 120 and the source region 130 may change to affect the working performance, and it should be determined that the test fails, but the test cannot be detected in the test process, thereby causing inaccurate test results. For this reason, in the step of performing one or more circuit tests in this embodiment, the preset test signal threshold is 35V.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (20)
1. A test structure, comprising:
The substrate comprises a channel region, a drain region adjacent to the channel region is formed in the substrate on one side of the channel region, a source region adjacent to the channel region is formed in the substrate on the other side of the channel region, the drain region is used as a first test signal loading end, and the source region is used as a second test signal loading end;
an interlayer dielectric layer covering the substrate;
And the metal layer is positioned on the interlayer dielectric layer above the channel region, the projection of the metal layer on the surface of the substrate covers the channel region, and the metal layer is used as a third test signal loading end.
2. The test structure of claim 1, wherein the test structure further comprises: a silicide blocking layer covering the substrate surface of the channel region;
The test structure further comprises: and the metal silicide layer is positioned on the top of the substrate of the drain region and the source region.
3. The test structure of claim 2, wherein the metal layer has a dimension greater than a dimension of the silicide blocking layer in a direction from the drain region toward the source region.
4. The test structure of claim 1, wherein the test structure further comprises: and the body contact area is positioned in the substrate at one side of the source area, which is opposite to the channel area, and is used as a fourth signal loading end.
5. The test structure of claim 4, wherein the test structure further comprises: and the body contact plug is positioned at the top of the body contact region and penetrates through the interlayer dielectric layer at the top of the body contact region.
6. The test structure of claim 4, wherein the fourth test signal loading terminal is configured to load a zero potential.
7. The test structure of claim 1, wherein the test structure further comprises: the drain region plug is positioned at the top of the drain region and penetrates through the interlayer dielectric layer at the top of the drain region;
And the source region plug is positioned at the top of the source region and penetrates through the interlayer dielectric layer at the top of the source region.
8. The test structure of claim 1, wherein the first test signal loading terminal is for loading a positive potential and the second test signal loading terminal is for loading a zero potential;
The third test signal loading end is used for loading positive potential.
9. The test structure of claim 1, wherein the test structure is disposed on a wafer, the wafer including dicing streets, the test structure being located in the dicing streets.
10. A method of forming a test structure, comprising:
Providing a substrate, wherein the substrate comprises a channel region, a drain region adjacent to the channel region is formed in the substrate on one side of the channel region, a source region adjacent to the channel region is formed in the substrate on the other side of the channel region, the drain region is used as a first test signal loading end, and the source region is used as a second test signal loading end;
forming an interlayer dielectric layer covering the substrate;
And forming a metal layer on the interlayer dielectric layer above the channel region, wherein the projection of the metal layer on the surface of the substrate covers the channel region, and the metal layer is used as a third test signal loading end.
11. The method of forming a test structure of claim 10, wherein prior to forming an interlayer dielectric layer overlying the substrate, the method further comprises: forming a silicide blocking layer covering the substrate surface of the channel region;
and after the silicide blocking layer is formed, forming a metal silicide layer on the top of the substrate of the drain region and the source region.
12. The method of claim 10, wherein in the step of providing the substrate, a body contact region is formed in the substrate on a side of the source region facing away from the channel region, the body contact region being used as a fourth signal loading terminal.
13. The method of forming a test structure of claim 12, wherein prior to forming a metal layer on an interlayer dielectric layer over the channel region, the method further comprises: and forming a body contact plug penetrating through the interlayer dielectric layer at the top of the body contact region.
14. The method of forming a test structure of claim 10, wherein prior to forming a metal layer on an interlayer dielectric layer over the channel region, the method further comprises: forming a drain region plug penetrating through the interlayer dielectric layer at the top of the drain region;
And forming a source region plug penetrating through the interlayer dielectric layer at the top of the source region.
15. A method of testing, comprising:
providing a test structure according to any one of claims 1-9;
loading corresponding test signals to the first test signal loading end and the second test signal loading end, wherein the test signals are used for enabling the substrate between the drain region and the source region to form a test path;
Performing one or more circuit tests, the circuit tests comprising:
Loading a corresponding test signal to the third test signal loading end, wherein the test signal loading end is used for loading a test signal to a test channel formed by the substrate between the drain region and the source region;
Detecting an electrical signal of a test path formed by the substrate between the drain region and the source region;
When the electric signal is smaller than a preset electric signal threshold value, increasing the test signal corresponding to the third test signal loading end, and returning to execute the loading of the test signal corresponding to the third test signal loading end until the test signal corresponding to the third test signal loading end reaches the preset test signal threshold value in the current circuit test, so as to complete the circuit test;
and when the electric signal is greater than or equal to a preset electric signal threshold value, the circuit test is not passed, and the circuit test is ended.
16. The method of claim 15, wherein the step of increasing the test signal corresponding to the third test signal loading terminal increases the difference between the test signals corresponding to the third test signal loading terminal in each circuit test when the electrical signal is less than a predetermined electrical signal threshold.
17. The test method of claim 15, wherein in the step of loading the first test signal loading terminal and the second test signal loading terminal with the corresponding test signals, the first test signal loading terminal is loaded with a positive potential, and the second test signal loading terminal is loaded with a zero potential;
In the step of loading the third test signal loading end with the corresponding test signal, loading the third test signal loading end with a positive potential;
in the step of detecting an electric signal of a test path constituted by the substrate between the drain region and the source region, a current of the test path constituted by the substrate between the drain region and the source region is detected.
18. The test method of claim 17, wherein in the step of loading the first test signal loading terminal with a positive potential, the positive potential loaded on the first test signal loading terminal is 0.1V to 5V;
in the step of performing one or more circuit tests, the preset test signal threshold is 35V;
in the step of performing one or more circuit tests, the preset electrical signal threshold is 10E-6A.
19. The method of testing of claim 15, wherein in the step of providing the test structure, the test structure further comprises: the body contact area is positioned in the substrate at one side of the source area, which is opposite to the channel area, and is used as a fourth signal loading end;
Before performing one or more circuit tests, the test method further comprises: and loading the corresponding test signals on the fourth signal loading end.
20. The method of testing as claimed in claim 18, wherein in the step of loading the fourth signal loading terminal with the corresponding test signal, the fourth signal loading terminal is loaded with a zero potential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211630533.9A CN118231378A (en) | 2022-12-19 | 2022-12-19 | Test structure, forming method thereof and test method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211630533.9A CN118231378A (en) | 2022-12-19 | 2022-12-19 | Test structure, forming method thereof and test method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118231378A true CN118231378A (en) | 2024-06-21 |
Family
ID=91504484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211630533.9A Pending CN118231378A (en) | 2022-12-19 | 2022-12-19 | Test structure, forming method thereof and test method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118231378A (en) |
-
2022
- 2022-12-19 CN CN202211630533.9A patent/CN118231378A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20040232522A1 (en) | Semiconductor device, method of manufacturing semiconductor device, and method of evaluating manufacturing process of semiconductor device | |
| CN113257790B (en) | Electric leakage test structure and electric leakage test method | |
| US6995027B2 (en) | Integrated semiconductor structure for reliability tests of dielectrics | |
| US8680883B2 (en) | Time dependent dielectric breakdown (TDDB) test structure of semiconductor device and method of performing TDDB test using the same | |
| US8000935B2 (en) | Diagnostic method for root-cause analysis of FET performance variation | |
| CN103941171A (en) | Semiconductor test structure and test method | |
| CN103887283A (en) | Polycrystalline silicon residue monitoring structure | |
| CN109300878B (en) | Forming method of interface defect characterization structure | |
| CN112151403A (en) | Characterization method based on junctionless transistor | |
| CN118231378A (en) | Test structure, forming method thereof and test method | |
| CN118231379A (en) | Test structure, forming method thereof and test method | |
| CN103258813A (en) | Testing structure and forming method of part depletion type SOI MOSFET | |
| US7327155B2 (en) | Elastic metal gate MOS transistor for surface mobility measurement in semiconductor materials | |
| CN112865773B (en) | MOS transistor with gate protection diode | |
| US20150123130A1 (en) | Test key structure | |
| CN109192676B (en) | Characterization method of interface defect | |
| CN103308772A (en) | Semiconductor detection circuit and detection method | |
| CN108037131B (en) | Method for detecting plug defect | |
| CN108417536B (en) | Semiconductor structure and forming method and working method thereof | |
| Garba-Seybou et al. | Location of Oxide Breakdown Events under Off-state TDDB in 28nm N-MOSFETs dedicated to RF applications | |
| Lin et al. | An application of a nanoprobe technique in the characterization of advanced SRAM devices | |
| CN108922857B (en) | Interface defect characterization structure and interface defect detection device | |
| CN109671766B (en) | Power mosfet | |
| CN116936543B (en) | Capacitance test structure, preparation method, test method and application | |
| US20240319267A1 (en) | Leakage testing structure and leakage testing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |