CN118231373B - CSP structure of semiconductor power device and device manufacturing method thereof - Google Patents
CSP structure of semiconductor power device and device manufacturing method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/6027—Mounting on semiconductor conductive members
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Geometry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to a CSP structure of a semiconductor power device and a device manufacturing method thereof. The device chip comprises a source vertical pad extending from the crystal face source electrode layer to the side edge of the first chip, a drain vertical pad extending from the crystal back drain electrode layer to the side edge of the second chip and a grid vertical pad positioned on the side edges of the other two parallel chips; the surface of the device chip facing the chip carrier is provided with a first heat conduction isolation film so as to cover the crystal face source electrode layer or the crystal back drain electrode layer. The first heat conduction isolation film is provided with a lower convex surface which can be flatly attached to the chip carrier, and the source electrode vertical pad, the drain electrode vertical pad and the grid electrode vertical pad are relatively contracted inwards to the lower convex surface so as to improve the solder receiving capacity. The preferred embodiment of the present invention achieves the technical achievement of mounting the chip of the semiconductor power device in the CSP configuration with a passive component surface bonder, and the chip carrier are fixed with solder without causing problems of excessive solder spreading and shorting.
Description
Technical Field
The invention relates to the technical field of packaging of semiconductor power devices, in particular to a CSP (CHIP SCALE PACKAGE, chip size packaging) structure of a semiconductor power device and a device manufacturing method thereof.
Background
Semiconductor power devices are typically MOSFET transistors, the electrodes of which include a source, a drain, and a gate, with the potential of the gate varying to control conduction between the source and the drain. Electrically, the transistor is divided into depletion and enhancement modes, and the depletion mode is turned on and the enhancement mode is turned off when the grid is in zero bias. Structurally, the electrode positions are divided into two distributions, namely a source electrode contact and a gate electrode contact are arranged on the top surface of a chip, a drain electrode contact is arranged on the bottom surface of the chip, and the source electrode contact and the drain electrode contact are not only fixedly mounted but also wire-bonded during packaging; the other is that the source electrode contact, the gate electrode contact and the drain electrode contact are all arranged on the top surface of the chip, when the chip is packaged, the flip-chip is connected to the carrier plate in a flip-chip mode, and the wiring is not needed, but the top surface of the chip is needed to reserve the position of the drain electrode contact, the conducting structure and the isolation structure are needed to be arranged in the chip, the whole chip is large in area size and easy to short-circuit. The electrode positions of the two existing semiconductor power devices are not beneficial to the development trend of Chip Size Packaging (CSP), because the wire bonding needs a large bonding wire space, the packaging material needs to package the wire bonding wire, and the chip mounting needs a die bonder and a wire bonding machine; the other type of flip chip bonding requires too much change of the internal structure of the chip to enable the source and drain grids to be located on the same chip surface, so that the chip size is enlarged, the chip surface of the flip chip facing the carrier is not beneficial to glue filling and heat conduction, the whole packaging size is also enlarged, the chip mounting requires a high-precision flip chip bonding machine, and the use amount of the bumps or the solder balls located at the bottom of the chip needs to be tightly controlled.
The invention patent application number CN112366230A discloses a power semiconductor device and a forming method. The grid electrode contact pad, the source electrode contact pad and the drain electrode contact pad of the power semiconductor device are all arranged on the front surface of the chip, a first area of the semiconductor layer is used for arranging a grid electrode, a source electrode, a conducting channel and a drift region inside the device, and the drain electrode contact pad is electrically connected with the semiconductor layer of the second area and further electrically connected with a drain electrode positioned on one side of the back surface. The electrode contact pads are arranged on the front surface, so that the packaging is convenient to carry out by adopting the mature CSP technology. In the related art, the gate contact pad, the source contact pad and the drain contact pad are all disposed on the front surface of the chip and are bump-shaped, occupy a larger area on the surface of the chip, and cannot use solder or cause a short circuit of solder spreading on the surface, so that a bottom bump metal (UBM) and a solder ball on the UBM are formed on each contact pad, and the chip is flip-chip mounted on a PCB or a package substrate by a flip-chip bonder during the packaging process. The solder balls are located on the bottom surface of the chip, and the single volume of the solder balls and the UBM size on the contact pads affect the diffusion of solder materials, so that a flip-chip bonder with high precision is required, and the internal electrical interconnection structure of the chip needs to be changed in a manner of increasing the surface size of the chip.
The invention patent application number CN114496987A discloses a CSP packaging module of a MOSFET power device, the device comprises a lower plug arranged in a first interlayer dielectric layer and an upper plug arranged in a second interlayer dielectric layer on a semiconductor substrate, a plurality of upper plugs are arranged in a staggered manner in the length direction of a gap between grid grooves, and at least one pair of adjacent source plugs are respectively connected with a first source electrode and a second source electrode through corresponding upper plugs. Since the distance between two adjacent source plugs respectively connecting the first source electrode and the second source electrode is small, when CSP packaging is performed and conducting, the drain current introduced by one source electrode can flow to the other source electrode along the conducting path in the substrate. In the related prior art, when CSP packaging is performed, a trench MOSFET power device adopts a dual cell structure (dual), a drain terminal is shared on a back surface, a gate terminal and a source terminal shared by a part of MOSFETs and a gate terminal and a source terminal shared by another part of MOSFETs are separately disposed on a front surface, and two gate terminals and two source terminals are mounted on a circuit board by CSP process. When the gate terminal and the source terminal are mounted in the reverse direction, the common gate terminal is generally upward, and the common gate terminal is connected to the circuit board by bonding wires connected by wire bonding; if the common gate terminal is used for forward mounting, the gate terminal and the source terminal are connected to the circuit board by bonding wires connected by wire bonding, which is a conventional CSP structure of a semiconductor power device, and the internal electrical interconnection structure of the chip does not need to be changed.
In the existing CSP structure of the semiconductor power device, the source drain grid is not positioned on the same surface of the chip, at least one electrode is upward to be in wire bonding, but the wire bonding does not meet the requirement of microminiaturization advanced packaging, under the requirement of completely packaging and coating bonding wires, the packaging height and length are larger than the arc height and plane wire length of the bonding wires, and the whole packaging size cannot be further reduced. If the internal electric interconnection structure of the chip is forcedly changed, the source and drain grids are positioned on the same surface of the chip, the surface size of the chip is increased, the areas of the source and drain grid electrodes attached to the bottom of the chip are different, the single volume using amount of the solder balls needs to be precisely controlled, and the chip attachment is carried out by a flip chip bonding machine. Due to the multi-directional acting force of cohesive surface tension and metal wettability of the welding material in the solder balls, the problem that the adjacent solder balls are in diffusion short circuit fusion or the solder balls are disconnected from the electrode pads in the CSP packaging structure is likely to occur. Therefore, how to manufacture CSP structures of semiconductor power devices with high durability at lower production cost is a technical focus of continuous development.
Disclosure of Invention
The main object of the present invention is to provide a CSP structure of a semiconductor power device, which is mainly advanced in that the source drain grid is intentionally disposed on the same surface of the chip without enlarging the surface size of the chip, and wire bonding is not required, and the chip mounting mode can also use a passive element surface bonding machine to mount the chip of the semiconductor power device in the CSP structure, and replace solder to fix the chip and the chip carrier without causing the problem of excessive solder scattering and shorting.
The second main object of the present invention is to provide a semiconductor power device, which can be applied to the manufacturing of CSP structure of semiconductor power device capable of accommodating excessive solder and supplementing insufficient solder to improve the durability of product without the need of lower production cost of flip chip bonder and wire bonding machine.
The third main object of the present invention is to provide a method for manufacturing a semiconductor power device, which can manufacture a semiconductor power device with a new architecture, the surface size of a chip is not required to be enlarged on the structural surface, the source drain grid is intentionally arranged on the same surface of the chip, and wire bonding is not required when the chip is attached on the application surface.
The main purpose of the invention is realized by the following technical scheme:
a CSP structure of a semiconductor power device is provided, comprising:
The upper surface of the chip carrier is provided with a source electrode surface pad, a drain electrode surface pad and a grid electrode surface pad positioned between the source electrode surface pad and the drain electrode surface pad;
The device chip is arranged on the chip carrier in a surface joint mode and comprises a source vertical pad extending from the crystal face source electrode layer to the side edge of the first chip, a drain vertical pad extending from the crystal back drain electrode layer to the side edge of the second chip and grid vertical pads positioned on the side edges of the other two parallel chips; a first heat conduction isolating film is arranged on the surface of the device chip facing the chip carrier so as to cover the crystal face source electrode layer or the crystal back drain electrode layer;
Solder respectively connecting the source electrode surface pad and the source electrode vertical pad, connecting the drain electrode surface pad and the drain electrode vertical pad, and connecting the gate electrode surface pad and the gate electrode vertical pad;
the first heat-conducting isolation film is provided with a lower convex surface which can be flatly attached to the chip carrier, and the source vertical pad, the drain vertical pad and the grid vertical pad are relatively contracted inwards to the lower convex surface so as to improve the solder receiving capacity.
By adopting the technical scheme, the device chip is provided with the source vertical pad, the drain vertical pad and the grid vertical pad which are positioned at the side edges of different chips, the pad height of the first heat conduction isolation film is matched, the welding point of the chip is an L surface with a broken bent angle or an inverted T surface with a broken connecting midpoint, and redundant solder can be contained outside a surface joint area of the device chip and can be used for supplementing missing solder during reflow. Because the cohesive force of solder reflow can not be guided to the beneficial development of the condensation ball all the time, the lower convex surface of the first heat conduction isolating film is driven to be flatly attached to the chip carrier, and the welding gap between the lowest point of the vertical pad of the device chip and the surface pad of the chip carrier is fixed by the first heat conduction isolating film, so that the expansion and the welding disconnection of the solder are not easy to occur. Since the solder does not need to accurately control the single volume usage as the solder ball, the redundant solder can be accommodated outside the surface joint area of the device chip, the bottom carrier gap of the device chip is kept fixed in the thickness direction of the first heat conduction isolating film, the chip of the semiconductor power device can be mounted on the chip carrier of the CSP structure in a surface joint manner by adopting a passive element surface joint machine, the solder with lower cost is used for replacing the solder ball with higher cost, the redundant solder can not cause quality problems, and the production cost and the reliability of the CSP structure of the semiconductor power device can be further developed advantageously.
The present invention in a preferred example may be further configured to: the device chip further comprises a crystal face grid pad connected with the grid vertical pad, when the coverage size of the first heat conduction isolation film only covers the main body of the crystal face source electrode layer but does not cover the crystal face grid pad completely, the solder for welding the grid vertical pad can be located at the bottom of the crystal face grid pad in a partially extending mode; specifically, the crystal face gate pad is in a plurality of symmetrical configurations.
By adopting the above preferred technical features, the crystal face gate pad is not covered by the first heat-conducting isolation film and faces the chip carrier, the solder connected with the crystal face gate pad can grasp the device chip in advance, and the forces of the solder connected with the drain vertical pad and the solder connected with the source vertical pad acting on the first chip side and the second chip side of the device chip counteract balance, so that the occurrence of the tombstoning defect of the device chip such as a passive element can be reduced, because the tombstoning premise of forming the device chip is that all the crystal face gate pads and the gate vertical pad connected with the crystal face gate pad cannot be welded on the corresponding gate face pad of the chip carrier. More particularly, even if the rollover of the device chip occurs, one crystal face grid pad is disconnected and turned towards the direction away from the chip carrier, the grid vertical pad connected with the other crystal face grid pad, the drain vertical pad and the source vertical pad are welded on the corresponding surface pad of the chip carrier, the electric connection relation of the whole source and drain grids is not destroyed, and the channel conduction of the transistor can be normally driven.
The present invention in a preferred example may be further configured to: the source vertical pad, the drain vertical pad and the grid vertical pad are formed by four side frame strips cut off by corner holes of metal rings; more specifically, the metal ring is buried in the outer periphery of the insulating ring.
By adopting the above preferable technical features, the three are formed simultaneously and have the same structure by utilizing the constitution forms of the source vertical pad, the drain vertical pad and the gate vertical pad. The side wall of the chip is provided with a vertical pad of the source drain grid, and the corners of the chip are separated from the vertical pad of the source drain grid in a concave arc or L-shaped notch mode. The insulating ring is positioned at the inner ring of the metal ring so as to obtain the effect of chip side pre-packaging.
The present invention in a preferred example may be further configured to: and a second heat conduction isolating film is arranged on the surface of the device chip, which is away from the chip carrier, so as to cover the crystal back drain electrode layer or the crystal face source electrode layer, and prevent excessive solder from creeping above the junction area of the corresponding surface of the device chip.
By adopting the above preferable technical characteristics, the second heat-conducting isolation film is utilized to cover the crystal back drain electrode layer or the crystal face source electrode layer which are positioned on the upper surface of the chip when the surface is jointed, and excessive redundant solder cannot climb to the upper surface of the device chip.
The present invention in a preferred example may be further configured to: the CSP structure also includes an encapsulant formed on an upper surface of the chip carrier to seal the device chip and the solder without wire bonding.
By adopting the above preferable technical characteristics, the vertical pad of the source drain grid is arranged on the side edge of the chip of the device chip, the vertical pad of the source drain grid is separated from the corner of the chip, and the device chip and the solder can be sealed without wire bonding by using the sealing colloid as a packaging material.
The present invention in a preferred example may be further configured to: the side wall of the sealing colloid is provided with a lead frame bent pin or a semi-plating through hole which is formed by connecting and extending the corresponding source electrode surface pad, the corresponding drain electrode surface pad and the corresponding gate electrode surface pad, and the packaging bonding size of the CSP structure of the semiconductor power device is within one and five times of the surface bonding size of the device chip.
By adopting the above preferable technical characteristics, the package bonding size of the CSP structure of the semiconductor power device is CSP level by using the lead frame bent pin or the semi-plated through hole on the side wall of the sealing colloid.
The main purpose of the invention is realized by the following technical scheme: the semiconductor power device comprises a source vertical pad extending from a crystal face source layer to the side of a first chip, a drain vertical pad extending from a crystal back drain layer to the side of a second chip and grid vertical pads positioned on the sides of other two parallel chips, wherein the source vertical pad is arranged on a chip carrier in a surface bonding mode, and redundant solder can be contained outside the surface bonding size of the device chip; a first heat conduction isolating film is arranged on the surface of the device chip facing the chip carrier so as to cover the crystal face source electrode layer or the crystal back drain electrode layer; the first heat conduction isolation film is provided with a lower convex surface which can be flatly attached to the chip carrier, and the source vertical pad, the drain vertical pad and the grid vertical pad are relatively contracted inwards to the lower convex surface so as to improve the solder receiving capacity.
By adopting the technical scheme, the first heat conduction isolating film is added on the source vertical pad, the drain vertical pad and the grid vertical pad, so that a passive element surface bonding machine can be used for mounting a chip of a semiconductor power device in a CSP structure, and a flip chip bonding machine and a wire bonding machine are not needed, thereby being beneficial to realizing the chip mounting process with the requirements of automation, high efficiency and low precision, being applied to the CSP structure of the semiconductor power device, being capable of accommodating redundant solder and supplementing insufficient solder, and improving the product durability.
The present invention in a preferred example may be further configured to: regarding the chip internal structure of the semiconductor power device, the device chip further includes a crystal plane gate pad connected to the gate vertical pad, when the covering size of the first heat conductive isolation film covers only the main body of the crystal plane source layer but not the crystal plane gate pad completely, so that the solder for soldering the gate vertical pad can be partially extended to be located at the bottom of the crystal plane gate pad; the source vertical pad, the drain vertical pad and the grid vertical pad are formed by four side frame strips cut off by corner holes of metal rings; more specifically, the metal ring is embedded in the periphery of the insulating ring; and a second heat conduction isolating film is arranged on the surface of the device chip, which is away from the chip carrier, so as to cover the crystal back drain electrode layer or the crystal face source electrode layer, and prevent excessive solder from creeping above the junction area of the corresponding surface of the device chip.
The main purpose of the invention is realized by the following technical scheme:
A method for manufacturing a semiconductor power device is provided, comprising:
S1, providing a wafer substrate, wherein a transistor structure is arranged in a chip area of the wafer substrate, and a cutting channel is formed between the chip areas of the wafer substrate;
s2, arranging a metal ring on a cutting path of the wafer substrate;
s3, setting a crystal face source electrode layer and a crystal face grid electrode pad on the upper surface of the wafer substrate, wherein the crystal face source electrode layer and the crystal face grid electrode pad are connected to the metal ring;
S4, arranging a wafer back drain electrode layer on the lower surface of the wafer substrate, wherein the wafer back drain electrode layer is connected to the metal ring;
S5, arranging a first heat conduction isolation film on the upper surface or the lower surface of the wafer substrate so as to cover the crystal face source electrode layer or the crystal back drain electrode layer;
S7, forming corner holes in corners of a chip area of the wafer substrate, and enabling four side frame strips separated by the metal ring to respectively form the source vertical pad, the drain vertical pad and the grid vertical pad which are parallel and symmetrical;
s9, cutting and separating the chip area of the wafer substrate along the cutting path of the wafer substrate to obtain the device chip.
By adopting the technical scheme of the method, the semiconductor power device which can be used for CSP construction is manufactured by utilizing the steps S1 to S5, S7 and S9, the source vertical pad, the drain vertical pad and the grid vertical pad are manufactured on different chip sides of the device chip at lower cost, the surface size of the chip does not need to be enlarged on the structural surface, and wire bonding is not needed when the chip on the application surface is pasted.
The present invention in a preferred example may be further configured to: after step S7 and before step S9, the method further includes: s8, performing wafer pole testing to detect the performance of the transistor structure before chip separation.
By adopting the above-mentioned method preferred technical scheme, the performance of the transistor can be detected by utilizing the step S8 before the chips are separated.
The present invention in a preferred example may be further configured to: after step S4 and before step S7 or after step S3 and before step S4, further includes: s6, arranging a second heat conduction isolation film on the lower surface or the upper surface of the wafer substrate so as to cover the back drain electrode layer or the crystal face source electrode layer.
By adopting the above-mentioned method preferred technical scheme, in step S6, the second heat-conducting isolation film can prevent the solder on the side of the chip from flowing upwards and being soldered to the above back-of-the-wafer drain layer or the crystal face source layer.
In summary, the present invention includes at least one of the following technical effects contributing to the prior art:
1. the CSP structure of the semiconductor power device and the device manufacturing method thereof can be widely applied to the manufacturing field, are particularly suitable for the application field of the semiconductor power device requiring high reliability, high performance and miniaturization, such as the fields of automobile electronics, power electronics and the like, use solder to replace solder balls, and can not cause the reduction of the reliability and the performance; when the device chip is installed, the production equipment can replace a flip chip bonder with a surface bonder of a passive element;
2. By arranging the source vertical pad, the drain vertical pad and the grid vertical pad of the device chip and adding the lower convex surface structures of the first heat conduction isolating film on the sides of different chips, the solder receiving capacity can be effectively improved, the reliable connection between the device chip and the chip carrier is ensured, the solder is prevented from being scattered and shorted, and the reliability and the electrical connection performance of the welding spots of the CSP structure of the semiconductor power device are improved.
Drawings
Fig. 1 is a schematic top view of a semiconductor power device CSP according to an embodiment of the present invention (the same viewing angle corresponds to the bottom surface of the device chip);
FIG. 2 is a schematic diagram of a top surface of a device chip of a CSP configuration of a semiconductor power device (the same view angle corresponds to a bottom surface of a perspective chip carrier of the CSP configuration) according to an embodiment of the invention;
FIG. 3 is a schematic cross-sectional view of a CSP structure of a semiconductor power device corresponding to line A-A of FIG. 1 according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of a CSP structure of a semiconductor power device corresponding to line B-B of FIG. 1 according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view showing a CSP structure of a semiconductor power device according to another embodiment of the invention;
FIG. 6 is a block diagram showing a device manufacturing method of a CSP structure of a semiconductor power device according to an embodiment of the invention;
FIG. 7 is a schematic diagram of the assembly corresponding to the step S1 in FIG. 6 (A is a partial plan view of the front surface of the wafer, and B is a partial cutaway view) according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of the assembly corresponding to the step S2 in FIG. 6 (A is a partial plan view of the front surface of the wafer, and B is a partial cutaway view) according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of the assembly corresponding to the step S3 in FIG. 6 (A is a partial plan view of the front surface of the wafer, and B is a partial cutaway view) according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of the assembly corresponding to the step S5 in FIG. 6 (A is a partial plan view of the front surface of the wafer, and B is a partial cutaway view) according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of the assembly corresponding to the step S4 in FIG. 6 (A is a partial plan view of the back surface of the wafer, and B is a partial cutaway view) according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of the assembly corresponding to the step S6 in FIG. 6 (A is a partial plan view of the back surface of the wafer, and B is a partial cutaway view) according to an embodiment of the present invention;
FIG. 13 is a schematic diagram of the assembly corresponding to the step S7 in FIG. 6 (A is a partial plan view of the front surface of the wafer, and B is a partial cutaway view) according to an embodiment of the present invention;
FIG. 14 is a schematic diagram of the assembly corresponding to the step S8 in FIG. 6 (A is a partial plan view of the front surface of the wafer, and B is a partial cutaway view) according to the embodiment of the present invention;
Fig. 15 is a schematic diagram of an assembly corresponding to step S9 in fig. 6 according to an embodiment of the present invention (a is a partial plan view of a device corresponding to a front surface of a wafer, and B is a partial cutaway view).
Reference numerals: 10. a chip carrier; 11. a source electrode pad; 12. a drain pad; 13. a gate pad; 14. bending feet of the lead frame; 20. a device chip; 20A, a wafer substrate; 21. a source vertical pad; 22. a drain vertical pad; 23. a grid vertical pad; 24. a crystal plane source layer; 25. a back-of-the-crystal drain layer; 25A, bottom gate pad; 26. a crystal face gate pad; 27. a transistor structure; 28. cutting the channel; 29. an interlayer dielectric layer; 30. solder; 40. a first thermally conductive separator film; 41. a lower convex surface; 50. a second thermally conductive separator film; 60. a metal ring; 61. a corner hole; 62. a corner cut-off notch; 70. an insulating ring; 80. a sealing colloid; 81. semi-plated through holes; 90. and (3) a probe.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only examples for understanding a part of the inventive concept of the present invention, and are not representative of all embodiments, nor are they to be construed as the only embodiments. All other embodiments, based on the embodiments of the present invention, which are obtained by those of ordinary skill in the art under the understanding of the inventive concept of the present invention, are within the scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are included in the embodiments of the present invention, the directional indications are merely used to explain the relative positional relationship, movement conditions, etc. between the components in a specific posture, and if the specific posture is changed, the directional indications are correspondingly changed. In order to facilitate understanding of the technical solution of the present invention, the following further describes and explains the CSP structure of the semiconductor power device and the manufacturing method of the device of the present invention in detail, but is not intended to limit the scope of protection of the present invention.
Fig. 1 is a schematic top view of a semiconductor power device CSP according to the preferred embodiment of the invention, fig. 2 is a schematic top view of a device chip of the CSP, fig. 3 is a schematic cross-sectional view of A-A in fig. 1, and fig. 4 is a schematic cross-sectional view of B-B in fig. 1. Fig. 5 is a schematic cross-sectional view showing a CSP structure of a semiconductor power device according to another embodiment. Fig. 6 is a block diagram illustrating a manufacturing method of the device chip, and fig. 7 to 15 are schematic component cross-sectional views of the device chip of the CSP structure of the semiconductor power device corresponding to the main steps of fig. 6 in the manufacturing method, wherein part (a) in fig. 11 and 12 is a partial plan view of the back surface of the wafer, and part (a) in the remaining figures is a partial plan view of the front surface of the wafer. The drawings show only those parts that are common to many embodiments, and that differ or otherwise differ in what is depicted in the figures or otherwise presented in a written manner. Thus, based on the industrial characteristics and technical essence, those skilled in the art should correctly and reasonably understand and determine whether individual features or any combination of several features described below can be characterized in the same embodiment or whether features mutually exclusive in technical essence can be characterized only in different variant embodiments. Embodiments in which the figures are too similar are not repeated.
As referred to herein, "solder yield" is the allowable volume change that a CSP build product can accommodate solder at the junction corresponding to the source drain grid without inducing solder joint cracking and solder joint shorting. The volume of the solder balls is usually the smallest variable, and the ball diameter of the solder balls is selected after being screened and determined in advance, so that the accommodating volume of the solder balls is fixed. The solder is generally formed by spot coating, screen printing or steel stamping, and the larger volume variation exists between the joints, and the allowable range of the solder receiving capacity of the CSP structural product is larger than the volume variation of the solder formed between the joints of the source drain grid. That is, the amount of solder used may be small, and the solder yield has a wide elastic range. Further, "solder yield" can be further divided into "effective solder yield" and "excess solder yield", the "effective solder yield" being located within the surface bonding area of the device chip, at the bottom of the device chip, to provide effective soldering; the "excess solder volume" is located outside the surface bonding area of the device chip, exposed to the device chip, and provides spare solder prior to effective soldering. The solder is integrally connected to another part of the "excess solder receiving volume" at the part of the "effective solder receiving volume".
The term "relatively retracted" as used herein refers to that, based on the surface bonding surface of the object to be mounted (in particular, the device chip), the first distance from the first designated portion of the object to be mounted to the bonded carrier is greater than the second distance from the second designated portion of the object to be mounted to the bonded carrier, and the first designated portion of the object to be mounted is relatively retracted to the second designated portion. The specific definition of "the source vertical pad, the drain vertical pad, and the gate vertical pad are relatively retracted to the lower convex surface of the first heat-conducting isolation film" is that the vertical pad gap between any one of the source vertical pad, the drain vertical pad, and the gate vertical pad and the chip carrier is greater than the gap distance between the lower convex surface of the first heat-conducting isolation film and the chip carrier, and in a specific example, the gap distance approaches zero or can be a negative value; if negative, it means that the first thermally conductive isolation film is partially embedded in the chip carrier in the CSP configuration.
The term "surface pad" and "vertical pad" as used herein refers to a carrier bonding pad having a surface for attachment to a chip mounting surface of a chip carrier; the vertical pad refers to the fact that the arrangement attachment surface of the chip bonding pad is not consistent with the surface joint surface of the device chip, and can be vertical or inclined at an angle, and the vertical pad is positioned at the side edge of the chip.
The term "crystal face" and "crystal back" as referred to herein refer to a portion of the front surface of a device chip that is processed by a semiconductor processing process on a wafer substrate, and may particularly be a processed surface that forms a gate trench; "wafer back" refers to a portion of the reverse surface of a device chip that is processed against a wafer substrate away from the semiconductor processing process during fabrication of the device chip.
Referring to fig. 1 to 4, referring mainly to fig. 3 and 4, an embodiment of the present invention discloses a CSP structure of a semiconductor power device, which mainly includes: a chip carrier 10 for carrying the device chip 20, the device chip 20 with the MOSFET transistor structure 27, and a solder 30 interconnecting the chip carrier 10 and the device chip 20 internally. Fig. 1 is a schematic top view of a CSP structure perspective encapsulant 80 (corresponding to a bottom surface of a device chip 20 from the same perspective), fig. 2 is a schematic top view of the device chip 20 (corresponding to a bottom schematic surface of a CSP structure perspective chip carrier 10 from the same perspective), fig. 3 is a schematic cut-away view of a CSP structure of a semiconductor power device formed by A-A lines in fig. 1, and fig. 4 is a schematic cut-away view of a CSP structure of a semiconductor power device formed by B-B lines in fig. 1. The chip carrier 10 may be one of a micro printed circuit board, a ceramic circuit board, a relay silicon substrate, a lead frame pre-mold to carry the device chip 20 during packaging. The ratio of the area size of the chip carrier 10 to the device chip 20 should be controlled to be (1 to 1.44): 1, in particular the length and width of the chip carrier 10, do not exceed a point twice the length and width of all side-by-side lower device chips 20. The device chip 20 may be one or a plurality of device chips.
Referring to fig. 1,3 and 4, the upper surface of the chip carrier 10 is provided with a source electrode pad 11, a drain electrode pad 12 and a gate electrode pad 13 therebetween, which are usually made of metal, such as copper, aluminum or alloys thereof, and the surface thereof may be electroplated with an oxidation-resistant protection layer such as nickel-gold or tin-silver. The chip carrier 10, more particularly, one of a ceramic circuit board, a printed circuit board and a lead frame (or leadframe), is used to carry and electrically connect the device chip 20. In this example, the gate pad 13 is spaced between the source pad 11 and the drain pad 12. The gate pads 13 may be one or more, in this example two symmetrical.
Referring again to fig. 3 and 4, the device chip 20 is disposed on the chip carrier 10 in a Surface Mount (SMT) manner; the device chip 20 includes a source vertical pad 21 extending from a crystal plane source layer 24 to a first chip side, a drain vertical pad 22 extending from a crystal back drain layer 25 to a second chip side, and a gate vertical pad 23 located on the other two parallel chip sides, typically made of metal, such as copper, aluminum, or alloys thereof. A plurality of transistor structures 27 are arranged in the device chip 20, the transistor structures 27 comprise a grid electrode and grid oxide layers at two sides, an active well layer of the device chip 20 forms a channel at the side edge of the grid oxide layer, and an interlayer dielectric layer 29 covers the upper part of the grid electrode to isolate the grid electrode of the transistor structures 27 from the crystal face source layer 24; the electric conduction and the electric blocking between the source vertical pad 21 and the drain vertical pad 22 are realized by controlling the electric potential of the grid electrode vertical pad 23 connected to the grid electrode of the transistor structure 27 to connect and disconnect the transistor structure 27. The surface of the device chip 20 facing the chip carrier 10 is provided with a first thermally conductive isolation film 40, such as a thermally conductive silicon gel, to cover the crystal face source layer 24 or the crystal back drain layer 25. In an example, the surface of the device chip 20 facing the chip carrier 10 is a surface provided with a crystal plane source layer 24, so that the first thermally conductive isolation film 40 covers the crystal plane source layer 24. Referring to fig. 1 and 2, the source vertical pad 21, the drain vertical pad 22 and the two gate vertical pads 23 are respectively located at four chip sides of the device chip 20, and are relatively vertically located on the corresponding source surface pad 11, drain surface pad 12 and gate surface pad 13, and the three vertical pads are respectively connected to the crystal plane source layer 24, the crystal back drain layer 25 and the crystal plane gate pad 26. The first thermally conductive isolation film 40 is used to maintain a minimum gap between the face pad and the corresponding vertical pad and to block the solder 30 from shorting across the area. The body material of the device chip 20 is a semiconductor, such as silicon, silicon carbide, gallium nitride, and has a MOSFET transistor structure 27 disposed therein, specifically in a plurality of parallel configurations. By means of the electric field driving of the drain vertical pad 22, the transistor structure 27 can switch on or switch off the carrier flow channel path between the crystal face source layer 24 and the crystal back drain layer 25, wherein the carrier flow channel path is located in an active well layer of the transistor structure 27 at the side wall gate oxide layer of the embedded gate, for example, a P-channel transistor, the electrical property of the active well layer is N-type, and the electrical property of the N-channel transistor is P-type. The embedded gate of the transistor structure 27 is integrally connected with a contact gate, specifically a trench parallel to the transistor structure 27 on the right side as shown in fig. 3 and a trench parallel to the transistor structure 27 on the left side as shown in fig. 4, the contact gate is connected with a crystal plane gate pad 26 by using a contact hole, and the crystal plane gate pad 26 is connected to the gate vertical pad 23.
Referring to fig. 3, 4 and 1, the multi-region solder 30 is respectively located on the source electrode pad 11, the drain electrode pad 12 and the gate electrode pad 13, and the solder 30 is respectively soldered to connect the source electrode pad 11 and the source vertical pad 21, to connect the drain electrode pad 12 and the drain vertical pad 22, and to connect the gate electrode pad 13 and the gate vertical pad 23. The first thermally conductive isolation film 40 has a lower convex surface 41 for being flatly attached to the chip carrier 10, the lower ends of the source vertical pad 21, the drain vertical pad 22 and the gate vertical pad 23 close to the first thermally conductive isolation film 40 are relatively retracted to the lower convex surface 41, and the bottom ends of the source vertical pad 21, the drain vertical pad 22 and the gate vertical pad 23 are not in direct contact with the chip carrier 10, so as to increase the capacity of the solder 30. Specifically, the excess solder is contained outside the surface bonding area of the device chip 20. Wherein the surface-bonding regions substantially correspond to the area dimensions of the device chip 20 projected perpendicularly onto the chip carrier 10. Solder 30 is specifically a lead-free solder, such as tin silver copper, and may not need to be pre-condensed into balls prior to being applied to the chip carrier 10. Solder 30 may be specifically defined as a die-attach grade solder material.
The structure implementation principle of this embodiment is as follows, the device chip 20 is provided with the source vertical pad 21, the drain vertical pad 22 and the gate vertical pad 23 located at the sides of different chips, and in cooperation with the pad height of the first heat conduction isolation film 40, the chip welding point formed between the corresponding vertical pad and the surface pad is an L-shaped surface (I-shaped surface is floated on the left and right sides of the line, the floating gap is filled with solder 30) with a bent angle or an inverted T-shaped surface (I-shaped surface is floated on the line, the floating gap is filled with solder 30) with a connecting midpoint, and the redundant solder can be contained outside the surface joint area of the device chip 20 and can be supplied for the missing solder 30 during reflow. Because the reflow cohesion of the solder 30 can not be guided and condensed to form a sphere, the lower convex surface 41 of the first heat-conducting isolation film 40 is driven to be flatly attached to the chip carrier 10, and the welding gap between the lowest point of the vertical pad of the device chip 20 and the surface pad of the chip carrier 10 is fixed by the first heat-conducting isolation film 40, so that the extrusion spreading and the tilting welding disconnection of the solder 30 are not easy to occur. Since the solder 30 does not need to accurately control the single volume amount as the solder ball, the surplus solder can be contained outside the surface bonding area of the device chip 20, the bottom carrier gap of the device chip 20 is kept fixed in the thickness direction of the first heat conductive isolation film 40, the device chip 20 of the semiconductor power device can be mounted on the chip carrier 10 of the CSP structure in a surface bonding manner by using the passive component surface bonding machine, the higher cost solder ball is replaced by the lower cost solder 30, and the surplus solder does not cause quality problems. In the CSP structure of the application, wire bonding is not needed, the space of a device chip is not needed to be enlarged, the through holes and the back electrode are arranged to enable the source electrode and the drain electrode to be positioned on the internal circuit structure of the same surface, the problem of solder scattering short circuit is avoided, and the production cost and the reliability of the CSP structure of the semiconductor power device can be further developed advantageously.
In a preferred example, referring again to fig. 3 and 4, the device chip 20 further includes a crystal plane gate pad 26 connected to the gate standing pad 23, which may be single or multiple. When the first thermally conductive isolation film 40 covers the crystalline plane source layer 24 but does not completely cover the crystalline plane gate pad 26, the solder 30 soldered to the gate standing pad 23 can be partially extended at the bottom of the crystalline plane gate pad 26 to enhance the bottom fixation of the device chip 20. In a specific example, the crystal plane gate pad 26 is configured in a plurality of symmetry. With the crystal plane gate pad 26 not covered by the first thermally conductive isolation film 40 and facing the chip carrier 10, the solder 30 connecting the crystal plane gate pad 26 can grasp the device chip 20 in advance, and the forces acting on the first chip side and the second chip side of the device chip 20 by the solder 30 connecting the drain vertical pad 22 and the solder 30 of the source vertical pad 21 are balanced, so that occurrence of a tombstoning defect of the device chip 20 such as a passive element can be reduced, because a possible precondition for forming the tombstoning defect of the device chip 20 is that all the crystal plane gate pads 26 and the gate vertical pad 23 connected thereto cannot be soldered to the corresponding gate surface pad 13 of the chip carrier 10. More specifically, even if the rollover of the device chip 20 occurs, one of the crystal face gate pads 26 is disconnected and flipped away from the chip carrier 10, the other crystal face gate pad 26, the gate vertical pad 23 connected thereto, the drain vertical pad 22 and the source vertical pad 21 are soldered to the corresponding surface pad of the chip carrier 10, so that the electrical connection relationship between the whole source and drain gates is not broken, and the channel of the transistor structure 27 can be normally driven to be conducted.
In a preferred example, the source vertical pad 21, the drain vertical pad 22 and the gate vertical pad 23 may be perpendicular to the lower convex surface 41 of the first thermal isolation film 40, or may be relatively inclined to the lower convex surface 41 of the first thermal isolation film 40. The virtual included angle between the attaching surfaces of the source vertical pad 21, the drain vertical pad 22 and the gate vertical pad 23, relative to the lower convex surface 41 of the first thermal isolation film 40, is located at a position close to the boundary in the surface bonding area, and the virtual included angle is greater than or equal to 90 degrees and less than or equal to 150 degrees, more specifically, is between 90 degrees and 120 degrees, and is favorable for the solder 30 to climb in a direction away from the surface bonding area. The lower convex surface 41 may be flat, smooth or rough, and is preferably tacky based on the first thermally conductive isolation film 40 to provide affinity to the surface of the chip carrier 10. The first thermally conductive isolation film 40 may have a single-layer or multi-layer structure, and the main body or the surface layer of the first thermally conductive isolation film 40 is preferably post-cured during curing of the encapsulant 80.
In a preferred example, the source vertical pad 21, the drain vertical pad 22 and the gate vertical pad 23 are formed by four side frame bars cut by corner holes 61 of metal rings 60 (see the variation of step S5 to step S7 in fig. 11 and 13 corresponding to fig. 6). In terms of structural performance, the device chip 20 forms a corner cut-off notch 62 (as shown in fig. 1 and 2) at the corner to divide the source vertical pad 21 and the gate vertical pad 23 and the drain vertical pad 22 and the gate vertical pad 23. In this example, the corner cut-off notch 62 may be a concave arc, but is not limited to a concave arc, and in a variation example, the corner cut-off notch 62 may be a concave L-shape, and specifically, a square hole may be formed at the intersection of the cutting lanes by using an eccentrically arranged leno triangle drill, and the concave L-shape corner cut-off notch 62 may be obtained after the chips are separated. In a more specific example, the metal ring 60 is embedded in the periphery of the insulating ring 70. The source vertical pad 21, the drain vertical pad 22 and the gate vertical pad 23 are formed simultaneously and have the same structure. The side wall of the chip is provided with vertical pads of the source and drain grid, the corners of the chip are separated from the vertical pads of the source and drain grid in the form of concave arcs or L-shaped notches, and the source vertical pad 21, the drain vertical pad 22 and the grid vertical pad 23 can be obtained simultaneously and are separated from each other in a space adjacent non-planar mode, namely, the side contact pad of the chip is metallized. In a more preferred example, the insulating ring 70 is located at the inner ring of the metal ring 60 (see fig. 11) to obtain the effect of chip-side pre-packaging. In a more specific example, an insulating solder resist, i.e., a corner insulating solder resist of a chip corner, may be filled at the corner hole 61.
In a preferred example, a second thermally conductive isolation film 50 is provided on the surface of the device chip 20 facing away from the chip carrier 10 to cover the back drain layer 25 or the crystal plane source layer 24 to prevent excessive solder 30 from creeping over the corresponding surface bonding area of the device chip 20. In this example, the second thermally conductive isolation film 50 covers the back drain layer 25 (as shown in fig. 3 and 4). With the second thermally conductive isolation film 50, the back drain layer 25 or the source layer 24 on the upper surface of the chip is covered when the surface is bonded, and excessive solder does not flow up to the upper surface of the device chip 20 when packaged. The material of the second heat-conducting isolation film 50 may be the same as that of the first heat-conducting isolation film 40. In addition, an insulating ring 70 may be provided at the periphery of the device chip 20 to relatively isolate any one of the source vertical pad 21, the drain vertical pad 22 and the gate vertical pad 23 from the device layer inside the device chip 20.
In a preferred example, the CSP construction further includes an encapsulant 80 formed on the upper surface of the chip carrier 10 to seal the device chip 20 and the solder 30 without wire bonding. The source vertical pad 21, the drain vertical pad 22 and the gate vertical pad 23 are respectively arranged on the different chip sides of the device chip 20, the source vertical pad 21, the drain vertical pad 22 and the gate vertical pad 23 are separated by the chip corners therebetween, and the sealing colloid 80 serving as the packaging material can seal the device chip 20 and the solder 30 without wire bonding, and the bottom of the device chip 20 is not required to be filled in specific application. The encapsulant 80 may be a conventional encapsulant material that is formed over the chip carrier 10 in a mold-sealing manner. The encapsulant 80 may also be a non-conventional molding encapsulant, for example, formed by printing, dispensing, film bonding, etc., and since the first thermally conductive isolation film 40 is pre-disposed at the wafer stage, the underfill on the bottom of the device chip 20 is not required to be fabricated during packaging, and the encapsulant 80 does not need to be filled into a large amount of bottom voids between the device chip 20 and the chip carrier 10 during packaging. The device die 20 has a relatively good adhesion prior to the formation of the encapsulant 80.
In a preferred example, the sidewalls of the molding compound 80 are provided with half plated through holes 81 (as shown in fig. 3 and 4) or leadframe leads 14 (as shown in the variation of fig. 5) that are formed by connecting and extending the corresponding source surface pad 11, drain surface pad 12 and gate surface pad 13. In this example, half plated through holes 81 are provided on four or two of the sidewalls of the encapsulant 80, and can be used as external terminals of CSP configuration. The package bond size of the semiconductor power device CSP configuration is within one and five times the surface bond size of the device chip 20. The package bonding size of the CSP structure of the semiconductor power device is CSP-level by using the leadframe leads 14 or the semi-plated through holes 81 on the side walls of the molding compound 80.
Therefore, the present invention may also provide a semiconductor power device configured as the CSP, specifically, a device chip 20 disposed on a chip carrier 10 in a surface bonding manner, including a source vertical pad 21 extending from a crystal plane source layer 24 to a first chip side, a drain vertical pad 22 extending from a crystal back drain layer 25 to a second chip side, and gate vertical pads 23 located on two other parallel chip sides, so that the redundant solder 30 can be contained outside the surface bonding dimensions of the device chip 20; a first heat-conducting isolation film 40 is disposed on the surface of the device chip 20 facing the chip carrier 10 to cover the crystal face source layer 24 or the crystal back drain layer 25; the first heat-conducting isolation film 40 has a lower convex surface 41 that can be flatly attached to the chip carrier 10, so that the bottom ends of the source vertical pad 21, the drain vertical pad 22 and the gate vertical pad 23 are relatively retracted to the lower convex surface 41, so as to increase the capacity of the solder 30.
With the first heat conductive isolation film 40 added to the source vertical pad 21, the drain vertical pad 22 and the gate vertical pad 23 provided in the chip stage, the device chip 20 of the semiconductor power device can be mounted on the chip carrier 10 by using the passive device surface bonding machine in the packaging stage, and the flip chip bonding machine and the wire bonding machine are not needed, which is helpful for realizing the chip mounting process with the requirements of automation, high efficiency and low precision, and can be applied to the CSP structure of the semiconductor power device to accommodate redundant solder and supplement insufficient solder so as to improve the product durability.
In a preferred example, regarding the chip internal structure of the semiconductor power device, the device chip 20 further includes a crystal plane gate pad 26 connected to the gate riser pad 23, when the first thermally conductive isolation film 40 covers only the main body of the crystal plane source layer 24 and does not completely cover the crystal plane gate pad 26, so that the solder 30 soldering the gate riser pad 23 can be partially extended at the bottom of the crystal plane gate pad 26; the source vertical pad 21, the drain vertical pad 22, and the gate vertical pad 23 are formed of four side frame bars cut by corner holes 61 of a metal ring 60, and a corner cut-off notch 62 is formed at a corner of the chip in terms of structural representation. More specifically, the metal ring 60 is buried in the outer periphery of the insulating ring 70; the surface of the device chip 20 facing away from the chip carrier 10 is provided with a second heat-conducting isolation film 50 to cover the back drain layer 25 or the crystal plane source layer 24, so as to prevent the excessive solder 30 from creeping above the corresponding surface bonding area of the device chip 20, and further adhere to the chip mounting fixture.
Fig. 5 is a schematic cross-sectional view showing a CSP structure of a semiconductor power device according to another embodiment of the invention. Referring to fig. 5, in a variation, the CSP configuration of the semiconductor power device includes: the chip carrier 10 for carrying the device chip 20, the device chip 20 having a MOSFET transistor structure, and the solder 30 interconnecting the chip carrier 10 and the device chip 20 internally are substantially identical to the above-described embodiment in that the device chip 20 is mounted on the chip carrier 10 with the surface provided with the crystal plane source layer 24 facing upward, and the above-described embodiment is mounted on the chip carrier 10 with the surface provided with the crystal plane source layer 24 facing downward. Therefore, the surface of the device chip 20 facing the chip carrier 10 in the variation example is the surface provided with the back-of-crystal drain layer 25, so that the first thermally conductive isolation film 40 covers the back-of-crystal drain layer 25. In a more specific variation, the surface of the device chip 20 facing away from the chip carrier 10 is the surface provided with the crystal plane source layer 24, and the second thermally conductive isolation film 50 covers the crystal plane source layer 24. In a more preferred variation, the crystal plane gate pad 26 is connected to the upper end of the gate standing pad 23, and the lower end of the gate standing pad 23 may be connected to the bottom surface gate pad 25A located on the same surface as the back drain layer 25. The first thermally conductive isolation film 40 may not cover the bottom gate pad 25A. The side wall of the molding compound 80 may be provided with a leadframe bent pin 14 formed by connecting and extending the corresponding source surface pad 11, drain surface pad 12 and gate surface pad 13, as an external connection terminal of CSP structure. In summary, the present invention, under the teachings of the combined embodiments and variations, has the technical advantage that device chip 20 is coupled to chip carrier 10 in either a front-side mounting or a back-side mounting.
Referring to fig. 6, an embodiment of the present invention further provides a device manufacturing method of a CSP structure of a semiconductor power device, which includes steps S1 to S9, wherein the intermediate steps S6 and S8 are optional steps, and are indicated by dashed boxes. The second heat conductive isolation film 50 is disposed in the selecting step S6, and the wafer electrode test using the probe 90 is performed in the selecting step S8. The present exemplary structure described above employs the left-hand process route in fig. 6, and the modified structure described above employs the right-hand process route in fig. 6, and is described in detail below with respect to the left-hand process route in fig. 6.
Referring to fig. 7 in conjunction with step S1, a wafer substrate 20A is provided, a transistor structure 27 is disposed in a chip area of the wafer substrate 20A, and a scribe line 28 is formed between the chip areas of the wafer substrate 20A. The chip area is sized for the device chip 20. The wafer substrate 20A specifically includes a substrate layer, a drift layer of an epitaxial structure, an active well layer and a source field layer, a gate trench and a contact trench communicating with the gate trench are formed by etching, a gate trench of the transistor structure 27 penetrates through the source field layer and the active well layer, a trench bottom isolation well can be formed below the bottom of the gate trench, the trench bottom isolation well is located in the drift layer, a gate oxide layer is formed on the inner wall of the gate trench, a buried gate is disposed in the gate trench and is communicated with a gate connector in the contact trench, and an interlayer dielectric layer 29 is covered above both the gate trench and the contact trench. A first contact hole between the patterns of the interlayer dielectric layer 29 may penetrate the source region layer, and a hole bottom isolation well may be formed under the hole bottom of the first contact hole. The periphery of the transistor structure 27 may be provided with an insulating ring 70.
Step S2 is performed with reference to fig. 8, and a metal ring 60 is disposed on the scribe line 28 of the wafer substrate 20A. The metal ring 60 partially passes through the inner space of the chip area as a precursor of the aforementioned vertical pad combinations. The metal ring 60 is provided by a method including semiconductor etching and metal deposition. In this example, the metal ring 60 is located on the side of the scribe line 28, in a waffle structure.
Step S3, referring to fig. 9, a crystal plane source layer 24 and a crystal plane gate pad 26 are disposed on the upper surface of the wafer substrate 20A, and the crystal plane source layer 24 and the crystal plane gate pad 26 are connected to the metal ring 60 at different chip sides. In this example, the crystal plane source layer 24 is conducted to the source region layer through the contact hole between the isolation layer patterns above the gate trench, and the crystal plane source layer 24 extends to the first chip side (right side of the wellhead structure of the metal ring 60 in fig. 9) to connect the metal ring 60 where the source vertical pad is to be formed. The crystal plane gate pad 26 is conducted to the gate connector through a second contact hole above the contact trench, the second contact hole is located in the isolation layer above the contact trench in a penetrating manner, and the crystal plane gate pad 26 extends to two parallel symmetrical chip sides to connect the metal rings 60 (the upper and lower sides of the wellhead structure of the metal ring 60 in fig. 9) where the gate vertical pad is formed.
In step S5, referring to fig. 10, a first thermally conductive isolation film 40 is disposed on the upper surface or the lower surface (the upper surface in this example) of the wafer substrate 20A to cover the crystalline plane source layer 24 or the back drain layer 25. In this example, the first thermally conductive isolation film 40 is disposed on the upper surface of the wafer substrate 20A, and the disposing method includes at least one of printing, stamping, transfer, and depositing. The composition of the first thermally conductive barrier film 40 preferably includes a post-curing agent. After the first heat-conducting isolation film 40 is disposed, the coverage surface of the first heat-conducting isolation film 40 also isolates the side gap of the crystal face source layer 24, which is formed by the drain vertical pad 22 and the gate vertical pad 23 corresponding to the metal ring 60, and fills the gap between the crystal face source layer 24 and the crystal face gate pad 26.
Step S4 is performed with reference to fig. 11, and a back drain layer 25 is disposed on the lower surface of the wafer substrate 20A, where the back drain layer 25 is connected to the metal ring 60 (the left side of the wellhead structure of the metal ring 60 in fig. 9). In step S4, before the back drain layer 25 is disposed, back grinding may be performed on the back surface of the wafer substrate 20A to expose the lower end portion of the metal ring 60.
In addition, the step S4 and the step S5 are operations in mutually interchangeable order; when the first thermally conductive isolation film 40 covers the crystal plane source layer 24, step S5 is performed before step S4; a second thermally conductive isolation film 50 may also be disposed on the lower surface of the wafer substrate 20A after step S4. When the first thermally conductive isolation film 40 covers the back drain layer 25, step S5 is performed after step S4; a second thermally conductive isolation film 50 may also be disposed on the upper surface of the wafer substrate 20A prior to step S4.
Optional step S6 referring to fig. 12 in combination with fig. 12, in a preferred example, referring to fig. 12 in combination, step S6 is further included after step S4 and before step S7 or before step S3 and before step S4, where a second thermally conductive isolation film 50 is disposed on the lower surface or the upper surface (in this example, the lower surface) of the wafer substrate 20A to cover the back drain layer 25 or the crystal plane source layer 24 (in this example, to cover the back drain layer 25). The specific two process steps between step S3 and step S7 are as follows: s3, S5, S4, S6, S7 (the process route shown by the left arrow in fig. 6) correspond to the device chip 20 shown in fig. 3 and 4 in the previous embodiment; and, the order is S3, S6, S4, S5, S7 (the process route shown by the right arrow in fig. 6), corresponding to the aforementioned variations such as the device chip 20 shown in fig. 5. With step S6, the second thermally conductive isolation film 50 can block the solder 30 on the side of the chip from flowing upward and being soldered to the upper back drain layer 25 or the crystal plane source layer 24 (covering the back drain layer 25 in this example).
Step S7, referring to fig. 13, is performed to form corner holes 61 at corners of the chip area of the wafer substrate 20A, so that the four side frame bars separated by the metal ring 60 respectively form the source vertical pad 21, the drain vertical pad 22 and the two parallel and symmetrical gate vertical pads 23. Specifically, the hole diameter of the corner hole 61 is larger than the width of the dicing street 28, and is sufficient to cut off the corner of the metal ring 60 into a circular hole shape. In a different variant, the corner hole 61 may also be a square hole (not shown).
Optional step S8 referring to fig. 14, in a preferred example, after step S7 and before step S9, the manufacturing method further includes step S8, performing a wafer level test to test the performance of the transistor structure 27 before the chip is separated. In step S8, the probe 90 is used to probe the crystal face source layer 24 connected to the source vertical pad 21 and the crystal face gate pad 26 connected to the gate vertical pad 23, the drain vertical pad 22 can be connected to the bottom by using the back-of-wafer drain layer 25, and the conduction between the crystal face source layer 24 and the back-of-wafer drain layer 25 is detected by the embedded gate of the transistor structure 27, so that the performance of the transistor structure 27 can be detected at the wafer level before the chip is separated.
Step S9, referring to fig. 14 and 15 in combination, cuts the chip area of the wafer substrate 20A along the scribe line 28 of the wafer substrate 20A to obtain the device chip 20.
The method of this embodiment is implemented by using steps S1 to S5, S7 and S9 as described below to manufacture a semiconductor power device capable of being used in CSP configuration, and the source vertical pad 21, the drain vertical pad 22 and the gate vertical pad 23 are manufactured at low cost on different chip sides of the device chip 20, so that the chip surface size does not need to be enlarged on the structure surface, and wire bonding is not needed when the chip on the application surface is mounted.
The embodiments of the present invention are all preferred embodiments for easy understanding or implementation of the technical solution of the present invention, and are not limited in scope by the present invention, and all equivalent changes according to the structure, shape and principle of the present invention should be covered in the scope of the claimed invention.
Claims (9)
1. A CSP structure for a semiconductor power device, comprising:
The upper surface of the chip carrier is provided with a source electrode surface pad, a drain electrode surface pad and a grid electrode surface pad positioned between the source electrode surface pad and the drain electrode surface pad;
The device chip is arranged on the chip carrier in a surface joint mode and comprises a source vertical pad extending from the crystal face source electrode layer to the side edge of the first chip, a drain vertical pad extending from the crystal back drain electrode layer to the side edge of the second chip and grid vertical pads positioned on the side edges of the other two parallel chips; a first heat conduction isolating film is arranged on the surface of the device chip facing the chip carrier so as to cover the crystal face source electrode layer or the crystal back drain electrode layer;
Solder respectively connecting the source electrode surface pad and the source electrode vertical pad, connecting the drain electrode surface pad and the drain electrode vertical pad, and connecting the gate electrode surface pad and the gate electrode vertical pad;
the first heat conduction isolation film is provided with a lower convex surface which can be flatly attached to the chip carrier, and the source vertical pad, the drain vertical pad and the grid vertical pad are relatively contracted inwards to the lower convex surface so as to improve the solder receiving capacity;
The source vertical pad, the drain vertical pad and the grid vertical pad are formed by four side frame strips cut off by corner holes of metal rings, and the metal rings are embedded outside the insulating rings; the device chip forms a corner cut-off notch at a corner to divide the source vertical pad and the gate vertical pad and the drain vertical pad and the gate vertical pad.
2. The CSP construction of semiconductor power devices of claim 1, wherein the device chip further comprises a crystalline plane gate pad connecting the gate riser pad, when the first thermally conductive isolation film has a cover dimension that covers only the body of the crystalline plane source layer and does not completely cover the crystalline plane gate pad, such that solder that soldered the gate riser pad can be partially extended to lie at the bottom of the crystalline plane gate pad; the crystal face grid electrode pad is in a plurality of symmetrical configurations.
3. The CSP construction of semiconductor power devices of claim 1, wherein a surface of the device chip facing away from the chip carrier is provided with a second thermally conductive isolation film to cover the back-of-the-wafer drain layer or the crystal plane source layer to prevent excessive solder from creeping over the device chip's corresponding surface bonding area.
4. A semiconductor power device CSP construction according to any one of claims 1-3, further comprising an encapsulant formed on an upper surface of the chip carrier to seal the device chip and the solder without wire bonding.
5. The CSP structure of claim 4, wherein the sidewalls of the encapsulant are provided with leadframe leads or semi-plated through holes extending from the corresponding source, drain and gate pads, the package bond size of the CSP structure being within one and five times the surface bond size of the device die.
6. The semiconductor power device is characterized in that the semiconductor power device is a device chip arranged on a chip carrier in a surface bonding mode and comprises a source vertical pad extending from a crystal face source electrode layer to the side edge of a first chip, a drain vertical pad extending from a crystal back drain electrode layer to the side edge of a second chip and grid vertical pads positioned on the side edges of other two parallel chips, so that redundant solder can be contained outside the surface bonding size of the device chip; a first heat conduction isolating film is arranged on the surface of the device chip facing the chip carrier so as to cover the crystal face source electrode layer or the crystal back drain electrode layer; the first heat conduction isolation film is provided with a lower convex surface which can be flatly attached to the chip carrier, and the source vertical pad, the drain vertical pad and the grid vertical pad are relatively contracted inwards to the lower convex surface so as to improve the solder receiving capacity;
The source vertical pad, the drain vertical pad and the grid vertical pad are formed by four side frame strips cut off by corner holes of metal rings, and the metal rings are embedded in the periphery of the insulating ring; the device chip forms a corner cut-off notch at a corner to divide the source vertical pad and the gate vertical pad and the drain vertical pad and the gate vertical pad.
7. The semiconductor power device of claim 6, wherein the device die further comprises a crystal plane gate pad connected to the gate riser pad, when the first thermally conductive isolation film has a cover dimension that covers only the body of the crystal plane source layer and does not completely cover the crystal plane gate pad, such that solder the gate riser pad can be partially extended to lie at the bottom of the crystal plane gate pad; and a second heat conduction isolating film is arranged on the surface of the device chip, which is away from the chip carrier, so as to cover the crystal back drain electrode layer or the crystal face source electrode layer, and prevent excessive solder from creeping above the junction area of the corresponding surface of the device chip.
8. A method of manufacturing the semiconductor power device according to claim 6 or 7, comprising:
S1, providing a wafer substrate, wherein a transistor structure is arranged in a chip area of the wafer substrate, and a cutting channel is formed between the chip areas of the wafer substrate;
s2, arranging a metal ring on a cutting path of the wafer substrate;
s3, setting a crystal face source electrode layer and a crystal face grid electrode pad on the upper surface of the wafer substrate, wherein the crystal face source electrode layer and the crystal face grid electrode pad are connected to the metal ring;
S4, arranging a wafer back drain electrode layer on the lower surface of the wafer substrate, wherein the wafer back drain electrode layer is connected to the metal ring;
S5, arranging a first heat conduction isolation film on the upper surface or the lower surface of the wafer substrate so as to cover the crystal face source electrode layer or the crystal back drain electrode layer;
S7, forming corner holes in corners of a chip area of the wafer substrate, and enabling four side frame strips separated by the metal ring to respectively form the source vertical pad, the drain vertical pad and the grid vertical pad which are parallel and symmetrical;
s9, cutting and separating the chip area of the wafer substrate along the cutting path of the wafer substrate to obtain the device chip.
9. The method of manufacturing a semiconductor power device according to claim 8, further comprising, after step S7 and before step S9:
S8, performing wafer pole test to detect the performance of the transistor structure before chip separation;
after step S4 and before step S7 or after step S3 and before step S4, further includes:
S6, arranging a second heat conduction isolation film on the lower surface or the upper surface of the wafer substrate so as to cover the back drain electrode layer or the crystal face source electrode layer.
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| CN102214623A (en) * | 2010-04-07 | 2011-10-12 | 精材科技股份有限公司 | Chip package and method for forming the same |
| CN102347299A (en) * | 2010-07-29 | 2012-02-08 | 万国半导体股份有限公司 | Wafer level chip scale package |
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| JP2011009437A (en) * | 2009-06-25 | 2011-01-13 | Panasonic Electric Works Co Ltd | Laminated substrate having cavity structure, manufacturing method for the same, circuit module using the laminated substrate, and manufacturing method for the circuit module |
| KR102380840B1 (en) * | 2017-06-08 | 2022-04-01 | 삼성전기주식회사 | Electronic component and board having the same mounted thereon |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102214623A (en) * | 2010-04-07 | 2011-10-12 | 精材科技股份有限公司 | Chip package and method for forming the same |
| CN102347299A (en) * | 2010-07-29 | 2012-02-08 | 万国半导体股份有限公司 | Wafer level chip scale package |
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