CN118202472A

CN118202472A - Transistor device, manufacturing method thereof and electronic device

Info

Publication number: CN118202472A
Application number: CN202180103907.9A
Authority: CN
Inventors: 殷士辉; 景蔚亮; 黄凯亮; 冯君校; 王正波
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-12-06
Filing date: 2021-12-06
Publication date: 2024-06-14
Also published as: WO2023102698A1

Abstract

The application provides a transistor device, a preparation method thereof and an electronic device. The transistor device includes a substrate structure, a channel layer disposed on the substrate structure, a first electrode, and an electrode structure; the first electrode is isolated from the electrode structure; the electrode structure comprises at least two electrode layers arranged along a first direction, wherein any two adjacent electrode layers are electrically isolated, and the first direction is perpendicular to the substrate structure; along the first direction, the at least two electrode layers comprise at least one source electrode and at least one drain electrode which are alternately arranged; when at least two sources and at least two drains are arranged, any two sources are electrically connected, and any two drains are electrically connected; the channel layer is positioned between the first electrode and the electrode structure, and the channel layer is contacted with any one electrode layer. The transistor device can obtain a plurality of equivalent channels by adding the electrode layer on the basis of not increasing the unit area of the device, and the effective channel width of the whole transistor device is increased to increase the output current of the device.

Description

Transistor device, manufacturing method thereof and electronic device

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to a transistor device, a method for manufacturing the transistor device, and an electronic device.

Background

With the development of internet technology and cloud computing technology, the information age is rapidly changing to the big data age, so that the demands of storage systems are continuously improved, and the increasing information quantity makes the storage chips occupy very important positions in the whole integrated circuit industry market. However, according to moore's law, the gap between the processor and the memory is larger and larger, and the performance of the microprocessor is greatly increased over that of the memory, which eventually results in that the storage density and the read-write speed of the memory cannot keep pace with the operation speed of the processor, and finally affects the overall performance of the system.

The reading speed of the gain-cell memory can be as low as nanosecond, and the gain-cell memory adopts a two-transistor device structure, so that the occupied area of a device unit can be reduced, and high-speed reading and writing and high-density integration can be realized. However, because of the leakage phenomenon in the memory cell, the memory cell needs to be refreshed at intervals in practical application to maintain the integrity of data, so that larger dynamic power consumption is brought. The use of ultra low leakage thin film transistors (thin film transistor, TFT) as transistors in gain cell memories can reduce dynamic power consumption and increase memory market. However, the current operating current of the read transistor in the gain cell memory is relatively small, resulting in a limited operating frequency of the read transistor.

Disclosure of Invention

The application provides a transistor device, a preparation method thereof and an electronic device.

In a first aspect, the present application provides a transistor arrangement which may be applied to devices such as memories, meeting the channel width requirements of such devices. The transistor device specifically comprises a substrate structure, wherein an electrode structure is arranged on the substrate structure, the electrode structure comprises at least two electrode layers which are alternately arranged in a first direction, and any two adjacent electrode layers in the at least two electrode layers are electrically isolated to prevent electrode short circuit; the at least two electrode layers include at least one source electrode and at least one drain electrode, and when the number of source electrodes is at least two, any two source electrodes are electrically connected to form the source electrode of the whole transistor device, and when the number of drain electrodes is at least two, any two drain electrodes are electrically connected to form the drain electrode of the whole transistor device, so that when the transistor device is connected with an external device, an external source electrode interface and a drain electrode interface are connected. The first direction is perpendicular to the substrate structure. The substrate structure is also provided with a first electrode. The substrate structure is also provided with a channel layer, the channel layer is positioned between the first electrode and the electrode structure, the channel layer is in contact with any one of the electrode layers, the first electrode at least partially corresponds to the channel layer along a second direction, and the second direction is perpendicular to the first direction. A channel can be formed between any adjacent source electrode and drain electrode, and the first electrode can regulate and control the concentration of carriers in the channel between any two electrode layers; when the first electrode is conducted, the first electrode can drive electrons in the channel layer between any adjacent source electrode and drain electrode to move, so that channel current is formed. The distance between the source and the drain in the first direction corresponds to the length of the channel, and the length of the surface of the source (or the drain) in contact with the channel layer perpendicular to the first direction corresponds to the width of the channel. For the whole transistor device, when the number of the electrode layers is n, n-1 channels can be formed, in the reasonable height range of the transistor device, the number of the channels can be increased by adding the electrode layers (namely alternately increasing the source electrode and the drain electrode), so that the effective channel width of the transistor device is increased, and the size of the channel current can be increased on the basis that the factors such as the atom mobility, the channel length and the gate oxide thickness of the transistor device are unchanged.

The transistor device further comprises an isolation medium layer, wherein the isolation medium layer is generally arranged on the surface of the first electrode, and the isolation medium layer is positioned between the first electrode and the electrode structure so as to electrically isolate the first electrode from the electrode structure and electrically isolate the first electrode from the channel layer; in some embodiments, an isolation dielectric layer is disposed between the first electrode and the channel layer. When the first electrode is a grid electrode, the isolation dielectric layer is equivalent to the grid dielectric layer.

The transistor device may have different structural forms, in one of which the channel layer may be disposed outside the first electrode in the second direction, and the electrode structure may be disposed outside the channel layer; a first groove is arranged in the electrode structure, extends along the first direction and is communicated with the at least two electrode layers; the first electrode is arranged in the first groove, and a channel layer and an isolation medium layer are sequentially laminated on the bottom surface and the side surface of the first groove, wherein the isolation medium layer is contacted with the first electrode, and the channel layer is contacted with any electrode layer. In such a structure, a projection of the channel layer onto the substrate structure may be provided covering a projection of the first electrode onto the substrate structure towards an end of the substrate structure.

In the transistor device of another structure, the electrode structure may be formed in a columnar shape in the second direction, the channel layer may be disposed outside the electrode structure, and the first electrode may be disposed outside the channel layer. In such a structure, a projection of the channel layer onto the substrate structure may be provided covering a projection of an end of the electrode structure remote from the substrate structure onto the substrate structure.

In some embodiments, to avoid source (drain) diffusion at the contact region with the channel layer, to reduce the fermi-pinning effect of the contact, an insulating layer may be provided at the contact interface of each electrode layer with the channel layer, and a metal-insulating layer-semiconductor structure may be formed at the interface of the electrode layer with the channel layer. Wherein the thickness of the insulating layer may be selected to be 0.1-2 nanometers (nm).

In the transistor device, electrical isolation between any two adjacent electrode layers includes: an electrode dielectric layer is arranged between any two adjacent electrode layers so as to electrically isolate the two electrode layers. In order to facilitate the process preparation and the electrical property calculation, the distance between any two adjacent electrode layers may be set to be the same.

The materials of each structure in the transistor device are selected as follows: the electrode layer is made of titanium (Ti), gold (aurum, au), tungsten (W), aluminum (Al), copper (cuprum, cu), ruthenium (Ru), molybdenum (Mo), silver (argentum, ag), platinum (Pt), bismuth (bismuth, bi), titanium nitride (TiN), tungsten nitride (tungsten nitride, WN), indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO); the first electrode is made of one or more of titanium, gold, tungsten, aluminum, copper, ruthenium, molybdenum, silver, platinum, titanium nitride, indium tin oxide or indium zinc oxide; the isolation dielectric layer is made of silicon oxide (SiO _x), silicon nitride (SiN _x), aluminum oxide (Al ₂O ₃), hafnium oxide (HfO ₂), zirconium dioxide (zirconium dioxide, zrO ₂), titanium dioxide (titanium dioxide, TiO ₂) or yttria (Y ₂O ₃) in a combination of materials doping combinations, stack combinations, or combinations of doping and stack combinations; the channel layer may be made of one or more of metal oxide, multi-component compound, graphene, molybdenum disulfide (molybdenum sulfide, moS ₂), and black phosphorus, such as silicon semiconductor (Si), polysilicon (polycrystalline silicon, poly-Si), or amorphous silicon (amorphorus-Si), indium oxide (In ₂O ₃), zinc oxide (ZnO), Metal oxides such as gallium oxide (Ga ₂O ₃), indium Tin Oxide (ITO), or titanium dioxide.

In a second aspect, the present application further provides a transistor device, specifically including a first electrode, a pocket structure, and a connection structure; the pocket structure comprises an inner structure layer and an outer structure layer which are nested inside and outside; the inner structure layer comprises a doped semiconductor material, and the inner structure layer surrounds a pocket and is used for accommodating the first electrode; the outer structural layer is wrapped outside the inner structural layer; the outer structure layer corresponds to an electrode structure and comprises a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer and a third electrode layer which are stacked in sequence, wherein the first dielectric layer is used for isolating the first electrode layer from the second electrode layer and preventing the first electrode layer from being in short circuit with the second electrode layer; the second dielectric layer is used for isolating the second electrode layer from the third electrode layer and preventing the second electrode layer from being short-circuited with the third electrode layer; the first electrode layer, the first dielectric layer, the second electrode layer, the second dielectric layer and the third electrode layer are all annular and are wound outside the inner structure; the first electrode layer and the third electrode layer are electrically connected through a connection structure, which may be specifically a wire. In this structure, the first electrode may serve as a gate electrode of the transistor device, the inner structure layer may serve as a channel layer of the transistor device, and the first electrode layer, the second electrode layer, and the third electrode layer in the outer structure layer may serve as source and drain electrodes of the transistor device; the first electrode layer and the third electrode layer have the same polarity (both are sources or both are drains), and the second electrode layer has the opposite polarity to the first electrode layer and the third electrode layer (when the first electrode layer and the third electrode layer are sources, the second electrode layer is a drain, and when the first electrode layer and the third electrode layer are drains, the second electrode layer is a source).

Specifically, the transistor device further comprises an isolation medium layer arranged on the outer side of the first electrode, and the isolation medium layer is located between the first electrode and the inner structure layer. The isolation dielectric layer herein may be used as a gate dielectric layer of a transistor device to prevent shorting of the gate (i.e., the first electrode) to other electrodes. The first dielectric layer and the second dielectric layer are electrode dielectric layers, and the materials of the first dielectric layer and the second dielectric layer can be the same.

In a third aspect, the present application further provides a transistor device, specifically including an electrode structure, a pocket structure, and a connection structure; the electrode structure comprises a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer and a third electrode layer which are stacked in sequence, wherein the first dielectric layer is used for isolating the first electrode layer from the second electrode layer and preventing the first electrode layer from being in short circuit with the second electrode layer; the second dielectric layer is used for isolating the second electrode layer from the third electrode layer and preventing the second electrode layer from being short-circuited with the third electrode layer; the pocket structure comprises an inner structure layer and an outer structure layer which are nested inside and outside; the inner structure layer comprises a doped semiconductor material, and the inner structure layer surrounds a pocket and is used for accommodating the electrode structure; the outer structural layer is wrapped outside the inner structural layer; the first electrode layer and the third electrode layer are electrically connected through a connection structure, which may be specifically a wire. In this structure, the first electrode may serve as a gate electrode of the transistor device, the inner structure layer may serve as a channel layer of the transistor device, and the first electrode layer, the second electrode layer, and the third electrode layer in the electrode structure may serve as source and drain electrodes of the transistor device; the first electrode layer and the third electrode layer have the same polarity (both are sources or both are drains), and the second electrode layer has the opposite polarity to the first electrode layer and the third electrode layer (when the first electrode layer and the third electrode layer are sources, the second electrode layer is a drain, and when the first electrode layer and the third electrode layer are drains, the second electrode layer is a source).

Specifically, the transistor device further comprises an isolation medium layer arranged on the surface (corresponding to the inner wall of the outer structure layer) of the first electrode facing the electrode structure, and the isolation medium layer is located between the first electrode and the inner structure layer. The isolation dielectric layer herein may be used as an isolation dielectric layer for a transistor device, preventing shorting of the gate (i.e., the first electrode) to other electrodes. The first dielectric layer and the second dielectric layer are electrode dielectric layers, and the materials of the first dielectric layer and the second dielectric layer can be the same. In a fourth aspect, the present application further provides an electronic device, taking a memory as an example, where the electronic device includes a write transistor, a read transistor, a memory cell, a first write signal line, a second write signal line, a first read signal line, and a second read signal line, where the read transistor is any one of the transistor devices described above; the first write signal line is connected with a first electrode of the write transistor, and the second write signal line is connected with a source electrode of the write transistor; the first reading signal line is connected with the source electrode of the reading transistor, and the second reading signal line is connected with the drain electrode of the reading transistor; the drain of the write transistor is connected with the first electrode structure of the read transistor, and the memory cell is connected between the write transistor and the read transistor. Since the transistor device serving as a read transistor can increase a channel current, a read delay can be reduced when reading data.

In a fifth aspect, the present application further provides a method for manufacturing a transistor device, which may be used to manufacture a portion of the transistor device, where the method specifically includes:

sequentially and alternately arranging electrode layers and electrode medium layers on the substrate structure along a first direction to form an electrode structure; the electrode layers are at least two, the at least two electrode layers comprise at least one source electrode and at least one drain electrode which are alternately arranged, the at least two source electrodes are electrically connected with each other, and the at least two drain electrodes are electrically connected with each other;

Etching the electrode structure to form a first groove extending along a first direction, wherein the first groove is communicated with each electrode layer;

Forming a channel layer in the first groove, and forming a second groove by the channel layer;

A first electrode is formed in the second recess.

When the transistor device further comprises an isolation medium layer, the isolation medium layer is arranged on the surface of the first electrode, and the isolation medium layer is positioned between the first electrode and the channel layer; the forming the first electrode in the second groove includes:

Forming an isolation medium layer in the second groove, and forming a third groove on the isolation medium layer;

The first electrode is formed in the third groove.

The application also provides a preparation method of the transistor device, which can be used for preparing the other part of the transistor device, and specifically comprises the following steps:

Forming a channel layer outside the electrode structure;

A first electrode is formed on the outside of the channel layer.

When the transistor device further comprises an isolation medium layer, the isolation medium layer is arranged on the surface of the first electrode, and the isolation medium layer is positioned between the first electrode and the channel layer; forming the first electrode outside the channel layer includes:

Forming the isolation medium layer outside the channel layer;

And forming the first electrode on the outer side of the isolation medium layer.

Drawings

FIGS. 1a and 1b are schematic circuit diagrams of a prior art gain cell memory;

fig. 2 is a schematic structural diagram of a transistor device according to an embodiment of the present application;

fig. 3 is a schematic cross-sectional structure of a transistor device according to an embodiment of the present application;

fig. 4a to 4d are schematic cross-sectional structures of the transistor device shown in fig. 3 along the B-plane;

Fig. 5a to 5d are schematic cross-sectional structures of a transistor device according to an embodiment of the present application;

Fig. 6 is a schematic cross-sectional structure of a transistor device according to an embodiment of the present application;

fig. 7a to 7e are schematic cross-sectional structures of the transistor device shown in fig. 6, taken along the B-plane;

fig. 8 is a schematic cross-sectional view of another transistor device according to an embodiment of the present application;

Fig. 9a to 9d are schematic cross-sectional views of the transistor device shown in fig. 8, taken along the B-plane;

fig. 10 is a schematic cross-sectional view of a transistor device according to an embodiment of the present application;

fig. 11a to 11e are schematic cross-sectional structures of the transistor device shown in fig. 10 taken along the B-plane;

Fig. 12a to fig. 12c are schematic structural diagrams of an isolation dielectric layer in a transistor device according to an embodiment of the present application;

FIG. 13a is a diagram showing electrical characterization of a first electrode voltage and channel current of a transistor device according to the prior art;

fig. 13b is an electrical representation of a first electrode voltage versus channel current of a transistor device according to an embodiment of the present application;

fig. 14 is a schematic circuit diagram of an electronic device according to an embodiment of the present application;

fig. 15 is a schematic diagram of a method for manufacturing a transistor device according to an embodiment of the present application;

fig. 16 is a schematic diagram of an electrode structure formed in a transistor device manufacturing process according to an embodiment of the present application;

Fig. 17a to 17c are schematic views showing structural changes of the transistor device shown in fig. 3 during the manufacturing process;

fig. 18 is a schematic diagram of a method for manufacturing another transistor device according to an embodiment of the present application;

Fig. 19a to 19c are schematic views showing structural changes of the transistor device shown in fig. 8 during the manufacturing process.

Icon: a 1-write transistor; a 2-read transistor; a 3-memory unit; 41-a first write signal line; 42-a second write signal line; 51-a first read signal line; 52-a second read signal line; 11-a substrate structure; 12-functional structure; 121-a first electrode; 122-a channel layer; 123-electrode structure; 1231-source; 1232-drain; 1233-dielectric layer; 124-isolating dielectric layer; 125-insulating layer.

Detailed Description

In an electronic device using a thin film transistor, a thin film transistor of a vertical structure can realize high-speed reading and writing and high-density integration. Taking the gain unit memory as an example, two thin film transistors with vertical structures can be adopted, and as the conducting channel of the thin film transistor is selected from amorphous metal oxide (such as indium gallium zinc oxide, indium gallium zinc oxid, IGZO) or other wide-bandgap semiconductor materials with extremely low leakage characteristics, the dynamic power consumption can be reduced, and the storage requirement can be met. Meanwhile, the memory unit can be applied to a back end of line (BEOL) process by utilizing the advantages of low process temperature, compatibility with the traditional microelectronic process and the like of the thin film transistor, so that heterogeneous integration and stacked integration are realized, and the memory density can be improved. Moreover, the selection of the thin film transistor with the vertical structure can improve the area utilization rate, is favorable for realizing a memory array with high integration density, and enables the occupied area of each memory cell to be close to 4F ² (F refers to half of one byte distance), and the parameter is only one third of a static random-access memory (SRAM).

Fig. 1a and 1b show the circuit principle of two gain cell memories. In fig. 1a, the gain cell memory includes a Write Transistor (WTR), a Read Transistor (RTR), and a Storage Node (SN) connected between the write transistor and the read transistor; in the "write" operation, the turn-on of the write transistor is controlled by a Write Word Line (WWL), and the potential of a Write Bit Line (WBL) is transferred to the gate of the read transistor, so that the gate potential of the read transistor is synchronized with the write bit line to achieve the writing of "0" and "1"; then, the writing node line controls the writing transistor to be turned off, the gate potential of the reading transistor is determined by the electric quantity stored in the node, and the leakage condition of the current on the gate of the reading transistor through the writing transistor is improved because the leakage of the thin film transistor is much lower than that of the silicon transistor, so that the storage duration of the memory can be prolonged. In the "read" operation, the memory state can be determined by only reading the current change of the read transistor or the voltage change of the Read Bit Line (RBL). In fig. 1b, a pre-charge transistor (PRECHARGE TRANSISTOR, PTR), a signal Sense Transistor (STR), and a capacitor (Cap) of at least one ferroelectric material connected between the pre-charge transistor and the read transistor; in the operation of writing, the Control Line (CL) is used for controlling the starting of the pre-charge transistor, when the writing bit line writes 1, the polarization effect of the capacitor ferroelectric material is utilized to enable the internal charge of the capacitor ferroelectric material to be inverted, so that the gate potential of the signal reading transistor is changed; in a "read" operation, the memory state can be determined by only a current change of the read signal sense transistor or a read bit line voltage change. The read transistor or the signal read transistor is a thin film transistor, and the operating current is relatively small due to the low mobility of the conductive channel material of the thin film transistor, so that the operating frequency of the read transistor or the signal read transistor is limited.

Therefore, the embodiment of the application provides a transistor device, a preparation method thereof and an electronic device, wherein the transistor device is a thin film transistor, the working current of the transistor device can be improved by increasing the effective channel width of the transistor device, and when the transistor device is used for reading data, the reading delay can be reduced.

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings.

The terminology used in the following examples is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include, for example, "one or more" such forms of expression, unless the context clearly indicates to the contrary.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

Referring to fig. 2, an embodiment of the present application provides a transistor device, which can be used as a read transistor in a memory circuit, and can also be applied in a scenario where logic, analog, radio frequency circuits, etc. need to provide different transistor width choices. The transistor device includes a substrate structure 11 and a functional structure 12 (including but not limited to source, drain, gate, etc. structures for performing transistor functions) disposed over the substrate structure 11, it being understood that "over the substrate structure 11" herein is merely illustrative of a relative positional relationship and is not limiting of the connection of the functional structure 12 to the substrate structure 11. That is, with reference to the structure of the entire transistor device, the substrate structure 11 is located at the bottom of the transistor, and when the transistor device is applied, the substrate structure 11 may be correspondingly disposed on a carrying surface for carrying the transistor device, and the functional structures 12 are located on the side of the substrate structure 11 away from the carrying surface.

The substrate structure 11 may be a base of the transistor device when used alone, and may serve as a load support. When the transistor arrangement is part of a semiconductor device, the functional structure 12 of the transistor arrangement, except for the substrate structure 11, may be stacked directly onto the substrate of the semiconductor device, which may serve as the transistor arrangement substrate structure 11, to perform the transistor function. At this time, the substrate structure 11 refers to a structure prepared by a previous process of the semiconductor device, and the preparation of the functional structure 12 of the transistor device other than the substrate structure 11 may be realized in a subsequent process of the semiconductor device preparation.

The substrate structure 11 may specifically include one or a combination of more of an element semiconductor, a compound semiconductor, an alloy semiconductor, or other materials, wherein the element semiconductor may include single crystal silicon, polycrystalline silicon, single crystal germanium (Ge), polycrystalline germanium (polycrystalline germanium, poly-Ge), amorphous structure, or the like, the compound semiconductor may include silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (gallium phosphide, gaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (indium antimonide, inSb), or the like, and the alloy semiconductor may include silicon germanium (SiGe), aluminum indium arsenide (aluminium indium arsenide, alInAs), aluminum gallium arsenide (aluminium gallium arsenide, alGaAs), indium gallium arsenide (indium gallium arsenide, as), indium gallium indium phosphide (gallium indium phosphide, gaInP), gallium arsenide (gallium indium phosphide arsenide, gapas), or the like.

In fig. 2, a first direction Z, a second direction X, and a third direction Y perpendicular to each other are set, and a stacking direction of the substrate structure 11 and the functional structure 12 of the transistor device is the first direction Z, which is perpendicular to the substrate structure 11. The structure of the transistor device may be implemented in various ways, and the transistor device may be cut along a plane a perpendicular to the third direction Y and a plane B perpendicular to the first direction Z, so that a specific structure of the transistor device may be obtained, and the transistor device will be described by means of a specific illustration.

Fig. 3 shows a schematic cross-sectional structure of a transistor device, in which the functional structure 12 specifically includes a first electrode 121, a channel layer 122, an electrode structure 123, and an isolation dielectric layer 124. The first electrode 121 may serve as a gate electrode of the transistor device, and the first electrode 121 may have a columnar shape and extend along the first direction Z, and in particular, the first electrode 121 may have a columnar shape, a prismatic shape, or other irregular columnar shape, and a length direction thereof is parallel to the first direction Z. The isolation dielectric layer 124 corresponds to a gate dielectric layer. A pedestal M may also be formed parallel to the substrate structure 11 at an end of the first electrode 121 remote from the substrate structure 11, which may be parallel to the substrate structure 11. The channel layer 122 comprises a doped semiconductor material, the doped atoms being capable of providing carriers that can be used to conduct current. The electrode structure 123 specifically includes at least two electrode layers stacked in sequence along a first direction Z and an electrode dielectric layer located between any two electrode layers, and specifically includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, and a third electrode layer stacked in sequence, where the first dielectric layer is used to isolate the first electrode layer from the second electrode layer and prevent the first electrode layer from shorting with the second electrode layer; the second dielectric layer is used for isolating the second electrode layer from the third electrode layer and preventing the second electrode layer from being short-circuited with the third electrode layer; the stacking direction corresponds to the first direction Z, and may be directed from the substrate structure 11 to the base M or from the base M to the substrate structure. The polarities of the first electrode layer and the third electrode layer are identical (both are source electrodes or drain electrodes), and the second electrode layer is opposite to the first electrode layer and the third electrode layer (when the first electrode layer and the third electrode layer are source electrodes, the second electrode layer is drain electrodes, and when the first electrode layer and the third electrode layer are drain electrodes, the second electrode layer is source electrodes). As shown in fig. 3, the first electrode layer and the third electrode layer are two drains 1232, the second electrode layer is one source 1231, and the first dielectric layer and the second dielectric layer are electrode dielectric layers 1233.

With continued reference to fig. 3, the first electrode 121 is configured to be columnar and extend along the first direction Z, and the channel layer 122 is disposed along a circumferential outer surface of the first electrode 121 (i.e., an outer surface of the first electrode 121 parallel to the first direction Z); the electrode structure 123 is disposed along a circumferential outer surface of the channel layer 122 (i.e., the channel layer 122 is parallel to an outer surface of the first matrix Z); specifically, the channel layer 122 is disposed on the circumferential outer surface of the first electrode 121 and the end surface of the first electrode 121 extending in the first direction Z, and the channel layer 122 also covers the surface of the base M facing the substrate structure 11. The isolation dielectric layer 124 is disposed between the channel layer 122 and the first electrode 121, and the base M. The electrode structure 123 is disposed outside the channel layer 122. An isolation dielectric layer 124 is disposed on the surface of the first electrode 121, where the isolation dielectric layer 124 is located between the first electrode 121 and the channel layer 122 (also referred to as the isolation dielectric layer 124 being located between the first electrode 121 and the electrode structure 123), and may electrically isolate the first electrode 121 from the electrode structure 123. The electrode structure 123 includes a first electrode layer (drain electrode 1232), a first dielectric layer (electrode dielectric layer 1233), a second electrode layer (source electrode 1231), a second dielectric layer (electrode dielectric layer 1233), and a third electrode layer (drain electrode 1232) arranged along the first direction Z, and any two adjacent electrode layers are electrically isolated by the electrode dielectric layer 1233, so that short circuit between the two adjacent electrode layers is prevented. Wherein the first electrode layer and the third electrode layer (corresponding to the two drains 1232) are electrically connected by a connection structure (e.g., a wire, not shown here). An electrode dielectric layer 1233 is also disposed between the electrode layer closest to the pedestal M and the channel layer 122. In the transistor device, the channel layer 122 is in contact with any one of the electrode layers, and two adjacent electrode layers (corresponding to one source electrode 1231 and one drain electrode 1232) can realize electron transport through the channel layer 122 between the two electrode layers under the driving of the first electrode 121 to form a channel current, wherein electrons flow in the channel layer 122, and the structural parameters of the channel layer 122 can affect the current between the source electrode and the drain electrode. Here, a distance between two adjacent electrode layers (corresponding to one source electrode 1231 and one drain electrode 1232) in the first direction Z corresponds to a channel length L of the channel layer 122 between the two electrode layers. In order to realize driving of the channel layer 122 by the first electrode 121, the first electrode 121 corresponds to the channel layer 122 between any two electrode layers along the second direction X perpendicular to the first direction Z.

It should be understood that the first electrode layer and the third electrode layer in fig. 3 may also be the source electrode 1231, and the second electrode layer is the drain electrode 1232, which is not limited herein; and fig. 3 is equivalent to a structure showing the simplest transistor device provided by the embodiment of the present application, in specific application, the number of electrode layers may be more according to the transistor device structure, and only any two electrode layers need to be electrically isolated by a dielectric layer 1233, and electrode layers with the same polarity are electrically connected. When the number of electrode layers serving as the source electrodes 1231 is 2 or more, any two source electrodes 1231 are electrically connected to each other, and can serve as source electrodes of the transistor device; when the number of electrode layers serving as the drain electrode 1232 is 2 or more, any two drain electrodes 1232 are electrically connected to each other, and can function as a drain electrode of the transistor device. Electrode dielectric layers for convenience of description, a certain electrode layer is directly referred to hereinafter as a source electrode 1231 and a drain electrode 1232, and a certain electrode dielectric layer is directly referred to hereinafter as a dielectric layer 1233. Fig. 4a shows a schematic cross-sectional structure of the transistor device of fig. 2, taken through a B-plane perpendicular to the first direction Z and passing through one of the electrode layers. As shown in fig. 4a, in the range where the first electrode 121 corresponds to the channel layer 122, the isolation dielectric layer 124 surrounds the first electrode 121, the channel layer 122 surrounds the isolation dielectric layer 124, the electrode structure 123 (shown here as an electrode layer) surrounds the channel layer 122, the cross section of the first electrode 121 may be circular, and the cross section of the channel layer 122, the cross section of the electrode structure 123, and the cross section of the isolation dielectric layer 124 are all concentric circles. Wherein the intersection length of the surface of the channel layer 122 in contact with the electrode layer and the surface perpendicular to the first direction Z corresponds to the channel width W of the channel between two adjacent electrode layers. When the transistor device is provided with n electrode layers, n is more than or equal to 2, a channel exists between every two electrode layers, n-1 channels exist in the transistor device, which is equivalent to n-1 channel widths W, and the effective channel width W _{Total (S)} of the whole transistor device is approximately equal to (n-1) W; increasing the number of electrode layers along the first direction Z, within a reasonable size range of the transistor device, may increase the effective channel width W _{Total (S)}, which is advantageous for increasing the current level of the transistor device.

Referring to fig. 3 and fig. 4a, in the transistor device according to the embodiment of the present application, from the final structural aspect, the electrode structure 123 and the channel layer 122 are equivalent to form a pocket structure having an accommodating space, where the accommodating space has an opening, and the opening faces the base M of the first electrode 121, and the accommodating space is used for accommodating the first electrode 121. The channel layer 122 corresponds to an inner structure layer of the pocket structure, the electrode structure 123 corresponds to an outer structure layer of the pocket structure, and the electrode structure 123 is wrapped outside the channel layer 122. And in the structure shown in fig. 3 and 4a, each electrode layer (e.g., the first electrode layer, the second electrode layer, and the third electrode layer) and the electrode dielectric layer (e.g., the first dielectric layer and the second dielectric layer) in the electrode structure 123 are ring-shaped and surround the outside of the channel layer 122. Fig. 4B shows another cross-sectional structure of the transistor device of fig. 2, taken along the B-plane, similar to the structure shown in fig. 4a, with an isolation dielectric layer 124 surrounding the first electrode 121, a channel layer 122 surrounding the isolation dielectric layer 124, and an electrode structure 123 (shown here as an electrode layer) surrounding the channel layer 122. In this transistor device, the cross section of the first electrode 121 may be rectangular, and the cross section of the isolation dielectric layer 124, the cross section of the channel layer 122, and the cross section of the electrode structure 123 are square rings. It should be understood that the cross-section of the first electrode 121 may also be other polygons (e.g., a hexagon as shown in fig. 4 c), and the cross-section of the isolation dielectric layer 124, the cross-section of the channel layer 122, and the cross-section of the electrode structure 123 may be polygonal rings corresponding to the shape of the first electrode 121. The cross-section of the first electrode 121 may also be of other irregular shape (e.g. parabolic like shape as shown in fig. 4 d), the cross-section of the isolation dielectric layer 124, the cross-section of the channel layer 122 and the cross-section of the electrode structure 123 being irregularly shaped rings corresponding to the shape of the first electrode 121. Of course, the cross section of the isolation dielectric layer 124, the cross section of the channel layer 122, and the cross section of the electrode structure 123 may not correspond to the shape of the first electrode 121 (for example, the cross section of the first electrode 121 is circular, and the cross section of the isolation dielectric layer 124, the cross section of the channel layer 122, and the cross section of the electrode structure 123 are square rings), which are not described herein.

Fig. 5a to 5d show schematic cross-sectional structures of other transistor devices after being cut by the a-plane. In the transistor device shown in fig. 5a, an isolation dielectric layer 124 covers the surface of the first electrode 121 facing the channel layer 122, and the isolation dielectric layer 124 electrically isolates the electrode structure 123 from the first electrode 121. The channel layer 122 is located outside the isolation dielectric layer 124, and there is some structural intersection of the channel layer 122 with the electrode structure 123. The electrode structure 123 has a drain electrode 1232, a source electrode 1231, and a drain electrode 1232 sequentially distributed along the first direction Z, and structurally crossing the channel layer 122 and the electrode structure 123 means that: the drain 1232 and source 1231 closest to the substrate structure 11 are located outside the channel layer 122, and the drain 1232 closest to the pedestal M is located between the isolation dielectric layer 124 and the channel layer 122. The transistor arrangement shown in fig. 5b is compared with the transistor arrangement shown in fig. 5a, with the difference that: in fig. 5b the channel layer 122 is near the end face of the substrate structure 11, closest to the surface of the substrate structure 11 where the drain 1232 is facing the substrate structure 11, both lying in the same plane. In the transistor device shown in fig. 5c, an isolation dielectric layer 124 covers the surface of the first electrode 121 facing the channel layer 122, and the isolation dielectric layer 124 electrically isolates the electrode structure 123 from the first electrode 121. The channel layer 122 is located between the isolation dielectric layer 124 and the electrode structure 123, specifically, the channel layer 122 is disposed only on the circumferential outer surface of the first electrode 121, and does not cover the end portion of the first electrode 121 toward the substrate structure 11 in the first direction Z. On the side of the end of the first electrode 121 facing the substrate structure 11, the isolation dielectric layer 124 is in contact with the drain electrode 1232 closest to the substrate structure 11. In fig. 5d, in order to avoid diffusion of the electrode layer in the region in contact with the channel layer 122, and to reduce the fermi-pinning effect of the two contacts, an insulating layer 125 is provided between the electrode layer and the channel layer 122, and the presence of the insulating layer 125 may enable a metal-insulating layer-semiconductor structure to be formed between the electrode layer and the channel layer 122. Specifically, the thickness of the insulating layer 125 may be set to 0.1 to 2nm.

In some embodiments, the present application further provides a transistor device as shown in fig. 6. The first electrode 121 in the transistor device is similar to the first electrode 121 in the transistor device shown in fig. 3, i.e. the first electrode 121 is columnar and extends in the first direction Z. A pedestal M is also provided at the end of the first electrode 121 remote from the substrate structure 11, the pedestal M being parallel to the substrate structure 11. The channel layer 122 is disposed along the circumferential outer surface of the first electrode 121, but the channel layer 122 does not entirely encapsulate the circumferential outer surface of the first electrode 121, and the electrode structure 123 is disposed along the circumferential outer surface of the channel layer 122, but the electrode structure 123 does not entirely encapsulate the circumferential outer surface of the channel layer 122. The isolation dielectric layer 124 is disposed between the channel layer 122 and the first electrode 121, and between the channel layer 122 and the base M, and the isolation dielectric layer 124 can electrically isolate the first electrode 121 from the electrode structure 123. The electrode structure 123 includes at least two electrode layers arranged along the first direction Z, and electrical isolation is achieved between any two adjacent electrode layers through the electrode dielectric layer 1233, so as to prevent short circuit between the two adjacent electrode layers.

In fig. 6, the electrode structure 123 illustratively includes three electrode layers (one source electrode 1231 and two drain electrodes 1232), with the source electrode 1231 being located between the two drain electrodes 1232. An electrode dielectric layer 1233 is also disposed between the electrode layer closest to the pedestal M and the channel layer 122. In order to realize driving of the channel layer 122 by the first electrode 121, the first electrode 121 corresponds to the channel layer 122 between any two electrode layers along the second direction X perpendicular to the first direction Z.

The transistor device shown in fig. 6 is cut in the plane of B in fig. 2 to obtain a schematic cross-sectional structure shown in fig. 7a, in which the isolation dielectric layer 124 semi-surrounds the first electrode 121 in a range corresponding to the channel layer 122, the channel layer 122 semi-surrounds the isolation dielectric layer 124, and the electrode structure 123 (shown here as an electrode layer) semi-surrounds the channel layer 122. The intersection length of the surface of the channel layer 122 in contact with the electrode layer and the surface perpendicular to the first direction Z corresponds to the channel width W of the channel between any two adjacent electrode layers.

Referring to fig. 7B, a cross-sectional structure of another transistor device along the plane of B-B shown in fig. 6 may be referred to, and similar to the structure shown in fig. 7a, the isolation dielectric layer 124 semi-surrounds the first electrode 121, the channel layer 122 semi-surrounds the isolation dielectric layer 124, and the electrode structure 123 (shown here as an electrode layer) semi-surrounds the channel layer 122. In this transistor device, the cross section of the first electrode 121 is rectangular, and the cross section of the isolation dielectric layer 124, the cross section of the channel layer 122, and the cross section of the electrode structure 123 are all polygonal half rings.

It should be understood that the cross-section of the first electrode 121 may also be other polygonal shapes (e.g. as shown in fig. 7 c), and the cross-section of the isolation dielectric layer 124, the cross-section of the channel layer 122, and the cross-section of the electrode structure 123 are polygonal half-rings corresponding to the shape of the first electrode 121. The cross-section of the first electrode 121 may also be of other irregular shape (e.g. fan-like as shown in fig. 7 d), the cross-section of the isolation dielectric layer 124, the cross-section of the channel layer 122 and the cross-section of the electrode structure 123 being irregularly shaped rings corresponding to the shape of the first electrode 121. Of course, the cross section of the isolation dielectric layer 124, the cross section of the channel layer 122, and the cross section of the electrode structure 123 may not correspond to the shape of the first electrode 121, which is not described herein.

A cross-sectional structure along the plane of B-B based on another transistor device shown in fig. 6 may be shown with reference to fig. 7e, where the first electrode 121, the isolation dielectric layer 124, the channel layer 122 and the electrode structure 123 (here shown as electrode layers) are arranged along the second direction X. Here, the structures of the first electrode 121, the isolation dielectric layer 124, the channel layer 122, and the electrode structure 123 are regular, and the extending directions of the layers are parallel to the third direction Y and the first direction Z. Of course, the structures of the first electrode 121, the isolation dielectric layer 124, the channel layer 122, and the electrode structure 123 may also be irregular, and will not be described herein.

Note that, the transistor device shown in fig. 6 corresponds to one half of the transistor device shown in fig. 3 divided in half along the first direction Z, correspondingly, the transistor device shown in fig. 7a corresponds to one half of the transistor device shown in fig. 4a divided in half along the first direction Z, the transistor device shown in fig. 7b corresponds to one half of the transistor device shown in fig. 4b divided in half perpendicular to the second direction X, the transistor device shown in fig. 7c corresponds to one half of the transistor device shown in fig. 4c divided in half perpendicular to the second direction X, and the transistor device shown in fig. 7d corresponds to one half of the transistor device shown in fig. 4d divided in half perpendicular to the second direction X, which can be referred to each other.

Fig. 8 shows a schematic cross-sectional structure of another transistor device, which is cut by the a-plane, wherein the functional structure 12 specifically includes a first electrode 121, a channel layer 122, an electrode structure 123, and an isolation dielectric layer 124. In the transistor device, the electrode structure 123 includes at least two electrode layers stacked in sequence along a first direction Z and an electrode dielectric layer 1233 located between any two electrode layers, and specifically includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, and a third electrode layer stacked in sequence, where the first dielectric layer is used to isolate the first electrode layer from the second electrode layer and prevent the first electrode layer from shorting with the second electrode layer; the second dielectric layer is used for isolating the second electrode layer from the third electrode layer and preventing the second electrode layer from being short-circuited with the third electrode layer; the stacking direction corresponds to the first direction Z, and may be directed from the substrate structure 11 to the base M or from the base M to the substrate structure. The polarities of the first electrode layer and the third electrode layer are identical (both are source electrodes or drain electrodes), and the second electrode layer is opposite to the first electrode layer and the third electrode layer (when the first electrode layer and the third electrode layer are source electrodes, the second electrode layer is drain electrodes, and when the first electrode layer and the third electrode layer are drain electrodes, the second electrode layer is source electrodes). As shown in fig. 3, the first electrode layer and the third electrode layer are two drains 1232, the second electrode layer is one source 1231, and the first dielectric layer and the second dielectric layer are electrode dielectric layers 1233. In fig. 8, the electrode structure 123 other than the drain electrode 1232 closest to the substrate structure 11 is columnar and extends in the first direction Z. The channel layer 122 comprises a doped semiconductor material, the doped atoms being capable of providing carriers which may be used for conducting a current, the channel layer 122 being arranged outside the electrode structure 123 to be in contact with either one of the electrode layers. The first electrode 121 is wrapped outside the channel layer 122, and the isolation dielectric layer 124 is disposed between the first electrode 121 and the channel layer 122. The first electrode 121 may be used as a gate of the transistor device, and the first electrode 121 also has a pedestal M parallel to the substrate structure 11.

With continued reference to fig. 8, in the transistor device, the electrode structure 123 includes a first electrode layer (drain electrode 1232), a first dielectric layer (electrode dielectric layer 1233), a second electrode layer (source electrode 1231), a second dielectric layer (electrode dielectric layer 1233), and a third electrode layer (drain electrode 1232) arranged along the first direction Z, and any two adjacent electrode layers are electrically isolated by the electrode dielectric layer 1233, so as to prevent shorting between the two adjacent electrode layers. Wherein the first electrode layer and the third electrode layer (corresponding to the two drains 1232) are electrically connected by a connection structure (e.g., a wire, not shown here). The channel layer 122 is in contact with any one of the electrode layers, and two adjacent electrode layers (corresponding to one source electrode 1231 and one drain electrode 1232) may perform electron transport through the channel layer 122 between the two electrode layers under the driving of the first electrode 121 to form a channel current. Here, a distance between two adjacent electrode layers (corresponding to one source electrode 1231 and one drain electrode 1232) in the first direction Z corresponds to a channel length L of a channel between the two electrode layers. It should be appreciated that in order to achieve driving of the channel layer 122 by the first electrode 121, the first electrode 121 corresponds to the channel layer 122 between any two electrode layers along the second direction X perpendicular to the first direction Z.

It should be understood that the first electrode layer and the third electrode layer in fig. 8 may also be the source electrode 1231, and the second electrode layer is the drain electrode, which is not limited herein; and fig. 8 is equivalent to a structure showing the simplest transistor device provided by the embodiment of the present application, in specific application, the number of electrode layers may be more according to the transistor device structure, and only any two electrode layers need to be electrically isolated by the electrode dielectric layer 1233, and electrode layers with the same polarity are electrically connected. When the number of electrode layers serving as the source electrodes 1231 is 2 or more, any two source electrodes 1231 are electrically connected to each other, and can serve as source electrodes of the transistor device; when the number of electrode layers serving as the drain electrode 1232 is 2 or more, any two drain electrodes 1232 are electrically connected to each other, and can function as a drain electrode of the transistor device. For convenience of description, a certain electrode layer is directly referred to as a source electrode 1231 and a drain electrode 1232 hereinafter. It should be understood that the structure of the electrode layer, the electrode dielectric layer 1233, the channel layer 122, and the isolation dielectric layer 124 may be modified as needed, so long as the corresponding relationship between the first electrode 121 and the electrode structure 123 is satisfied.

Fig. 9a shows a schematic cross-sectional structure of the transistor device of fig. 8, taken through a B-plane perpendicular to the first direction Z and passing through one of the electrode layers. As shown in fig. 9a, the channel layer 122 surrounds the electrode structure 123 (here shown as an electrode layer) within the range where the first electrode 121 corresponds to the channel layer 122, the isolation dielectric layer 124 surrounds the channel layer 122, and the first electrode 121 surrounds the isolation dielectric layer 124. The intersection length of the surface of the channel layer 122 in contact with the electrode layer and the surface perpendicular to the first direction Z corresponds to the channel width W of the channel between any two adjacent electrode layers. When the transistor device has n electrode layers, n is greater than or equal to 2, a channel exists between every two electrode layers, the transistor device will have n-1 channels, which is equivalent to n-1 channel widths W, and the effective channel width W _{Total (S)} of the entire transistor device is equivalent to (n-1) W; increasing the number of electrode layers along the first direction Z, within a reasonable size range of the transistor device, may increase the effective channel width W _{Total (S)}, which is advantageous for increasing the current level of the transistor device.

Referring to fig. 8 and fig. 9a, in the transistor device according to the embodiment of the present application, the first electrode 121 and the channel layer 122 are equivalent to forming a pocket structure with a receiving space, where the receiving space has an opening facing the substrate structure 11, and the receiving space is used for receiving the electrode structure 123. The channel layer 122 corresponds to an inner structure layer of the pocket structure, the first electrode 121 corresponds to an outer structure layer of the pocket structure, and the first electrode 121 is wrapped around the channel layer 122. Fig. 9B shows another cross-sectional structure of the transistor device of fig. 8, taken along the B-plane, similar to the structure shown in fig. 9a, with the channel layer 122 surrounding the electrode structure 123 (here shown as an electrode layer), the isolation dielectric layer 124 surrounding the channel layer 122, and the first electrode 121 surrounding the isolation dielectric layer 124. In this transistor device, the cross section of the electrode structure 123 is rectangular, and the cross section of the isolation dielectric layer 124, the cross section of the channel layer 122, and the cross section of the first electrode 121 are square rings. It should be understood that the cross-section of the electrode structure 123 may also be other polygons (e.g., a hexagon as shown in fig. 9 c), and the cross-section of the isolation dielectric layer 124, the cross-section of the channel layer 122, and the cross-section of the first electrode 121 may be polygonal rings corresponding to the shape of the electrode structure 123. The cross-section of the electrode structure 123 may also be of other irregular shape (e.g. parabolic like shape as shown in fig. 9 d), the cross-section of the isolation dielectric layer 124, the cross-section of the channel layer 122 and the cross-section of the first electrode 121 being irregularly shaped rings corresponding to the shape of the electrode structure 123. Of course, in an alternative case, the cross section of the isolation dielectric layer 124, the cross section of the channel layer 122, and the cross section of the first electrode 121 do not correspond to the shape of the electrode structure 123 (e.g., the cross section of the electrode structure 123 is circular, and the cross section of the isolation dielectric layer 124, the cross section of the channel layer 122, and the cross section of the first electrode 121 are square rings), which will not be described herein.

In some embodiments, the present application further provides a transistor device as shown in fig. 10. In the transistor device shown in fig. 10, the electrode structure 123 is similar to the electrode structure 123 in the transistor device shown in fig. 8, and includes at least two electrode layers arranged along the first direction Z, and electrical isolation is achieved between any two adjacent electrode layers through the electrode dielectric layer 1233, so as to prevent shorting between the two adjacent electrode layers. The electrode structure 123 is columnar and extends in the first direction Z except for the drain electrode 1232 closest to the substrate structure 11. The channel layer 122 is disposed along a circumferential outer surface of the electrode structure 123 (i.e., an outer surface of the electrode structure 123 parallel to the first direction Z), but the channel layer 122 does not wrap around the circumferential outer surface of the electrode structure 123, the first electrode 121 is disposed along the circumferential outer surface of the channel layer 122 (i.e., an outer surface of the channel layer 122 parallel to the first direction Z), but the first electrode 121 does not wrap around the circumferential surface of the channel layer 122. An isolation dielectric layer 124 is disposed between the channel layer 122 and the first electrode 121, and the isolation dielectric layer 124 may electrically isolate the first electrode 121 from the electrode structure 123. In order to realize driving of the channel layer 122 by the first electrode 121, the first electrode 121 corresponds to the channel layer 122 between any two electrode layers along the second direction X perpendicular to the first direction Z.

The transistor device shown in fig. 10 is sectioned by the plane of B in fig. 2 to obtain a schematic cross-sectional structure shown in fig. 11a, where the channel layer 122 is semi-looped around the electrode structure 123 (herein shown as an electrode layer) within a range corresponding to the first electrode 121 and the channel layer 122, the isolation dielectric layer 124 is semi-looped around the channel layer 122, and the isolation dielectric layer 124 is semi-looped around the first electrode 121. The intersection length of the surface of the channel layer 122 in contact with the electrode layer and the surface perpendicular to the first direction Z corresponds to the channel width W of the channel between any two adjacent electrode layers.

Based on the cross-sectional structure of another transistor device along the plane of B-B shown in fig. 10, reference can be made to fig. 11B, where the channel layer 122 is semi-looped around the electrode structure 123 (here shown as an electrode layer) similar to the structure shown in fig. 11a, the isolation dielectric layer 124 is semi-looped around the channel layer 122, and the isolation dielectric layer 124 is semi-looped around the first electrode 121. In this transistor device, the cross section of the electrode structure 123 is rectangular, and the cross section of the isolation dielectric layer 124, the cross section of the channel layer 122, and the cross section of the first electrode 121 are all polygonal half rings. It should be understood that the cross-section of the electrode structure 123 may also be other zigzag shapes (e.g. as shown in fig. 11 c), and the cross-section of the isolation dielectric layer 124, the cross-section of the channel layer 122, and the cross-section of the first electrode 121 are polygonal semi-circles corresponding to the shape of the electrode structure 123. The cross-section of the electrode structure 123 may also be of other irregular shape (e.g. fan-like as shown in fig. 11 d), the cross-section of the isolation dielectric layer 124, the cross-section of the channel layer 122 and the cross-section of the first electrode 121 being irregularly shaped rings corresponding to the shape of the electrode structure 123. Of course, the cross section of the isolation dielectric layer 124, the cross section of the channel layer 122, and the cross section of the first electrode 121 may not correspond to the shape of the electrode structure 123, which is not described herein.

A cross-sectional structure along the plane of B-B based on another transistor device shown in fig. 10 may be shown with reference to fig. 11e, where the first electrode 121, the isolation dielectric layer 124, the channel layer 122, and the electrode structure 123 (shown here as electrode layers) are arranged along the second direction. Here, the structures of the first electrode 121, the isolation dielectric layer 124, the channel layer 122, and the electrode structure 123 are regular, and the extending directions of the layers are parallel to the third direction Y and the first direction Z. Of course, the structures of the first electrode 121, the isolation dielectric layer 124, the channel layer 122, and the electrode structure 123 may also be irregular, and will not be described herein.

Note that, the transistor device shown in fig. 10 corresponds to the half structure of the transistor device shown in fig. 8 divided in half perpendicular to the second direction X, correspondingly, the transistor device shown in fig. 11a corresponds to the half structure of the transistor device shown in fig. 9a divided in half perpendicular to the second direction X, the transistor device shown in fig. 11b corresponds to the half structure of the transistor device shown in fig. 9b divided in half perpendicular to the second direction X, the transistor device shown in fig. 11c corresponds to the half structure of the transistor device shown in fig. 9c divided in half perpendicular to the second direction X, and the transistor device shown in fig. 11d corresponds to the half structure of the transistor device shown in fig. 9b divided in half perpendicular to the second direction X, which can be referred to each other.

It should be understood that the cross-sectional structures shown in fig. 3 to 11e are all exemplary illustrations of the transistor device shown in fig. 2, and that other variations of the portions of the functional structure 12 are possible in the implementation, but the electrode structures 123 thereof each include a plurality of electrode layers arranged along the first direction Z and electrically isolated from each other, and the other first electrodes 121, the channel layer 122, the isolation dielectric layer 124, and other portions are all intended to implement the transistor function.

Illustratively, the electrode layer should be made of a conductive material, specifically a metal or other conductive compound, such as one or more of titanium, gold, tungsten, aluminum, copper, ruthenium, molybdenum, silver, platinum, or bismuth, and any one of the electrode layers may be in electrical contact with the channel layer 122.

The material of the first electrode 121 is also a conductive material, specifically a metal or other compounds with conductive function, such as one or more of titanium, gold, tungsten, aluminum, copper, ruthenium, molybdenum, silver, platinum, titanium nitride, indium tin oxide or indium zinc oxide; the isolation dielectric layer 124 may be made of one or more of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, and yttrium oxide, and may be made of a combination of materials doped (the second material is doped into the first material as a matrix as shown in fig. 12 a), a combination of stacked layers (the first material and the second material are alternately stacked as shown in fig. 12 b), or a combination of doped and stacked layers (the second material is doped into the first material as a matrix as shown in fig. 12 c), and the first material and the second material are alternately stacked. The material of the channel layer 122 may be one or more of metal oxide, multi-component compound, graphene, molybdenum disulfide, and black phosphorus, such as silicon-based semiconductor including silicon, polysilicon, and amorphous silicon, and metal oxide including indium oxide, zinc oxide, gallium oxide, indium tin oxide, and titanium oxide. The electrode dielectric layer 1233 may be made of the same material as the isolation dielectric layer 124.

In some embodiments, the distance between any two adjacent electrode layers may be set to be the same along the first direction Z, and in the process of manufacturing the electrode structure 123 of the transistor device, multiple electrode layers may be manufactured by using the same process, which is advantageous for simplifying the device manufacturing process, and such a structure is also advantageous for parameter calculation of the transistor device, i.e. n electrode layers, which may correspond to the transistor device having n-1 channel widths, and the channel current corresponds to multiplication.

Taking the transistor device shown in fig. 3 as an example, which has one source electrode 1231 and two drain electrodes 1232, the distance between any two electrode layers is set to be the same, so that the transistor device can form a channel width of 2 times. Simulation of the transistor device in the prior art and the transistor device provided by the embodiment of the present application can obtain the electrical characterization diagrams shown in fig. 13a and 13b, where the abscissa of the diagrams in fig. 13a and 13b is the voltage of the first electrode, the unit is volt (V), the ordinate is the channel current, and the unit is ampere (a). As shown in fig. 13a, in the conventional transistor device, the channel current is positively correlated with the first electrode voltage, but the rate of rise of the channel current is slow with the increase of the first electrode voltage, and when the first electrode voltage reaches 2V, the channel current reaches around 0.000024 a; in the transistor device provided by the embodiment of the application shown in fig. 13b, when the voltage of the first electrode is gradually increased, the channel current is obviously increased, and when the voltage of the first electrode reaches 2V, the channel current can reach about 0.00005A, which is equivalent to twice the channel current in the prior art. Compared with the prior art, the transistor device provided by the application can realize multiplication of working current under the condition that the original mobility, channel length, gate oxide thickness and other factors are unchanged, has the advantages of low cost, simple process and the like in the prior art, does not increase the area in the horizontal direction (vertical to the height direction of the transistor device, namely the first direction Z), and keeps the integration density.

It can be seen that, in the transistor device provided by the embodiment of the application, on the basis of not increasing the unit area of the device, a plurality of equivalent channels can be obtained by adding the electrode layer (i.e. alternately adding the source electrode and the drain electrode), so that the effective channel width of the whole transistor device is improved, and the output current of the device is improved. The transistor device is applied to the gain cell memory as a reading transistor, so that the reading efficiency can be improved. Of course, the transistor arrangement may also be applied in situations where logic, analog, radio frequency circuits, etc. are required to provide different transistor width choices.

The embodiment of the present application further provides an electronic device as shown in fig. 14, which is exemplified by a memory, and includes a signal writing transistor 1, a reading transistor 2, a memory cell 3, a first writing signal line 41, a second writing signal line 42, a first reading signal line 51, and a second reading signal line 52, where the reading transistor 2 may be any of the transistor devices provided in the foregoing embodiments.

Specifically, the first write signal line 41 is connected to the first electrode of the signal write transistor 1, and the second write signal line 42 is connected to the source of the write transistor 1; the first read signal line 51 is connected to the source (or drain) of the read transistor 2, and the second read signal line 52 is connected to the drain (or source) of the read transistor 2; the drain of the write transistor 1 is connected to the first electrode structure of the read transistor 2, and the memory cell 3 is connected between the write transistor 1 and the read transistor 2.

In the operation of writing, the first writing signal line 41 controls the writing transistor 1 to be turned on, and the potential of the second writing signal line 42 is transferred to the first electrode of the reading transistor 2, so that the potential of the first electrode of the reading transistor 2 is synchronous with the potential of the second writing signal line 42 to realize writing of 0 and 1; then, the first write signal line 41 controls the write transistor 1 to be turned off, and the first electrode potential of the read transistor 2 is determined by the amount of electricity stored in the memory cell 3. In the "read" operation, the memory state can be determined by only reading the current change of the read transistor 2 or the voltage change of the second read signal line 52. Since the read transistor 2 has a large current, the memory has a high read rate when the signal is read.

As shown in fig. 3 and 8, there may be at least two structures of the transistor device, and the manufacturing method of the transistor device may have different embodiments for different structures of the transistor device.

The embodiment of the application provides a preparation method of a transistor device, which is used for preparing the transistor device shown in fig. 3. As shown in fig. 15, the preparation method includes:

Step S11: alternately disposing electrode layers and electrode dielectric layers 1233 in sequence on the substrate structure 11 along the first direction Z to form an electrode structure 123, resulting in the structure shown in fig. 16; the number of the electrode layers is at least two, and the at least two electrode layers include at least one source electrode 1231 and at least one drain electrode 1232 which are alternately arranged, and when the number of the source electrodes 1231 is at least two, any two source electrodes 1231 are electrically connected, and when the number of the drain electrodes 1232 is at least two, any two drain electrodes 1232 are electrically connected.

The electrode structure 123 is specifically implemented by sequentially laying an electrode layer and an electrode dielectric layer 1233. The order of the source electrode 1231 and the drain electrode 1232 in the fabrication is not limited, but they must be alternately fabricated, and eventually, adjacent ones of the source electrode 1231 and the drain electrode 1232 correspond to one channel. When the number of the source electrodes 1231 is greater than or equal to two, any two source electrodes 1231 are electrically connected to form a source electrode of the entire transistor device; when the number of the drains 1232 is equal to or greater than two, any two of the drains 1232 are electrically connected to form the drain of the entire transistor device. It should be appreciated that the electrical connection between any two sources 1231 may be made by external wiring (corresponding to a connection structure), not shown here; similarly, the electrical connection between any two drains 1232 may be made by external wiring (corresponding to a connection structure), not shown here.

Step S12: etching the electrode structure 123 to form a first groove K1 extending along the first direction Z, the first groove K1 communicating with each electrode layer, resulting in the structure shown in fig. 17 a;

Step S13: a channel layer 122 is formed in the first groove K1, and a second groove K2 is formed in the channel layer 122, resulting in the structure shown in fig. 17 b. To this end, the electrode structure 123 and the channel layer 122 form a structure corresponding to a pocket structure, and the second groove K2 corresponds to an accommodating space of the pocket structure.

Wherein, when the channel layer 122 is filled in the first groove K1, the channel layer 122 may be etched along the first direction Z to form a second groove K2; when the channel layer 122 is attached to the inner surface of the first groove K1, the second groove K2 may be naturally formed on the side of the channel layer 122 facing away from the inner surface of the first groove K1.

Step S14: forming a first electrode 121 in the second groove K2; specifically, the isolation dielectric layer 124 may be formed in the second groove K2, and the isolation dielectric layer 124 may be formed with the third groove K3, to obtain the structure shown in fig. 17 c; when the isolation dielectric layer 124 is filled in the second groove K2, the isolation dielectric layer 124 may be etched along the first direction Z to form a third groove K3; when the isolation dielectric layer 124 is attached to the inner surface of the second groove K2, the third groove K3 may be naturally formed on the side of the isolation dielectric layer 124 facing away from the inner surface of the first groove K2. Then, the third groove K3 is filled with the first electrode material to form the first electrode 121, resulting in the structure shown in fig. 3. The first electrode 121 further has a base M.

It will be appreciated that this method may also be employed in the preparation of the transistor device structures shown in fig. 5c and 6. In preparing the structures of fig. 5a and fig. 5b, the structures of the partial electrode layer, the electrode dielectric layer 1233, the channel layer 122 and the isolation dielectric layer 124 need to be adjusted, which is not described herein, but only needs to satisfy the corresponding relationship between the first electrode 121 and the electrode structure 123.

The embodiment of the application provides a preparation method of a transistor device, which is used for preparing the transistor device shown in fig. 8. As shown in fig. 18, the preparation method includes:

for the transistor structure shown in fig. 8, the preparation method after the step S1 specifically includes:

Step S21: alternately disposing electrode layers and electrode dielectric layers 1233 in sequence on the substrate structure 11 along the first direction Z to form an electrode structure 123, resulting in the structure shown in fig. 16; the number of the electrode layers is at least two, and the at least two electrode layers include at least one source electrode 1231 and at least one drain electrode 1232 which are alternately arranged, and when the number of the source electrodes 1231 is at least two, any two source electrodes 1231 are electrically connected, and when the number of the drain electrodes 1232 is at least two, any two drain electrodes 1232 are electrically connected. This step S21 is similar to step S11 above and will not be described here again.

Step S22: forming a channel layer 122 outside the electrode structure 123; specifically, the structure shown in fig. 16 may be etched to form the structure shown in fig. 19a, so that the electrode structure 123 except for the drain electrode 1232 closest to the substrate structure 11 is columnar, and then a channel material is deposited on the outer side of the electrode structure 123 to form the channel layer 122, so that the structure shown in fig. 19b is obtained, and the channel layer 122 is also columnar.

Step S23: forming a first electrode 121 outside the channel layer 122; before forming the first electrode 121, forming an isolation dielectric layer 124 on the outer side of the channel layer 122 to obtain the structure shown in fig. 19 c; then, an electrode material is deposited on the outer side of the isolation dielectric layer 124 to form a first electrode 121, resulting in the structure shown in fig. 8.

It will be appreciated that this approach may also be employed in preparing the transistor device structure shown in fig. 10. The structures of the partial electrode layer, the electrode dielectric layer 1233, the channel layer 122, and the isolation dielectric layer 124 may be adjusted as necessary, and the correspondence between the first electrode 121 and the electrode structure 123 may be satisfied.

The foregoing is merely illustrative embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present application, and the application should be covered. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims

A transistor device, comprising: a substrate structure, a channel layer disposed on the substrate structure, a first electrode, and an electrode structure;

The electrode structure comprises at least two electrode layers arranged along a first direction, wherein the electrode layers are electrically isolated from each other, and the first direction is perpendicular to the substrate structure; along the first direction, the at least two electrode layers include at least one source electrode and at least one drain electrode alternately arranged; when the number of the source electrodes is at least two, any two source electrodes are electrically connected; when the number of the drain electrodes is at least two, any two drain electrodes are electrically connected;

the channel layer is positioned between the first electrode and the electrode structure, and the channel layer is in contact with any one of the electrode layers.
The transistor device of claim 1, wherein the channel layer is disposed outside of the first electrode and the electrode structure is disposed outside of the channel layer.
The transistor device of claim 2, wherein a projection of the channel layer onto the substrate structure covers a projection of the first electrode onto the substrate structure towards an end of the substrate structure.
The transistor device of claim 1, wherein the channel layer is disposed outside of the electrode structure and the first electrode is disposed outside of the channel layer.
The transistor device of claim 4, wherein a projection of the channel layer onto the substrate structure covers a projection of an end of the electrode structure away from the substrate structure onto the substrate structure.
The transistor device of any one of claims 1-5, further comprising an isolation dielectric layer disposed between the first electrode and the channel layer.
The transistor device according to any one of claims 1 to 6, wherein a contact interface of each of the electrode layers and the channel layer is provided with an insulating layer.
The transistor device of claim 7, wherein the insulating layer has a thickness of 0.1-2 nm.
The transistor device according to any one of claims 1 to 7, wherein the first electrode extends in the first direction.
The transistor device according to any one of claims 1 to 9, wherein a distance between any two adjacent electrode layers is the same in the first direction.
The transistor device according to any one of claims 1-10, wherein the electrical isolation between any two adjacent electrode layers comprises: an isolation medium layer is arranged between any two adjacent electrode layers.
The transistor device according to any one of claims 1 to 11, wherein the electrode layer is made of one or more of titanium, gold, tungsten, aluminum, copper, ruthenium, molybdenum, silver, platinum, bismuth, titanium nitride, tungsten nitride, indium tin oxide, and indium zinc oxide.
The transistor device according to any one of claims 1 to 12, wherein the first electrode is made of one or more of titanium, gold, tungsten, aluminum, copper, ruthenium, molybdenum, silver, platinum, titanium nitride, indium tin oxide, or indium zinc oxide.
The transistor device of any one of claims 1-13, wherein the channel layer is made of one or more of a poly-compound, graphene, molybdenum disulfide, or black phosphorus.
A transistor device, comprising:

A first electrode;

The pocket structure comprises an inner structure layer and an outer structure layer, wherein the inner structure layer comprises a doped semiconductor material, and the inner structure layer surrounds a pocket and is used for accommodating the first electrode; the outer structural layer is wrapped outside the inner structural layer; the outer structure layer comprises a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer and a third electrode layer which are sequentially stacked, and the first electrode layer, the first dielectric layer, the second electrode layer, the second dielectric layer and the third electrode layer are annular and encircle the inner structure;

And a connection structure for electrically connecting the first electrode layer and the third electrode layer.
The transistor device of claim 15, wherein the second electrode and the fourth electrode are both sources and the first electrode layer is a drain; or alternatively, the first and second heat exchangers may be,

The second electrode and the fourth electrode are drain electrodes, and the third electrode is a source electrode.
The transistor device of claim 15 or 16, further comprising an isolation dielectric layer disposed outside the first electrode, the isolation dielectric layer being located between the first electrode and the inner structural layer.
The transistor device of any of claims 15-17, wherein the first dielectric layer and the second dielectric layer are the same material.
An electronic device comprising a write transistor, a read transistor, a memory cell, a first write signal line, a second write signal line, a first read signal line, and a second read signal line, the read transistor being the transistor arrangement of any of claims 1-14 or claims 15-18;

The first write signal line is connected with a first electrode of the write transistor, and the second write signal line is connected with a source electrode of the write transistor; the first reading signal line is connected with the source electrode of the reading transistor, and the second reading signal line is connected with the drain electrode of the reading transistor;

The drain of the write transistor is connected to the first electrode of the read transistor, and the memory cell is connected between the write transistor and the read transistor.
A method of manufacturing a transistor device, comprising:

Sequentially and alternately arranging electrode layers and isolation medium layers on the substrate structure along a first direction to form an electrode structure; the electrode layers are at least two, and the at least two electrode layers comprise at least one source electrode and at least one drain electrode which are alternately arranged; when the number of the source electrodes is at least two, any two source electrodes are electrically connected; when the number of the drain electrodes is at least two, any two drain electrodes are electrically connected;

Etching the electrode structure to form a first groove extending along the first direction, wherein the first groove is communicated with each electrode layer;

Forming a channel layer in the first groove, wherein the channel layer forms a second groove;

the first electrode is formed in the second groove.
The method of manufacturing a transistor device according to claim 20, further comprising an isolation dielectric layer disposed on a surface of the first electrode, the isolation dielectric layer being between the first electrode and the channel layer; the forming the first electrode in the second groove includes:

forming the isolation medium layer in the second groove, wherein the isolation medium layer forms a third groove;

The first electrode is formed in the third groove.
A method of manufacturing a transistor device, comprising:

Arranging an electrode layer and an isolation medium layer along a first direction to form an electrode structure; the electrode layers are at least two, and the at least two electrode layers comprise at least one source electrode and at least one drain electrode which are alternately arranged; when the number of the source electrodes is at least two, any two source electrodes are electrically connected; when the number of the drain electrodes is at least two, any two drain electrodes are electrically connected;

Forming a channel layer outside the electrode structure;

a first electrode is formed outside the channel layer.
The method of manufacturing a transistor device according to claim 22, wherein the transistor device further comprises an isolation dielectric layer, the isolation dielectric layer is disposed on a surface of the first electrode, and the isolation dielectric layer is located between the first electrode and the channel layer; the forming the first electrode on the surface of the channel layer includes:

Forming the isolation medium layer outside the channel layer;

And forming the first electrode on the outer side of the isolation medium layer.