CN117915653A - Memory cell structure, preparation method thereof, read-write circuit and memory - Google Patents
Memory cell structure, preparation method thereof, read-write circuit and memory Download PDFInfo
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The present disclosure relates to a memory cell structure and a method of manufacturing the same, a read-write circuit and a memory, the memory cell structure including a substrate, an isolation structure, a floating body cell structure, a channel structure, a first gate structure and a second gate structure; the isolation structure is formed on the surface of the substrate; the floating body unit structure is positioned on the surface of the isolation structure, which is far away from the substrate, and extends along the first direction; the channel structure is partially overlapped with the floating body unit structure and comprises a first part positioned on the outer surface of the floating body unit structure, a second part and a third part positioned on two opposite sides of the floating body unit structure along the second direction; the first gate structure is positioned on the surface of the first part far away from the substrate; the second grid structure is formed at one end of the floating body unit structure along the first direction and is mutually insulated with the first grid structure, so that the increase of the volume and the power consumption of the memory cell caused by a refreshing circuit is avoided, and the reliability, the response speed and the storage density of the semiconductor memory device are improved.
Description
Technical Field
The present disclosure relates to the field of integrated circuit design and manufacturing technology, and in particular, to a memory cell structure, a manufacturing method thereof, a read-write circuit and a memory.
Background
With the continued development of integrated circuit fabrication processes, the market has placed higher demands on the performance and size of semiconductor products. For semiconductor memory devices, how to ensure that the power consumption of the product is not increased and the response speed and the storage density are not reduced while the device size is reduced is one of the targets that related developers continuously pursue.
However, in the conventional dynamic random access memory, the memory cell is made of a single transistor and a single capacitor, and for the semiconductor memory device of this structure, the reading consumes the capacity of the capacitor, resulting in a reduction in response speed. Even if reading is not performed, charges may leak from the capacitor through the transistor, resulting in a decrease in reliability of the semiconductor memory device. Therefore, the memory cells of the single transistor and the single capacitor need to be periodically refreshed to hold data, resulting in an increase in power consumption of the device. In addition, the refresh circuit occupies the volume of the memory cell, which hinders the size reduction of the dynamic random access memory.
Disclosure of Invention
Based on the above, the present disclosure provides a memory cell structure, a method for manufacturing the same, a read-write circuit and a memory, which can at least avoid the increase of the volume and power consumption of a memory cell caused by a refresh circuit, avoid the decrease of the reliability of a semiconductor memory device caused by the leakage of charges of the memory cell, and improve the response speed and the memory density of the semiconductor memory device.
To solve the above technical problems and other problems, according to some embodiments, an aspect of the present disclosure provides a memory cell structure including a substrate, an isolation structure, a floating body cell structure, a channel structure, a first gate structure, and a second gate structure; the isolation structure is formed on the surface of the substrate; the floating body unit structure is positioned on the surface of the isolation structure, which is far away from the substrate, and extends along the first direction; the channel structure partially overlaps and is insulated from the floating body cell structure, the channel structure configured to: the floating body unit structure comprises a first part positioned on the outer surface of the floating body unit structure, a second part and a third part positioned on two opposite sides of the floating body unit structure along a second direction, wherein the second part and the third part are electrically connected with the first part and are positioned on the surface of the isolation structure far away from the substrate, and the second direction is intersected with the first direction; the first gate structure is positioned on the surface of the first part far away from the substrate; the second gate structure is formed at one end of the floating body unit structure along the first direction and is insulated from the first gate structure.
In the memory cell structure of the above embodiment, by sequentially disposing the isolation structure, the floating body cell structure, the channel structure, the first gate structure, and the second gate structure on the substrate, charges can be stored in the floating body cell structure, and a current flows between the floating body cell structure and the channel structure to realize a memory function of the memory cell, while avoiding leakage of charges; the embodiment reduces the power consumption of the semiconductor memory device, reduces the volume of the memory cell on the premise of ensuring the memory capacity of the semiconductor memory device, and improves the response speed and the memory density of the semiconductor memory device due to the relative reduction of the volume of the single capacitor structure and the reduction of the power consumption of the peripheral circuit.
In some embodiments, the first, second and third portions of the channel structure are integrally formed structures fabricated using the same process steps, with an insulating layer between the first portion of the channel structure and the floating body cell structure.
In some embodiments, the first gate structure includes a first gate dielectric layer and a first gate conductive layer; the first gate dielectric layer at least covers the outer surface of the channel structure; the first gate conductive layer is positioned on the surface of the first gate dielectric layer, which is far away from the substrate, and covers at least the surface of the first part of the floating body unit structure, which is far away from the substrate.
In some embodiments, the memory cell structure further includes a target protection structure covering an exposed outer surface of the floating body cell structure configured to: the target protection structure comprises a first oxide protection layer, a nitride protection layer and a second oxide protection layer, wherein the first oxide protection layer is formed on the outer surface of the floating body unit structure, the nitride protection layer is located on the surface of the first oxide protection layer, which is far away from the floating body unit structure, and the second oxide protection layer is located on the surface of the nitride protection layer, which is far away from the floating body unit structure, and the top surface of the second oxide protection layer is flush with the top surface of the first gate conductive layer.
In some embodiments, the second gate structure includes a second gate conductive layer and a second gate dielectric layer; the second gate conducting layer and the first gate conducting layer are prepared in the same process step and are positioned at one end face of the floating body unit structure; the second gate dielectric layer is a portion of the second oxide protection layer located between the end face and the second gate conductive layer.
In some embodiments, the memory cell structure further includes a first gate electrode structure, a second gate electrode structure, a source electrode structure, and a drain electrode structure; the first gate electrode structure is positioned on the top surface of the first gate conductive layer; the second gate electrode structure is positioned on the top surface of the second gate conductive layer; the source electrode structure is positioned on the top surface of the second part of the channel structure; the drain electrode structure is located on a top surface of the third portion of the channel structure.
In some embodiments, the isolation structure includes a first oxide isolation layer, a nitride isolation layer, and a second oxide isolation layer; the first oxide isolation layer is positioned on the surface of the substrate; the nitride isolation layer is positioned on the surface of the first oxide isolation layer, which is far away from the substrate; the second oxide isolation layer is positioned on the surface of the nitride isolation layer away from the substrate.
In some embodiments, the material of the channel structure comprises polysilicon, indium gallium zinc oxide, indium gallium arsenide, gallium nitride, or combinations thereof; the material of the floating body cell structure includes doped polysilicon.
According to some embodiments, another aspect of the present disclosure provides a read-write circuit, including the memory cell structure of any one of the above embodiments, configured to: the first grid structure is electrically connected with the read word line; the second grid structure is electrically connected with the writing wire; a second portion of the channel structure is electrically connected to the read bit line; a third portion of the channel structure is electrically connected to the write bit line; during the write state: controlling the write line to provide a first level signal to the second gate structure such that the floating body cell structure captures and stores electrons, written with a first value; controlling the writing line to provide a second level signal to the second grid structure and the reading line to provide a third level signal to the first grid structure, so that the electrons stored in the floating body unit structure are reset and written with a second value, and the amplitude of the second level signal is smaller than that of the first level signal; during the read state: the control word line provides a third level signal to the first gate structure, reads a first value according to the acquired first drain current determination, reads a second value according to the acquired second drain current determination, and the amplitude of the first drain current is smaller than that of the second drain current.
In the read-write circuit of the above embodiment, the first gate structure and the second gate structure are electrically connected with the word line, the channel structure is electrically connected with the bit line, the control word line provides level signals for the first gate structure and the second gate structure, electrons in the floating body unit structure flow, and drain current is obtained, so that the storage function and the read-write function of the storage unit are realized, and meanwhile, charge leakage is avoided; the embodiment reduces the power consumption of the semiconductor memory device, reduces the volume of the memory cell on the premise of ensuring the memory capacity of the semiconductor memory device, and improves the response speed and the memory density of the semiconductor memory device due to the relative reduction of the volume of the single capacitor structure and the reduction of the power consumption of the peripheral circuit.
In some embodiments, the plurality of memory cell structures are arranged in a plurality of rows and columns configured to: the memory cell structures in the same row are connected to the same read word line and the same write word line; the memory cell structures in the same column are all connected to the same read bit line and the same write bit line; the memory cell structures in two adjacent rows are connected to different read word lines and different write word lines; the memory cell structures in two adjacent columns are connected to different read bit lines and different write bit lines.
In some embodiments, the first value is "0" and the second value is "1", thereby implementing the read-write function of the read-write circuit for the values "0" and "1".
According to some embodiments, a further aspect of the present disclosure provides a memory comprising the read-write circuit of any one of the above embodiments.
According to some embodiments, a further aspect of the present disclosure provides a read-write circuit control method, the read-write circuit including the memory cell structure of any one of the above embodiments, the memory cell structure being configured to: the first gate structure is electrically connected with the read word line, the second gate structure is electrically connected with the write word line, the second part of the channel structure is electrically connected with the read bit line, and the third part of the channel structure is electrically connected with the write bit line; the read-write control method comprises the following steps: during the write state: controlling the write line to provide a first level signal to the second gate structure such that the floating body cell structure captures and stores electrons, written with a first value; or controlling the writing line to provide a second level signal to the second grid structure and the reading line to provide a third level signal to the first grid structure, so that the electrons stored in the floating body unit structure are reset and written with a second value, and the amplitude of the second level signal is smaller than that of the first level signal; during the read state: the control word line provides a third level signal to the first gate structure, reads a first value according to the acquired first drain current determination, reads a second value according to the acquired second drain current determination, and the amplitude of the first drain current is smaller than that of the second drain current.
In the read-write circuit control method of the above embodiment, the write word line is controlled to provide the level signals to the first gate structure and the second gate structure, so that electrons in the floating body unit structure flow, thereby realizing the storage function and the writing function of the storage unit; providing a level signal and acquiring drain current to the first grid structure by controlling a read word line, so that the reading function of the memory cell is realized; the embodiment reduces the power consumption of the semiconductor memory device, reduces the volume of the memory cell on the premise of ensuring the memory capacity of the semiconductor memory device, and improves the response speed and the memory density of the semiconductor memory device due to the relative reduction of the volume of the single capacitor structure and the reduction of the power consumption of the peripheral circuit.
According to some embodiments, still another aspect of the present disclosure provides a memory cell structure fabrication method, including: providing a substrate; forming an isolation structure on the surface of the substrate; forming a floating body unit structure extending along a first direction on the surface of the isolation structure away from the substrate; forming a channel structure partially overlapping the floating body cell structure, the channel structure including a first portion located on an outer surface of the floating body cell structure, and a second portion and a third portion located on opposite sides of the floating body cell structure in a second direction, the second portion and the third portion both being electrically connected to the first portion and both being located on a surface of the isolation structure remote from the substrate; the second direction intersects the first direction; a first gate structure is formed on a surface of the first portion, which is away from the substrate, and a second gate structure is formed on one end of the floating body unit structure along the first direction, wherein the second gate structure and the first gate structure are mutually insulated.
In the method for manufacturing the memory cell structure in the above embodiment, by sequentially forming the isolation structure, the floating body cell structure, the channel structure, the first gate structure and the second gate structure on the substrate, charges can be stored in the floating body cell structure, and a current flows between the floating body cell structure and the channel structure to realize the storage function of the memory cell, and meanwhile, charge leakage is avoided.
In some embodiments, the memory cell structure fabrication method further comprises: the outer surface of the floating body unit structure is covered with an initial protection structure; forming a channel structure that partially overlaps with the floating body cell structure includes: removing part of the initial protection structure to obtain a target protection structure with the middle part exposed out of the floating body unit structure, and forming an insulating layer on the exposed outer surface of the floating body unit structure; the channel structure is formed to cover the outer surface of the insulating layer, and comprises a first part covering the outer surface of the floating body unit structure, and a second part and a third part which are positioned on two opposite sides of the floating body unit structure along the second direction.
In some embodiments, the target protection structure includes a first oxide protection layer, a nitride protection layer and a second oxide protection layer, the first oxide protection layer is formed on an outer surface of the floating body cell structure, the nitride protection layer is located on a surface of the first oxide protection layer away from the floating body cell structure, and the second oxide protection layer is located on a surface of the nitride protection layer away from the floating body cell structure; forming a first gate structure on a surface of the first portion away from the substrate, and forming a second gate structure on one end of the floating body cell structure along the first direction, comprising: forming a first gate dielectric layer covering the outer surface of the channel structure; forming a first gate conductive layer on the surface of the first gate dielectric layer, which is far away from the substrate, and forming a second gate conductive layer on one end of the floating body unit structure, wherein the first gate conductive layer at least covers the surface, far away from the substrate, of the first part of the floating body unit structure; the top surface of the first gate conducting layer is flush with the top surface of the second oxide protective layer, and the first gate dielectric layer and the first gate conducting layer form a first gate structure; the part of the second oxide protective layer between the end face and the second gate conductive layer forms a second gate dielectric layer, and the second gate dielectric layer and the second gate conductive layer form a second gate structure.
In some embodiments, the memory cell structure fabrication method further comprises: removing the part of the first gate dielectric layer on the top surface of the second part of the channel structure to obtain a first via hole exposing the top surface of the second part; removing the part of the first gate dielectric layer positioned on the top surface of the third part of the channel structure to obtain a second via hole exposing the top surface of the third part; forming a source electrode structure penetrating the first via hole and in contact connection with the top surface of the second part; and forming a drain electrode structure penetrating the second via hole and in contact connection with the top surface of the third part.
In some embodiments, the memory cell structure fabrication method further comprises: forming a first gate electrode structure on the top surface of the first gate conductive layer; and forming a second gate electrode structure on the top surface of the second gate conductive layer.
In some embodiments, the memory cell structure fabrication method further comprises: forming an isolation structure on a surface of a substrate, comprising: forming a first oxide isolation layer on the surface of the substrate; forming a nitride isolation layer on the surface of the first oxide isolation layer away from the substrate; a second oxide isolation layer is formed on the surface of the nitride isolation layer away from the substrate.
In some embodiments, the memory cell structure fabrication method further comprises: the materials of the channel structure include: polysilicon, indium gallium zinc oxide, indium gallium arsenide, gallium nitride, or combinations thereof; the material of the floating body cell structure includes doped polysilicon.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic view of a memory cell structure according to an embodiment of the present disclosure;
FIG. 2 is a schematic cross-sectional view along the direction AA' of the schematic perspective view of FIG. 1;
FIG. 3 is a schematic cross-sectional view along BB' of the schematic perspective view of FIG. 1;
FIG. 4 is a schematic flow chart of a method for manufacturing a memory cell structure according to an embodiment of the disclosure;
FIGS. 5a to 5g are schematic views of three-dimensional structures obtained by different steps in a method for manufacturing a memory cell structure according to an embodiment of the present disclosure;
Fig. 6 is a schematic diagram of a read-write circuit according to an embodiment of the disclosure.
Reference numerals illustrate:
10. A substrate; 20. an isolation structure; 210. a first oxide isolation layer; 220. a nitride isolation layer; 230. a second oxide isolation layer; 30. a floating body cell structure; 310. an insulating layer; 301. a floating body cell structure sacrificial layer; 40. a channel structure; 410. A first portion of the channel structure; 420. a second portion of the channel structure; 430. a third portion of the channel structure; 510. a first gate structure; 511. a first gate dielectric layer; 512. a first gate conductive layer; 513. a first gate electrode structure; 520. a second gate structure; 521. a second gate dielectric layer; 522. a second gate conductive layer; 523. a second gate electrode structure; 60. a target protection structure; 601. an initial protection structure; 610. a first oxide protective layer; 620. a nitride protective layer; 630. a second oxide protective layer; 710. a source electrode structure; 720. and a drain electrode structure.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. Where the terms "comprising," "having," and "including" are used herein, another component may also be added unless a specifically defined term is used, such as "consisting of only," "… …," etc. Unless mentioned to the contrary, singular terms may include plural and are not to be construed as being one in number.
It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.
In the description of the present disclosure, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; the connection may be direct or indirect via an intermediate medium, or may be internal communication between two components. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art in the specific context.
In the description of the present disclosure, a "deposition" process includes, but is not limited to, one or more of physical vapor deposition (Physical Vapor Deposition, PVD for short), chemical vapor deposition (Chemical Vapor Deposition, CVD for short), atomic layer deposition (Atomic Layer Deposition, ALD for short), or the like. Note that the mutual insulation between the two described in the embodiments of the present disclosure includes, but is not limited to, the presence of one or more of an insulating material, an insulating breath, a gap, etc. between the two.
In order to better accommodate the demand for device scaling, the gradual transition of semiconductor processes from planar transistors to three-dimensional transistors with higher power efficiency, and in particular, the development of three-dimensional dynamic random access memory (3D Dynamic Random Access Memory,3D DRAM) technology has taken a significant place in the semiconductor memory device market. A conventional 3D DRAM memory cell is composed of a single transistor and a single capacitor (1T 1C structure), and a logic state is distinguished by whether or not a charge is stored on the capacitor, and for a semiconductor memory device of such a structure, the reading consumes the amount of electricity of the capacitor, resulting in a reduction in response speed. Even if reading is not performed, charges leak out from the capacitor, resulting in reduced reliability. Therefore, the memory cells of the single transistor and the single capacitor need to be regularly refreshed to hold data, resulting in an increase in power consumption. In addition, the refresh circuit occupies the volume of the memory cell, which hinders the size reduction of the dynamic random access memory. The current specific process of the traditional 1T1C 3D DRAM has small development, such as increased complexity of capacitor manufacturing process, increased risk of charge leakage, increased static power consumption and the like under small-size nodes.
The disclosure aims to provide a memory cell structure, a preparation method thereof, a read-write circuit and a memory, which can at least reduce charge leakage and power consumption of a memory cell and improve response speed, storage density and reliability of a semiconductor memory device.
Referring to fig. 1-3, in some embodiments, a memory cell structure is provided, the memory cell structure includes a substrate 10, an isolation structure 20, a floating body cell structure 30, a channel structure 40, a first gate structure 510, and a second gate structure 520; the isolation structure 20 is formed on the surface of the substrate 10; floating body cell structure 30 is located on a surface of isolation structure 20 remote from substrate 10 and extends in a first direction, which may be parallel to the OX direction, for example; the channel structure 40 and the floating body unit structure 30 are partially overlapped and insulated from each other, the channel structure 40 comprises a first part 410, a second part 420 and a third part 430, the first part 410 of the channel structure is positioned on the outer surface of the floating body unit structure 30, the second part 420 and the third part 430 of the channel structure are positioned on two opposite sides of the floating body unit structure 30 along the second direction, and the second part 420 and the third part 430 of the channel structure are electrically connected with the first part 410 of the channel structure and are positioned on the surface of the isolation structure 20 far away from the substrate 10; the second direction may be parallel to the OY direction, the second direction intersecting the first direction; for example, the angle between the first direction and the second direction may be 30 degrees, 45 degrees, 60 degrees, 75 degrees, 90 degrees, 135 degrees, 120 degrees, or the like; the first gate structure 510 is located at a surface of the first portion 410 remote from the substrate 10; the second gate structure 520 is formed at one end of the floating body cell structure 30 along the first direction and is insulated from the first gate structure 510.
With continued reference to fig. 1-2, in some embodiments, by sequentially disposing the isolation structure 20, the floating body cell structure 30, the channel structure 40, the first gate structure 510, and the second gate structure 520 on the substrate 10, charges can be stored in the floating body cell structure 30, and a current flows between the floating body cell structure 30 and the channel structure 40, thereby realizing the storage function of the storage unit, avoiding leakage of charges, reducing the power consumption of the semiconductor storage device due to relatively reducing the volume of the individual capacitor structure and reducing the power consumption of the peripheral circuit, and being capable of reducing the volume of the storage unit and improving the response speed and the storage density of the semiconductor storage device on the premise of ensuring the storage capability of the semiconductor storage device.
With continued reference to fig. 1-2, in some embodiments, an insulating layer 310 is disposed between the floating body cell structure 30 and the channel structure 40, and electrons may form an F-N tunneling effect between the floating body cell structure 30 and the channel structure 40, where the F-N tunneling effect (fowler-Nordheim Tunneling) refers to a potential barrier region into which microscopic particles can tunnel, which is not possible to enter according to classical mechanical rules, and is a basic effect reflecting the volatility of the microscopic particles; according to quantum mechanics theory, electrons have volatility, and the phenomenon of electron migration in a semiconductor or an insulator can be understood as electrons bound in one atom under an external electric field, so that the electrons have a probability of tunneling a potential barrier higher than the energy of the electrons per se into the other atom; in some embodiments, the insulating layer 310 forms a potential barrier, when a voltage is applied between the second gate structure 520 and the substrate 10, an electric field is generated in the insulating layer 310, and since the effective mass of holes and the interface potential barrier are larger than those of electrons, when the electric field in the insulating layer 310 reaches a certain intensity E and the insulating layer 310 reaches a certain thickness S, electrons can pass through the tunneling dielectric layer from the channel structure 40 into the floating body cell structure 30 to form an F-N tunneling effect, thereby forming a tunneling current; the electric field strength E of the insulating layer 310 may be set in a range of 10 megavolts per centimeter to 100 megavolts per centimeter, for example, E may be set to 10 megavolts per centimeter, 30 megavolts per centimeter, 50 megavolts per centimeter, 70 megavolts per centimeter, 90 megavolts per centimeter, 100 megavolts per centimeter, or the like; the thickness S of the insulating layer 310 may be set in a range of 1 nm to 10 nm, for example, S may be set to 1 nm, 2 nm, 4 nm, 6 nm, 8 nm, 10 nm, or the like; in some embodiments, the material of insulating layer 310 comprises polysilicon oxide, and a deposition process may be used to form insulating layer 310; since the occurrence speed of the tunnel effect is faster than the response speed of the conventional capacitor, there is no limitation of the transit time, and thus the response speed of the semiconductor memory device can be further improved.
Referring to fig. 2, in some embodiments, the first portion 410, the second portion 420, and the third portion 430 of the channel structure are integrally formed structures prepared by the same process steps, thereby simplifying the process flow.
Referring to fig. 2, in some embodiments, the first gate structure 510 includes a first gate dielectric layer 511 and a first gate conductive layer 512; the first gate dielectric layer 511 covers at least the outer surface of the channel structure 40; the first gate conductive layer 512 is located on a surface of the first gate dielectric layer 511 away from the substrate 10 and covers at least a surface of the first portion 410 of the channel structure on the floating body cell structure 30 away from the substrate 10; in some embodiments, the material of the first gate conductive layer 512 includes titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride, or a combination thereof; the material of the first gate dielectric layer 511 may include silicon oxide, aluminum oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide, or a combination thereof.
Referring to fig. 3, in some embodiments, the memory cell structure further includes a target protection structure 60, the target protection structure 60 covering an exposed outer surface of the floating body cell structure 30, configured to: the target protection structure 60 includes a first oxide protection layer 610, a nitride protection layer 620 and a second oxide protection layer 630, wherein the first oxide protection layer 610 is formed on the outer surface of the floating body cell structure 30, the nitride protection layer 620 is located on the surface of the first oxide protection layer 310 away from the floating body cell structure 30, and the second oxide protection layer 630 is located on the surface of the nitride protection layer 620 away from the floating body cell structure 30, wherein the top surface of the second oxide protection layer 630 is level with the top surface of the first gate conductive layer 512; in some embodiments, the nitride isolation layer 220 and the second oxide protection layer 630 are formed by a furnace Low Pressure Chemical Vapor Deposition (LPCVD) process, the first oxide protection layer 610 is formed by a thermal oxidation process, or the first oxide protection layer 610 and the second oxide protection layer 630 are formed by a thermal oxidation process, the nitride protection layer 620 is formed by a CVD deposition process, or the first oxide protection layer 610, the nitride protection layer 620 and the second oxide protection layer 630 may be formed in one step in the same machine, for example, by sequential deposition in a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. In some embodiments, the material of the first oxide protection layer 610 comprises silicon oxide, the material of the nitride protection layer 620 comprises silicon nitride, and/or the material of the second oxide protection layer 630 comprises silicon oxide. The target protection structure 60 is used to avoid charge leakage in the floating body cell structure 30, improve charge retention and reliability of the device, reduce power consumption and defect density of the device, and prolong failure average time.
Referring to fig. 2-3, in some embodiments, the second gate structure 520 includes a second gate conductive layer 522 and a second gate dielectric layer 521; the second gate conductive layer 522 is formed in the same process step as the first gate conductive layer 512, and the second gate conductive layer 522 is located at one end surface of the floating body cell structure 30; the second gate dielectric layer 521 is a portion of the second oxide protection layer 630 located between the end surface of the floating body cell structure 30 and the second gate conductive layer 522; in some embodiments, the material of the second gate conductive layer 522 includes titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride, or a combination thereof; the material of the second gate dielectric layer 521 includes silicon oxide, aluminum oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide, or a combination thereof. By adopting the double-grid structure which is transversely distributed, the on-resistance of the channel structure is reduced, the through-current capability and the control capability are enhanced, and the generation of leakage current is reduced.
Referring to fig. 2-3, in some embodiments, the memory cell structure further includes a first gate electrode structure 513, a second gate electrode structure 523, a source electrode structure 710, and a drain electrode structure 720; the first gate electrode structure 513 is located on the top surface of the first gate conductive layer 512; the second gate electrode structure 523 is located on the top surface of the second gate conductive layer 522; the source electrode structure 710 is located on top of the second portion 420 of the channel structure; the drain electrode structure 720 is located on the top surface of the third portion 430 of the channel structure, so that read-write control and/or performance test can be conveniently performed on the memory cell structure through the first gate electrode structure 513, the second gate electrode structure 523, the source electrode structure 710 and the drain electrode structure 720, and performance and reliability of the product are improved.
Referring to fig. 2-3, in some embodiments, the isolation structure 20 includes a first oxide isolation layer 210, a nitride isolation layer 220, and a second oxide isolation layer 230; the first oxide isolation layer 210 is located on the surface of the substrate 10; the nitride isolation layer 220 is located on a surface of the first oxide isolation layer 210 remote from the substrate 10; the second oxide isolation layer 230 is located on the surface of the nitride isolation layer 220 remote from the substrate 10. In some embodiments, the nitride isolation layer 220 and the second oxide isolation layer 230 are formed by a furnace Low Pressure Chemical Vapor Deposition (LPCVD) process, the first oxide isolation layer 210 is formed by a thermal oxidation process, or the first oxide isolation layer 210 and the second oxide isolation layer 230 are formed by a thermal oxidation process, the nitride isolation layer 220 is formed by a CVD deposition process, or the first oxide isolation layer 210, the nitride isolation layer 220 and the second oxide isolation layer 230 may be sequentially deposited in one station in the same machine, for example, by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. In some embodiments, the material of first oxide isolation layer 210 comprises silicon oxide, the material of nitride isolation layer 220 comprises silicon nitride and/or the material of second oxide isolation layer 230 comprises silicon oxide. The isolation structure 20 is used to avoid charge leakage in the floating body cell structure 30, improve charge retention and reliability of the device, reduce power consumption and defect density of the device, and prolong failure average time.
Referring to fig. 1-3, in some embodiments, the material of the channel structure 40 includes polysilicon, indium Gallium Zinc Oxide (IGZO), indium gallium arsenide (InGaAs), gallium nitride (GaN), or a combination thereof; the material of floating body cell structure 30 includes doped polysilicon. By adopting the materials, the problems of stress and doping of the traditional materials in the process of stacking are solved, so that the difficulty of a multilayer deposition process is reduced; as an example, the carrier mobility of IGZO is 20 to 30 times that of amorphous silicon, and the charge-discharge rate and response speed can be improved by adopting IGZO, so that a faster refresh frequency can be realized.
Referring to fig. 1-4, according to some embodiments, the disclosure provides a method for manufacturing a memory cell structure, including:
Step S10: providing a substrate 10;
step S20: forming an isolation structure 20 on the surface of the substrate 10;
Step S30: forming a floating body cell structure 30 extending in a first direction on a surface of the isolation structure 20 remote from the substrate 10;
Step S40: forming a channel structure 40 partially overlapping the floating body cell structure 30, the channel structure 40 including a channel structure first portion 410 located at an outer surface of the floating body cell structure 30, and a channel structure second portion 420 and a channel structure third portion 430 located at opposite sides of the floating body cell structure 30 in the second direction, the channel structure second portion 420 and the channel structure third portion 430 being both electrically connected to the channel structure first portion 410 and both located at a surface of the isolation structure 20 remote from the substrate 10; the second direction intersects the first direction;
Step S50: a first gate structure 510 is formed on a surface of the first portion 410 of the channel structure remote from the substrate 10, and a second gate structure 520 is formed on one end of the floating body cell structure 30 along the first direction, and the second gate structure 520 is insulated from the first gate structure 510.
In step S10, please refer to fig. 5a, a substrate 10 is provided; in step S20, please continue to refer to fig. 5a, an isolation structure 20 is formed on the surface of the substrate 10; in step S30, referring to fig. 5b and 5c, floating body cell structures 30 extending along a first direction, which may be parallel to the OX direction, are formed on the surface of the isolation structures 20 away from the substrate 10; for example, a deposition process is used to form a floating body cell structure sacrificial layer 301 extending along a first direction on a surface of the isolation structure 20 away from the substrate 10, and an etching process is used to remove a portion of the floating body cell structure sacrificial layer 301 to form a floating body cell structure 30; in step S40, referring to fig. 2, 5e and 5g, a channel structure 40 partially overlapping the floating body cell structure 30 is formed, the channel structure 40 includes a first portion 410 located on an outer surface of the floating body cell structure 30, and a second portion 420 and a third portion 430 located on opposite sides of the floating body cell structure 30 along the second direction, wherein the second portion 420 and the third portion 430 are electrically connected to the first portion 410 and are located on a surface of the isolation structure 20 away from the substrate 10; the second direction may be parallel to the OY direction, the second direction intersecting the first direction, e.g., the first direction may be at an angle of 30 degrees, 45 degrees, 60 degrees, 75 degrees, 90 degrees, 135 degrees, 120 degrees, etc. to the second direction; in step S50, referring to fig. 1, a first gate structure 510 is formed on a surface of the first portion 410 away from the substrate 10, and a second gate structure 520 is formed on one end of the floating body unit structure 30 along the first direction, wherein the second gate structure 520 is insulated from the first gate structure 510.
Referring to fig. 1,2, and 5a to 5g, in some embodiments, by sequentially forming an isolation structure 20, a floating body cell structure 30, a channel structure 40, a first gate structure 510, and a second gate structure 520 on a substrate 10, charges can be stored in the floating body cell structure 30, and a current flows between the floating body cell structure 30 and the channel structure 40, thereby realizing a storage function of a memory cell while avoiding leakage of charges; the embodiment reduces the power consumption of the semiconductor memory device, reduces the volume of the memory cell on the premise of ensuring the memory capacity of the semiconductor memory device, and improves the response speed and the memory density of the semiconductor memory device due to the relative reduction of the volume of the single capacitor structure and the reduction of the power consumption of the peripheral circuit.
Referring to fig. 1 and 5f, in some embodiments, the method for manufacturing a memory cell structure further includes: an insulating layer 310 is formed between the floating body cell structure 30 and the channel structure 40, and when a voltage is applied between the second gate structure 520 and the substrate 10, an electric field is established in the insulating layer 310, and electrons can tunnel from the channel structure 40 through the tunneling dielectric layer into the floating body cell structure 30 to form an F-N tunneling effect, thereby forming a tunneling current. In some embodiments, the material of insulating layer 310 comprises polysilicon oxide, and a deposition process may be used to form insulating layer 310. Since the occurrence speed of the tunnel effect is faster than the response speed of the conventional capacitor, there is no limitation of the transit time, and thus the response speed of the semiconductor memory device can be further improved.
Referring to fig. 2 and fig. 5 c-5 g, in some embodiments, the method for manufacturing a memory cell structure further includes: referring to fig. 5d, the outer surface of the floating body cell structure 30 is covered with an initial protection structure 601; forming channel structure 40 to partially overlap floating body cell structure 30 includes: referring to fig. 5d to 5e, a portion of the initial protection structure is removed to obtain a target protection structure 60 with a middle portion exposed out of the floating body cell structure 30; referring to fig. 5f, an insulating layer 310 is formed on the exposed outer surface of the floating body cell structure 30; referring to fig. 5e and 5g, a channel structure 40 is formed to cover the exposed outer surface of the floating body cell structure 30. Referring to fig. 2, the channel structure 40 includes a first portion 410 to cover the outer surface of the floating body cell structure 30, and a second portion 420 and a third portion 430 located on opposite sides of the floating body cell structure 30 along the second direction.
Referring to fig. 2 and 3, in some embodiments, the target protection structure 60 includes a first oxide protection layer 610, a nitride protection layer 620 and a second oxide protection layer 630, the first oxide protection layer 610 is formed on the outer surface of the floating body cell structure 30, the nitride protection layer 620 is located on the surface of the first oxide protection layer 310 away from the floating body cell structure 30, and the second oxide protection layer 630 is located on the surface of the nitride protection layer 620 away from the floating body cell structure 30; in some embodiments, the nitride isolation layer 620 and the second oxide protection layer 630 are formed by a furnace Low Pressure Chemical Vapor Deposition (LPCVD) process, the first oxide protection layer 610 is formed by a thermal oxidation process, or the first oxide protection layer 610 and the second oxide protection layer 630 are formed by a thermal oxidation process, the nitride protection layer 620 is formed by a CVD deposition process, or, alternatively, the first oxide protection layer 610, the nitride protection layer 620 and the second oxide protection layer 630 may be formed in one step in the same machine, for example, by sequential deposition in a vapor deposition (PECVD) process using plasma enhanced chemistry. In some embodiments, the material of the first oxide protection layer 610 comprises silicon oxide, the material of the nitride protection layer 620 comprises silicon nitride and/or the material of the second oxide protection layer 630 comprises silicon oxide. The target protection structure 60 is used to avoid charge leakage in the floating body cell structure 30, improve charge retention and reliability of the device, reduce power consumption and defect density of the device, and prolong failure average time.
With continued reference to fig. 2 and 3, in some embodiments, the method for manufacturing a memory cell structure further includes: forming a first gate structure 510 on a surface of the first portion 410 of the channel structure remote from the substrate 10 and forming a second gate structure 520 on one end of the floating body cell structure 30 in the first direction, comprising: forming a first gate dielectric layer 511 covering an outer surface of the channel structure 40; forming a first gate conductive layer 512 on the surface of the first gate dielectric layer 511 away from the substrate 10, and forming a second gate conductive layer 522 on one end surface of the floating body unit structure 30, wherein the first gate conductive layer 512 at least covers the surface of the first portion 410 of the channel structure of the floating body unit structure 30 away from the substrate 10; the top surface of the first gate conductive layer 512 is flush with the top surface of the second oxide protection layer 630, and the first gate dielectric layer 511 and the first gate conductive layer 512 form a first gate structure 510; the second oxide protection layer 630 is located between the end face and the second gate conductive layer 522 to form a second gate dielectric layer 521, and the second gate dielectric layer 521 and the second gate conductive layer 522 form a second gate structure 520. In some embodiments, the material of the first gate conductive layer 512 includes titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride, or a combination thereof; the material of the first gate dielectric layer 511 may include silicon oxide, aluminum oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide, or a combination thereof. By adopting the double-grid structure which is transversely distributed, the on-resistance of the channel structure is reduced, the through-current capability and the control capability are enhanced, and the generation of leakage current is reduced.
Referring to fig. 2, in some embodiments, the method for manufacturing a memory cell structure further includes: removing the portion of the first gate dielectric layer 511 located on the top surface of the second portion 420 of the channel structure to obtain a first via hole (not shown in the figure) exposing the top surface of the second portion 420 of the channel structure; removing the portion of the first gate dielectric layer 511 located on the top surface of the third portion 430 of the channel structure to obtain a second via hole (not shown in the figure) exposing the top surface of the third portion 430 of the channel structure; forming a source electrode structure 710 penetrating the first via hole and in contact with the top surface of the second portion 420 of the channel structure; the drain electrode structure 720 penetrating the second via hole and contacting the top surface of the third portion 430 of the channel structure is formed, so that read-write control and/or performance test can be conveniently performed on the memory cell structure through the first gate electrode structure 513, the second gate electrode structure 523, the source electrode structure 710 and the drain electrode structure 720, and the performance and reliability of the product are improved.
Referring to fig. 3, in some embodiments, the method for manufacturing a memory cell structure further includes: forming a first gate electrode structure 513 on the top surface of the first gate conductive layer 512; a second gate electrode structure 523 is formed on the top surface of the second gate conductive layer 522, so that the on-resistance of the channel structure is reduced, the current-through capability and the control capability are enhanced, and the generation of leakage current is reduced by adopting a laterally distributed double gate electrode structure.
Referring to fig. 5c, in some embodiments, forming the isolation structure 20 on the surface of the substrate 10 includes: forming a first oxide isolation layer 210 on the surface of the substrate 10; forming a nitride isolation layer 220 on a surface of the first oxide isolation layer 210 remote from the substrate 10; a second oxide isolation layer 230 is formed on the surface of the nitride isolation layer 220 remote from the substrate 10. In some embodiments, the nitride isolation layer 220 and the second oxide isolation layer 230 are formed by a furnace Low Pressure Chemical Vapor Deposition (LPCVD) process, the first oxide isolation layer 210 is formed by a thermal oxidation process, or the first oxide isolation layer 210 and the second oxide isolation layer 230 are formed by a thermal oxidation process, the nitride isolation layer 220 is formed by a CVD deposition process, or the first oxide isolation layer 210, the nitride isolation layer 220 and the second oxide isolation layer 230 may be sequentially deposited in one station in the same machine, for example, by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. In some embodiments, the material of first oxide isolation layer 210 comprises silicon oxide, the material of nitride isolation layer 220 comprises silicon nitride and/or the material of second oxide isolation layer 230 comprises silicon oxide. The isolation structure 20 is used to avoid charge leakage in the floating body cell structure 30, improve charge retention and reliability of the device, reduce power consumption and defect density of the device, and prolong failure average time.
In some embodiments, the material of channel structure 40 includes polysilicon, indium gallium zinc oxide, indium gallium arsenide, gallium nitride, or combinations thereof; the material of floating body cell structure 30 includes doped polysilicon. By adopting the materials, the problems of stress and doping of the traditional materials in the process of stacking are solved, so that the difficulty of a multilayer deposition process is reduced; as an example, the carrier mobility of IGZO is 20 to 30 times that of amorphous silicon, and the charge-discharge rate and response speed can be improved by adopting IGZO, so that a faster refresh frequency can be realized.
Referring to fig. 1,3 and 6, according to some embodiments, the disclosure provides a read-write circuit, which includes a memory cell structure of any one of the above embodiments, configured to: the first gate structure 510 is electrically connected to the read word line RWL; the second gate structure 520 is electrically connected to the write word line WWL; the second portion 420 of the channel structure is electrically connected to the read bit line RBL; the third portion 430 of the channel structure is electrically connected to the write bit line WBL; during the write state: the control write word line WWL provides a first level signal to the second gate structure 520 such that the floating body cell structure 30 captures and stores electrons, written to a first value; the control write word line WWL provides a second level signal to the second gate structure 520 and the read word line RWL provides a third level signal to the first gate structure 510 such that the electrons stored by the floating body cell structure 30 are reset, written with a second value, the magnitude of the second level signal being less than the magnitude of the first level signal; during the read state: the control read word line RWL provides a third level signal to the first gate structure 510, determines to read a first value according to the acquired first drain current Id1, determines to read a second value according to the acquired second drain current, and the magnitude of the first drain current is smaller than the magnitude of the second drain current.
With continued reference to fig. 1,3, and 6, in some embodiments, during the write state: the magnitude relation between the voltage VG2 of the second gate electrode structure 523 and the first level signal G21 includes: vg2=g21 >0, the magnitude of the voltage VD of the drain electrode structure 710 being equal to the magnitude of the drain power supply voltage VDD, thereby writing a first value; the magnitude relationship between the voltage VG3 of the second gate electrode structure 513 and the second level signal G22 includes: g22 The magnitude relationship between the voltage VG1 of the first gate electrode structure 513 and the third level signal G1 includes: v1=g1 >0, thereby writing a second value, and the amplitude relationship of the second level signal G22 and the first level signal G1 includes: g22< G1; during the read state: the magnitude relationship between the voltage VG1 of the first gate electrode structure 513 and the third level signal G1 includes: vg1=g1; the magnitude relation between the first drain current Id1 and the second drain current Id2 includes: id1< Id2. In some embodiments, the first gate structure 510 and the second gate structure 520 are electrically connected to the word line, the channel structure 40 is electrically connected to the bit line, the control word line provides a level signal to the first gate structure 510 and the second gate structure 520, electrons in the floating body unit structure 30 flow, and drain current is obtained, so that the memory function and the read-write function of the memory cell are realized, and the conventional capacitor and the refresh circuit are not present in the read-write circuit, so that the power consumption increase caused by frequent refresh of the refresh circuit is reduced, and the response speed and the memory density of the semiconductor memory device can be improved on the premise of ensuring the memory capability of the semiconductor memory device.
Referring to fig. 6, in some embodiments, the plurality of memory cell structures are arranged in a plurality of rows and columns configured to: the memory cell structures in the same row are all connected to the same read word line RWL and the same write word line WWL; the memory cell structures in the same column are all connected to the same read bit line RBL and the same write bit line WBL; the memory cell structures in two adjacent rows are connected to different read word lines RWL and different write word lines WWL; the memory cell structures in two adjacent columns are connected to different read bit lines RBL and different write bit lines WBL, so that the read-write function and/or performance test can be conveniently realized in a read-write circuit through word lines and bit lines, and the performance and reliability of the product are improved.
In some embodiments, the first value is "0" and the second value is "1", thereby implementing the read-write function of the read-write circuit for the values "0" and "1".
According to some embodiments, the present disclosure provides a memory, where the memory includes the read-write circuit of any one of the above embodiments, at least capable of reducing charge leakage and power consumption of the memory, and improving response speed, storage density, and reliability of the memory.
Referring to fig. 1, 3 and 6, according to some embodiments, the disclosure provides a read-write circuit control method, where the read-write circuit includes a memory cell structure according to any one of the above embodiments, and the memory cell structure is configured to: the first gate structure 510 is electrically connected to the read word line RWL, the second gate structure 520 is electrically connected to the write word line WWL, the second portion 420 of the channel structure is electrically connected to the read bit line RBL, and the third portion 430 of the channel structure is electrically connected to the write bit line WBL; the read-write circuit control method comprises the following steps: during the write state: the control write word line WWL provides a first level signal to the second gate structure 520 such that the floating body cell structure 30 captures and stores electrons, written to a first value; or the write word line WWL is controlled to provide a second level signal to the second gate structure 520 and the read word line RWL is controlled to provide a third level signal to the first gate structure 510, such that the electronic reset stored by the floating body cell structure 30 is written with a second value, the magnitude of the second level signal being less than the magnitude of the first level signal; during the read state: the control read word line RWL provides a third level signal to the first gate structure 510, determines to read a first value according to the acquired first drain current, determines to read a second value according to the acquired second drain current, and the magnitude of the first drain current is smaller than the magnitude of the second drain current.
With continued reference to fig. 1, 3, and 6, in some embodiments, during the write state: the magnitude relation between the voltage VG2 of the second gate electrode structure 523 and the first level signal G21 includes: vg2=g21 >0, the magnitude of the voltage VD of the drain electrode structure 710 being equal to the magnitude of the drain power supply voltage VDD, thereby writing a first value; the magnitude relationship between the voltage VG3 of the second gate electrode structure 513 and the second level signal G22 includes: g22 The magnitude relationship between the voltage VG1 of the first gate electrode structure 513 and the third level signal G1 includes: v1=g1 >0, thereby writing a second value, and the amplitude relationship of the second level signal G22 and the first level signal G1 includes: g22< G1; during the read state: the magnitude relationship between the voltage VG1 of the first gate electrode structure 513 and the third level signal G1 includes: vg1=g1; the magnitude relation between the first drain current Id1 and the second drain current Id2 includes: id1< Id2. As an example, the first value is "0" and the second value is "1". In some embodiments, the storage function and the writing function of the memory cell are achieved by controlling the write word line WWL to provide a level signal to the first gate structure 510 and the second gate structure 520, resulting in electron flow in the floating body cell structure 30; the read word line RWL is controlled to provide a level signal to the first gate structure 510 and obtain a drain current, so that a read function of the memory cell is realized; because the traditional capacitor and the refreshing circuit are not arranged in the memory, the charge leakage caused by the capacitor is avoided, the power consumption increase caused by frequent refreshing of the refreshing circuit is reduced, and the response speed and the storage density of the semiconductor memory device can be improved on the premise of ensuring the storage capacity of the semiconductor memory device.
Note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples merely represent several embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the disclosure. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the following claims.
Claims (20)
1. A memory cell structure comprising:
A substrate;
The isolation structure is formed on the surface of the substrate;
a floating body cell structure located on a surface of the isolation structure away from the substrate, extending in a first direction;
The channel structure is overlapped with the floating body unit structure part and is insulated from each other, and comprises a first part positioned on the outer surface of the floating body unit structure, and a second part and a third part positioned on two opposite sides of the floating body unit structure along a second direction, wherein the second part and the third part are electrically connected with the first part and are positioned on the surface of the isolation structure, which is far away from the substrate; the second direction intersects the first direction;
a first gate structure located on a surface of the first portion remote from the substrate;
And the second grid structure is formed at one end of the floating body unit structure along the first direction and is mutually insulated with the first grid structure.
2. The memory cell structure of claim 1, wherein the first portion, the second portion, and the third portion of the channel structure are integrally formed structures fabricated using the same process steps; and
An insulating layer is provided between the first portion and the floating body cell structure.
3. The memory cell structure of claim 2, wherein the first gate structure comprises:
the first gate dielectric layer at least covers the outer surface of the channel structure; and
The first gate conducting layer is positioned on the surface of the first gate dielectric layer, which is far away from the substrate, and at least covers the surface of the first part of the floating body unit structure, which is far away from the substrate.
4. The memory cell structure of claim 3, further comprising:
A target protection structure covering an exposed outer surface of the floating body cell structure;
The target protection structure includes: a first oxide protection layer formed on an outer surface of the floating body cell structure, a nitride protection layer located on a surface of the first oxide protection layer remote from the floating body cell structure, and a second oxide protection layer located on a surface of the nitride protection layer remote from the floating body cell structure;
wherein the top surface of the first gate conductive layer is flush with the top surface of the second oxide protection layer.
5. The memory cell structure of claim 4, wherein the second gate structure comprises:
The second gate conducting layer is prepared in the same process step with the first gate conducting layer and is positioned at one end face of the floating body unit structure;
and the second gate dielectric layer is a part of the second oxide protection layer, which is positioned between the end face and the second gate conductive layer.
6. The memory cell structure of claim 5, further comprising:
the first gate electrode structure is positioned on the top surface of the first gate conducting layer;
the second gate electrode structure is positioned on the top surface of the second gate conducting layer;
a source electrode structure located on a top surface of the second portion of the channel structure; and
And a drain electrode structure located on top of the third portion of the channel structure.
7. The memory cell structure of any of claims 1-6, wherein the isolation structure comprises:
A first oxide isolation layer located on the surface of the substrate;
a nitride isolation layer located on a surface of the first oxide isolation layer away from the substrate; and
And a second oxide isolation layer located on a surface of the nitride isolation layer away from the substrate.
8. The memory cell structure of any one of claims 1-6, wherein:
the channel structure comprises the following materials: polysilicon, indium gallium zinc oxide, indium gallium arsenide, gallium nitride, or combinations thereof; and/or
The material of the floating body cell structure comprises doped polysilicon.
9. A read-write circuit, comprising:
The memory cell structure of any one of claims 1-8, configured to:
the first grid structure is electrically connected with the read word line;
the second grid structure is electrically connected with the writing wire;
a second portion of the channel structure is electrically connected to the read bit line;
a third portion of the channel structure is electrically connected to the write bit line;
during the write state:
Controlling the write line to provide a first level signal to the second gate structure so that the floating body cell structure captures and stores electrons, written with a first value;
Controlling the write word line to provide a second level signal to the second gate structure and the read word line to provide a third level signal to the first gate structure, such that the electronic reset stored by the floating body cell structure is written with a second value, the magnitude of the second level signal being less than the magnitude of the first level signal;
During the read state:
And controlling the read word line to provide the third level signal to the first grid structure, judging and reading the first numerical value according to the acquired first drain current, judging and reading the second numerical value according to the acquired second drain current, wherein the amplitude of the first drain current is smaller than that of the second drain current.
10. The read-write circuit of claim 9 wherein a plurality of said memory cell structures are arranged in a plurality of rows and columns;
the memory cell structures in the same row are all connected to the same read word line and the same write word line;
the memory cell structures in the same column are all connected to the same read bit line and the same write bit line;
the memory cell structures in two adjacent rows are connected to different read word lines and different write word lines;
The memory cell structures in two adjacent columns are connected to different read bit lines and different write bit lines.
11. The read-write circuit according to claim 9 or 10, wherein the first value is "0" and the second value is "1".
12. A memory, comprising:
The read-write circuit of any one of claims 9-11.
13. A read-write circuit control method, characterized in that the read-write circuit comprises the memory cell structure of any one of claims 1 to 8, the memory cell structure being configured to: the first gate structure is electrically connected with the read word line, the second gate structure is electrically connected with the write word line, the second part of the channel structure is electrically connected with the read bit line, and the third part of the channel structure is electrically connected with the write bit line; the control method comprises the following steps:
During the write state: controlling the write line to provide a first level signal to the second gate structure so that the floating body cell structure captures and stores electrons, written with a first value; or controlling the writing line to provide a second level signal to the second gate structure, and the reading line to provide a third level signal to the first gate structure, so that the electrons stored in the floating body unit structure are reset and written with a second value, and the amplitude of the second level signal is smaller than that of the first level signal;
During the read state: and controlling the read word line to provide the third level signal to the first grid structure, judging and reading the first numerical value according to the acquired first drain current, judging and reading the second numerical value according to the acquired second drain current, wherein the amplitude of the first drain current is smaller than that of the second drain current.
14. A method for manufacturing a memory cell structure, comprising:
Providing a substrate;
forming an isolation structure on the surface of the substrate;
forming a floating body unit structure extending along a first direction on the surface of the isolation structure away from the substrate;
Forming a channel structure partially overlapping the floating body cell structure, the channel structure including a first portion located on an outer surface of the floating body cell structure, and second and third portions located on opposite sides of the floating body cell structure in a second direction, the second and third portions each being electrically connected to the first portion and each located on a surface of the isolation structure remote from the substrate; the second direction intersects the first direction;
And forming a first grid structure on the surface of the first part far away from the substrate, and forming a second grid structure at one end of the floating body unit structure along the first direction, wherein the second grid structure and the first grid structure are mutually insulated.
15. The method of claim 14, wherein the outer surface of the floating body cell structure is covered with an initial protection structure; the forming a channel structure partially overlapping the floating body cell structure, comprising:
Removing part of the initial protection structure to obtain a target protection structure with the middle part exposed out of the floating body unit structure;
Forming an insulating layer on the exposed outer surface of the floating body unit structure;
And forming a channel structure covering the outer surface of the insulating layer, wherein the channel structure comprises a first part covering the outer surface of the floating body unit structure, and the second part and the third part which are positioned on two opposite sides of the floating body unit structure along the second direction.
16. The method of claim 15, wherein the target protection structure comprises: a first oxide protection layer formed on an outer surface of the floating body cell structure, a nitride protection layer located on a surface of the first oxide protection layer remote from the floating body cell structure, and a second oxide protection layer located on a surface of the nitride protection layer remote from the floating body cell structure; forming a first gate structure on a surface of the first portion away from the substrate, and forming a second gate structure on one end of the floating body unit structure along the first direction, including:
forming a first gate dielectric layer covering the outer surface of the channel structure;
Forming a first gate conductive layer on one end of the floating body unit structure while forming a first gate conductive layer on the surface of the first gate dielectric layer, which is far away from the substrate, wherein the first gate conductive layer at least covers the surface of the first part of the floating body unit structure, which is far away from the substrate; the top surface of the first gate conductive layer is flush with the top surface of the second oxide protective layer, and the first gate dielectric layer and the first gate conductive layer form the first gate structure; and the part of the second oxide protection layer between the end face and the second gate conductive layer forms a second gate dielectric layer, and the second gate dielectric layer and the second gate conductive layer form the second gate structure.
17. The method of manufacturing a memory cell structure of claim 16, further comprising:
Removing the part of the first gate dielectric layer, which is positioned on the top surface of the second part of the channel structure, to obtain a first via hole exposing the top surface of the second part;
Removing the part of the first gate dielectric layer positioned on the top surface of the third part of the channel structure to obtain a second via hole exposing the top surface of the third part;
forming a source electrode structure penetrating the first via hole and in contact connection with the top surface of the second part;
and forming a drain electrode structure penetrating the second via hole and in contact connection with the top surface of the third part.
18. The method of manufacturing a memory cell structure of claim 16, further comprising:
Forming a first gate electrode structure on the top surface of the first gate conductive layer;
and forming a second gate electrode structure on the top surface of the second gate conductive layer.
19. The method of any one of claims 14-18, wherein forming an isolation structure on the surface of the substrate comprises:
Forming a first oxide isolation layer on the surface of the substrate;
forming a nitride isolation layer on the surface of the first oxide isolation layer away from the substrate;
And forming a second oxide isolation layer on the surface of the nitride isolation layer, which is far away from the substrate.
20. The method for manufacturing a memory cell structure according to any one of claims 14 to 18, wherein:
The channel structure comprises the following materials: polysilicon, indium gallium zinc oxide, indium gallium arsenide, gallium nitride, or combinations thereof: and/or
The material of the floating body cell structure comprises doped polysilicon.
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| CN202211234874.4A CN117915653A (en) | 2022-10-10 | 2022-10-10 | Memory cell structure, preparation method thereof, read-write circuit and memory |
| PCT/CN2023/088416 WO2024077910A1 (en) | 2022-10-10 | 2023-04-14 | Storage unit structure and preparation method therefor, read-write circuit, and memory |
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| CN202211234874.4A CN117915653A (en) | 2022-10-10 | 2022-10-10 | Memory cell structure, preparation method thereof, read-write circuit and memory |
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| US20040004863A1 (en) * | 2002-07-05 | 2004-01-08 | Chih-Hsin Wang | Nonvolatile electrically alterable memory device and array made thereby |
| US20090173984A1 (en) * | 2008-01-08 | 2009-07-09 | Qimonda Ag | Integrated circuit and method of manufacturing an integrated circuit |
| CN102376715B (en) * | 2010-08-11 | 2014-03-12 | 中国科学院微电子研究所 | Capacitance-free dynamic random access memory structure and preparation method thereof |
| CN104112748B (en) * | 2013-04-19 | 2016-12-28 | 中国科学院微电子研究所 | Memory device and manufacture method thereof and access method |
| CN109742073A (en) * | 2018-12-17 | 2019-05-10 | 复旦大学 | A kind of half floating transistor and preparation method thereof with high charge holding capacity |
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