CN118193418A

CN118193418A - Interface time sequence adjustment method and device, storage medium and electronic equipment

Info

Publication number: CN118193418A
Application number: CN202211593059.7A
Authority: CN
Inventors: 黄仁芳; 廖裕民; 杨岳青; 刘宇骐
Original assignee: Suteng Innovation Technology Co Ltd
Current assignee: Suteng Innovation Technology Co Ltd
Priority date: 2022-12-13
Filing date: 2022-12-13
Publication date: 2024-06-14

Abstract

The embodiment of the application discloses an interface time sequence adjusting method, an interface time sequence adjusting device, a storage medium and electronic equipment, and relates to the technical field of communication. The method is applied to a communication interface between the FPGA device and the off-chip physical layer chip, and comprises the following steps: circularly sending a first test message to the communication interface and receiving a corresponding second test message output by the communication interface; setting a delay value of a first delay of the communication interface, training the second delay of the communication interface based on a comparison result of the second test message and the first test message, and determining an expected value of the second delay; training the first delay based on the expected value of the second delay and the comparison result of the second test message and the first test message, and determining the expected value of the first delay. According to the technical scheme provided by the embodiment of the application, the interface time sequence of the communication interface between the FPGA device and the off-chip physical layer chip can be accurately adjusted, and the problem of data sampling errors of the communication interface is avoided.

Description

Interface time sequence adjustment method and device, storage medium and electronic equipment

Technical Field

The present application relates to the field of communications technologies, and in particular, to an interface timing adjustment method and apparatus, a storage medium, and an electronic device.

Background

With the development of FPGA (Field Programmable GATE ARRAY) technology, FPGA devices are increasingly being used in the communications industry.

Currently, when an FPGA device is connected to an external Physical layer chip such as an RGMII (Reduced Gigabit media independent interface) PHY (Physical layer) chip, the timing sequence of the RGMII interface on the FPGA side needs to be constrained according to the routing delay on the FPGA device and the interface timing requirement of the external PHY chip. When the external PHY chip is changed or the delay estimation of the FPGA side wiring is not correct, the data sampling error of the communication interface is caused, and the communication failure of the communication interface is caused.

Therefore, how to accurately adjust the interface timing of the communication interface between the FPGA device and the off-chip physical layer chip becomes a technical problem to be solved.

Disclosure of Invention

The embodiment of the application provides an interface time sequence adjusting method, an interface time sequence adjusting device, a storage medium and electronic equipment, which can accurately adjust the interface time sequence of a communication interface between an FPGA device and an off-chip physical layer chip, so that the interface time sequence can be self-adaptive to the change of the off-chip physical layer chip, and the problem of data sampling errors of the communication interface is avoided. The technical scheme is as follows:

In a first aspect, an embodiment of the present application provides an interface timing adjustment method, configured to adjust a timing of a communication interface between a field programmable gate array FPGA device and an off-chip physical layer chip, where the method includes:

Circularly sending a first test message to the communication interface and receiving a corresponding second test message output by the communication interface;

Setting a delay value of a first delay of the communication interface, training the second delay of the communication interface based on a comparison result of the second test message and the first test message, and determining an expected value of the second delay;

Training the first delay based on the expected value of the second delay and the comparison result of the second test message and the first test message, determining the expected value of the first delay,

The first delay is an output delay of the communication interface and the second delay is an input delay of the communication interface, or the first delay is an input delay of the communication interface and the second delay is an output delay of the communication interface.

In a second aspect, an embodiment of the present application provides an interface timing adjustment apparatus for adjusting a timing of a communication interface between a field programmable gate array FPGA device and an off-chip physical layer chip, the apparatus including:

the receiving and transmitting module is used for circularly transmitting a first test message to the communication interface and receiving a corresponding second test message output by the communication interface;

The first training module is used for setting a delay value of a first delay of the communication interface, training the second delay of the communication interface based on a comparison result of the second test message and the first test message, and determining an expected value of the second delay;

A second training module, configured to train the first delay based on the expected value of the second delay and a comparison result of the second test packet and the first test packet, determine the expected value of the first delay,

In a third aspect, embodiments of the present application provide a computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the steps of the method described above.

In a fourth aspect, an embodiment of the present application provides an electronic device, which may include: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the steps of the method described above.

The technical scheme provided by the embodiments of the application has the beneficial effects that at least:

in one or more embodiments of the present application, on the one hand, a test packet sent to a communication interface is compared with a test packet output by the communication interface, and according to the comparison result, the input delay and the output delay of the communication interface are adaptively adjusted, and by training, the better input delay and the output delay of the communication interface capable of correctly receiving and transmitting data can be obtained at the same time, so that the interface time sequence of the communication interface between the FPGA device and the off-chip physical layer chip can be accurately adjusted; on the other hand, when the off-chip physical layer chip changes, the interface time sequence of the communication interface can adapt to the change of the off-chip physical layer chip, so that the problem of data sampling errors of the communication interface is avoided.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram illustrating an application scenario of an interface timing adjustment method according to some embodiments of the present application;

FIG. 2 is a flow chart illustrating an interface timing adjustment method provided in accordance with some embodiments of the present application;

FIG. 3 is a flow chart illustrating an interface timing adjustment method according to other embodiments of the present application;

FIG. 4 is a schematic diagram of an interface timing adjustment method according to further embodiments of the present application;

fig. 5 shows a schematic structural diagram of an interface timing adjustment device according to an embodiment of the present application;

Fig. 6 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

First, terms related to one or more embodiments of the present specification will be explained.

The RGMII (Reduced Gigabit MEDIA INDEPENDENT INTERFACE) interface is a simplified Gigabit media independent interface, with a data bit width of 4 bits and a clock frequency of 125MHz at 1000 Mbps; at a rate of 100Mbps, the clock frequency is 25M; at a rate of 10Mbps, the clock frequency is 2.5MHz.

Input delay: the input interface includes a clock interface and a data interface, and the input delay represents a delay of input data relative to a clock, such as a data time-clock rising edge time.

Output delay: the output interface includes a clock interface and a data interface, and the output delay represents a delay of output data relative to a clock.

Training: the method can be used for determining the delay interval of the input delay or the output delay of the communication interface capable of correctly receiving the data according to the comparison result of the received message and the sent message, and determining the expected value of the delay according to the delay interval capable of correctly receiving the data.

The embodiment of the application provides an interface time sequence adjusting method and an interface time sequence adjusting device, which are used for adjusting the time sequence of a communication interface between an FPGA device and an off-chip physical layer chip. According to the technical scheme of the embodiment of the application, on one hand, the test message sent to the communication interface is compared with the test message received by the communication interface, and the input delay and the output delay of the communication interface are adaptively adjusted according to the comparison result, so that the interface time sequence of the communication interface between the FPGA device and the off-chip physical layer chip can be accurately adjusted; on the other hand, when the off-chip physical layer chip changes, the interface time sequence of the communication interface can adapt to the change of the off-chip physical layer chip, so that the problem of data sampling errors of the communication interface is avoided.

Further, the interface timing adjustment method may be implemented in dependence on a computer program, and may be run on an interface timing adjustment device based on von neumann systems. The computer program may be integrated in the application or may run as a stand-alone tool class application. The interface timing adjustment device in the embodiment of the present application may be a terminal device, including but not limited to: interactive smart tablets, personal computers, tablet computers, handheld devices, wearable devices, computing devices, or other processing devices connected to a wireless modem, etc. Terminal devices in different networks may be called different names, for example: a user equipment, an access terminal, a subscriber unit, a subscriber station, a mobile station, a remote terminal, a mobile device, a user terminal, a wireless communication device, a user agent or user equipment, a cellular telephone, a cordless telephone, a terminal device in a 5G network or future evolution network, etc.

The following describes in detail the technical scheme of the interface timing adjustment method according to the embodiment of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic diagram illustrating an application scenario of an interface timing adjustment method according to an embodiment of the present application.

As shown in fig. 1, the application scenario includes a MAC side 110 and a PHY side 120. The MAC side 110 may be an FPGA chip and the PHY side 120 may be an off-chip PHY chip such as an off-chip RGMIIPHY chip. The MAC side 110 and the PHY side 120 are connected through a communication interface, such as an RGMII interface, which is used for data transmission between the MAC side 110 and the PHY side 120, for example, when the PHY side 120 transmits data to the MAC side 110 and the MAC side 110 receives data. When the communication interface such as the RGMII interface receives and transmits data, time sequence constraint is needed, otherwise, data receiving errors occur.

Further, the communication interface between the MAC side 110 and the PHY side 120 may include a reception signal and a transmission signal, wherein the reception signal may include a reception clock signal rx_clk, a reception data signal RXD, and a reception control signal rx_ctl. The transmit signal may include a transmit clock signal tx_clk, a transmit data signal TXD, and a receive control signal tx_ctl.

In some example embodiments, there is a cell on the FPGA device that can dynamically adjust the delay. The DELAY CELL units on the FPGA device have input delay of IDELAY and output delay of ODELAY. The delay of the communication interface can be adaptively adjusted through DELAY CELL units on the FPGA device.

It should be understood that the communication interface may also be other suitable interfaces such as SMII (SERIAL MEDIA INDEPENDANT INTERFACE, serial media independent interface) or GMII (Gigabit MEDIA INDEPENDANT INTERFACE, gigabit media independent interface) and the like, which are also within the scope of embodiments of the present application.

The interface timing adjustment method provided in the embodiments of the present disclosure may be executed by a computing device having a computing capability, such as an upper computer, and accordingly, the interface timing adjustment apparatus may be disposed in the computing device.

Based on the application scenario shown in fig. 1, the following will describe in detail the interface timing adjustment method provided in the embodiment of the present disclosure with reference to fig. 2 to 5. It should be noted that the above application scenario is only shown for the convenience of understanding the spirit and principle of the present specification, and the embodiments of the present specification are not limited in this respect. Rather, embodiments of the present description may be applied to any scenario where applicable.

Fig. 2 is a flow chart illustrating an interface timing adjustment method according to some embodiments of the application. The execution body of the interface timing adjustment method may be a computing device having a computing processing function, such as the above-mentioned upper computer. The interface timing adjustment method includes steps S210 to S230, and the interface timing adjustment method in the exemplary embodiment is described in detail with reference to the accompanying drawings.

Referring to fig. 2, in step S210, a first test message is cyclically sent to a communication interface, and a corresponding second test message output by the communication interface is received.

In an example embodiment, the communication interface is a communication interface between the FPGA device and the off-chip physical layer chip, e.g., the communication interface may be an RGMII interface. The first test message is a message for testing the time sequence of the communication interface, the test message selects message data with rich jump edges, for example, the first test message data can be 32' h5a, and the tail part of the test message is provided with check data, for example, 4 bytes of CRC check data.

It should be noted that, although the RGMII interface is described as an example, it should be understood by those skilled in the art that the communication interface may be other suitable interfaces, such as an SMII interface or a GMII interface, and the like, which is also within the scope of the embodiments of the present application.

Further, in an example embodiment, the first test message is sent to the communication interface in a round robin manner. For example, the test message of 60byte data is circularly sent to the communication interface in a mode of 32'h5a, 32' h5a5 interleaving, and the data structure of the test message is shown in table 1 below.

TABLE 1 data structure of test message

Preamble code

Frame initiator

32'h5a5a5a5a

32'ha5a5a5a5

…

32'h5a5a5a5a

32'ha5a5a5a5

32'h0E3D007B

Because of the delay of the communication interface, the first test message output by the communication interface may not be consistent with the transmitted first test message. Therefore, the second test message corresponding to the first test message can be obtained from the data output by the communication interface according to the preamble and the frame initiator of the test message.

Further, in other example embodiments, the first test message is cyclically sent to the communication interface and the corresponding second test message output by the communication interface is received in response to a change in the off-chip physical layer chip. For example, if the off-chip PHY chip is replaced, that is, when a new off-chip PHY chip is accessed to the communication interface, a first test message is sent to the communication interface in a circulating manner, and a corresponding second test message received by the communication interface is obtained.

In step S220, an initial delay value of the first delay of the communication interface is set, and based on a comparison result of the second test message and the first test message, training is performed on the second delay of the communication interface, and an expected value of the second delay is determined.

In an example embodiment, the first delay of the communication interface is an output delay of the communication interface and the second delay is an input delay of the communication interface, or the first delay is an input delay of the communication interface and the second delay is an output delay of the communication interface. The expected value of the second delay represents the delay value of the second delay after training is completed. Training may mean determining a delay interval of an input delay or an output delay of a communication interface capable of correctly receiving data according to a comparison result of a received message and a transmitted message, determining an expected value of the delay, i.e., an optimal delay value, according to the delay interval capable of correctly receiving data, for example, a minimum value and a maximum value of the input delay of the communication interface capable of correctly receiving data, and taking an average value of the minimum value and the maximum value as the expected value of the input delay.

For example, taking the first delay as the output delay of the communication interface and the second delay as the input delay of the communication interface as an example, the first delay ODELAY is inserted on the output IO signal of the FPGA, i.e., eth_tx_clk, and the second delay IDELAY is inserted on the input IO signal of the FPGA, i.e., eth_rx_clk. The minimum and maximum values of the first delay ODELAY and the minimum and maximum values of the second delay IDELAY that the communication interface can correctly receive data are determined through training.

Further, in an example embodiment, a delay value of the first delay of the communication interface may be set in a fixed mode, for example, an initial delay value of the first delay is set to 0, the received second test packet is compared with the sent first test packet, and training is performed on the second delay of the communication interface based on the comparison result, so as to determine an expected value of the second delay.

For example, taking the first delay as the output delay of the communication interface and the second delay as the input delay of the communication interface as an example, if the second test message received at the first time is consistent with the first test message sent at the first time and the second test message received at the last time at the first time is inconsistent with the first test message sent at the first time, recording the first boundary delay T0 corresponding to the input delay at the first time; increasing the delay value of the input delay of the communication interface, and if the second test message received at the second moment is inconsistent with the first test message sent, recording the second boundary delay T1 of the input delay at the second moment; based on the first boundary delay T0 and the second boundary delay T1 corresponding to the input delay, an expected value of the input delay is determined, for example, an average value, which is an intermediate value between the first boundary delay T0 and the second boundary delay T1, is selected as the expected value of the input delay of the communication interface.

In step S230, training is performed on the first delay based on the expected value of the second delay and the comparison result of the second test message and the first test message, so as to determine the expected value of the first delay.

In an example embodiment, the delay value of the second delay is set to an expected value of the second delay, the received second test message is compared with the sent first test message, and training is performed on the first delay of the communication interface based on the comparison result to determine the expected value of the first delay.

For example, taking the first delay as the output delay of the communication interface, the second delay as the input delay of the communication interface, setting the delay value of the input delay as the expected value of the input delay, and if the second test message received at the third moment is consistent with the first test message sent and the second test message received at the last moment of the third moment is inconsistent with the first test message sent, recording the first boundary delay T2 corresponding to the output delay of the third moment; increasing the delay value of the output delay of the communication interface, and if the second test message received at the fourth moment is inconsistent with the first test message sent, recording the second boundary delay T3 of the output delay at the fourth moment; the expected value of the output delay is determined based on the first boundary delay T2 and the second boundary delay T3 corresponding to the output delay, for example, an intermediate value, that is, an average value, between the first boundary delay T2 and the second boundary delay T3 is selected as the expected value of the output delay of the communication interface.

According to the technical scheme in the example embodiment of fig. 2, on one hand, a test message sent to a communication interface is compared with a test message output by the communication interface, and according to the comparison result, the input delay and the output delay of the communication interface are adaptively adjusted, and the better input delay and the better output delay of the communication interface capable of correctly receiving and transmitting data can be obtained through training, so that the interface time sequence of the communication interface between the FPGA device and the off-chip physical layer chip can be accurately adjusted; on the other hand, when the off-chip physical layer chip changes, the interface time sequence of the communication interface can adapt to the change of the off-chip physical layer chip, so that the problem of data sampling errors of the communication interface is avoided.

Further, in the example embodiment, when training the second delay of the communication interface, if the second test packet received at the first time is inconsistent with the first test packet sent at the first time, that is, the boundary delay of the second delay is not found when the first delay is present, the delay value of the first delay is incremented; training the second delay of the communication interface based on the delay value of the first delay after increment and the comparison result of the second test message and the first test message, and determining the expected value of the second delay.

For example, when the first delay is set as the output delay of the communication interface and the second delay is set as the input delay of the communication interface and the input delay of the communication interface is trained, if the values of the first boundary delay T0 and the second boundary delay T1 of the input delay are not found under the delay value of the current output delay, it indicates that the transmission timing of the current transmission signal Tx still has deviation, the data delay of the output delay ODELAY is increased, and the searching of the values of the first boundary delay T0 and the second boundary delay T1 of the input delay IDELAY is continued until the adjustment process of the current output delay ODELAY is stopped after the values of a group of the first boundary delay T0 and the second boundary delay T1 are found.

According to the technical scheme in the above example embodiment, by increasing the delay value of the first delay and training the second delay of the communication interface based on the comparison result of the increased second test message and the first test message, the optimal input delay of the communication interface capable of correctly receiving data can be accurately determined.

Fig. 3 is a flow chart illustrating an interface timing adjustment method according to other embodiments of the application.

Referring to fig. 3, in step S310, a first test message is cyclically sent to the communication interface, and a corresponding second test message output by the communication interface is received.

In the example embodiment, the implementation process and implementation effect of step S310 are similar to those of step S210, and are not described here again.

In step S320, the delay value of the second delay is set to be the expected value of the second delay, and if the second test message received at the third moment is consistent with the first test message sent and the second test message received at the last moment is inconsistent with the first test message sent, the first boundary delay of the first delay at the third moment is recorded.

In an example embodiment, the first delay is an output delay of the communication interface and the second delay is an input delay of the communication interface. After the expected value of the input delay is determined, the delay value of the input delay is set as the expected value of the input delay, and the first delay of the communication interface is trained. And if the second test message received at the third moment is consistent with the first test message sent, recording the first boundary delay T2 of the output delay at the third moment.

For example, taking the first delay as the output delay of the communication interface and the second delay as the input delay of the communication interface as an example, the first delay ODELAY is inserted on the output IO signal of the FPGA, i.e., eth_tx_clk, and the second delay IDELAY is inserted on the input IO signal of the FPGA, i.e., eth_rx_clk. If the second test message received at the third moment is consistent with the first test message sent at the third moment and the second test message received at the last moment of the third moment is inconsistent with the first test message sent at the third moment, the first boundary delay T2 of the output delay ODELAY at the third moment is recorded, namely the minimum delay that the communication interface can correctly receive data.

In step S330, the delay value of the first delay of the communication interface is incremented, and if the second test packet received at the fourth time is inconsistent with the first test packet, the second boundary delay of the first delay at the fourth time is recorded.

In an example embodiment, the first delay is an output delay of the communication interface and the second delay is an input delay of the communication interface. The delay VALUE of the first delay of the communication interface is incremented, for example, the first delay is set to a variable VARIABLE mode, in VARIABLE delay variable mode, the initial delay VALUE is determined by idelay_value, in operation, under the action of the C clock, when ce=1, the increase (inc=1) or decrease (inc=0) of the delay VALUE is controlled by the INC pin in the range of 0-31. Out of range moves automatically to either 0 or 31.

Further, the first delay ODELAY is inserted on the output IO signal of the FPGA, i.e., eth_tx_clk, and the second delay IDELAY is inserted on the input IO signal of the FPGA, i.e., eth_rx_clk. If the second test message received at the fourth moment is inconsistent with the first test message, the second boundary delay T3 of the first delay at the fourth moment is recorded, namely the maximum delay of the communication interface capable of correctly receiving the data.

In step S340, an expected value of the first delay is determined based on the first boundary delay and the second boundary delay corresponding to the first delay.

In an example embodiment, after the first boundary delay T2 and the second boundary delay T3 corresponding to the first delay are obtained, an average value, which is an intermediate value between the first boundary delay T2 and the second boundary delay T3 corresponding to the first delay, is determined, and the average value is taken as the expected value of the first delay.

According to the technical solution in the example embodiment of fig. 3, on the one hand, by increasing the delay value of the first delay of the communication interface and training the first delay of the communication interface, the minimum value and the maximum value of the delay interval of the first delay in which the communication interface can correctly receive data can be determined, so that the optimal delay in which the communication interface can correctly receive data can be accurately determined; on the other hand, the minimum value and the maximum value of the delay interval of the first delay, in which the communication interface can correctly receive data, can be determined, so that the interface time sequence of the RGMII can be dynamically adjusted within a certain range, and the interface time sequence of the RGMII is self-adaptive to the change of the PHY chip on the board.

Fig. 4 is a schematic diagram illustrating an interface timing adjustment method according to further embodiments of the present application.

Referring to fig. 4, in step S405, an initial delay value of the output delay/input delay is set.

In an example embodiment, an initial delay value of the output delay/input delay of the communication interface is set, for example, to 0, before training is performed.

In step S410, the operation mode of the RGMIIPHY chip is configured as a loop-back mode.

In an example embodiment, the loopback mode is used to train the latency of the communication interface, and in the loopback mode, the test message may return to the data transmitting end after passing through the FPGA.

In step S415, the transmission signal line Tx transmits a test message, and the reception signal line Rx receives a message.

The transmission signal line Tx of RGMIIPHY chip transmits test message to the communication interface, and the reception signal line Rx receives message output from the communication interface. For example, a message of 60 bytes data is circularly sent in a mode of 32'h5a, 32' h5a5 interleaving, and the tail part of the message is provided with 4 bytes of CRC.

In step S420, it is determined whether the comparison of the received and transmitted messages is consistent.

In an example embodiment, determining whether the received and transmitted messages are consistent through the CRC check portion of the received and transmitted messages, and if so, proceeding to step S425; if the comparison is inconsistent, the process proceeds to step S435.

In step S425, the previous transmission/reception comparison fails, and the current transmission/reception comparison passes?

In an example embodiment, if the comparison of the previous received and transmitted messages is inconsistent, the comparison of the previous received and transmitted messages is consistent, then proceed to step S430; otherwise, the process proceeds to step S435.

In step S430, a boundary value of 1 is obtained, and the current delay data is recorded.

In an example embodiment, a first delay boundary of the delay of the communication interface, namely, a boundary value 1, is obtained, and current delay data is recorded. For example, let the delay be the input delay, if the received message is consistent with the transmitted message, record the value T0 of the delay at this moment.

In step S435, whether the boundary value 1 (T0) and the boundary value 2 (T1) of the input delay are both found?

In an example embodiment, it is determined whether both the boundary value 1 (T0) and the boundary value 2 (T1) of the input delay have been found, and if both have been found, then it proceeds to step S455; otherwise, the process proceeds to step S440.

In step S440, the delay value of the input delay is incremented.

In an example embodiment, the input delay is set to a variable VARIABLE mode, in which VARIABLE delay variable mode the initial delay VALUE is determined by idelay_value, in operation, under the action of the C clock, when ce=1, the increase (inc=1) or decrease (inc=0) of the delay VALUE is controlled by the INC pin in the range of 0-31. Out of range moves automatically to either 0 or 31.

In step S445, the previous transmission/reception comparison passes, and the current transmission/reception comparison fails?

In an example embodiment, if it is determined that the previous transceiving comparison is consistent, the current transceiving comparison is inconsistent, that is, the received message is inconsistent with the transmitted message, proceeding to step S450; otherwise, step S435 is performed.

In step S450, a boundary value of 2 is obtained, and the current delay data is recorded.

In an exemplary embodiment, if the received message is inconsistent with the transmitted message, the value T1 of the delay of IDELAY at this point is recorded.

In step S455, the boundary value 1 (T2) and the boundary value 2 (T3) of the output delay are both found?

In an example embodiment, it is determined whether both the boundary value 1 (T2) and the boundary value 2 (T3) of the output delay have been found, and if both have been found, then proceed to step S470; otherwise, the process proceeds to step S460.

In step S460, the delay value of the fixed input delay is the intermediate value between the boundary values T0 and T1.

In an exemplary embodiment, an intermediate value, i.e., an average value, of the interval of the boundary values T0 and T1 of the input delay is determined, and the average value is taken as the delay value of the input delay. That is, an intermediate value between T0 and T1 is chosen as the delay of IDELAY for the completion of the final training.

In step S465, the delay value of the output delay is incremented.

In step S470, the delay value of the output delay is determined as an intermediate value between the boundary value T2 and the boundary value T3.

In an example embodiment, an intermediate value, i.e., an average value, of the boundary value T2 and the boundary value T3 of the output delay is determined, and the average value is taken as the delay value of the output delay. That is, an intermediate value between T2 and T3 is chosen as the time delay of ODELAY for the completion of the final training.

According to the technical scheme in the example embodiment of fig. 4, on one hand, a test packet sent to a communication interface is compared with a test packet received by the communication interface, and according to a comparison result, the input delay and the output delay of the communication interface are adaptively adjusted, so that the minimum value and the maximum value of a delay interval in which the communication interface can correctly receive data can be determined, and therefore, the optimal input and output delay in which the communication interface can correctly receive data can be simultaneously and accurately determined, and further, the interface time sequence of the communication interface between the FPGA device and the off-chip physical layer chip can be accurately adjusted; on the other hand, the minimum value and the maximum value of the delay interval of the communication interface capable of correctly receiving data can be determined, so that the interface time sequence of the communication interface can be dynamically adjusted within a certain range, and the interface time sequence of the communication interface is self-adaptive to the change of the PHY chip on the board; in still another aspect, when the off-chip physical layer chip changes, the interface timing sequence of the communication interface can adapt to the change of the off-chip physical layer chip, so that the problem of data sampling errors of the communication interface is avoided.

The following are examples of the apparatus of the present application that may be used to perform the method embodiments of the present application. For details not disclosed in the embodiments of the apparatus of the present application, please refer to the embodiments of the method of the present application.

Fig. 5 is a schematic structural diagram of an interface timing adjustment device according to an exemplary embodiment of the application. The interface timing adjustment means may be implemented as all or part of the apparatus by software, hardware or a combination of both. The interface timing adjustment device 500 includes a transceiver module 510, a first training module 520, and a second training module 530. Wherein,

The transceiver module 510 is configured to send a first test packet to the communication interface in a cyclic manner, and receive a corresponding second test packet output by the communication interface;

The first training module 520 is configured to set a delay value of a first delay of the communication interface, train the second delay of the communication interface based on a comparison result of the second test packet and the first test packet, and determine an expected value of the second delay;

A second training module 530, configured to train the first delay based on the expected value of the second delay and the comparison result of the second test packet and the first test packet, determine the expected value of the first delay,

In some example embodiments, based on the above-described scheme, the first training module 520 includes:

A first boundary determining unit, configured to record a first boundary delay corresponding to the second delay at a first moment if the second test packet received at the first moment is consistent with the first test packet sent at the first moment and the second test packet received at a time previous to the first moment is inconsistent with the first test packet sent at the first moment;

A second boundary determining unit, configured to increment a delay value of the second delay of the communication interface, and if the second test packet received at a second moment is inconsistent with the first test packet sent at the second moment, record a second boundary delay of the second delay at the second moment;

and the first expected value determining unit is used for determining an expected value of the second delay based on the first boundary delay and the second boundary delay corresponding to the second delay.

In some example embodiments, based on the above-described scheme, the expected value determining unit is configured to:

And determining an average value of the first boundary delay and the second boundary delay corresponding to the second delay, and taking the average value as an expected value of the second delay.

In some example embodiments, based on the above-described scheme, the first training module 520 is further configured to:

If the second test message received at the first moment is inconsistent with the first test message sent, increasing the delay value of the first delay;

Training the second delay of the communication interface based on the increased delay value of the first delay and the comparison result of the second test message and the first test message, and determining the expected value of the second delay.

In some example embodiments, based on the above-described scheme, the second training module 530 includes:

A third boundary determining unit, configured to set a delay value of the second delay as an expected value of the second delay, and if the second test packet received at a third time is consistent with the first test packet sent, and the second test packet received at a previous time of the third time is inconsistent with the first test packet sent, record a first boundary delay of the first delay at the third time;

a fourth boundary determining unit, configured to increment a delay value of the first delay of the communication interface, and if the second test packet received at a fourth time is inconsistent with the first test packet, record a second boundary delay of the first delay at the fourth time;

and the second expected value determining unit is used for determining an expected value of the first delay based on the first boundary delay and the second boundary delay corresponding to the first delay.

In some example embodiments, based on the above-described scheme, the second expected value determining unit is configured to:

And determining an average value of the first boundary delay and the second boundary delay corresponding to the first delay, and taking the average value as an expected value of the first delay.

In some example embodiments, based on the above scheme, the communication interface is a gigabit media independent interface RGMII interface, and the operation mode of the off-chip physical layer chip is configured to be a loopback mode. .

According to the technical scheme in the example embodiment of fig. 5, on one hand, a test message sent to a communication interface is compared with a test message received by the communication interface, and according to a comparison result, the input delay and the output delay of the communication interface are adaptively adjusted, so that the interface time sequence of the communication interface between the FPGA device and the off-chip physical layer chip can be accurately adjusted; on the other hand, when the off-chip physical layer chip changes, the interface time sequence of the communication interface can adapt to the change of the off-chip physical layer chip, so that the problem of data sampling errors of the communication interface is avoided.

It should be noted that, when the interface timing adjustment device provided in the above embodiment performs the interface timing adjustment method, only the division of the above functional modules is used as an example, in practical application, the above functional allocation may be performed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the interface timing adjustment device and the interface timing adjustment method provided in the foregoing embodiments belong to the same concept, which embody the detailed implementation process in the method embodiment, and are not repeated here.

The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

The embodiment of the present application further provides a computer storage medium, where the computer storage medium may store a plurality of instructions, where the instructions are adapted to be loaded by a processor and execute the interface timing adjustment method according to the foregoing embodiment, and a specific execution process may refer to a specific description of the foregoing embodiment, which is not repeated herein.

The present application also provides a computer program product, which stores at least one instruction, where the at least one instruction is loaded by the processor and executed by the processor to perform the interface timing adjustment method according to the foregoing embodiment, and the specific execution process may refer to the specific description of the foregoing embodiment, which is not repeated herein.

Referring to fig. 6, a schematic structural diagram of an electronic device is provided in an embodiment of the present application. As shown in fig. 6, the electronic device 600 may include: at least one processor 601, at least one network interface 604, an input output interface 603, a memory 605, at least one communication bus 602.

Wherein the communication bus 602 is used to enable connected communications between these components.

The input/output interface 603 may include a Display screen (Display) and a Camera (Camera), and the optional input/output interface 603 may further include a standard wired interface and a standard wireless interface.

The network interface 604 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others.

Wherein the processor 601 may include one or more processing cores. The processor 601 connects various portions of the overall electronic device 600 using various interfaces and lines, performs various functions of the electronic device 600 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 605, and invoking data stored in the memory 605. Alternatively, the processor 601 may be implemented in at least one hardware form of digital signal Processing (DIGITAL SIGNAL Processing, DSP), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 601 may integrate one or a combination of several of a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), and a modem, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It will be appreciated that the modem may not be integrated into the processor 601 and may be implemented by a single chip.

The Memory 605 may include a random access Memory (Random Access Memory, RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 605 includes a non-transitory computer readable medium (non-transitory computer-readable storage medium). Memory 605 may be used to store instructions, programs, code, sets of codes, or sets of instructions. The memory 605 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, etc.; the storage data area may store data or the like referred to in the above respective method embodiments. The memory 605 may also optionally be at least one storage device located remotely from the processor 601. As shown in fig. 6, an operating system, a network communication module, an input-output interface module, and an interface timing adjustment application program may be included in the memory 605, which is one type of computer storage medium.

In the electronic device 600 shown in fig. 6, the input/output interface 603 is mainly used for providing an input interface for a user, and acquiring data input by the user; and the processor 601 may be configured to invoke an interface timing adjustment application stored in the memory 605, where the interface timing adjustment application is configured to adjust the timing of a communication interface between the field programmable gate array FPGA device and the off-chip physical layer chip, and the processor 601 specifically performs the following operations:

In some embodiments, based on the above-mentioned scheme, when the processor 601 performs the training on the second delay of the communication interface based on the comparison result of the second test packet and the first test packet, and determines the expected value of the second delay, the processor specifically performs the following operations:

if the second test message received at the first moment is consistent with the first test message transmitted and the second test message received at the last moment of the first moment is inconsistent with the first test message transmitted, recording a first boundary delay corresponding to the second delay at the first moment;

Increasing the delay value of the second delay of the communication interface, and if the second test message received at the second moment is inconsistent with the first test message sent, recording the second boundary delay of the second delay at the second moment;

and determining an expected value of the second delay based on the first boundary delay and the second boundary delay corresponding to the second delay.

In some embodiments, based on the foregoing solution, when the processor 601 determines the expected value of the second delay by executing the first boundary delay and the second boundary delay corresponding to the second delay, the following operations are specifically executed:

In some embodiments, based on the above-mentioned scheme, when executing the setting of the delay value of the first delay of the communication interface, based on the comparison result of the second test packet and the first test packet, the processor 601 trains the second delay of the communication interface, and determines the expected value of the second delay, the processor specifically executes the following operations:

In some embodiments, based on the foregoing solution, when the processor 601 performs the comparison result between the second test packet and the first test packet based on the expected value of the second delay, trains the first delay, and determines the expected value of the first delay, the processor specifically performs the following operations:

If the second test message received at the third moment is consistent with the first test message transmitted and the second test message received at the last moment of the third moment is inconsistent with the first test message transmitted, recording the first boundary delay of the first delay at the third moment;

increasing the delay value of the first delay of the communication interface, and if the second test message received at the fourth moment is inconsistent with the first test message, recording the second boundary delay of the first delay at the fourth moment;

And determining an expected value of the first delay based on the first boundary delay and the second boundary delay corresponding to the first delay.

In some embodiments, based on the foregoing solution, when the processor 601 determines the expected value of the first delay by executing the first boundary delay and the second boundary delay corresponding to the first delay, the following operations are specifically executed:

In some example embodiments, based on the above scheme, the communication interface is a gigabit media independent interface RGMII interface, and the operation mode of the off-chip physical layer chip is configured to be a loopback mode.

The foregoing is a schematic solution of an electronic device according to an embodiment of the present disclosure. It should be noted that, the technical solution of the electronic device and the technical solution of the interface timing adjustment processing method belong to the same concept, and details of the technical solution of the electronic device, which are not described in detail, can be referred to the description of the technical solution of the interface timing adjustment processing method.

In the description of the present application, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present application, it should be noted that, unless expressly specified and limited otherwise, "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art. Furthermore, in the description of the present application, unless otherwise indicated, "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory, a random access memory, or the like.

The foregoing disclosure is illustrative of the present application and is not to be construed as limiting the scope of the application, which is defined by the appended claims.

Claims

1. An interface timing adjustment method, for adjusting timing of a communication interface between a field programmable gate array FPGA device and an off-chip physical layer chip, the method comprising:

Setting an initial delay value of a first delay of the communication interface, training the second delay of the communication interface based on a comparison result of the second test message and the first test message, and determining an expected value of the second delay;

2. The method of claim 1, wherein training the second delay of the communication interface based on the comparison of the second test message and the first test message, determining the expected value of the second delay, comprises:

if the second test message received at the first moment is consistent with the first test message sent, recording a delay value corresponding to the second delay at the first moment as a first boundary delay;

increasing the delay value of the second delay of the communication interface, and if the second test message received at the second moment is inconsistent with the first test message sent, recording the delay value of the second delay at the second moment as a second boundary delay;

3. The method of claim 2, wherein the determining the expected value of the second delay based on the first and second boundary delays corresponding to the second delay comprises:

4. The method of claim 2, wherein the setting the initial delay value of the first delay of the communication interface, training the second delay of the communication interface based on the comparison result of the second test packet and the first test packet, and determining the expected value of the second delay further comprises:

5. The method of claim 1, wherein the training the first delay to determine the expected value of the first delay based on the expected value of the second delay and a comparison of the second test message and the first test message comprises:

Setting the delay value of the second delay as an expected value of the second delay, and if the second test message received at a third moment is consistent with the first test message sent, recording the delay value of the first delay at the third moment as a first boundary delay;

Increasing the delay value of the first delay of the communication interface, and if the second test message received at the fourth moment is inconsistent with the first test message, recording the delay value of the first delay at the fourth moment as a second boundary delay;

6. The method of claim 5, wherein the determining the desired value of the first delay based on the first and second boundary delays corresponding to the first delay comprises:

7. The method of any of claims 1 to 6, wherein the communication interface is a gigabit media independent interface, RGMII, interface and the off-chip physical layer chip is configured in a loopback mode.

8. An interface timing adjustment apparatus for adjusting timing of a communication interface between an FPGA device and an off-chip physical layer chip, the apparatus comprising:

9. A computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the steps of the method according to any one of claims 1 to 7.

10. An electronic device, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the steps of the method according to any one of claims 1-7.