CN118191549A - Wafer test machine and method for testing dynamic parameters of wafer - Google Patents
Wafer test machine and method for testing dynamic parameters of wafer Download PDFInfo
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- CN118191549A CN118191549A CN202410598190.5A CN202410598190A CN118191549A CN 118191549 A CN118191549 A CN 118191549A CN 202410598190 A CN202410598190 A CN 202410598190A CN 118191549 A CN118191549 A CN 118191549A
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- 238000012360 testing method Methods 0.000 title claims abstract description 195
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000000523 sample Substances 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 7
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 9
- 238000013461 design Methods 0.000 abstract description 6
- 235000012431 wafers Nutrition 0.000 description 185
- 238000012216 screening Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010998 test method Methods 0.000 description 2
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- 239000013256 coordination polymer Substances 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
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Abstract
The invention provides a wafer test machine and a method for testing dynamic parameters of a wafer, wherein the test machine comprises: the wafer tray is used for placing a wafer to be tested and is electrically connected with a Drain electrode of the wafer to be tested; the central connecting frame is positioned above the wafer tray, contacted with the edge of the wafer tray and electrically connected with the edge of the wafer tray; the test equipment lower bottom plate is positioned above the central connecting frame; the wafer tray is raised so that the central connection frame contacts the test equipment lower plate to form a closed cavity surrounding the wafer to be tested, and the test equipment lower plate is electrically connected with the central connection frame to connect the Drain electrode of the wafer to be tested to the test equipment. According to the invention, the wafer Drain electrode to be tested is connected to the testing equipment through the wafer tray, the central connecting frame and the testing equipment lower bottom plate, no connecting wire is needed, and a closed cavity is formed, and stray inductance can be reduced through optimizing the magnetic field design of the cavity, so that dynamic parameters can be tested at the wafer stage, and the packaging cost is reduced.
Description
Technical Field
The present invention relates to the field of testing, and in particular, to a wafer testing machine and a method for testing dynamic parameters of a wafer.
Background
Currently, the wafer probe stations on the market, whether manual or automatic, are of an open structure. Basically, the wafer is held stationary using a wafer tray support and is connected as a Drain electrode (Drain) to a Drain electrode test port of an external test device by a wafer tray wire. Probes are then used externally to probe over the wafer, contact the Gate and Source electrodes on the wafer surface, and electrically connect to corresponding pins of the test equipment. This approach is well suited for DC parameter testing of wafers.
However, in recent years, with the popularization and application of third-generation semiconductors, and the rapid development of EVs (electric car markets), new and higher demands are being made on the test. Power components (e.g., siC MOSFETs, si MOSFETs, IGBTs) begin to require 100% test dynamic parameters such as switching time, switching energy loss, shorts, etc. However, the third generation semiconductor devices such as SiC are not yet mature and have low yields. If the test is placed in the back end, such as the finished end, significant packaging costs are wasted. Therefore, advancing the testing stage is an excellent way to reduce costs.
The cost is reduced by 90% for every forward movement. For example, the popular way of advancing the test of the finished product section to KGD (bare die) at the present stage can save 90% of the package test cost compared with the method of advancing the test of the finished product section at the present stage. If it is possible to move from the KGD stage to the CP (wafer) stage again, the cost may be reduced by a further 90%.
However, the wafer probe stations currently on the market are only suitable for DC (direct current) testing of wafers and have little ability to test AC (dynamic parameters).
Disclosure of Invention
The invention aims to provide a wafer test machine and a wafer dynamic parameter test method, which can test the dynamic parameters of a wafer in a wafer stage, thereby reducing the packaging cost.
In order to solve the above technical problems, the present invention provides a wafer testing machine, comprising:
The wafer tray is used for placing a wafer to be tested and is electrically connected with the Drain electrode of the wafer to be tested;
The central connecting frame is annular in section, is positioned above the wafer tray, and is in contact with and electrically connected with the edge of the wafer tray; and
The lower bottom plate of the test equipment is plate-shaped and is positioned above the central connecting frame;
The wafer tray can drive the central connecting frame to ascend or descend relative to the lower bottom plate of the testing device, the wafer tray ascends to enable the central connecting frame to be in contact with the lower bottom plate of the testing device to form a closed cavity surrounding the wafer to be tested, and the lower bottom plate of the testing device is electrically connected with the central connecting frame so as to connect the Drain electrode of the wafer to be tested to the testing device.
Optionally, a first connection portion penetrating through the central connection frame is disposed on the central connection frame, so as to electrically connect the wafer tray and the test equipment lower plate.
Optionally, the first connection portion includes a plurality of double-sided spring pins or a plurality of metal spring plates.
Optionally, the double-sided spring pins or the metal spring plates are uniformly distributed on the central connecting frame.
Optionally, the wafer test machine further includes a second connection portion; when the lower bottom plate of the testing device is in contact connection with the central connecting frame, one end of the second connecting part is connected with the Source electrode or the Gate electrode of the wafer to be tested, and the other end of the second connecting part is connected with the testing device.
Optionally, the second connection portion is disposed in the lower bottom plate of the test device and protrudes from the upper and lower surfaces of the lower bottom plate of the test device.
Optionally, the second connection portion includes a plurality of vertical probes, and adjacent vertical probes are insulated from each other.
Optionally, the diameter of the lower bottom plate of the testing device is greater than or equal to twice the diameter of the wafer to be tested.
Correspondingly, the invention also provides a testing method of the wafer dynamic parameters, which adopts the wafer testing machine to test, and comprises the following steps:
placing a wafer to be tested on a wafer tray, wherein a Drain electrode of the wafer to be tested is connected with the wafer tray;
Lifting the wafer tray, wherein a closed cavity is formed by the wafer tray, the central connecting frame and the test equipment lower base plate to surround the wafer to be tested, and the test equipment lower base plate is electrically connected with the central connecting frame so as to connect the Drain electrode of the wafer to be tested to test equipment;
And testing the wafer to be tested.
Optionally, after the wafer tray is lifted, the test device provides signals to the Source electrode and the Gate electrode of the wafer to be tested through the second connection part.
In summary, in the wafer test machine and the method for testing dynamic parameters of a wafer provided by the invention, the test machine includes a wafer tray for placing a wafer to be tested and electrically connecting with a Drain electrode of the wafer to be tested; the central connecting frame is annular in section, is positioned above the wafer tray, and is in contact with and electrically connected with the edge of the wafer tray; the lower bottom plate of the test equipment is plate-shaped and is positioned above the central connecting frame; the wafer tray can drive the central connecting frame to ascend or descend relative to the lower bottom plate of the testing device, the wafer tray ascends to enable the central connecting frame to be in contact with the lower bottom plate of the testing device to form a closed cavity surrounding the wafer to be tested, and the lower bottom plate of the testing device is electrically connected with the central connecting frame so as to connect the Drain electrode of the wafer to be tested to the testing device. According to the invention, the wafer Drain electrode to be tested is connected to the testing equipment through the wafer tray, the central connecting frame and the testing equipment lower bottom plate, no connecting wire is needed, and a closed cavity is formed, and the stray inductance can be reduced in the safe creepage gap by optimizing the magnetic field design, so that the requirement of testing dynamic parameters in the wafer stage is completely met, and the key technology of testing dynamic parameters in the wafer stage is broken through. Meanwhile, the method has a great breakthrough in industry for reducing packaging cost, is suitable for high-requirement product reliability screening and mass production, and can improve product quality and reduce risk.
Furthermore, the vertical probe is used for connecting the Source electrode or Gate electrode of the wafer to be tested with the testing equipment, so that the distance from the testing circuit to the wafer to be tested can be shortened, and stray inductance is further reduced.
Drawings
Fig. 1 is a schematic view of a wafer structure.
Fig. 2 is a cross-sectional view of a conventional wafer probe station.
FIG. 3 is a cross-sectional view of a wafer test station according to one embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a wafer testing machine according to an embodiment of the invention.
Reference numerals illustrate:
in fig. 2, 10-wafer pallet; 20-a probe holder plate; 30-a wafer to be tested;
In fig. 3 and 4, a 100-wafer tray; 110-a central connection rack; 120-a test equipment lower plate; 130-a first connection; 140-a second connection; 150-a base; 160-a bracket; 200-wafer to be tested.
Detailed Description
Fig. 1 is a schematic view of a wafer structure. Referring to fig. 1, the front surface of the wafer is divided into a plurality of small blocks, each of which is a chip (die), the front surface of each chip is provided with a Gate electrode (G) and a Source electrode (S), and the whole back surface is a Drain electrode. After the test is completed, the wafer is divided and packaged to form a finished device.
Fig. 2 is a cross-sectional view of a conventional wafer probe station. Referring to fig. 2, the wafer probe station includes a wafer tray 10 and a probe support tray 20, the probe support tray 20 and the wafer tray 10 are not physically connected, and when a test is performed, a tri-axis platform (not shown) below the wafer tray 10 is automatically aligned and then lifted up, so that a wafer 30 to be tested in the wafer tray 10 contacts with a probe above the probe support tray 20, thereby completing a circuit. The test equipment is then connected to the probes through external wires, contacts the Gate and Source electrodes of the chips on the wafer, and is connected to the Drain electrode of the wafer through the wafer tray, completing the test.
The inventors have found that: the conventional wafer probe station is only suitable for DC test of the wafer, and has little capability on AC test because the Drain pin on the conventional wafer probe station needs to be connected with a long connecting line to be connected with test equipment, so that the stray inductance cannot be ignored. According to the test requirement of the dynamic parameters, the dynamic parameters of the device can be detected more accurately, and the stray inductance of the circuit needs to be controlled below 40 nH. This requirement is almost impossible to accomplish with conventional wafer probe stations.
Through further research, the invention provides a wafer test machine and a wafer dynamic parameter test method, a wafer Drain electrode to be tested is connected to test equipment through a wafer tray, a central connecting frame and a test equipment lower bottom plate, no connecting wire is needed, and a closed cavity is formed. Meanwhile, the method has a great breakthrough in industry for reducing packaging cost, is suitable for high-requirement product reliability screening and mass production, and can improve product quality and reduce risk.
The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
As used in this disclosure, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. As used in this disclosure, the term "or" is generally employed in its sense including "and/or" unless the content clearly dictates otherwise. As used in this disclosure, the term "plurality" is generally employed in its sense including "at least one" unless the content clearly dictates otherwise. As used in this disclosure, the term "at least two" is generally employed in its sense including "two or more", unless the content clearly dictates otherwise. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", "a third" may include one or at least two such features, either explicitly or implicitly.
Fig. 3 is a cross-sectional view of a wafer testing machine according to an embodiment of the present invention, and fig. 4 is a schematic structural diagram of the wafer testing machine according to an embodiment of the present invention. Referring to fig. 3 and 4, the present embodiment provides a wafer testing apparatus, which includes:
A wafer tray 100, configured to place a wafer 200 to be tested and electrically connect to a Drain electrode of the wafer 200 to be tested;
a central connection frame 110 having a ring-shaped cross section, located above the wafer tray 100, contacting and electrically connected to an edge of the wafer tray 100;
A lower testing device base plate 120 having a plate shape and located above the central connecting frame 110;
The wafer tray 100 can drive the central connection frame 110 to ascend or descend relative to the test equipment lower plate 120, the wafer tray 100 ascends to enable the central connection frame 110 to be in contact with the test equipment lower plate 120 to form a closed cavity surrounding the wafer 200 to be tested, and the test equipment lower plate 120 is electrically connected with the central connection frame 110 to connect the Drain electrode of the wafer 200 to be tested to the test equipment.
In this embodiment, the cross section of the central connection frame 110 is circular, the central connection frame 110 contacts with the edge of the wafer tray 100, and the central connection frame 110 may be fixed to the edge of the wafer tray 100, and forms a bottom and a sidewall of the cavity together with the wafer tray 100. The wafer tray 100 is connected to the Drain pole of the wafer 200 to be tested placed thereon, and the center connection frame 110 is electrically connected to the wafer tray 100, and thus to the Drain pole of the wafer 200 to be tested.
The wafer tray 100 can drive the central connection frame 110 to ascend or descend relative to the test equipment lower plate 120, and the wafer tray 100 ascends to enable the central connection frame 110 to contact with the test equipment lower plate 120, so as to form a closed cavity surrounding the wafer 200 to be tested. I.e. the test equipment lower plate 120 acts as a top cover for the cavity. The test equipment lower plate 120 is electrically connected to the center connection frame 110 to connect the Drain pole of the wafer 200 to be tested to a Drain pole test port of a test equipment (not shown). The wafer tray 100 is lowered so that the central connection frame 110 is separated from the test equipment lower plate 120, and the wafer 200 to be tested can be taken out or put in.
According to the invention, the Drain pole of the wafer 200 to be tested is connected to the testing equipment through the wafer tray 100, the central connecting frame 110 and the testing equipment lower plate 120 without connecting wires, and the three components of the wafer tray 100, the central connecting frame 110 and the testing equipment lower plate 120 form a closed cavity, so that the stray inductance of the whole testing loop can be reduced to 10 nH orders of magnitude within a safe creepage clearance by optimizing a magnetic field design, the requirement of dynamic parameter testing is completely met, and the key technology for testing dynamic parameters in the wafer stage is broken through. Meanwhile, the method has a great breakthrough in industry for reducing packaging cost, is suitable for high-requirement product reliability screening and mass production, can improve product quality and reduce risk, and lays a road for popularization and application of third-generation semiconductor devices.
In an embodiment of the present invention, as shown in fig. 4, a first connection portion 130 penetrating through the central connection frame 110 is disposed on the central connection frame 110 to electrically connect the wafer tray 100 with the test equipment lower plate 120, i.e. one end of the first connection portion 130 is electrically connected with the wafer tray 100, and the other end is electrically connected with the test equipment lower plate 120. In this embodiment, the first connection portion 130 includes a plurality of double-sided spring pins or a plurality of metal spring plates. The double-sided spring pins or the metal spring plates are uniformly distributed on the central connecting frame 110. The central connecting frame 110 is made of insulating material, and the double-sided spring pins or the metal spring plates are embedded in the central connecting frame 110 and are exposed on the upper surface and the lower surface of the central connecting frame 110.
In an embodiment of the present invention, referring to fig. 3 and 4, a second connection portion 140 is disposed on the lower bottom board 120 of the testing apparatus, and when the lower bottom board 120 of the testing apparatus is in contact connection with the central connection frame 110, one end of the second connection portion 140 is connected to the Source electrode or Gate electrode of the wafer 200 to be tested, and the other end is connected to the testing apparatus. That is, when the lower board 120 of the testing apparatus is in contact connection with the central connection frame 110, the second connection portion 140 connects the Source electrode of the wafer 200 to be tested with the Source electrode testing port of the testing apparatus, and connects the Gate electrode of the wafer 200 to be tested with the Gate electrode testing port of the testing apparatus.
In this embodiment, the second connection portion 140 is disposed in the lower test device chassis 120 and protrudes from the upper and lower surfaces of the lower test device chassis 120, that is, the second connection portion 140 penetrates the lower test device chassis 120 and extends from the upper and lower surfaces of the lower test device chassis 120. The second connection part 140 is insulated from the lower bottom plate 120 of the testing apparatus, when the wafer tray 100 is lifted up to make the central connection frame 110 contact and connect with the lower bottom plate 120 of the testing apparatus, one end of the second connection part 140 is just connected with the Source electrode or Gate electrode of the wafer 200 to be tested, and the other end of the second connection part 140 is connected with the testing port of the testing apparatus, so as to communicate the testing apparatus with the Source electrode or Gate electrode of the wafer 200 to be tested.
In this embodiment, the second connection portion 140 includes a plurality of vertical probes, and adjacent vertical probes are insulated from each other. Preferably, the second connection portion 140 has a columnar shape, and includes a plurality of vertical probes and an insulating layer surrounding and isolating the adjacent vertical probes. The vertical probe can shorten the distance from the test circuit to the wafer 200 to be tested, and further reduce the stray inductance.
In an embodiment of the present invention, the diameter of the lower bottom plate 120 of the testing apparatus is greater than or equal to twice the diameter of the wafer 200 to be tested. Regardless of how the wafer 200 to be tested moves, after the wafer tray 100 is lifted, the wafer tray does not go beyond the range of the lower bottom plate 120 of the test equipment, and can be perfectly contacted with the lower bottom plate 120 of the test equipment, so that a closed cavity is formed.
Referring to fig. 4, the wafer test machine further includes a base 150 and a support 160, where the support 160 is connected to the base 150 to support the lower bottom plate 120 of the test apparatus. Of course, the base 150 and the stand 160 of fig. 4 are both simple schematic diagrams. In addition, in fig. 4, for better displaying the central connection frame 110 and the second connection portion 140, only the circular shape is used to represent the test equipment lower plate 120.
The wafer test machine provided by the invention comprises a wafer tray 100, a first electrode and a second electrode, wherein the wafer tray 100 is used for placing a wafer 200 to be tested and is electrically connected with a Drain electrode of the wafer 200 to be tested; a central connection frame 110 having a ring-shaped cross section, located above the wafer tray 100, contacting and electrically connected to an edge of the wafer tray 100; a lower testing device base plate 120 having a plate shape and located above the central connecting frame 110; the wafer tray 100 can drive the central connection frame 110 to ascend or descend relative to the test equipment lower plate 120, the wafer tray 100 ascends to enable the central connection frame 110 to be in contact with the test equipment lower plate 120 to form a closed cavity surrounding the wafer 200 to be tested, and the test equipment lower plate 120 is electrically connected with the central connection frame 110 to connect the Drain electrode of the wafer 200 to be tested to the test equipment. According to the invention, the Drain electrode of the wafer 200 to be tested is connected to the testing equipment through the wafer tray 100, the central connecting frame 110 and the testing equipment lower base plate 120, no connection is needed, and a closed cavity is formed, and the cavity can reduce stray inductance in a safe creepage gap by optimizing magnetic field design, so that the requirement of testing dynamic parameters in the wafer stage is completely met, and the key technology of testing dynamic parameters in the wafer stage is broken through. The method has a great breakthrough in reducing the packaging cost in the industry, is suitable for screening and mass production of high-requirement products, and can improve the product quality and reduce the risk.
Correspondingly, the invention also provides a testing method of wafer dynamic parameters, which adopts the wafer testing machine to test, and referring to fig. 3 and 4, the testing method comprises the following steps:
placing a wafer 200 to be tested on a wafer tray 100, wherein a Drain electrode of the wafer 200 to be tested is connected with the wafer tray 100;
raising the wafer tray 100, wherein the wafer tray 100 and the central connection frame 110 and the test equipment lower plate 120 form a closed cavity to enclose the wafer 200 to be tested, and the test equipment lower plate 120 is electrically connected with the central connection frame 110 so as to connect the Drain electrode of the wafer 200 to be tested to a test equipment;
and testing the wafer 200 to be tested.
The wafer tray 100 ascends, the wafer tray 100, the central connection frame 110 and the test equipment lower plate 120 form a closed cavity, the Drain electrode of the wafer 200 to be tested is connected to the test equipment through the wafer tray 100, the central connection frame 110 and the test equipment lower plate 120, no connection is needed, and a closed cavity is formed, and stray inductance can be reduced within a safe creepage gap by optimizing a magnetic field design, so that the requirement of testing dynamic parameters in a wafer stage is completely met, and the key technology of testing dynamic parameters in the wafer stage is broken through. The method has a great breakthrough in reducing the packaging cost in the industry, is suitable for screening and mass production of high-requirement products, and can improve the product quality and reduce the risk.
In this embodiment, after the wafer tray 100 is lifted, the testing device provides signals to the Source electrode and Gate electrode of the wafer 200 to be tested through the second connection portion 140, and the testing device provides signals to the Drain electrode of the wafer 200 to be tested through the testing device lower plate 120, the first connection portion 130 located in the central connection frame 110, and the wafer tray 100, so as to perform dynamic parameter testing on the wafer 200 to be tested.
In summary, in the wafer test machine and the method for testing dynamic parameters of a wafer provided by the invention, the test machine includes a wafer tray for placing a wafer to be tested and electrically connecting with a Drain electrode of the wafer to be tested; the central connecting frame is annular in section, is positioned above the wafer tray, and is in contact with and electrically connected with the edge of the wafer tray; the lower bottom plate of the test equipment is plate-shaped and is positioned above the central connecting frame; the wafer tray can drive the central connecting frame to ascend or descend relative to the lower bottom plate of the testing device, the wafer tray ascends to enable the central connecting frame to be in contact with the lower bottom plate of the testing device to form a closed cavity surrounding the wafer to be tested, and the lower bottom plate of the testing device is electrically connected with the central connecting frame so as to connect the Drain electrode of the wafer to be tested to the testing device. According to the invention, the wafer Drain electrode to be tested is connected to the testing equipment through the wafer tray, the central connecting frame and the testing equipment lower bottom plate, no connecting wire is needed, and a closed cavity is formed, and the stray inductance can be reduced in the safe creepage gap by optimizing the magnetic field design, so that the requirement of testing dynamic parameters in the wafer stage is completely met, and the key technology of testing dynamic parameters in the wafer stage is broken through. Meanwhile, the method has a great breakthrough in industry for reducing packaging cost, is suitable for high-requirement product reliability screening and mass production, and can improve product quality and reduce risk.
Furthermore, the vertical probe is used for connecting the Source electrode or Gate electrode of the wafer to be tested with the testing equipment, so that the distance from the testing circuit to the wafer to be tested can be shortened, and stray inductance is further reduced.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (10)
1. A wafer test station, comprising:
The wafer tray is used for placing a wafer to be tested and is electrically connected with the Drain electrode of the wafer to be tested;
The central connecting frame is annular in section, is positioned above the wafer tray, and is in contact with and electrically connected with the edge of the wafer tray; and
The lower bottom plate of the test equipment is plate-shaped and is positioned above the central connecting frame;
The wafer tray can drive the central connecting frame to ascend or descend relative to the lower bottom plate of the testing device, the wafer tray ascends to enable the central connecting frame to be in contact with the lower bottom plate of the testing device to form a closed cavity surrounding the wafer to be tested, and the lower bottom plate of the testing device is electrically connected with the central connecting frame so as to connect the Drain electrode of the wafer to be tested to the testing device.
2. The wafer test station of claim 1, wherein the central connection frame is provided with a first connection portion penetrating the central connection frame to electrically connect the wafer tray and the test equipment lower plate.
3. The wafer test tool of claim 2, wherein the first connection portion comprises a plurality of double-sided pogo pins or a plurality of metal spring strips.
4. The wafer test station of claim 3, wherein the double-sided spring pins or the metal spring plates are uniformly distributed on the central connection frame.
5. The wafer test station of claim 1, further comprising a second connection; when the lower bottom plate of the testing device is in contact connection with the central connecting frame, one end of the second connecting part is connected with the Source electrode or the Gate electrode of the wafer to be tested, and the other end of the second connecting part is connected with the testing device.
6. The wafer testing machine of claim 5, wherein the second connecting portion is disposed in the testing apparatus lower plate and protrudes from the upper and lower surfaces of the testing apparatus lower plate.
7. The wafer test station of claim 6, wherein the second connection portion includes a plurality of vertical probes, adjacent ones of the vertical probes being insulated from each other.
8. The wafer test station of any one of claims 1-7, wherein a diameter of the test equipment lower plate is equal to or greater than twice a diameter of the wafer to be tested.
9. A method for testing dynamic parameters of a wafer, wherein the wafer testing machine according to any one of claims 1 to 8 is used for testing, and the method comprises:
placing a wafer to be tested on a wafer tray, wherein a Drain electrode of the wafer to be tested is connected with the wafer tray;
Lifting the wafer tray, wherein a closed cavity is formed by the wafer tray, the central connecting frame and the test equipment lower base plate to surround the wafer to be tested, and the test equipment lower base plate is electrically connected with the central connecting frame so as to connect the Drain electrode of the wafer to be tested to test equipment;
And testing the wafer to be tested.
10. The method of claim 9, wherein after the wafer tray is lifted, the test apparatus provides signals to Source and Gate of the wafer to be tested via a second connection.
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| JP2011138865A (en) * | 2009-12-28 | 2011-07-14 | Micronics Japan Co Ltd | Inspection apparatus of semiconductor device |
| US20130141132A1 (en) * | 2011-12-05 | 2013-06-06 | Kabushiki Kaisha Nihon Micronics | Inspection apparatus for semiconductor devices and chuck stage used for the inspectionapparatus |
| JP2018037538A (en) * | 2016-08-31 | 2018-03-08 | 株式会社東京精密 | Prober |
| CN112005352A (en) * | 2018-03-30 | 2020-11-27 | 日本麦可罗尼克斯股份有限公司 | Probe station |
| TW202204917A (en) * | 2020-04-17 | 2022-02-01 | 美商盧曼頓運作有限公司 | Wafer prober to facilitate testing of a wafer using nanosecond pulses |
| CN114188238A (en) * | 2021-04-20 | 2022-03-15 | 山东大学 | Semiconductor device wafer dynamic parameter testing and sorting system and method |
| CN219831302U (en) * | 2023-04-10 | 2023-10-13 | 盛合晶微半导体(江阴)有限公司 | Probe station for wafer test |
| CN117517914A (en) * | 2023-10-20 | 2024-02-06 | 中国电子科技集团公司第二十四研究所 | Back drain MOSFET wafer dynamic parameter test structure and method |
| CN117577552A (en) * | 2023-12-01 | 2024-02-20 | 忱芯科技(上海)有限公司 | Wafer reliability test system |
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