CN118175841A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN118175841A CN118175841A CN202211579699.2A CN202211579699A CN118175841A CN 118175841 A CN118175841 A CN 118175841A CN 202211579699 A CN202211579699 A CN 202211579699A CN 118175841 A CN118175841 A CN 118175841A
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Abstract
A semiconductor structure and a method of forming the same, the semiconductor structure comprising: a substrate including a capacitive region; the first electrode layer is positioned on the substrate of the capacitance area, and a groove is formed in the first electrode layer of the capacitance area; a second electrode layer covering the first electrode layer at the side wall and bottom of the groove and the top of the first electrode layer; and the first dielectric layer is positioned between the first electrode layer and the second electrode layer, and conformally covers the bottom and the side wall of the groove and the top of the first electrode layer outside the groove. The grooves are formed in the first electrode layer, so that the effective area right opposite to the first electrode layer and the second electrode layer can be increased under the condition that the occupied area of the capacitance area is not increased, the capacitance value of a capacitor formed by the first electrode layer, the first dielectric layer and the second electrode layer is correspondingly increased, the capacitance value of the semiconductor device is also increased, and further the performance of the semiconductor structure is improved.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid growth of the semiconductor integrated circuit (INTEGRATED CIRCUIT, IC) industry, semiconductor technology continues to advance toward smaller process nodes driven by moore's law, resulting in integrated circuits that are evolving toward smaller volumes, higher circuit precision, and higher circuit complexity.
In the development of integrated circuits, the functional density (i.e., the number of interconnect structures per chip) has generally increased while the geometry (i.e., the minimum device size that can be produced using process steps) has been reduced, which has correspondingly increased the difficulty and complexity of integrated circuit fabrication.
As one of the passive devices commonly used in the integrated circuit process, capacitors are widely used in various electronic circuits for preventing the emission of noise, modulation frequency, charge pump (charge pump), and the like from analog circuits. At present, under the condition that process nodes are continuously reduced, the process cost of the capacitor device formed by the prior art is high, and the performance of the capacitor device still needs to be improved.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of the semiconductor structure.
To solve the above problems, the present invention provides a semiconductor structure, including: a substrate comprising a capacitive region; the first electrode layer is positioned on the substrate of the capacitance area, and a groove is formed in the first electrode layer of the capacitance area; a second electrode layer covering the first electrode layer at the side wall and bottom of the groove and the top of the first electrode layer; and the first dielectric layer is positioned between the first electrode layer and the second electrode layer, and conformally covers the bottom and the side wall of the groove and the top of the first electrode layer outside the groove.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: comprising the following steps: providing a substrate, wherein the substrate comprises a capacitance region; forming a first electrode layer on a substrate of the capacitor region; forming a groove in the first electrode layer in the capacitance region; forming a first dielectric layer conformally covering the bottom and the side walls of the groove and the top of the first electrode layer outside the groove; and forming a second electrode layer covering the first dielectric layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
In the semiconductor structure provided by the embodiment, the first electrode layer located in the capacitance region is provided with the groove, the second electrode layer covers the first electrode layer on the side wall and the bottom of the groove and the top of the first electrode layer, and the first electrode layer and the second electrode layer are isolated through the first dielectric layer, so that the effective area right between the first electrode layer and the second electrode layer can be increased under the condition that the occupied area of the capacitance region is not increased, the capacitance value of a capacitor formed by the first electrode layer, the first dielectric layer and the second electrode layer is correspondingly increased, the capacitance value of the semiconductor device is also increased, and further the performance of the semiconductor structure is improved.
In the method for forming a semiconductor structure provided by the embodiment of the invention, a groove in the first electrode layer is formed in the capacitor region; forming a first dielectric layer which conformally covers the bottom and the side wall of the groove and the top of the first electrode layer outside the groove; and then forming a second electrode layer covering the first dielectric layer, so that the effective area right opposite to the first electrode layer and the second electrode layer can be increased under the condition of not increasing the occupied area of the capacitance area, the capacitance value of a capacitor formed by the first electrode plate, the first dielectric layer and the second electrode plate is correspondingly increased, the capacitance value of the semiconductor device is also increased, and the performance of the semiconductor structure is further improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
FIG. 2 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;
fig. 3 to 11 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
Currently, the performance of semiconductor structures is still to be improved. The reason why the performance of a semiconductor structure is to be improved is now analyzed in combination with a semiconductor structure.
Fig. 1 is a schematic structural diagram of a semiconductor structure.
Referring to fig. 1, a semiconductor structure comprising: a substrate 10, the substrate 10 including a capacitive region (not shown); a first electrode layer 11 on the substrate 10 of the capacitor region; a first dielectric layer 12 covering the first electrode layer 11; the second electrode layer 13 is covered on the first dielectric layer 12.
Through researches, the conventional capacitor structure is a two-dimensional plane structure, and is limited by the opposite effective area between the first electrode layer 11 and the second electrode layer 13, so that the capacitance value of the capacitor is smaller, if the capacitance value of the capacitor is increased, the area of the capacitor area needs to be increased, the area of a chip is often increased, and thus the increase of the functional density of the integrated circuit and the reduction of the geometric dimension are not facilitated, and the economic benefit is correspondingly reduced. Therefore, a new method is needed to increase the capacitance value of the capacitor on a substrate per unit area.
In order to solve the above-mentioned technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate including a capacitive region; the first electrode layer is positioned on the substrate of the capacitance area, and a groove is formed in the first electrode layer of the capacitance area; a second electrode layer covering the first electrode layer at the side wall and bottom of the groove and the top of the first electrode layer; and the first dielectric layer is positioned between the first electrode layer and the second electrode layer, and conformally covers the bottom and the side wall of the groove and the top of the first electrode layer outside the groove.
In the semiconductor structure provided by the embodiment, the first electrode layer positioned in the capacitance region is provided with the groove, the second electrode layer covers the first electrode layer on the side wall and the bottom of the groove and the top of the first electrode layer, and the first electrode layer and the second electrode layer are isolated by the first dielectric layer, so that the effective area right between the first electrode layer and the second electrode layer can be increased under the condition that the occupied area of the capacitance region is not increased, the capacitance value of a capacitor formed by the first electrode layer, the first dielectric layer and the second electrode layer is correspondingly increased, the capacitance value of the semiconductor device is also increased, and further the performance of the semiconductor structure is improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings.
Fig. 2 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.
In this embodiment, the semiconductor structure includes: comprising the following steps: a substrate 100, the substrate 100 including a capacitive region I; a first electrode layer 110 on the substrate 100 in the capacitance region I, wherein a groove 111 is formed in the first electrode layer 110 in the capacitance region I; a second electrode layer 130 covering the first electrode layer 110 at the sidewall and bottom of the recess 111, and the top of the first electrode layer 110; the first dielectric layer 120 is located between the first electrode layer 110 and the second electrode layer 130, and the first dielectric layer 120 conformally covers the bottom and the sidewalls of the recess 111, and the top of the first electrode layer 110 outside the recess 111.
The substrate 100 is used to provide a process platform for forming a capacitor, and the capacitor is correspondingly formed on the substrate 100 in the capacitor region I.
The capacitor is typically composed of two plates and an insulating layer between the two plates, and the main types include MOS (metal-oxide-semiconductor) capacitor, PIP (polysilicon-insulator-polysilicon) capacitor, MIM (metal-insulator-metal) capacitor, MOM (metal-oxide-metal) capacitor, etc.
In this embodiment, the base 100 includes a substrate (not shown), which is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrate or germanium on insulator substrate.
The first electrode layer 110 serves as a bottom plate of a capacitor.
The material of the first electrode layer 110 includes polysilicon or metal. In this embodiment, taking a PIP capacitor as an example, the material of the first electrode layer 110 is polysilicon.
The first electrode layer 110 located in the capacitance area I has the groove 111, so that the second electrode layer 130 covers the first electrode layer 110 on the sidewall and bottom of the groove 111 and the top of the first electrode layer 110, and is isolated from each other by the first dielectric layer 120, thereby increasing the effective area opposite to the first electrode layer 110 and the second electrode layer 130 without increasing the occupied area of the capacitance area, correspondingly increasing the capacitance value of the capacitor formed by the first electrode layer 110, the first dielectric layer 120 and the second electrode layer 130, and also increasing the capacitance value of the semiconductor device, and further being beneficial to improving the performance of the semiconductor structure.
In the present embodiment, the depth of the groove 111 isThe linewidth dimension of the grooves 111 is 200nm to 2000nm.
It should be noted that the depth of the groove 111 should not be too large or too small. If the depth of the recess 111 is too large, the aspect ratio of the recess 111 is too large, which may easily cause a difficulty in forming the first dielectric layer 120 conformally covering the first electrode layer 110. If the depth of the grooves 111 is too small, the exposed area of the sidewalls of the grooves 111 is correspondingly smaller under the condition that the number of the grooves 111 is not changed, that is, the effective increase between the first electrode layer 110 and the second electrode layer 130 is smaller, so that the capacitance value increasing effect is not obvious on the substrate with unit area.
It should be noted that the line width of the groove 111 should not be too large or too small. If the line width of the grooves 111 is too large, the number of grooves 111 on the substrate 100 per unit area is small, that is, the effective area facing between the first electrode layer 110 and the second electrode layer 130 on the substrate 100 per unit area is increased less, so that the capacitance value increasing effect of the capacitor is not significant on the substrate per unit area. If the line width of the groove 111 is too small, it is easy to make the first dielectric layer 120 difficult to cover the first electrode layer 110 in a conformal manner, and it is easy to make the second electrode layer 130 difficult to cover the first electrode layer 110 on the sidewall and bottom of the groove 111, so that the effective area facing between the first electrode layer 110 and the second electrode layer 130 cannot be increased.
The second electrode layer 130 serves as an upper plate of a capacitor.
The material of the second electrode layer 130 includes polysilicon or metal. In this embodiment, the material of the second electrode layer 130 is polysilicon.
The first dielectric layer 120 is used to form an insulating layer in the capacitor.
The material of the first dielectric layer 120 is an insulating material. For example, the material of the first dielectric layer 120 includes one or more of silicon oxide and a high-k dielectric material.
Wherein the high-k dielectric material refers to a dielectric material having a dielectric constant greater than 3.9, the high-k dielectric material may include any of a plurality of HfO2、HfSiO、TiO2、HfZrO、HfSiON、HfTaO、HfTiO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3、BaSrTiO.
In this embodiment, the substrate 100 further includes a storage area II.
In a memory device (e.g., a Flash memory), PIP capacitors are often used in charge pump (charge pump) boost circuits, and a larger capacitor is often required in order to improve boost efficiency and voltage stability.
In this embodiment, the capacitor in the capacitor area I is a PIP capacitor, and the capacitor is fabricated in the capacitor area I during the process of fabricating the memory device in the memory area II by using the compatible characteristic of the PIP capacitor and the material of the memory device.
For this purpose, the first electrode layer 110 is further located on the substrate 100 of the storage area II, a trench (not labeled) penetrating the first electrode layer 110 is formed in the first electrode layer 110 of the storage area II, and the first electrode layer 110 located in the storage area II is used as a Floating Gate (FG) structure; the first dielectric layer 120 also conformally covers the bottom and sidewalls of the trench, and the top of the first electrode layer 110 outside the trench; the second electrode layer 130 located in the storage region II serves as a Control Gate (GG) structure.
The first electrode layer 110 of the storage area II is used as a floating gate structure, which can capture electrons and store electrons, and after power failure, electrons stored in the floating gate structure are not lost, thereby realizing storage of information.
The trenches are used for the separation as the first electrode layer 110 of the floating gate structure.
The first dielectric layer 120 of the storage area II conformally covers the bottom and sidewalls of the trench, for reserving space in the trench for the formation of the second electrode layer 130 of the storage area II, and the first dielectric layer 120 of the storage area II also serves to isolate the floating gate structure and the control gate structure.
The second electrode layer 130 located in the storage region II is used as a control gate structure through which electrons are changed to be injected into or erased from the floating gate structure, thereby realizing programming.
In this embodiment, the semiconductor structure further includes: isolation structure 104, isolation structure 104 is located in substrate 100 at the bottom of the trench.
The isolation structure 104 is used to isolate the first electrode layer 110 as a floating gate structure.
Specifically, the material of the isolation structure 104 is an insulating material such as silicon oxide, silicon nitride, or aluminum oxide.
In this embodiment, the thickness of the first electrode layer 110 at the bottom of the recess 111 is equal to the thickness of the first electrode layer 110 located in the storage area II along the normal direction of the substrate 100.
The thickness of the first electrode layer 110 at the bottom of the groove 111 is equal to the thickness of the first electrode layer 110 located in the storage area II, so that the groove 111 located in the first electrode layer 110 of the capacitor area I and the first electrode layer 110 located in the storage area II can be formed simultaneously in the same process step, which is beneficial to combining with the existing process and saving the process cost.
Specifically, after the first electrode layer 110 with a thickness greater than the target thickness of the floating gate structure is formed in the capacitor region I and the storage region II, a partial region of the first electrode layer 110 in the capacitor region I may be selectively etched to form the recess 111, and simultaneously the first electrode layer 110 in the storage region II may be globally etched to reduce the thickness of the first electrode layer 110 in the storage region II, so as to obtain the floating gate structure reaching the target thickness.
In this embodiment, the top of the second electrode layer 130 located in the capacitor region I is flush with the top of the second electrode layer 130 located in the storage region II.
The top of the second electrode layer 130 located in the capacitor region I is flush with the top of the second electrode layer 130 located in the storage region II, so that the second electrode layer 130 located in the capacitor region I and the second electrode layer 130 located in the storage region II can be formed simultaneously in the same process step, which is beneficial to combining with the existing process and manufacturing procedure, and saves the process cost.
In addition, the second electrode layers 130 of the capacitor region I and the storage region II need to be led out through electrode layer connectors, and the top surfaces of the second electrode layers 130 of the two regions are flush, so that electrode layer connectors for electrically connecting the second electrode layers 130 of the capacitor region I and the storage region II respectively can be formed in the same step. Meanwhile, an interlayer dielectric layer covering the second electrode layer 130 is generally formed on the substrate 100, and the top of the second electrode layer 130 in the capacitor region I is flush with the top of the second electrode layer 130 in the storage region II, so that an interlayer dielectric layer with a flat top surface is also obtained.
In the present embodiment, the substrate 100 of the capacitor region I is used as a third electrode layer (not labeled); the semiconductor structure further includes: the second dielectric layer 140 is located between the substrate 100 and the first electrode layer 110.
Specifically, the third electrode layer is used as a lower electrode plate of another capacitor, the first electrode layer 110 of the capacitor area I is used as an upper electrode plate of another capacitor, and the second dielectric layer 140 on the substrate 100 of the capacitor area I is used as an insulating layer in another capacitor.
It should be noted that, the third electrode plate is used as the lower electrode plate of the other capacitor, the first electrode layer 110 of the capacitor area I is used as the upper electrode plate of the other capacitor, the second dielectric layer 140 on the substrate 100 of the capacitor area I is used as the insulating layer in the other capacitor, and the other capacitor can be formed in the capacitor area I, so that stacking of the capacitors in the longitudinal direction is realized, that is, the capacitance value of the capacitor area I is increased, thereby increasing the capacitance value of the semiconductor device, and further being beneficial to improving the performance of the semiconductor structure.
It should be noted that the second dielectric layer 140 is not only located between the substrate 100 and the first electrode layer 110 of the capacitive area I, but also located between the substrate 100 and the first electrode layer 110 of the storage area II. The second dielectric layer 140 in the storage area II is used to provide a Tunneling channel for electrons from the active area (not labeled) to the floating gate structure, i.e., a Tunneling Oxide (TOX) layer, and the Tunneling Oxide layer is used as a gate Oxide layer to isolate the floating gate structure from the active area.
The material of the second dielectric layer 140 is an insulating material, and in this embodiment, the material of the second dielectric layer 140 is silicon oxide. In other embodiments, the material of the second dielectric layer is also MgO、SrO、BaO、RaO、SiO2、Al2O3、HfO2、NiO、GdO、Ta2O5、MoO2、TiO2 or WO 2.
In the present embodiment, in the capacitance region I, the second electrode layer 130 exposes a portion of the top of the first electrode layer 110, and the first electrode layer 110 and the second electrode layer 130 expose a portion of the top of the substrate 100.
Since the second electrode layer 130 covers the first electrode layer 110, the second electrode layer 130 of the capacitive region I exposes a portion of the top of the first electrode layer 110, so as to reduce the difficulty of the process of forming the first electrode layer joint 112 electrically connected to the first electrode layer 110. That is, when the electrode layer joints are formed, the objects etched by the etching process are all dielectric materials, so that the difficulty of the etching process is reduced.
The semiconductor structure further includes: an interlayer dielectric layer 150 covering the second electrode layer 130, and the first electrode layer 110 and the substrate 100 at the side of the second electrode layer 130.
An interlayer dielectric layer 150 for electrically isolating the first electrode layer tab 112, the second electrode layer tab 132, and the third electrode layer tab 102 from each other.
The material of the interlayer dielectric layer 150 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
The semiconductor structure further includes: the first electrode layer joint 112 is located in the capacitance area I, and the first electrode layer joint 112 penetrates through the interlayer dielectric layer 150 at the side part of the second electrode layer 130 and is electrically connected with the first electrode layer 110 at the side part of the second electrode layer 130; the second electrode layer joint 132 penetrates through the interlayer dielectric layer 150 on top of the second electrode layer 130 and is electrically connected with the second electrode layer 130; the third electrode layer tab 102 penetrates the interlayer dielectric layer 150 on the side of the first electrode layer 110 and the second electrode layer 130 and is electrically connected to the substrate 100 on the side of the first electrode layer 110.
In the capacitor region I, the first electrode layer tab 112, the second electrode layer tab 132, and the third electrode layer tab 102 are used to interconnect the respective plates of the capacitor with an external circuit or other, and in the memory region II, the second electrode layer tab 132 is used to interconnect the control gate structure of the memory device with an external circuit or other, and the third electrode layer tab 102 is used to interconnect the substrate 100 with an external circuit or other.
Specifically, the first electrode layer connector 112 is used to electrically connect the first electrode layer 110 to an external circuit or other interconnect structure, the second electrode layer connector 132 is used to electrically connect the second electrode layer 130 to an external circuit or other interconnect structure, and the third electrode layer connector 102 is used to electrically connect the third electrode layer to an external circuit or other interconnect structure.
The materials of the first electrode layer tab 112, the second electrode layer tab 132, and the third electrode layer tab 102 are conductive materials, such as: one or more of copper, tungsten, cobalt, nickel, etc.
Correspondingly, the invention further provides a method for forming the semiconductor structure. Fig. 3 to 11 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 3, a substrate 500 is provided, the substrate 500 including a capacitive region i.
The substrate 500 is used to provide a process platform for the formation of a capacitor, which is correspondingly formed on the substrate 500 in the capacitor region i.
The capacitor is typically composed of two plates and an insulating layer between the two plates, and the main types include MOS (metal-oxide-semiconductor) capacitor, PIP (polysilicon-insulator-polysilicon) capacitor, MIM (metal-insulator-metal) capacitor, MOM (metal-oxide-metal) capacitor, etc. In this embodiment, a PIP capacitor is taken as an example.
In this embodiment, the base 500 includes a substrate (not shown), which is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrate or germanium on insulator substrate.
In this embodiment, the substrate 500 of the capacitor region i is used as a third electrode layer (not shown).
Specifically, the third electrode layer serves as a lower plate of the other capacitor. In this embodiment, the PIP capacitor is taken as an example, so the silicon substrate can be used as the bottom plate of another capacitor.
It should be noted that the first electrode layer of the subsequently formed capacitor region i is used as the upper electrode plate of the other capacitor, and the subsequently formed second dielectric layer on the substrate 500 of the capacitor region i is used as the insulating layer in the other capacitor.
It should be noted that, the third electrode layer is used as the lower electrode plate of another capacitor, the subsequently formed first electrode layer of the capacitor region i is used as the upper electrode plate of another capacitor, the subsequently formed second dielectric layer on the substrate 500 of the capacitor region i is used as the insulating layer in another capacitor, and another capacitor can be formed in the capacitor region i, so that stacking of capacitors in the longitudinal direction is realized, that is, the capacitance value of the capacitor region i is increased, thereby increasing the capacitance value of the semiconductor device, and further being beneficial to improving the performance of the semiconductor structure.
With continued reference to fig. 3, in the step of providing the substrate 500, the substrate 500 further includes a storage area ii.
Above the substrate 500 of the storage region ii is used to form a memory device.
Referring to fig. 3 to 6, in the step of providing the substrate 500, an initial isolation structure 503 is formed in the substrate 500 of the storage region ii, and a top surface of the initial isolation structure 503 is higher than a top surface of the substrate 500.
The top surface of the initial isolation structure 503 is higher than the top surface of the substrate 500, and the first electrode layer subsequently formed in the storage region ii is used as a floating gate structure, and the initial isolation structure 503 is used to define the height of the top surface of the floating gate structure and isolate the floating gate structures from each other.
Specifically, referring to fig. 3 to 4, an insulating material layer 506, a hard mask layer 507, and a photolithography mask material layer (not shown) are sequentially covered on a substrate 500; patterning the photoresist material layer in the storage region ii, forming a first mask opening 508 in the photoresist material layer in the storage region ii, and using the remaining photoresist material layer as a photoresist layer 509; the hard mask layer 507, the insulating material layer 506, and a portion of the substrate 500 at the bottom of the first mask opening 508 are sequentially removed along the first mask opening 508, forming isolation trenches 5031.
As an example, the process of sequentially removing the hard mask layer 507, the insulating material layer 506, and a portion of the substrate 500 along the first mask opening 508 at the bottom of the first mask opening 508 includes an anisotropic dry etching process, and the pattern transfer accuracy of the anisotropic dry etching process is high.
Referring to fig. 5, after the step of forming the isolation trenches 5031, an initial isolation structure material layer (not shown) is formed in the isolation trenches 5031; and taking the top of the hard mask layer 507 as a stop position, performing first planarization treatment on the initial isolation structure material layer, and taking the rest initial isolation structure material layer as an initial isolation structure 503.
As an example, the first planarization process is a chemical mechanical planarization process, which is a global planarization process, and has a high planarization efficiency, which is beneficial to improving the surface flatness of the planarized initial isolation structure 503.
Referring to fig. 6, after the step of forming the initial isolation structure 503, the hard mask layer 507 and the insulating material layer 506 are sequentially removed.
In this embodiment, the process of removing the hard mask layer 507 and the insulating material layer 506 is a wet etching process. As an example, the etching solutions used to remove the hard mask layer 507 and the insulating material layer 506 are a phosphoric acid-containing solution and a hydrogen fluoride-containing solution, respectively.
It should also be noted that the initial isolation structures 503 may also be located in other areas of the substrate 500 that are higher than the top surface of the substrate 500; the probability of dishing (dishing) of the surface of the remaining initial structural material layer during the first planarization process may be reduced, thereby facilitating an increase in the surface planarity of the initial isolation structure 503.
Referring to fig. 7, in this embodiment, before forming the first electrode layer 510 on the substrate 500 of the capacitor region i, the forming method further includes: a second dielectric layer 540 is formed overlying the substrate 500.
The second dielectric layer 540 on the substrate 500 in the capacitive region i serves as an insulating layer in the other capacitor.
In this embodiment, the second dielectric layer 540 further covers the substrate 500 of the storage area ii, and is used to provide a Tunneling channel for electrons from the active area (not labeled) to the floating gate structure, i.e. a Tunneling Oxide (TOX) layer, and the Tunneling Oxide layer is used as a gate Oxide layer to isolate the floating gate structure from the active area.
Specifically, the material of the second dielectric layer 540 is an insulating material, and in this embodiment, the material of the second dielectric layer 540 is silicon oxide. In other embodiments, the material of the second dielectric layer 540 may also be MgO、SrO、BaO、RaO、SiO2、Al2O3、HfO2、NiO、GdO、Ta2O5、MoO2、TiO2 or WO 2.
Referring to fig. 7 to 9, a first electrode layer 510 is formed on a substrate 500 of a capacitance region i, and a groove 511 in the first electrode layer 510 is formed in the capacitance region i.
The first electrode layer 510 is used to form a bottom plate of a capacitor.
Specifically, the material of the first electrode layer 510 includes polysilicon or metal. In this embodiment, taking a PIP capacitor as an example, the material of the first electrode layer 510 is polysilicon.
In a memory device (e.g., a Flash memory), PIP capacitors are often used in charge pump (charge pump) boost circuits, and a larger capacitor is often required in order to improve boost efficiency and voltage stability.
In this embodiment, the capacitor in the capacitor region i is a PIP capacitor, and the capacitor is prepared in the capacitor region i in the process of preparing the memory device in the memory region ii by utilizing the property that the PIP capacitor is compatible with the material of the memory device, so that the first electrode layer 510 is further formed on the substrate 500 of the memory region ii in the step of forming the first electrode layer 510 on the substrate of the capacitor region i.
In this embodiment, in the step of forming the first electrode layer 510 on the substrate 500 of the capacitor region i, the first electrode layer 510 covers the top of the initial isolation structure 503.
The first electrode layer 510 covers the top of the initial isolation structure 503, and a second planarization process may be performed on the first electrode layer 510, so that the surface flatness of the first electrode layer 510 is better, and the top of the initial isolation structure 503 is not exposed.
As an example, the process of the second planarization process is a chemical mechanical planarization process.
Specifically, the forming method further includes: a trench 501 penetrating the first electrode layer 510 is formed in the memory region ii, and the discrete first electrode layer 510 remains for use as a Floating Gate (FG).
It should be noted that the trench 501 is used for the first electrode layer 510 that is a floating gate structure separately.
It should be further noted that, the first electrode layer 510 located in the storage area ii is used as a floating gate structure, and the floating gate structure can capture electrons and store electrons, and after power is turned off, electrons stored in the floating gate structure will not be lost, thereby realizing storage of information.
In this embodiment, in the step of forming the first electrode layer 510 on the substrate 500 of the capacitor region i, the thickness of the first electrode layer 510 is greater than the target thickness of the floating gate structure.
It should be further noted that the thickness of the first electrode layer 510 is greater than the target thickness of the floating gate structure, so as to provide a sufficient thickness for forming the recess 511 in the first electrode layer 510 of the capacitor region i.
Referring to fig. 8 to 9, the step of forming the groove 511 in the first electrode layer 510 in the capacitance region i includes: forming a mask layer 513 on the first electrode layer 510 of the capacitance region i, the mask layer 513 exposing the first electrode layer 510 of a partial region of the capacitance region i and the first electrode layer 510 of the storage region ii; the first electrode layer 510 exposed by the mask layer 513 is first etched using the mask layer 513 as a mask, so as to form a groove 511 in the first electrode layer 510 of the capacitor region i, and the thickness of the first electrode layer 510 of the storage region ii is thinned to the target thickness of the floating gate structure.
It should be noted that, in the process of etching the first electrode layer 510 to form the recess 511, the back etching of the first electrode layer 510 of the storage region ii is performed, so that the thickness of the first electrode layer 510 of the storage region ii is thinned to the target thickness of the floating gate structure, and thus the first electrode layer 510 with the recess 511 and the floating gate structure can be simultaneously formed by one deposition and one etching, which is advantageous in simplifying the process steps.
To this end, the bottom of the recess 511 is flush with the top of the first electrode layer 510 of the storage region ii.
In this embodiment, the forming method further includes: the mask layer 513 is removed.
The mask layer 513 is removed to expose the first electrode layer 510, thereby providing a process basis for the subsequent formation of the first dielectric layer.
With continued reference to fig. 8 to 9, it should be noted that the top surface of the initial isolation structure 503 is higher than the top surface of the substrate, so in this embodiment, the step of forming the recess 511 in the first electrode layer 510 in the capacitor region i includes: the first electrode layer 510 in the capacitor region i above the top of the initial isolation structure 503 is patterned to form a recess 511 in the first electrode layer 510 in the capacitor region i, and during the patterning process, the first electrode layer 510 in the memory region ii above the top of the initial isolation structure 503 is removed.
Specifically, the first electrode layer 510 in the capacitor region i above the top of the initial isolation structure 503 is patterned to form a recess 511 in the first electrode layer 510 in the capacitor region i, and during the patterning process, the first electrode layer 510 in the capacitor region ii above the top of the initial isolation structure 503 is removed, so that the surface of the initial isolation structure 503 is exposed while the recess 511 is formed in the first electrode layer 510 in the capacitor region i, and the remaining first electrode layer 510 in the capacitor region ii can be isolated by the initial isolation structure 503, thereby facilitating the removal of the initial isolation structure 503 above the substrate 500 in the capacitor region ii to form the trench 501.
With continued reference to fig. 8 to 9, in the present embodiment, the step of forming the trench 501 penetrating the first electrode layer 510 in the storage region ii includes: the initial isolation structure 503 is subjected to an etching back process to remove the initial isolation structure 503 between the remaining first electrode layers 510 of the storage region ii, a trench 501 surrounded by the remaining initial isolation structure 503 and the first electrode layers 510 is formed, and the remaining initial isolation structure 503 serves as an isolation structure 504.
Specifically, the isolation structure 504 is used to isolate the first electrode layer 510 as a floating gate structure.
In this embodiment, the etching back process performed on the initial isolation structure 503 includes a dry etching process, and parameters of the dry etching process include: the adopted gas comprises tetra-carbon hexafluoride, argon and oxygen, the gas flow rate of the tetra-carbon hexafluoride is 10 sccm-100 sccm, the gas flow rate of the argon is 500 sccm-1500 sccm, the gas flow rate of the oxygen is 20 sccm-800 sccm, and the process temperature is 20 ℃ to 80 ℃.
In this embodiment, the material of the isolation structure 504 is an insulating material such as silicon oxide, silicon nitride or aluminum oxide.
It should be noted that, by adjusting the gas and the process parameters of each etching step, the patterning process is sequentially performed on the first electrode layer 510 and the etching back process is performed on the initial isolation structure 503 by using the same etching process.
By adjusting the gas and the process parameters of each etching step in the same etching process, the first electrode layer 510 is subjected to patterning treatment and the initial isolation structure 503 is subjected to etching back treatment successively, so that the process efficiency is improved, and adverse effects caused by transmission among different etching devices are avoided.
In this embodiment, the patterning process includes a dry etching process, that is, the first etching includes a dry etching process.
Specifically, the process parameters of dry etching include: the adopted gas comprises carbon tetrafluoride and oxygen, the gas flow rate of the carbon tetrafluoride is 10 sccm-60 sccm, the gas flow rate of the oxygen is 5 sccm-200 sccm, and the process temperature is 20-80 ℃.
As can be seen from fig. 8 to 9, by forming the first electrode layer 510 covering the initial isolation structure 503, forming the recess 511 in the first electrode layer 510 of the capacitor region i in the same etching step, and making the thickness of the first electrode layer 510 of the storage region ii reach the target value, and the remaining first electrode layer 510 in the storage region ii is isolated by the initial isolation structure 503, the trench 501 between the floating gate structures can be formed by performing the etching back process on the initial isolation structure 503, thereby significantly simplifying the process steps, without adding additional processes, and making the manufacturing processes of the capacitor and the memory compatible; in addition, by forming the groove 511 in the first electrode layer 510 of the capacitor region i, the embodiment can not only realize the increase of the effective area of the capacitor and meet the requirement of devices, but also save the area of a chip and improve the economic benefit.
Referring to fig. 10, a first dielectric layer 520 conformally covering the bottom and sidewalls of the recess 511, and the top of the first electrode layer 510 outside the recess 511 is formed.
The first dielectric layer 520 is used to form an insulating layer in the capacitor.
The material of the first dielectric layer 520 is an insulating material. For example, the material of the first dielectric layer 520 includes one or more of silicon oxide and a high-k dielectric material.
Wherein the high-k dielectric material refers to a dielectric material having a dielectric constant greater than 3.9, the high-k dielectric material may include any of a plurality of HfO2、HfSiO、TiO2、HfZrO、HfSiON、HfTaO、HfTiO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3、BaSrTiO.
In this embodiment, in the step of forming the first dielectric layer 520, the first dielectric layer 520 also conformally covers the bottom and the sidewalls of the trench 501 and the top of the first electrode layer 510 outside the trench 501.
The first dielectric layer 520 of the storage region ii is used to isolate the floating gate structure and subsequently form the control gate structure.
It should be noted that, the first dielectric layer 520 conformally covers the bottom and the side wall of the trench 501 and the top of the first electrode layer 510 outside the trench 501, that is, the first dielectric layer 520 is not filled in the trench 501, so that a reserved space of the second electrode layer is formed subsequently, which can increase the effective area opposite to the space between the second electrode layer formed subsequently and the first electrode layer 510, correspondingly increase the capacitance of the capacitor formed by the first electrode layer 510 and the second electrode layer formed subsequently, and also increase the capacitance of the semiconductor device, thereby being beneficial to improving the performance of the semiconductor structure.
With continued reference to fig. 10, a second electrode layer 530 is formed overlying the first dielectric layer 520.
The second electrode layer 530 is used to form the upper plate of a capacitor.
Specifically, the material of the second electrode layer 530 includes polysilicon or metal. In this embodiment, the material of the second electrode layer 530 is polysilicon.
In this embodiment, the step of forming the second electrode layer 530 covering the first dielectric layer 520 includes: forming 520 a second electrode material layer (not shown) covering the first dielectric layer; the second electrode material layer is subjected to a third planarization process such that the top surface of the remaining second electrode material layer is planar and the remaining second electrode material layer serves as the second electrode layer 530.
And carrying out third planarization treatment on the second electrode material layer, so that the top surface of the remaining second electrode material layer is a plane, and correspondingly, the remaining second electrode material layer of the capacitor region i is flush with the top of the remaining second electrode material layer of the storage region ii, thereby simultaneously forming the second electrode layer 530 positioned in the capacitor region i and the second electrode layer 530 positioned in the storage region ii in the same process step, being beneficial to combining with the existing process, and saving the process cost.
In this embodiment, in the step of forming the second electrode layer 530 covering the first dielectric layer 520, the second electrode layer 530 located in the storage region ii is used as a Control Gate (GG).
The second electrode layer 530 located in the storage region ii is used as a control gate structure, through which electrons are changed to be injected into or erased from the floating gate structure, thereby realizing programming.
Referring to fig. 11, in this embodiment, the forming method further includes: in the capacitance region i, performing a second etching on the second electrode layer 530 to expose the first electrode layer 510; the second electrode layer 530 and the first electrode layer 510 are subjected to a third etching to expose the substrate 500.
The second electrode layer 530 of the capacitor region i is subjected to second etching to expose the first electrode layer 510, and the second electrode layer 530 and the first electrode layer 510 are subjected to third etching to expose the substrate 500, so that the process difficulty of subsequently forming the first electrode layer connector and the third electrode layer connector is reduced, that is, when each electrode layer connector is formed, the etched object of the etching process is the interlayer dielectric layer formed subsequently, and thus the difficulty of the etching process is reduced.
It will be appreciated that the etched areas of the second and third etches are different, thereby isolating the first and third electrode layer connections.
Note that, the first dielectric layer 520 is formed between the second electrode layer 530 and the first electrode layer 510, and therefore, the second electrode layer 530 and the first dielectric layer 520 below the second electrode layer 530 in the capacitor region i are etched to expose the first electrode layer 510, and the second electrode layer 530 and the first dielectric layer 520 and the first electrode layer 510 below the second electrode layer 530 in the capacitor region i and the storage region ii are etched to expose the substrate 500.
Specifically, a first photolithography mask layer (not shown) is covered on the second electrode layer 530 of the first partial region of the capacitor region i and the storage region ii; and taking the first photoetching mask layer as a mask, performing second etching on the second electrode layer 530 and the first dielectric layer 520, removing the second electrode layer 530 and the first dielectric layer 520 at the side part of the first photoetching mask layer to expose the first electrode layer 510, and removing the first photoetching mask layer after performing second etching. A second photolithographic mask layer (not shown) is covered on the second electrode layer 530 and the first electrode layer 510 of the second partial region of the capacitance region i and the storage region ii; and performing third etching by taking the second photoetching mask layer as a mask, removing the second electrode layer 530, the first dielectric layer 520, the first electrode layer 510 and the second dielectric layer 540 at the side part of the second photoetching mask layer to expose the substrate 500, and removing the second photoetching mask layer after performing third etching.
In this embodiment, the second etching process includes a dry etching process, and the third etching process includes a dry etching process.
With continued reference to fig. 11, in this embodiment, the forming method further includes: after the second and third etches, an interlayer dielectric layer 550 is formed covering the second electrode layer 530, and the first electrode layer 510 and the substrate 500 at the side of the second electrode layer 530.
And an interlayer dielectric layer 550 for electrically isolating the first electrode layer joint, the second electrode layer joint and the third electrode layer joint which are formed later.
The material of the interlayer dielectric layer 550 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
With continued reference to fig. 11, in this embodiment, the forming method further includes: in the capacitance region i, a first electrode layer tab 512 penetrating the interlayer dielectric layer 550 at the side of the second electrode layer 530 is formed, and the first electrode layer tab 512 is electrically connected to the first electrode layer 510 at the side of the second electrode layer 530; forming a second electrode layer tab 532 penetrating an interlayer dielectric layer 550 on top of the second electrode layer 530, the second electrode layer tab 532 being electrically connected to the second electrode layer 530; a third electrode layer tab 502 penetrating the interlayer dielectric layer 550 at the side of the first electrode layer 510 and the second electrode layer 530 is formed, and the third electrode layer tab 502 is electrically connected to the substrate 500 at the side of the first electrode layer 510.
Specifically, a first via hole (not shown) exposing the first electrode layer 510 is formed in the interlayer dielectric layer 550 of the capacitor region i, a second via hole (not shown) exposing the second electrode layer 530 is formed in the interlayer dielectric layer 550, and a third via hole (not shown) exposing the substrate 500; filling conductive materials in the first through hole, the second through hole and the third through hole to form a conductive material layer (not shown); performing fourth planarization treatment on the conductive material layer by taking the top surface of the interlayer dielectric layer 550 as a stop layer position, and removing the conductive material layer on the top of the interlayer dielectric layer 550; the conductive material layer in the first via is the first electrode layer tab 512, the conductive material layer in the second via is the second electrode layer tab 532, and the conductive material layer in the third via is the third electrode layer tab 502.
Note that the second electrode layer contacts 532 are formed in the capacitor region i and the storage region ii, respectively, the third electrode layer contacts 502 are formed in the capacitor region i and the storage region ii, respectively, and accordingly, a second via hole exposing the second electrode layer 530 and a third via hole exposing the substrate 500 are formed in the interlayer dielectric layer 550 of the capacitor region i and the storage region ii.
In this embodiment, the first electrode layer tab 512, the second electrode layer tab 532, and the third electrode layer tab 502 are formed in the same step for simplifying the process steps. In other embodiments, the first electrode layer tab, the second electrode layer tab, and the third electrode layer tab may also be formed in different steps.
It should also be noted that the first electrode layer tab 512, the second electrode layer tab 532, and the third electrode layer tab 502 are used for interconnection with external circuits or others.
Wherein in capacitor region i, first electrode layer tab 512, second electrode layer tab 532, and third electrode layer tab 502 are used to electrically connect the respective plates of the capacitor to an external circuit or other interconnect structure, and in memory region ii, second electrode layer tab 532 is used to interconnect the control gate structure of the memory device to an external circuit or other interconnect structure, and third electrode layer tab 502 is used to interconnect substrate 500 to an external circuit or other interconnect structure.
The materials of the first electrode layer tab 512, the second electrode layer tab 532, and the third electrode layer tab 502 are conductive materials, such as: one or more of copper, tungsten, cobalt, nickel, etc.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (18)
1. A semiconductor structure, comprising:
A substrate comprising a capacitive region;
The first electrode layer is positioned on the substrate of the capacitance area, and a groove is formed in the first electrode layer of the capacitance area;
A second electrode layer covering the first electrode layer at the side wall and bottom of the groove and the top of the first electrode layer;
And the first dielectric layer is positioned between the first electrode layer and the second electrode layer, and conformally covers the bottom and the side wall of the groove and the top of the first electrode layer outside the groove.
2. The semiconductor structure of claim 1, wherein the substrate further comprises a storage region;
the first electrode layer is also positioned on the substrate of the storage area, a groove penetrating through the first electrode layer is formed in the first electrode layer of the storage area, and the first electrode layer positioned in the storage area is used as a floating gate structure;
the first dielectric layer also conformally covers the bottom and the side wall of the groove and the top of the first electrode layer outside the groove;
The second electrode layer is located in the storage area and used as a control gate structure.
3. The semiconductor structure of claim 1 or 2, wherein the substrate of the capacitive region is configured to function as a third electrode layer;
The semiconductor structure further includes: and the second dielectric layer is positioned between the substrate and the first electrode layer.
4. The semiconductor structure of claim 2, wherein a thickness of the first electrode layer at the bottom of the recess is equal to a thickness of the first electrode layer at the storage region along a normal direction of the substrate.
5. The semiconductor structure of claim 1, 2 or 4, wherein the recess has a depth ofThe linewidth dimension of the groove is 200 nm-2000 nm.
6. The semiconductor structure of claim 2, wherein a top of the second electrode layer at the capacitive region is flush with a top of the second electrode layer at the storage region.
7. The semiconductor structure of claim 2, wherein the semiconductor structure further comprises: and the isolation structure is positioned in the substrate at the bottom of the groove.
8. The semiconductor structure of claim 2, wherein in the capacitive region, the second electrode layer exposes a portion of a top of the first electrode layer, the first and second electrode layers exposing a portion of a top of the substrate; the semiconductor structure further includes: an interlayer dielectric layer covering the second electrode layer, the first electrode layer and the substrate on the side of the second electrode layer;
the first electrode layer connector is positioned in the capacitance area, penetrates through the interlayer dielectric layer at the side part of the second electrode layer and is electrically connected with the first electrode layer at the side part of the second electrode layer;
The second electrode layer joint penetrates through the interlayer dielectric layer at the top of the second electrode layer and is electrically connected with the second electrode layer;
and the third electrode layer joint penetrates through the interlayer dielectric layers at the side parts of the first electrode layer and the second electrode layer and is electrically connected with the substrate at the side part of the first electrode layer.
9. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a capacitance region;
forming a first electrode layer on a substrate of the capacitance region, and forming a groove in the first electrode layer in the capacitance region;
forming a first dielectric layer conformally covering the bottom and the side walls of the groove and the top of the first electrode layer outside the groove;
and forming a second electrode layer covering the first dielectric layer.
10. The method of forming a semiconductor structure of claim 9, wherein in the step of providing a substrate, the substrate further comprises a storage region;
In the step of forming a first electrode layer on the substrate of the capacitor region, the first electrode layer is further formed on the substrate of the capacitor region;
The forming method further includes: forming a groove penetrating through the first electrode layer in the storage area, and enabling the remaining discrete first electrode layer to serve as a floating gate structure;
in the step of forming the first dielectric layer, the first dielectric layer also conformally covers the bottom and the side wall of the groove and the top of the first electrode layer outside the groove;
in the step of forming the second electrode layer covering the first dielectric layer, the second electrode layer located in the storage area is used as a control gate structure.
11. The method of forming a semiconductor structure according to claim 9 or 10, wherein a substrate of the capacitor region is used as a third electrode layer;
Before forming the first electrode layer on the substrate of the capacitance region, the forming method further comprises: and forming a second dielectric layer covering the substrate.
12. The method of forming a semiconductor structure of claim 10, wherein in the step of forming a first electrode layer on the substrate of the capacitor region, a thickness of the first electrode layer is greater than a target thickness of the floating gate structure;
The step of forming a recess in the first electrode layer in the capacitive region comprises: forming a mask layer on the first electrode layer of the capacitor region, wherein the mask layer exposes the first electrode layer of a partial region of the capacitor region and the first electrode layer of the storage region;
Taking the mask layer as a mask, performing first etching on the first electrode layer exposed by the mask layer to form a groove in the first electrode layer of the capacitor region, and thinning the thickness of the first electrode layer of the storage region to the target thickness of the floating gate structure;
The forming method further includes: and removing the mask layer.
13. The method of forming a semiconductor structure according to claim 10 or 12, wherein in the step of providing a substrate, an initial isolation structure is formed in the substrate of the memory region, a top surface of the initial isolation structure being higher than a top surface of the substrate;
in the step of forming a first electrode layer on the substrate of the capacitor region, the first electrode layer covers the top of the initial isolation structure;
The step of forming a recess in the first electrode layer in the capacitive region comprises: patterning the first electrode layer higher than the top of the initial isolation structure in the capacitor region to form a groove in the first electrode layer of the capacitor region, and removing the first electrode layer higher than the top of the initial isolation structure in the memory region in the patterning process;
The step of forming a trench in the storage region through the first electrode layer includes: and performing back etching treatment on the initial isolation structure to remove the initial isolation structure between the residual first electrode layers in the storage area, forming a groove surrounded by the residual initial isolation structure and the first electrode layers, and taking the residual initial isolation structure as an isolation structure.
14. The method of claim 13, wherein the patterning of the first electrode layer and the etching back of the initial isolation structure are performed sequentially by adjusting the gases and process parameters of each etching step using the same etching process.
15. The method of forming a semiconductor structure according to claim 9 or 10, wherein the step of forming a second electrode layer covering the first dielectric layer comprises: forming a second electrode material layer covering the first dielectric layer;
And carrying out planarization treatment on the second electrode material layer so that the top surface of the remaining second electrode material layer is a plane, and the remaining second electrode material layer is used as the second electrode layer.
16. The method of forming a semiconductor structure of claim 13, wherein the patterning process comprises a dry etching process.
17. The method of forming a semiconductor structure of claim 16, wherein the process parameters of the dry etch include: the adopted gas comprises carbon tetrafluoride and oxygen, the gas flow rate of the carbon tetrafluoride is 10 sccm-60 sccm, the gas flow rate of the oxygen is 5 sccm-200 sccm, and the process temperature is 20-80 ℃.
18. The method of forming a semiconductor structure of claim 10, wherein the method of forming further comprises: performing second etching on the second electrode layer in the capacitance region to expose the first electrode layer; performing third etching on the second electrode layer and the first electrode layer to expose the substrate;
forming an interlayer dielectric layer covering the second electrode layer, the first electrode layer on the side part of the second electrode layer and the substrate after the second etching and the third etching;
Forming a first electrode layer joint penetrating through an interlayer dielectric layer at the side part of the second electrode layer in the capacitor region, wherein the first electrode layer joint is electrically connected with the first electrode layer at the side part of the second electrode layer;
forming a second electrode layer joint penetrating through an interlayer dielectric layer at the top of the second electrode layer, wherein the second electrode layer joint is electrically connected with the second electrode layer;
And forming a third electrode layer joint penetrating through the interlayer dielectric layers at the side parts of the first electrode layer and the second electrode layer, wherein the third electrode layer joint is electrically connected with the substrate at the side part of the first electrode layer.
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