CN117651476A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 91
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 230000000149 penetrating effect Effects 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims description 61
- 238000005530 etching Methods 0.000 claims description 38
- 229910052721 tungsten Inorganic materials 0.000 claims description 13
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 239000002648 laminated material Substances 0.000 claims description 7
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 229910015801 BaSrTiO Inorganic materials 0.000 claims description 3
- 229910004129 HfSiO Inorganic materials 0.000 claims description 3
- 229910002367 SrTiO Inorganic materials 0.000 claims description 3
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 3
- 229910006501 ZrSiO Inorganic materials 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- 230000009286 beneficial effect Effects 0.000 abstract description 20
- 239000003990 capacitor Substances 0.000 description 62
- 229910052751 metal Inorganic materials 0.000 description 21
- 239000002184 metal Substances 0.000 description 21
- 230000015572 biosynthetic process Effects 0.000 description 15
- 239000003989 dielectric material Substances 0.000 description 10
- 239000004020 conductor Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000003475 lamination Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
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- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 238000011161 development Methods 0.000 description 2
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- 238000001312 dry etching Methods 0.000 description 2
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- 150000004767 nitrides Chemical class 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
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Abstract
A semiconductor structure and a method of forming the same, the structure comprising: a substrate; an electrode stack on the substrate, the electrode stack including a plurality of first electrode layers and second electrode layers alternately stacked in sequence in a longitudinal direction; a first electrical connection structure penetrating the electrode stack and electrically connected to the first electrode layer; a second electrical connection structure penetrating the electrode stack and electrically connected to the second electrode layer; and the dielectric layer is positioned between the adjacent first electrode layer and the second electrode layer, and extends upwards to the position between the first electrode layer and the second electrode layer of the previous layer along the interface between the first electric connection structure and the second electrode layer and downwards to the position between the first electrode layer and the second electrode layer of the next layer along the interface between the second electric connection structure and the first electrode layer. The invention is beneficial to saving the process photomask, thereby saving the process cost.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
The semiconductor Integrated Circuit (IC) industry has experienced a rapid growth. Technological advances in materials and design in the integrated circuit industry have produced one generation of yet another integrated circuit. Each generation has smaller and more complex circuitry than the previous generation. However, these advances increase the complexity of processing and manufacturing integrated circuits, and similar developments in integrated circuit processing and manufacturing are needed to achieve these advances. During the development of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) has gradually increased, while the geometry (i.e., the smallest component that can be manufactured by a manufacturing process) has gradually decreased.
One type of capacitor is a metal-insulator-metal (Metal Insulator Metal, miM) capacitor, commonly used in mixed signal devices and logic devices (e.g., embedded memory and radio frequency devices, etc.). The MiM capacitor is generally used to store charges in various semiconductor devices. Currently, to meet the performance requirements of high performance computing of high performance computers (High Performance Computing, HPC), the capacitance density of the MiM capacitor is gradually increasing, and a layer of insulator is generally used to provide 20fF/um 2 capacitor, and for the MiM capacitor that needs to provide a higher capacitance (e.g., 300fF/um 2), stacking is currently performed, as described in detail in patent US9627312B2, whereas in the conventional MiM capacitor, one plate needs one mask, and stacking multiple plates needs more masks. As shown in fig. 1, the structure of the conventional MiM capacitor includes: the bottom electrode layer 21, the dielectric layer 20 and the top electrode layer 22 are stacked sequentially from bottom to top, however, the morphology of each electrode layer is different and needs to be formed by adopting different photomasks, and the more the number of the electrode layers is, the more photomasks are needed, so that the forming method of the MiM capacitor is complex and the process cost is high.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, which are beneficial to saving a process photomask, thereby saving the process cost.
To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; an electrode stack on the substrate, the electrode stack including a plurality of first electrode layers and second electrode layers alternately stacked in sequence in a longitudinal direction; a first electrical connection structure penetrating the electrode stack and electrically connected to the first electrode layer; a second electrical connection structure penetrating the electrode stack and electrically connected to the second electrode layer; and the dielectric layer is positioned between the adjacent first electrode layer and the second electrode layer, and extends upwards to the position between the first electrode layer and the second electrode layer of the previous layer along the interface between the first electric connection structure and the second electrode layer and downwards to the position between the first electrode layer and the second electrode layer of the next layer along the interface between the second electric connection structure and the first electrode layer.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein a laminated structure is formed on the substrate, the laminated structure comprises a plurality of first target layers and second target layers which are alternately stacked in sequence along the longitudinal direction, any one of the first target layers and the second target layers is a first electrode layer, and the other one is a sacrificial layer; forming a first through hole penetrating through the laminated structure; forming a first electrical connection structure in the first via hole, the first electrical connection structure being electrically connected to the first electrode layer; forming a second through hole penetrating through the laminated structure after forming the first electric connection structure; removing the sacrificial layer through the second through hole to form a groove exposing the first electrode layer and the side wall of the first electric connection structure, which is in contact with the sacrificial layer, wherein the groove is communicated with the second through hole; forming a first dielectric layer conformally covering each side of the groove and the second through hole; and after the first dielectric layer is formed, filling the groove and the second through hole, forming a second electrode layer in the groove, and forming a second electric connection structure in the second through hole.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the semiconductor structure provided by the embodiment of the invention, the first electric connection structure penetrates through the electrode lamination and is electrically connected with the first electrode layer, the second electric connection structure penetrates through the electrode lamination and is electrically connected with the second electrode layer, the dielectric layer is positioned between the adjacent first electrode layer and the second electrode layer, and extends upwards to the position between the first electrode layer and the second electrode layer of the upper layer along the interface between the first electric connection structure and the second electrode layer and downwards to the position between the first electrode layer and the second electrode layer of the lower layer along the interface between the second electric connection structure and the first electrode layer; in the embodiment of the invention, the first electric connection structure and the second electrode layer are isolated by the dielectric layer of the capacitor, and the second electric connection structure and the first electrode layer are isolated, so that the formation process of the capacitor is simplified, the adjacent first electrode layer, the second electrode layer and the dielectric layer between the first electrode layer and the second electrode layer form the capacitor, the equivalent capacitance density is improved, and meanwhile, the electrode lamination is used for obtaining higher equivalent capacitance density, and the photomask for forming each first electrode layer and each second electrode layer is saved, so that the process photomask is saved, and the process cost is further saved.
In the method for forming the semiconductor structure provided by the embodiment of the invention, the sacrificial layer is removed through the second through hole, a groove exposing the first electrode layer and the side wall of the first electric connection structure, which is in contact with the sacrificial layer, is formed, the groove is communicated with the second through hole, a first dielectric layer which conformally covers all sides of the groove and the second through hole is formed, after the first dielectric layer is formed, the groove and the second through hole are filled, a second electrode layer is formed in the groove, and a second electric connection structure is formed in the second through hole; in the embodiment of the invention, the first electric connection structure and the second electrode layer are isolated by the dielectric layer of the capacitor, and the second electric connection structure and the first electrode layer are isolated, so that the formation process of the capacitor is simplified, the adjacent first electrode layer, the second electrode layer and the dielectric layer between the first electrode layer and the second electrode layer form the capacitor, the equivalent capacitance density is improved, and meanwhile, the higher equivalent capacitance density is obtained through the laminated structure, thereby being beneficial to saving a process photomask and further saving the process cost.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
FIGS. 2-4 are schematic diagrams illustrating the structure of an embodiment of a semiconductor structure according to the present invention;
fig. 5 to 14 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, the equivalent capacitance density of the conventional MiM capacitor needs to be improved, and the provided option of equivalent capacitance density is single. Specifically, the structure of the conventional MiM capacitor is shown in fig. 1, and includes: it is difficult to effectively increase the equivalent capacitance density by stacking the bottom electrode layer 21, the dielectric layer 20, and the top electrode layer 22 in this order from bottom to top. The structure of the conventional MiM capacitor may further include: the electrode layers are stacked alternately in the longitudinal direction, and dielectric layers are formed between the adjacent electrode layers, however, each electrode layer has different shapes and needs to be formed by adopting different photomasks, and the more the number of the electrode layers is, the more the number of the photomasks are needed, so that the forming method of the MiM capacitor is complex.
In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate; an electrode stack on the substrate, the electrode stack including a plurality of first electrode layers and second electrode layers alternately stacked in sequence in a longitudinal direction; a first electrical connection structure penetrating the electrode stack and electrically connected to the first electrode layer; a second electrical connection structure penetrating the electrode stack and electrically connected to the second electrode layer; and the dielectric layer is positioned between the adjacent first electrode layer and the second electrode layer, and extends upwards to the position between the first electrode layer and the second electrode layer of the previous layer along the interface between the first electric connection structure and the second electrode layer and downwards to the position between the first electrode layer and the second electrode layer of the next layer along the interface between the second electric connection structure and the first electrode layer.
In the embodiment of the invention, the first electric connection structure and the second electrode layer are isolated by the dielectric layer of the capacitor, and the second electric connection structure and the first electrode layer are isolated, so that the formation process of the capacitor is simplified, the adjacent first electrode layer, the second electrode layer and the dielectric layer between the first electrode layer and the second electrode layer form the capacitor, the equivalent capacitance density is improved, and meanwhile, the electrode lamination is used for obtaining higher equivalent capacitance density, and the photomask for forming each first electrode layer and each second electrode layer is saved, so that the process photomask is saved, and the process cost is further saved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Referring to fig. 2-4, schematic structural diagrams of an embodiment of the semiconductor structure of the present invention are shown. Fig. 2 is a plan view, fig. 3 is a sectional view taken along AA direction of fig. 2, and fig. 4 is a circuit diagram.
As shown in conjunction with reference to fig. 2-4, the semiconductor structure includes: a substrate 101; an electrode stack 201 on the substrate 101, the electrode stack 201 including a plurality of first electrode layers 241 and second electrode layers 221 alternately stacked in sequence in a longitudinal direction (as shown in a Z-direction in fig. 3); a first electrical connection structure 511 penetrating the electrode stack 201 and electrically connected to the first electrode layer 241; a second electrical connection structure 521 penetrating the electrode stack 201 and electrically connected to the second electrode layer 221; the dielectric layer 231 is located between the adjacent first electrode layer 241 and second electrode layer 221, and the dielectric layer 231 also extends up to between the first electrode layer 241 and second electrode layer 221 of the previous layer along the interface between the first electrical connection structure 511 and the second electrode layer 221, and extends down to between the first electrode layer 241 and second electrode layer 221 of the next layer along the interface between the second electrical connection structure 521 and the first electrode layer 241.
The substrate 101 is used to provide a process platform for the subsequent formation of the MiM capacitor. In this embodiment, the base 101 includes a substrate (not shown), which is a silicon substrate. In other embodiments, the material of the substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the MiM capacitor is formed in a back-end-of-line process, so that an inter-metal dielectric layer (Inter Metal Dielectric, IMD) (not shown) is further formed on the substrate 101, and one or more stacked metal layers are formed in the inter-metal dielectric layer along the normal direction of the substrate surface (i.e., the longitudinal direction) according to the process conditions, for example: a first metal (i.e., M1) layer, a second metal (i.e., M2) layer, etc.; when the metal layers are multiple layers, two adjacent metal layers are electrically connected through a through hole (Via) electrical connection structure between the two metal layers.
In this embodiment, the semiconductor structure further includes: an etch stop layer 111 is located between the substrate 101 and the first electrode layer 241.
The etching stop layer 111 is used to define the position of the etching stop in the process of forming the electrode stack 201, the first electrical connection structure 511 and the second electrical connection structure 521, so as to reduce the probability of damage to the substrate 101, and further facilitate improving the uniformity of the bottom height of the first electrical connection structure 511 and the uniformity of the bottom height of the second electrical connection structure 521.
As an example, the material of the etch stop layer 111 is silicon nitride. In other embodiments, the etch stop layer may also be other materials with higher etch selectivity to the substrate material, such as: one or more of silicon nitride, aluminum oxide, aluminum nitride and NDC (nitride doped carbon, carbon doped silicon nitride).
The electrode stack 201 is used to form a plurality of first electrode layers 241 and second electrode layers 221 alternately stacked in sequence in the longitudinal direction, thereby constituting a plurality of capacitors.
The first electrode layer 241 serves as an electrode plate of the MiM capacitor.
The material of the first electrode layer 241 is a conductive material. As one example, the material of the first electrode layer 241 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
The dielectric layer 231 located between adjacent first electrode layer 241 and second electrode layer 221 serves as an insulating layer in forming a MiM capacitor for isolating the first electrode layer 241 and second electrode layer 221.
In this embodiment, the material of the dielectric layer 231 is a high-k dielectric material; the high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. The high-k dielectric material is selected, so that the capacitance value of the MiM capacitor is improved, and the capacitance density is correspondingly improved.
Specifically, the dielectric layer 231 is a high-k dielectric layer formed by stacking, i.e., the dielectric layer 231 is a high-k composite dielectric layer. After the thickness of the high-k dielectric layer reaches a certain value, the formation quality of the high-k dielectric layer is easily deteriorated, and therefore, the thickness of the dielectric layer 231 can meet the process requirement and has better formation quality. For this purpose, the high-k dielectric material comprises HfO 2 、HfSiO、TiO 2 、HfZrO、HfSiON、HfTaO、HfTiO、Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 One or more of BaSrTiO and SiN.
In this embodiment, the dielectric layer 231 is a ZAZ layer. Wherein the ZAZ layer comprises a first ZrO layer formed by stacking 2 Layer, al 2 O 3 Layer and second ZrO 2 A layer. In other embodiments, the material of the dielectric layer may be one or more of silicon oxide, silicon oxynitride, and silicon nitride, depending on the process requirements.
The second electrode layer 221 is used as an electrode plate of the MiM capacitor.
The second electrode layer 221 covers the dielectric layer 231 on the first electrode layer 241, so that the first electrode layer 241 and the second electrode layer 221 of adjacent layers form a MiM capacitor, specifically a capacitor of a circuit diagram as shown in fig. 4.
The material of the second electrode layer 221 is a conductive material. As one example, the material of the second electrode layer 221 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
In this embodiment, a method for forming a semiconductor structure includes: a stacked structure including a plurality of sacrificial layers and second electrode layers 221 alternately stacked in sequence in a longitudinal direction is formed on the substrate 101; forming a first through hole penetrating through the laminated structure; forming a second electrical connection structure 521 electrically connected to the second electrode layer 221 in the first via hole; after forming the second electrical connection structure 521, forming a second through hole penetrating through the stacked structure; removing the sacrificial layer through the second via hole to form a trench exposing the second electrode layer 521 and a sidewall of the second electrical connection structure 521 in contact with the sacrificial layer, the trench communicating with the second via hole; forming a dielectric layer 231 conformally covering the respective sides of the trench and the second via; after the dielectric layer 231 is formed, the trench and the second via hole are filled, the first electrode layer 241 is formed in the trench, and the first electrical connection structure 511 is formed in the second via hole.
Therefore, in the present embodiment, the dielectric layer 231 further extends between the first electrical connection structure 511 and the second electrode layer 221, and between the second electrical connection structure 521 and the first electrode layer 241, so as to isolate the first electrical connection structure 511 from the second electrode layer 221, and isolate the second electrical connection structure 521 from the first electrode layer 241.
In the embodiment of the invention, the first electrical connection structure 511 and the second electrode layer 221 are isolated by the dielectric layer 231 of the capacitor, and the second electrical connection structure 521 and the first electrode layer 241 are isolated, which is beneficial to simplifying the formation process of the capacitor, and the adjacent first electrode layer 241, second electrode layer 221 and dielectric layer 231 between the two form the capacitor, which is beneficial to improving the equivalent capacitance density, and meanwhile, the electrode lamination 201 obtains higher equivalent capacitance density, which is beneficial to saving the light shield for forming each first electrode layer 241 and each second electrode layer 221, thereby being beneficial to saving the process light shield and further saving the process cost.
Accordingly, in the present embodiment, the first electrode layer 241 and the first electrical connection structure 511 are an integrated structure, which is beneficial to simplifying the process flow, saving the process cost and improving the process efficiency.
In other embodiments, the method for forming a semiconductor structure may further include forming the second electrode layer and the dielectric layer at the position of the sacrificial layer after the sacrificial layer is removed correspondingly and subsequently, where the second electrode layer and the second electrical connection structure may be an integrated structure in other embodiments.
The first electrical connection structure 511 is used to make an electrical connection between the MiM capacitor and an external circuit.
Specifically, the first electrical connection structure 511 is configured to electrically connect the first electrode layers 241 to an external circuit, and is further configured to electrically connect the respective first electrode layers 241, so that the first electrode layers 241 can all access the same potential when the capacitor is operated.
In this embodiment, the first electrode layer 241 and the second electrode layer 221 of adjacent layers all form a capacitor, and the first electrode layer 241 is connected to the same potential through the first electrical connection structure 511, so that the capacitors formed are connected in parallel two by two, and the capacitance value of the unit area is correspondingly improved, i.e. the equivalent capacitance density is improved.
The material of the first electrical connection structure 511 is a conductive material. In this embodiment, the material of the first electrical connection structure 511 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
In this embodiment, the dielectric layer 231 extends between the first electrical connection structure 511 and the second electrode layer 221, and separates the first electrical connection structure 511 from the second electrode layer 221, so that the first electrical connection structure 511 penetrating the electrode stack 201 can be used to electrically connect the first electrical connection structure 511 and the first electrode layer 241 and electrically separate the first electrical connection structure 511 and the second electrode layer 221.
The second electrical connection 521 is used to electrically connect the MiM capacitor to an external circuit.
Specifically, the second electrical connection structure 521 is configured to electrically connect the second electrode layers 221 to an external circuit, and is also configured to electrically connect the respective second electrode layers 221, so that the second electrode layers 221 can all access the same potential when the capacitor is operated.
In this embodiment, the first electrode layer 241 and the second electrode layer 221 of the adjacent layers all form a capacitor, and the second electrode layer 221 is connected to the same potential through the second electrical connection structure 521, so that the capacitors formed are connected in parallel two by two, and the capacitance value of the unit area is correspondingly improved, that is, the equivalent capacitance density is improved.
The material of the second electrical connection structure 521 is a conductive material. In this embodiment, the material of the second electrical connection structure 521 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
In this embodiment, the dielectric layer 231 extends between the second electrical connection structure 521 and the first electrode layer 241, and separates the second electrical connection structure 521 from the first electrode layer 241, so that the second electrical connection structure 521 penetrating the electrode stack 201 can be used to electrically connect the second electrical connection structure 521 and the second electrode layer 221 and electrically separate the second electrical connection structure 521 from the first electrode layer 241.
In this embodiment, the dielectric layer 231 is used as a first dielectric layer, and the semiconductor structure further includes: a second dielectric layer 301 is disposed on the substrate 101 and covers the electrode stack 201, the second dielectric layer 301 exposing the tops of the first electrical connection structure 511 and the second electrical connection structure 621.
The second dielectric layer 301 is used to achieve isolation between the electrical connection structures. The material of the second dielectric layer 301 is an insulating material. As an example, the material of the second dielectric layer 301 is silicon oxide.
The semiconductor structure shown in fig. 3 is illustrated by taking six stacked first electrode layers 241 and second electrode layers 221 as an example. In other embodiments, other unlimited numbers of first and second electrode layers may also be included.
Correspondingly, the invention further provides a method for forming the semiconductor structure. Fig. 5 to 14 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
The method for forming the semiconductor structure of the present embodiment will be described in detail below with reference to the accompanying drawings.
Referring to fig. 5 and 6 in combination, a substrate 100 is provided, and a stacked structure 200 is formed on the substrate 100, and includes a plurality of first target layers 212 and second target layers 222 alternately stacked in sequence in a longitudinal direction (as shown in a Z direction in fig. 6), wherein either one of the first target layers 212 and the second target layers 222 is a first electrode layer 220, and the other is a sacrificial layer 210.
The substrate 100 is used to provide a process platform for the subsequent formation of the MiM capacitor.
In this embodiment, the base 100 includes a substrate (not shown), which is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrate or germanium on insulator substrate.
In this embodiment, the MiM capacitor is formed in a back-end-of-line process, so that an inter-metal dielectric layer (Inter Metal Dielectric, IMD) (not shown) is further formed on the substrate 100, and one or more stacked metal layers are formed in the inter-metal dielectric layer along the normal direction of the substrate surface (i.e., the longitudinal direction) according to the process conditions, for example: a first metal (i.e., M1) layer, a second metal (i.e., M2) layer, etc.; when the metal layers are multiple layers, two adjacent metal layers are electrically connected through a through hole (Via) electrical connection structure between the two metal layers.
The stack structure 200 is used for subsequent electrode stack formation.
In this embodiment, the first target layer 212 is taken as the sacrificial layer 210, the second target layer 222 is taken as the first electrode layer 222 as an example, and in other embodiments, the first target layer may be taken as the first electrode layer, and the second target layer may be taken as the sacrificial layer.
The first electrode layer 220 is used as an electrode plate of the MiM capacitor.
The material of the first electrode layer 220 is a conductive material. As one example, the material of the first electrode layer 220 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
The sacrificial layer 210 is used to occupy space for the subsequent formation of the first dielectric layer and the second electrode layer.
In this embodiment, the sacrificial layer 210 is removed while the first electrode layer 220 is maintained, so that the sacrificial layer 210 needs to be made of a material having an etching selectivity to the first electrode layer 220, and the first electrode layer 220 is made of a metal material.
In this embodiment, before the step of providing the substrate 100, the method further includes: the laminate material layer 240 covering the substrate 100 is formed to include a plurality of first target layers 212 and second target layers 222 alternately stacked in sequence in a longitudinal direction, one of the first target layers 212 and the second target layers 222 being the first electrode layer 220 and the other being the sacrificial layer 210.
Accordingly, in the present embodiment, the first target layer 212 is the sacrificial layer 210, and the second target layer 222 is the first electrode layer 222.
The layer of laminate material 240 is used to directly pattern the laminate structure 200.
In this embodiment, an etch stop layer 110 is formed between the substrate 100 and the laminate layer 240.
The etching stop layer 110 is used for defining the position of the etching stop in the subsequent process of forming the electrode stack 200, the first electrical connection structure and the second electrical connection structure, so as to reduce the probability of damage to the substrate 100, and further facilitate improving the bottom height consistency of the first electrical connection structure and the second electrical connection structure.
As an example, the material of the etch stop layer 110 is silicon nitride. In other embodiments, the etching stop layer may be made of other materials having a higher etching selectivity with the substrate material, for example: one or more of silicon nitride, aluminum oxide, aluminum nitride and NDC (nitride doped carbon, carbon doped silicon nitride).
Referring to fig. 6, the stack material layer 240 is patterned to form the electrode stack 200.
In this embodiment, the stacked material layer 240 is patterned using an etching process.
Specifically, in this embodiment, the anisotropic etching process is used to pattern the stacked material layer 240, so that the patterning accuracy is high, which is beneficial to forming the electrode stack 200 with good sidewall quality.
In this embodiment, in the step of patterning the laminated material layer 240, the etching stop layer 110 is used as an etching stop position.
During the patterning of the stacked material layer 240, the etching stop layer 110 can serve to define an etching stop position, thereby reducing the probability of damage to the substrate 100 caused by the process of patterning the stacked material layer 240.
It should be noted that, the electrode stack 200 is formed by patterning the stack material layer 240, so that a multi-layer electrode can be formed by using one photomask, which is beneficial to saving the photomask and saving the process cost.
In this embodiment, before the first via hole penetrating through the stacked structure 200 is formed subsequently, the method further includes: a second dielectric layer 300 is formed overlying the stack 200.
The second dielectric layer 300 is used to achieve isolation between the electrical connection structures. The material of the second dielectric layer 300 is an insulating material. As an example, the material of the second dielectric layer 300 is silicon oxide.
Note that the semiconductor structure shown in fig. 6 is illustrated by taking the stacked structure 200 in which six layers are stacked as an example. In other embodiments, other laminate structures may be included that do not limit the number of film layers.
Referring to fig. 7, a first via 310 is formed through the stacked structure 200.
The first via 310 is used to provide a spatial location for forming a first electrical connection structure.
In this embodiment, an etching process is used, where the top surface of the etching stop layer 110 is used as an etching stop position to form the first through hole 310, so as to correspondingly reduce the probability of damage to the substrate 100 caused by the etching process for forming the first through hole 310, and improve the uniformity of the bottom height of the first through hole 310.
Specifically, in this embodiment, the first through hole 310 is formed by using an anisotropic etching process, so that the etching precision is high, which is beneficial to forming the first through hole 310 with good sidewall quality.
In this embodiment, the second dielectric layer 300 covers the stacked structure 200, and accordingly, in the step of forming the first via 310 penetrating through the stacked structure 200, the first via 310 also penetrates through the second dielectric layer 300 located on top of the stacked structure 200.
In this embodiment, the step of forming the first through hole 310 penetrating the stacked structure 200 includes: a first mask layer (not shown) is formed overlying the top of the stack 200.
Specifically, the first mask layer is located on the second dielectric layer 300 that covers the stacked structure 200, thereby reducing damage to the stacked structure 200 caused by the patterned first mask layer.
In this embodiment, the first mask layer is patterned to form a first mask opening (not shown).
The first mask opening exposes the top of the second dielectric layer 300 for use as an etch mask opening for etching the stack structure 200, thereby defining an etch location for the first via 310.
In this embodiment, the stacked structure 200 is etched along the first mask opening to form a first via 310.
In this embodiment, after the first via hole 310 is formed, the first mask layer is removed.
Referring to fig. 8, a first electrical connection structure 510 electrically connected to the first electrode layer 220 is formed in the first via 310.
The first electrical connection structure 510 is used to make an electrical connection between the MiM capacitor and an external circuit.
Specifically, the first electrical connection structure 510 is configured to electrically connect the first electrode layer 210 to an external circuit, and is further configured to electrically connect the first electrode layers 220, so that the first electrode layers 220 can all access the same potential when the capacitor is in operation.
The material of the first electrical connection structure 510 is a conductive material. In this embodiment, the material of the first electrical connection structure 510 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
Specifically, the step of forming the first electrical connection structure 510 electrically connected to the first electrode layer 220 in the first via 310 includes: a layer of electrical connection structure material (not shown) is formed overlying the second dielectric layer 300, filling the first via 310, for directly forming the first electrical connection structure 510.
In this embodiment, the electrical connection structure material layer higher than the top of the second dielectric layer 300 is removed, and the electrical connection structure material layer located in the first via 310 remains as the first electrical connection structure 510.
In this embodiment, the dry etching process is used to remove the material layer of the electrical connection structure higher than the top of the second dielectric layer 300, which is beneficial to forming the first electrical connection structure 510 with better top quality.
Referring to fig. 9, after the first electrical connection structure 510 is formed, a second via 320 is formed through the stacked structure 200.
The second via 320 is used to provide a spatial location for forming a second electrical connection structure.
In this embodiment, an etching process is used, where the top surface of the etching stop layer 110 is used as an etching stop position to form the second through hole 320, so as to correspondingly reduce the probability of damage to the substrate 100 caused by the etching process for forming the second through hole 320, and improve the bottom height consistency of the second through hole 320.
Specifically, in this embodiment, the second via hole 320 is formed by using an anisotropic etching process, so that the etching precision is high, and the formation of the second via hole 320 with good sidewall quality is facilitated.
In this embodiment, the second dielectric layer 300 covers the stacked structure 200, and accordingly, in the step of forming the second through hole 320 penetrating through the stacked structure 200, the second through hole 320 also penetrates through the second dielectric layer 300 located on top of the stacked structure 200.
In this embodiment, the step of forming the second through hole 320 penetrating the stacked structure 200 includes: a second mask layer (not shown) is formed overlying the top of the stack 200.
Specifically, the second mask layer is disposed on the second dielectric layer 300 that covers the stacked structure 200, thereby reducing damage to the stacked structure 200 caused by the patterned second mask layer.
In this embodiment, the second mask layer is patterned to form a second mask opening (not shown).
The second mask opening exposes the top of the second dielectric layer 300 and is used as an etching mask opening for etching the stacked structure 200, thereby defining an etching position of the second via 320.
In this embodiment, the stacked structure 200 is etched along the second mask opening to form the second via 320.
In this embodiment, after the second via hole 320 is formed, the second mask layer is removed.
Referring to fig. 10, the sacrificial layer 210 is removed through the second via hole 320, a trench 330 exposing the first electrode layer 220 and sidewalls of the first electrical connection structure 510 in contact with the sacrificial layer 210 is formed, and the trench 330 communicates with the second via hole 320.
The trenches 330 are used to provide spatial locations for the subsequent formation of the first dielectric layer and the second electrode layer.
In this embodiment, a wet etching process is used to remove the sacrificial layer 210 through the second via 320.
The wet etching process has relatively low cost and simple operation steps, and can realize a large etching selection ratio, thereby being beneficial to reducing the damage to the first electrode layer 220 in the process of removing the sacrificial layer 210.
In the step of removing the sacrificial layer 210 through the second via hole 320, the etching selectivity of the sacrificial layer 210 to the first electrode layer 220 is not too small. If the etching selection ratio of the sacrificial layer 210 to the first electrode layer 220 is too small, the first electrode layer 220 is easily damaged during the removal of the sacrificial layer 210, thereby affecting the operation performance of the semiconductor structure. For this reason, in the present embodiment, the etching selectivity of the sacrificial layer 210 to the first electrode layer 220 is greater than or equal to 3.
Referring to fig. 11, a first dielectric layer 230 conformally covering the respective sides of the trench 330 and the second via 320 is formed.
In this embodiment, the first dielectric layer 230 covering the horizontal surface of the first electrode layer 220 is used as an insulating layer in forming the MiM capacitor, for isolating the first electrode layer 220 from the subsequently formed second electrode layer.
In this embodiment, the first dielectric layer 230 located on the sidewall of the first electrical connection structure 510 is used to isolate the first electrical connection structure 510 from the second electrode layer formed subsequently, and the first dielectric layer 230 located on the vertical surface of the first electrode layer 220 is used to isolate the second electrical connection structure from the first electrode layer 220.
In the embodiment of the invention, the first dielectric layer 230 of the capacitor is utilized to isolate the first electric connection structure 510 from the second electrode layer and isolate the second electric connection structure from the first electrode layer 220, which is beneficial to simplifying the formation process of the capacitor, and the adjacent first electrode layer 220, second electrode layer and first dielectric layer 230 positioned between the two form the capacitor, which is beneficial to improving the equivalent capacitance density, and meanwhile, the laminated structure is utilized to obtain higher equivalent capacitance density, thereby being beneficial to saving the process photomask and further saving the process cost.
In this embodiment, the material of the first dielectric layer 230 is a high-k dielectric material; the high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. The high-k dielectric material is selected, so that the capacitance value of the MiM capacitor is improved, and the capacitance density is correspondingly improved.
Specifically, the first dielectric layer 230 is a high-k first dielectric layer formed by stacking, i.e., the first dielectric layer 230 is a high-k composite first dielectric layer. After the thickness of the high-k first dielectric layer reaches a certain value, itThe formation quality is easily deteriorated, and therefore, by adopting the high-k composite first dielectric layer, the thickness of the first dielectric layer 230 can meet the process requirement and have better formation quality. For this purpose, the high-k dielectric material comprises HfO 2 、HfSiO、TiO 2 、HfZrO、HfSiON、HfTaO、HfTiO、Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 One or more of BaSrTiO and SiN.
In this embodiment, the first dielectric layer 230 is a ZAZ layer. Wherein the ZAZ layer comprises a first ZrO layer formed by stacking 2 Layer, al 2 O 3 Layer and second ZrO 2 A layer. In other embodiments, the material of the first dielectric layer may be one or more of silicon oxide, silicon oxynitride, and silicon nitride, depending on the process requirements.
In this embodiment, the first dielectric layer 230 is formed by an atomic layer deposition process.
The first dielectric layer 230 formed by adopting the atomic layer deposition process has good thickness uniformity and good step coverage (step coverage) capability, so that the first dielectric layer 230 can well cover the surfaces of the trench 330 and the second through hole 320 in a conformal manner.
Referring to fig. 12 to 14 in combination, fig. 12 is a top view, fig. 13 is a cross-sectional view along the AA direction of fig. 12, fig. 14 is a circuit diagram, after forming the first dielectric layer 230, filling the trench 330 and the second via 320, forming the second electrode layer 240 in the trench 330, and forming the second electrical connection structure 520 in the second via 320.
In this embodiment, the first electrode layer 220 and the second electrode layer 240 of the adjacent layers and the first dielectric layer 230 located therebetween form a capacitor, which is beneficial to improving the equivalent capacitance density, and the stacked structure 200 is used to obtain a higher equivalent capacitance density, thereby being beneficial to saving the process photomask and further saving the process cost.
In this embodiment, the second electrode layer 240 and the second electrical connection structure 520 are formed in the same step, which simplifies the process flow and improves the process efficiency.
Accordingly, in the present embodiment, the second electrode layer 240 and the second electrical connection structure 520 are integrated.
Accordingly, in the present embodiment, the second electrode layer 240 is made of the same material as the second electrical connection structure 520.
In this embodiment, the trench 330 and the second via 320 are filled by an atomic layer deposition process, so as to form the second electrode layer 230 and the second electrical connection structure 520.
The second electrode layer 230 and the second electrical connection structure 520 formed by adopting the atomic layer deposition process have good thickness uniformity and good step coverage (step coverage) capability, which are beneficial to better filling the trench 330 and the second through hole 320, and forming the second electrode layer 230 and the second electrical connection structure 520 with higher film quality.
The second electrode layer 240 serves as an electrode plate of the MiM capacitor.
The second electrode layer 240 has a first dielectric layer 230 between the second electrode layer 240 and the first electrode layer 220 such that the first electrode layer 220 and the second electrode layer 240 of adjacent layers form a MiM capacitor.
The material of the second electrode layer 240 is a conductive material. As one example, the material of the second electrode layer 240 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
The second electrical connection structure 520 is used to make electrical connection between the MiM capacitor and an external circuit.
Specifically, the second electrical connection structure 520 is used for electrically connecting the second electrode layers 240 and an external circuit, and is also used for electrically connecting each second electrode layer 240, so that when the capacitor works, the second electrode layers 240 can all access the same potential, and thus the capacitor of the circuit diagram shown in fig. 14 is realized.
In this embodiment, the first electrode layer 220 and the second electrode layer 240 of the adjacent layers form capacitors, and the second electrode layer 220 is connected to the same potential through the second electrical connection structure 520, so that the capacitors formed are connected in parallel two by two, and the capacitance value of the unit area is correspondingly improved, i.e. the equivalent capacitance density is improved.
In this embodiment, the first electrode layer 220 and the second electrode layer 240 of the adjacent layers form capacitors, and the first electrode layer 220 is connected to the same potential through the first electrical connection structure 510, so that the capacitors formed are connected in parallel two by two, and the capacitance value of the unit area is correspondingly improved, that is, the equivalent capacitance density is improved.
The material of the second electrical connection structure 520 is a conductive material. In this embodiment, the material of the second electrical connection structure 520 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
Specifically, in the present embodiment, the step of forming the second electrode layer 230 and the second electrical connection structure 520 includes: a structural material layer (not shown) covering the second dielectric layer 300, the filling trench 330 and the second via 320 is formed for directly forming the second electrode layer 230 and the second electrical connection structure 520.
In this embodiment, the electrical connection structure material layer higher than the top of the second dielectric layer 300 is removed, and the structure material layer located in the second via 320 remains as the second electrical connection structure 520, and the structure material layer located in the trench 330 remains as the second electrode layer 230.
In this embodiment, a dry etching process is used to remove the structural material layer higher than the top of the second dielectric layer 300, which is beneficial to forming the second electrical connection structure 520 with better top quality.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (19)
1. A semiconductor structure, comprising:
a substrate;
an electrode stack on the substrate, the electrode stack including a plurality of first electrode layers and second electrode layers alternately stacked in sequence in a longitudinal direction;
a first electrical connection structure penetrating the electrode stack and electrically connected to the first electrode layer;
a second electrical connection structure penetrating the electrode stack and electrically connected to the second electrode layer;
and the dielectric layer is positioned between the adjacent first electrode layer and the second electrode layer, and extends upwards to the position between the first electrode layer and the second electrode layer of the previous layer along the interface between the first electric connection structure and the second electrode layer and downwards to the position between the first electrode layer and the second electrode layer of the next layer along the interface between the second electric connection structure and the first electrode layer.
2. The semiconductor structure of claim 1, wherein the first electrode layer and the first electrical connection structure are an integral structure or the second electrode layer and the second electrical connection structure are an integral structure.
3. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: an etch stop layer is located between the substrate and the first electrode layer.
4. The semiconductor structure of claim 1, wherein a material of the first electrode layer comprises one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al; the material of the second electrode layer includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
5. The semiconductor structure of claim 1, wherein a material of the first electrical connection structure comprises one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al; the material of the second electrical connection structure includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
6. The semiconductor structure of claim 1, wherein the material of the dielectric layer comprises HfO 2 、HfSiO、TiO 2 、HfZrO、HfSiON、HfTaO、HfTiO、Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 Any one or more of BaSrTiO and SiN.
7. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a laminated structure is formed on the substrate, the laminated structure comprises a plurality of first target layers and second target layers which are alternately stacked in sequence along the longitudinal direction, any one of the first target layers and the second target layers is a first electrode layer, and the other one is a sacrificial layer;
forming a first through hole penetrating through the laminated structure;
forming a first electrical connection structure in the first via hole, the first electrical connection structure being electrically connected to the first electrode layer;
forming a second through hole penetrating through the laminated structure after forming the first electric connection structure;
removing the sacrificial layer through the second through hole to form a groove exposing the first electrode layer and the side wall of the first electric connection structure, which is in contact with the sacrificial layer, wherein the groove is communicated with the second through hole;
forming a first dielectric layer conformally covering each side of the groove and the second through hole;
and after the first dielectric layer is formed, filling the groove and the second through hole, forming a second electrode layer in the groove, and forming a second electric connection structure in the second through hole.
8. The method of claim 7, wherein the second electrode layer is integral with the second electrical connection structure.
9. The method of forming a semiconductor structure of claim 7, wherein forming a first via through the stacked structure comprises: forming a first mask layer covering the top of the laminated structure;
patterning the first mask layer to form a first mask opening;
etching the laminated structure along the first mask opening to form the first through hole;
and removing the first mask layer after the first through hole is formed.
10. The method of forming a semiconductor structure of claim 7, wherein forming a second via through the stacked structure comprises: forming a second mask layer covering the laminated structure and the top of the first electric connection structure;
patterning the second mask layer to form a second film opening;
etching the laminated structure along the second mask opening to form the second through hole;
and removing the second mask layer after the second through hole is formed.
11. The method of forming a semiconductor structure of claim 7, further comprising, prior to forming a first via through the electrode stack: forming a second dielectric layer covering the laminated structure;
in the step of forming a first through hole penetrating through the laminated structure, the first through hole also penetrates through a second dielectric layer positioned at the top of the laminated structure;
in the step of forming a second through hole penetrating through the laminated structure, the second through hole also penetrates through a second dielectric layer positioned on the top of the laminated structure.
12. The method of forming a semiconductor structure of claim 11, wherein forming a first electrical connection structure in the first via electrically connected to the first electrode layer comprises: forming an electric connection structure material layer which covers the second dielectric layer and fills the first through hole;
and removing the electric connection structure material layer higher than the top of the second dielectric layer, and reserving the electric connection structure material layer positioned in the first through hole as the first electric connection structure.
13. The method of forming a semiconductor structure according to claim 7, wherein in the step of removing the sacrificial layer through the second via hole, an etching selectivity of the sacrificial layer to the first electrode layer is 3 or more.
14. The method of forming a semiconductor structure of claim 7, wherein in the step of providing the substrate, the material of the sacrificial layer comprises silicon nitride, amorphous silicon, titanium nitride, or tungsten.
15. The method of forming a semiconductor structure of claim 7, wherein the sacrificial layer is removed through the second via using a wet etch process.
16. The method of forming a semiconductor structure of claim 7, wherein the first dielectric layer conformally covering each side of the trench and the second via is formed using an atomic layer deposition process.
17. The method of forming a semiconductor structure of claim 7, wherein the trench and the second via are filled using an atomic layer deposition process to form the second electrode layer and the second electrical connection structure.
18. The method of forming a semiconductor structure of claim 7, wherein prior to the step of providing a substrate, further comprising: forming a laminated material layer covering the substrate, wherein the laminated material layer comprises a plurality of first target layers and second target layers which are alternately stacked in turn along the longitudinal direction, any one of the first target layers and the second target layers is a first electrode layer, and the other is a sacrificial layer;
and patterning the laminated material layer to form the laminated structure.
19. The method of forming a semiconductor structure of claim 18, wherein in the step of providing a substrate, an etch stop layer is formed between the substrate and the layer of stacked material;
and in the step of patterning the laminated material layer, the etching stop layer is used as an etching stop position.
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