CN118173513A - H bridge device structure of integrated NMOS tube - Google Patents
H bridge device structure of integrated NMOS tube Download PDFInfo
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- CN118173513A CN118173513A CN202410591927.0A CN202410591927A CN118173513A CN 118173513 A CN118173513 A CN 118173513A CN 202410591927 A CN202410591927 A CN 202410591927A CN 118173513 A CN118173513 A CN 118173513A
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- 239000002184 metal Substances 0.000 claims abstract description 124
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000002131 composite material Substances 0.000 claims abstract description 20
- 238000005538 encapsulation Methods 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 4
- 238000012544 monitoring process Methods 0.000 abstract description 4
- 230000006378 damage Effects 0.000 abstract description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000004806 packaging method and process Methods 0.000 description 9
- 238000009529 body temperature measurement Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 4
- 230000003685 thermal hair damage Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
The invention discloses an H-bridge device structure of an integrated NMOS (N-channel metal oxide semiconductor) tube, which belongs to the technical field of integrated circuits and comprises a substrate, wherein an N-type heavy doping region and an N-type light doping region are formed in the substrate, the N-type light doping region is positioned at the top of the N-type heavy doping region, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube are formed in the substrate to form an H-bridge circuit, a composite insulating layer is formed on the front surface of the substrate, a heat conducting metal layer is covered on the top of the composite insulating layer, a temperature measuring resistor is formed on the top of the heat conducting metal layer, and the bottom surface of the temperature measuring resistor is in contact with the heat conducting metal layer. Through integrating NMOS pipe on a substrate and constituting H bridge circuit, improve the device integrated level, set up temperature measuring resistor, match outside temperature acquisition and control circuit can play the effect of monitoring the device temperature, avoid the heat damage of device.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an H-bridge device structure of an integrated NMOS tube.
Background
The traditional NMOS-H bridge driving circuit is formed by combining 4 NMOS tubes and 4 freewheel diodes, a load is positioned at the center and is H-shaped, and the H bridge circuit can switch the polarity of an additional load power supply circuit and regulate and control the output power. The most common use of the H bridge is to drive a direct current motor, and in the use process, the heating value of the MOS tube can be increased sharply under the state of a non-ideal switch, so that the service life of the MOS tube is seriously influenced, and even the MOS tube can be directly damaged.
It should be noted that the information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide an H-bridge device structure integrating NMOS (N-channel metal oxide semiconductor) tubes, which aims to solve the problems that H-bridge circuit integrated devices are more and the devices are easy to damage due to heating.
In order to solve the technical problems, the invention provides an H-bridge device structure integrating NMOS tubes, which comprises a substrate, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube, wherein an N-type heavy doping region and an N-type light doping region are formed in the substrate, the N-type light doping region is positioned at the top of the N-type heavy doping region, the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are formed in the substrate so as to form an H-bridge circuit, the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube share the N-type heavy doping region and the N-type light doping region, a composite insulating layer is formed on the front surface of the substrate, a heat conducting metal layer is covered on the top of the composite insulating layer, a temperature measuring resistor is formed on the top of the heat conducting metal layer, and the bottom surface of the temperature measuring resistor is in contact with the heat conducting metal layer.
Preferably, the bottom of the temperature measuring resistor is further provided with a heat conducting metal body, the top of the heat conducting metal body penetrates through the composite insulating layer to be in contact with the heat conducting metal layer, the bottom extends into the N-type lightly doped region, and the bottom and the side wall of the heat conducting metal body are provided with external insulating layers for isolating the N-type lightly doped region and the composite insulating layer.
Preferably, the temperature measuring resistor further comprises a bottom metal layer and an insulating packaging layer, wherein the insulating packaging layer is arranged around the temperature measuring resistor so as to surround and fix the temperature measuring resistor, the bottom metal layer is positioned at the bottom of the N-type heavily doped region, electric pins are led out of the temperature measuring resistor, and the electric pins are positioned at the top of the insulating packaging layer.
Preferably, the first NMOS includes two first P-type heavily doped regions, the first P-type heavily doped regions are located at the top of the N-type lightly doped regions, the first N-type heavily doped regions are formed at the top of the first P-type heavily doped regions, first source metal outgoing lines are led out at the top of the first N-type heavily doped regions, a first gate is arranged in the composite insulating layer between the two first source metal outgoing lines, a space is formed between the bottom of the first gate and the substrate, and the first gate metal outgoing lines are led out at the top of the first gate.
Preferably, the first NMOS transistor further includes a first drain metal layer, the first drain metal layer is located at the bottom of the N-type heavily doped region, and a space is provided between the first drain metal layer and the bottom metal layer.
Preferably, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor have the same structure.
Preferably, the first source metal outgoing line of the first NMOS transistor is connected to the fourth drain metal layer of the fourth NMOS transistor, the first drain metal layer of the first NMOS transistor is interconnected with the second drain metal layer of the second NMOS transistor, the second source metal outgoing line of the second NMOS transistor is connected to the third drain metal layer of the third NMOS transistor, and the third source metal outgoing line of the third NMOS transistor is connected to the fourth source metal outgoing line of the fourth NMOS transistor.
Preferably, the first gate metal lead-out wire of the first NMOS tube is connected to a first gate control signal, the second gate metal lead-out wire of the second NMOS tube is connected to a second gate control signal, the third gate metal lead-out wire of the third NMOS tube is connected to a third gate control signal, and the fourth gate metal lead-out wire of the fourth NMOS tube is connected to a fourth gate control signal.
Preferably, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are arranged in a rectangular array.
Preferably, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are disposed around the temperature measuring resistor.
According to the H-bridge device structure of the integrated NMOS tube, the NMOS tube is integrated on the substrate to form the H-bridge circuit, the temperature measuring resistor is embedded into the front insulation packaging layer of the integrated device, and the heat conducting metal layer is manufactured below the temperature measuring resistor and connected to the inside of the integrated device, so that the temperature measurement is closer to the temperature saving inside the device, the measurement is more accurate, the effect of monitoring the temperature of the device can be achieved by matching with the external temperature acquisition and control circuit, and the internal MOS tube can be turned off in time to avoid the thermal damage of the device.
Drawings
Those of ordinary skill in the art will appreciate that the figures are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention. Wherein:
FIG. 1 is a schematic diagram of a 4NMOS-H bridge drive circuit;
FIG. 2 is a schematic cross-sectional view of a first NMOS transistor Q1 according to an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of a second NMOS transistor Q2 according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of a third NMOS transistor Q3 according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of a fourth NMOS transistor Q4 according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of a temperature measuring resistor according to an embodiment of the present invention;
FIG. 7 is a top view of an H-bridge device structure of an integrated NMOS transistor according to an embodiment of the present invention;
fig. 8 is a schematic perspective view of an H-bridge device structure integrated with NMOS transistors according to an embodiment of the present invention.
In the accompanying drawings:
1. A substrate; 2. an N-type heavily doped region; 3. an N-type lightly doped region; 4. a first P-type heavily doped region; 5. a first N-type heavily doped region; 6. a first gate; 7. a composite insulating layer; 8. a first drain metal layer; 9. a first source metal lead; 10. a second P-type heavily doped region; 11. a second N-type heavily doped region; 12. a second gate; 13. a second drain metal layer; 14. a second source metal lead; 15. a third P-type heavily doped region; 16. a third N-type heavily doped region; 17. a third gate; 18. a third drain metal layer; 19. a third source metal lead; 20. a fourth P-type heavily doped region; 21. a fourth N-type heavily doped region; 22. a fourth gate; 23. a fourth drain metal layer; 24. a fourth source metal lead; 25. a first gate metal lead; 26. a second gate metal lead; 27. a third gate metal lead; 28. a fourth gate metal lead; 29. a thermally conductive metal body; 30. an external insulating layer; 31. a thermally conductive metal layer; 32. a temperature measuring resistor; 33. an electrical pin; 34. an insulating encapsulation layer; 35. a bottom metal layer.
Q1, a first NMOS tube; q2, a second NMOS tube; q3, a third NMOS tube; q4, a fourth NMOS tube.
Detailed Description
The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" are generally used in the sense of comprising "and/or" and the term "several" are generally used in the sense of comprising "at least one," the term "at least two" are generally used in the sense of comprising "two or more," and the term "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or number of features indicated. Thus, a feature defining "first," "second," "third," or "third" may explicitly or implicitly include one or at least two such features, the term "proximal" typically being one end proximal to the operator, the term "distal" typically being one end proximal to the patient, "one end" and "other" and "proximal" and "distal" typically referring to corresponding two portions, including not only the endpoints, the terms "mounted," "connected," "coupled," or "coupled" are to be construed broadly, e.g., as either a fixed connection, a removable connection, or as one piece; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. Furthermore, as used in this disclosure, an element disposed on another element generally only refers to a connection, coupling, cooperation or transmission between two elements, and the connection, coupling, cooperation or transmission between two elements may be direct or indirect through intermediate elements, and should not be construed as indicating or implying any spatial positional relationship between the two elements, i.e., an element may be in any orientation, such as inside, outside, above, below, or on one side, of the other element unless the context clearly indicates otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
The inventor researches and discovers that a plurality of devices are required to be integrated in a conventional H-bridge circuit, and in the use process, the heating value of the MOS tube can be increased sharply in a non-ideal switching state, so that the service life of the MOS tube is seriously influenced, and even the MOS tube is directly damaged.
Based on the above, the invention has the core ideas that the use amount of discrete devices is reduced by integrating the MOS tube and the free-wheeling diode, meanwhile, the temperature measuring resistor is arranged in the integrated devices, the number of devices in an application scene is optimized, the cost and the occupied space of a system are reduced, and meanwhile, the internal temperature of the devices can be monitored.
Specifically, please refer to fig. 1-8, which are schematic diagrams of an embodiment of the present invention. The utility model provides an H bridge device structure of integrated NMOS pipe, includes substrate 1, first NMOS pipe Q1, second NMOS pipe Q2, third NMOS pipe Q3 and fourth NMOS pipe Q4, be formed with N type heavy doping district 2 and N type lightly doped district 3 in the substrate 1, N type lightly doped district 3 is located the top of N type heavy doping district 2, form in the substrate 1 first NMOS pipe Q1, second NMOS pipe Q2, third NMOS pipe Q3 and fourth NMOS pipe Q4 to constitute H bridge circuit, wherein first NMOS pipe Q1, second NMOS pipe Q2, third NMOS pipe Q3 and fourth NMOS pipe Q4 share N type heavy doping district 2 with N type lightly doped district 3, the front of substrate 1 is formed with composite insulation layer 7, composite insulation layer 7's top covers and is provided with heat conduction metal layer 31, the top of heat conduction metal layer 31 is formed with temperature measurement resistance 32, temperature measurement resistance 32's bottom surface and heat conduction metal layer 31 contact.
The NMOS tube is integrated on a substrate to form an H-bridge circuit, the integration level of the device is improved, discrete devices are reduced, the temperature measuring resistor 32 is embedded into the front insulation packaging layer 34 of the integrated device, the heat conducting metal layer 31 is manufactured below the temperature measuring resistor 32 and is connected to the inside of the integrated device, so that the temperature measurement is closer to the temperature saving inside the device, the measurement is more accurate, the effect of monitoring the temperature of the device can be achieved by matching with an external temperature acquisition and control circuit, and the internal MOS tube can be turned off in time to avoid the thermal damage of the device.
The first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, the fourth NMOS transistor Q4, and the freewheeling diodes D1, D2, D3, and D4 formed in the respective MOS transistors are all disposed on the substrate 1, so that an H-bridge circuit is shown in fig. 1, and it should be noted that, in fig. 1, a load motor M is not disposed on the substrate 1, and in the embodiment, a drain of the first NMOS transistor Q1 and a drain of the second NMOS transistor Q2 are externally connected with Vbat (load power supply), a load motor M is disposed between a source of the first NMOS transistor Q1 and a source of the second NMOS transistor Q2, and a source of the fourth NMOS transistor Q4 and a source of the third NMOS transistor Q3 are commonly grounded.
In one embodiment, the bottom of the temperature measuring resistor 32 is further provided with a heat conducting metal body 29, the top of the heat conducting metal body 29 penetrates through the composite insulating layer 7 to be in contact with the heat conducting metal layer 31, the bottom extends into the N-type lightly doped region 3, and the bottom and the side wall of the heat conducting metal body 29 are provided with an external insulating layer 30 for isolating the N-type lightly doped region 3 and the composite insulating layer 7. The temperature measuring resistor 32 is surrounded and fixed by the insulating packaging layer 34, the bottom metal layer 35 is located at the bottom of the N-type heavily doped region 2 and used for heat dissipation and conduction, the electrical pins 33 are led out of the temperature measuring resistor 32, and the electrical pins 33 are located at the top of the insulating packaging layer 34. The insulating encapsulation layer 34 is made of insulating encapsulation material, so as to surround the fixed temperature measuring resistor 32 and protect the whole device.
As shown in fig. 6, a heat conducting metal body 29 is disposed in the N-type lightly doped region 3, and an external insulating layer 30 is disposed on the heat conducting metal body 29, so that heat generated by the substrate 1 and the composite insulating layer 7 can be transferred to a temperature measuring resistor 32 through the heat conducting metal layer 31, and the heat conducting metal body is connected with an external device, such as a temperature control circuit, through an electrical pin 33 connected to the temperature measuring resistor 32, and an internal MOS tube can be turned off in time to avoid thermal damage of the device when the temperature exceeds the temperature.
Specifically, the first NMOS transistor Q1 includes two first P-type heavily doped regions 4, the first P-type heavily doped regions 4 are located at the top of the N-type lightly doped regions 3, the top of the first P-type heavily doped regions 4 is formed with first N-type heavily doped regions 5, the top of the first N-type heavily doped regions 5 is led out with first source metal lead-out wires 9, a first gate 6 is disposed in the composite insulating layer 7 between the two first source metal lead-out wires 9, an interval is formed between the bottom of the first gate 6 and the substrate 1, and a first gate metal lead-out wire 25 is connected to the top of the first gate 6. The first NMOS transistor Q1 further includes a first drain metal layer 8, where the first drain metal layer 8 is located at the bottom of the N-type heavily doped region 2, and a space is provided between the first drain metal layer 8 and the bottom metal layer 35.
As shown in fig. 2, the first P-type heavily doped region 4 in the first NMOS transistor Q1 is also used as the P-pole of the freewheeling diode D1, and the first drain metal layer 8 in the first NMOS transistor Q1 is also used as the N-pole metal layer of the freewheeling diode D1 and is connected to the second drain metal layer 13 of the second NMOS transistor Q2. The range and the P-type doping concentration of the well region of the MOS tube are optimized to serve as the P pole of the freewheel diode, the N-type doping concentration and the range of the substrate are optimized to serve as the N pole of the freewheel diode, and compared with the body diode of the traditional MOS tube, the optimized MOS tube body diode has better voltage withstanding freewheel capacity, and the traditional external freewheel diode can be directly replaced.
Specifically, the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4 have the same structure. It can be understood that, as shown in fig. 3 to 5, the second NMOS transistor Q2 also has two second P-type heavily doped regions 10, a second N-type heavily doped region 11 is disposed in the second P-type heavily doped region 10, a second source metal lead 14 is connected to the top of the second N-type heavily doped region 11, a second gate 12 and a second gate metal lead 26 are formed between the second source metal lead 14, and a second drain metal layer 13 is further disposed at the N-type heavily doped region 2 on the back surface of the second NMOS transistor Q2, and similarly, a third P-type heavily doped region 15, a third N-type heavily doped region 16, a third source metal lead 19, a third gate 17, a third gate metal lead 27 and a third drain metal layer 18 are disposed in the third NMOS transistor Q3; the fourth NMOS transistor Q4 has a fourth P-type heavily doped region 20, a fourth N-type heavily doped region 21, a fourth source metal lead 24, a fourth gate 22, and a fourth gate metal lead 28.
It will be appreciated that the first source metal lead 9 of the first NMOS transistor Q1 is connected to the fourth drain metal layer 23 of the fourth NMOS transistor Q4, the first drain metal layer 8 of the first NMOS transistor Q1 is interconnected with the second drain metal layer 13 of the second NMOS transistor Q2, the second source metal lead 14 of the second NMOS transistor Q2 is connected to the third drain metal layer 18 of the third NMOS transistor Q3, and the third source metal lead 19 of the third NMOS transistor Q3 is connected to the fourth source metal lead 24 of the fourth NMOS transistor Q4.
Specifically, the first gate metal lead-out wire 25 of the first NMOS transistor Q1 is connected to the first gate control signal G1, the second gate metal lead-out wire 26 of the second NMOS transistor Q2 is connected to the second gate control signal G2, the third gate metal lead-out wire 27 of the third NMOS transistor Q3 is connected to the third gate control signal G3, and the fourth gate metal lead-out wire 28 of the fourth NMOS transistor Q4 is connected to the fourth gate control signal G4.
As shown in fig. 7 to 8, the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4 are arranged in a rectangular array. The first NMOS tube Q1, the second NMOSQ tube, the third NMOS tube Q3 and the fourth NMOS tube Q4 are arranged around the temperature measuring resistor 32, the temperature measuring resistor 32 is positioned at the top of the substrate 1 and slightly higher than each NMOS tube, the subsequent process is facilitated to connect other devices, and the functions of the H-bridge device structure are expanded. It can be understood that, as shown in fig. 7 and fig. 8, the temperature measuring resistor 32 is similar to the temperature measuring resistor 32 in fig. 6, and the structures of the heat conducting metal body 29 (not labeled), the electrical pins 33 (not shown) and the like are also present at the lower part of the temperature measuring resistor 32 in fig. 8, which are not described herein.
The first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4 are arranged in a rectangular array of 2×2, and the temperature measuring resistor 32 is located on the composite insulating layer 7 in the center of the array, and receives heat transferred from the substrate 1 through the heat conducting metal layer 31 and the heat conducting metal body 29 at the bottom thereof.
The H-bridge device structure integrating NMOS tubes provided by the invention integrates 4 NMOS tubes and 4 equivalent freewheel diodes, meanwhile, a heat conduction metal area is added in the device, and a temperature measuring resistor is embedded in an insulating layer of the front packaging of the device. The N-type doping concentration and the range of the substrate are optimized to serve as the N pole of the free wheeling diode, and compared with the body diode of the traditional MOS tube, the optimized MOS tube body diode has better voltage withstanding free wheeling capability, and the traditional external free wheeling diode can be directly replaced. The temperature measuring resistor is embedded into the front packaging protection layer of the integrated device, the heat conducting metal layer is manufactured below the temperature measuring resistor and is connected to the inside of the integrated device, so that the temperature measurement is closer to the temperature saving inside the device, the measurement is more accurate, the effect of monitoring the temperature of the device can be achieved by matching with an external temperature acquisition and control circuit, and the internal MOS tube can be turned off in time to avoid the thermal damage of the device.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention in any way, and any changes and modifications made by those skilled in the art in light of the foregoing disclosure will be deemed to fall within the scope and spirit of the present invention.
Claims (10)
1. The H bridge device structure of the integrated NMOS tube is characterized by comprising a substrate, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube, wherein an N-type heavy doping region and an N-type light doping region are formed in the substrate, the N-type light doping region is positioned at the top of the N-type heavy doping region, the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are formed in the substrate so as to form an H bridge circuit, the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube share the N-type heavy doping region and the N-type light doping region, a composite insulating layer is formed on the front surface of the substrate, a heat conducting metal layer covers the top of the composite insulating layer, a temperature measuring resistor is formed at the top of the heat conducting metal layer, and the bottom surface of the temperature measuring resistor is in contact with the heat conducting metal layer.
2. The H-bridge device structure of an integrated NMOS tube of claim 1, wherein the bottom of the temperature sensing resistor is further provided with a thermally conductive metal body, the top of the thermally conductive metal body penetrates through the composite insulating layer to be in contact with the thermally conductive metal layer, the bottom extends into the N-type lightly doped region, and the bottom and the sidewall of the thermally conductive metal body are provided with external insulating layers for isolating the N-type lightly doped region and the composite insulating layer.
3. The NMOS integrated H-bridge device structure of claim 2 further comprising a bottom metal layer and an insulating encapsulation layer, said insulating encapsulation layer disposed around said temperature sensing resistor to surround and secure said temperature sensing resistor, said bottom metal layer being located at the bottom of said N-type heavily doped region, said temperature sensing resistor having electrical pins drawn therefrom, said electrical pins being located at the top of said insulating encapsulation layer.
4. The H-bridge device structure of an integrated NMOS of claim 1, wherein said first NMOS comprises two first P-type heavily doped regions, said first P-type heavily doped regions being located at the top of said N-type lightly doped regions, said first N-type heavily doped regions each having a first N-type heavily doped region formed at the top thereof, said first N-type heavily doped regions each having a first source metal lead out, a first gate being disposed in the composite insulating layer between said two first source metal leads, a space being provided between the bottom of said first gate and said substrate, said first gate having a first gate metal lead out connected to the top thereof.
5. The NMOS transistor integrated H-bridge device structure of claim 3, wherein said first NMOS transistor further comprises a first drain metal layer, said first drain metal layer being located at a bottom of said N-type heavily doped region, said first drain metal layer and said bottom metal layer having a space therebetween.
6. The NMOS integrated H-bridge device structure of claim 4, wherein said first, second, third, and fourth NMOS transistors are identical in structure.
7. The NMOS integrated H-bridge device structure of claim 6, wherein said first source metal lead of said first NMOS is connected to said fourth drain metal layer of said fourth NMOS, said first drain metal layer of said first NMOS is interconnected to said second drain metal layer of said second NMOS, said second source metal lead of said second NMOS is connected to said third drain metal layer of said third NMOS, and said third source metal lead of said third NMOS is connected to said fourth source metal lead of said fourth NMOS.
8. The H-bridge device structure of integrated NMOS of claim 1, wherein a first gate metal lead of said first NMOS is connected to a first gate control signal, a second gate metal lead of said second NMOS is connected to a second gate control signal, a third gate metal lead of said third NMOS is connected to a third gate control signal, and a fourth gate metal lead of said fourth NMOS is connected to a fourth gate control signal.
9. The NMOS transistor integrated H-bridge device structure of claim 1, wherein said first, second, third, and fourth NMOS transistors are arranged in a rectangular array.
10. The NMOS integrated H-bridge device structure of claim 9, wherein said first, second, third, and fourth NMOS transistors are disposed around said temperature sensing resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410591927.0A CN118173513B (en) | 2024-05-14 | 2024-05-14 | H bridge device structure of integrated NMOS tube |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410591927.0A CN118173513B (en) | 2024-05-14 | 2024-05-14 | H bridge device structure of integrated NMOS tube |
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| CN118173513A true CN118173513A (en) | 2024-06-11 |
| CN118173513B CN118173513B (en) | 2024-08-09 |
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| CN202410591927.0A Active CN118173513B (en) | 2024-05-14 | 2024-05-14 | H bridge device structure of integrated NMOS tube |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005043271A1 (en) * | 2005-09-12 | 2007-03-15 | Infineon Technologies Ag | Resistance sensor measuring temperature in e.g. vertical power field effect transistor, is integrated with heater into substrate accommodating transistor, to test operational reliability |
| US20150115359A1 (en) * | 2013-10-30 | 2015-04-30 | Renesas Electronics Corporation | Semiconductor device |
| CN206849840U (en) * | 2017-06-25 | 2018-01-05 | 上海矽诚科技有限公司 | A kind of H bridge devices of high integration |
| CN112447832A (en) * | 2019-08-28 | 2021-03-05 | 珠海零边界集成电路有限公司 | Semiconductor power device and preparation method |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005043271A1 (en) * | 2005-09-12 | 2007-03-15 | Infineon Technologies Ag | Resistance sensor measuring temperature in e.g. vertical power field effect transistor, is integrated with heater into substrate accommodating transistor, to test operational reliability |
| US20150115359A1 (en) * | 2013-10-30 | 2015-04-30 | Renesas Electronics Corporation | Semiconductor device |
| CN206849840U (en) * | 2017-06-25 | 2018-01-05 | 上海矽诚科技有限公司 | A kind of H bridge devices of high integration |
| CN112447832A (en) * | 2019-08-28 | 2021-03-05 | 珠海零边界集成电路有限公司 | Semiconductor power device and preparation method |
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