CN118173513A - H bridge device structure of integrated NMOS tube - Google Patents

Abstract

The invention discloses an H-bridge device structure of an integrated NMOS (N-channel metal oxide semiconductor) tube, which belongs to the technical field of integrated circuits and comprises a substrate, wherein an N-type heavy doping region and an N-type light doping region are formed in the substrate, the N-type light doping region is positioned at the top of the N-type heavy doping region, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube are formed in the substrate to form an H-bridge circuit, a composite insulating layer is formed on the front surface of the substrate, a heat conducting metal layer is covered on the top of the composite insulating layer, a temperature measuring resistor is formed on the top of the heat conducting metal layer, and the bottom surface of the temperature measuring resistor is in contact with the heat conducting metal layer. Through integrating NMOS pipe on a substrate and constituting H bridge circuit, improve the device integrated level, set up temperature measuring resistor, match outside temperature acquisition and control circuit can play the effect of monitoring the device temperature, avoid the heat damage of device.

Description

An H-bridge device structure integrating NMOS tubes

Technical Field

The invention relates to the technical field of integrated circuits, and in particular to an H-bridge device structure integrating an NMOS tube.

Background technique

The traditional NMOS-H bridge drive circuit is composed of 4 NMOS tubes and 4 freewheeling diodes. The load is located in the center, forming an H shape. The H bridge circuit can switch the polarity of the additional load power supply circuit and adjust the output power. The most common use of the H bridge is to drive a DC motor. During use, the heat generated by the MOS tube will increase sharply under the non-ideal switching state, which will seriously affect the life of the MOS tube and even directly damage the MOS tube.

It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as acknowledging or suggesting in any form that the information constitutes prior art already known to those skilled in the art.

Summary of the invention

The object of the present invention is to provide an H-bridge device structure integrating NMOS tubes, so as to solve the problem that the H-bridge circuit has many integrated devices and the devices are easily damaged due to heating.

In order to solve the above technical problems, the present invention provides an H-bridge device structure integrating NMOS tubes, comprising a substrate, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube, wherein an N-type heavily doped region and an N-type lightly doped region are formed in the substrate, and the N-type lightly doped region is located on the top of the N-type heavily doped region, and the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are formed in the substrate to form an H-bridge circuit, wherein the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube share the N-type heavily doped region and the N-type lightly doped region, a composite insulating layer is formed on the front side of the substrate, the top of the composite insulating layer is covered with a heat-conducting metal layer, a temperature measuring resistor is formed on the top of the heat-conducting metal layer, and the bottom surface of the temperature measuring resistor is in contact with the heat-conducting metal layer.

Preferably, a thermally conductive metal body is also provided at the bottom of the temperature measuring resistor, the top of the thermally conductive metal body penetrates the composite insulating layer and contacts the thermally conductive metal layer, and the bottom extends into the N-type lightly doped region, and an external insulating layer is provided at the bottom and side walls of the thermally conductive metal body for isolating the N-type lightly doped region and the composite insulating layer.

Preferably, it also includes a bottom metal layer and an insulating packaging layer, wherein the insulating packaging layer is arranged around the temperature measuring resistor to surround and fix the temperature measuring resistor, the bottom metal layer is located at the bottom of the N-type heavily doped region, and electrical pins are led out from the temperature measuring resistor, and the electrical pins are located at the top of the insulating packaging layer.

Preferably, the first NMOS tube includes two first P-type heavily doped regions, the first P-type heavily doped regions are located on the top of the N-type lightly doped regions, the tops of the first P-type heavily doped regions are formed with first N-type heavily doped regions, the tops of the first N-type heavily doped regions are led out with first source metal lead wires, a first gate is arranged in the composite insulating layer between the two first source metal lead wires, a gap is provided between the bottom of the first gate and the substrate, and a first gate metal lead wire is connected to the top of the first gate.

Preferably, the first NMOS tube further includes a first drain metal layer, the first drain metal layer is located at the bottom of the N-type heavily doped region, and there is a gap between the first drain metal layer and the bottom metal layer.

Preferably, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor have the same structure.

Preferably, the first source metal lead-out line of the first NMOS tube is connected to the fourth drain metal layer of the fourth NMOS tube, the first drain metal layer of the first NMOS tube is interconnected with the second drain metal layer of the second NMOS tube, the second source metal lead-out line of the second NMOS tube is connected to the third drain metal layer of the third NMOS tube, and the third source metal lead-out line of the third NMOS tube is connected to the fourth source metal lead-out line of the fourth NMOS tube.

Preferably, the first gate metal lead wire of the first NMOS tube is connected to the first gate control signal, the second gate metal lead wire of the second NMOS tube is connected to the second gate control signal, the third gate metal lead wire of the third NMOS tube is connected to the third gate control signal, and the fourth gate metal lead wire of the fourth NMOS tube is connected to the fourth gate control signal.

Preferably, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are arranged in a rectangular array.

Preferably, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are arranged around the temperature measuring resistor.

In the H-bridge device structure of the integrated NMOS tube provided by the present invention, the NMOS tube is integrated on a substrate to form an H-bridge circuit, and the temperature measuring resistor is embedded in the front insulating packaging layer of the integrated device. A thermal conductive metal layer is made under the temperature measuring resistor to connect to the inside of the integrated device, so that the temperature measurement is closer to the temperature inside the device, and the measurement is more accurate. In combination with an external temperature acquisition and control circuit, the device temperature can be monitored. If the temperature is over, the internal MOS tube can be shut down in time to avoid thermal damage to the device.

BRIEF DESCRIPTION OF THE DRAWINGS

Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

FIG1 is a schematic diagram of a 4NMOS-H bridge driving circuit;

FIG2 is a schematic cross-sectional view of a first NMOS transistor Q1 according to an embodiment of the present invention;

FIG3 is a schematic cross-sectional view of a second NMOS transistor Q2 according to an embodiment of the present invention;

FIG4 is a schematic cross-sectional view of a third NMOS transistor Q3 according to an embodiment of the present invention;

FIG5 is a schematic cross-sectional view of a fourth NMOS transistor Q4 according to an embodiment of the present invention;

6 is a schematic cross-sectional view of a temperature measuring resistor according to an embodiment of the present invention;

7 is a top view of an H-bridge device structure of an integrated NMOS tube according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a three-dimensional structure of an H-bridge device structure integrating NMOS tubes according to an embodiment of the present invention.

In the attached figure:

1. Substrate; 2. N-type heavily doped region; 3. N-type lightly doped region; 4. First P-type heavily doped region; 5. First N-type heavily doped region; 6. First gate; 7. Composite insulating layer; 8. First drain metal layer; 9. First source metal lead; 10. Second P-type heavily doped region; 11. Second N-type heavily doped region; 12. Second gate; 13. Second drain metal layer; 14. Second source metal lead; 15. Third P-type heavily doped region; 16. Third N-type heavily doped region; 17. Third gate; 18. Third drain metal layer; 19. The third source metal lead wire; 20. The fourth P-type heavily doped region; 21. The fourth N-type heavily doped region; 22. The fourth gate; 23. The fourth drain metal layer; 24. The fourth source metal lead wire; 25. The first gate metal lead wire; 26. The second gate metal lead wire; 27. The third gate metal lead wire; 28. The fourth gate metal lead wire; 29. The thermally conductive metal body; 30. The external insulating layer; 31. The thermally conductive metal layer; 32. The temperature measuring resistor; 33. The electrical pin; 34. The insulating packaging layer; 35. The bottom metal layer.

Q1, the first NMOS tube; Q2, the second NMOS tube; Q3, the third NMOS tube; Q4, the fourth NMOS tube.

Detailed ways

In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is generally used to include the meaning of "and/or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, the term "proximal end" is generally the end close to the operator, the term "distal end" is generally the end close to the patient, "one end" and "the other end" as well as "proximal end" and "distal end" generally refer to two corresponding parts, which include not only the endpoints, and the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. In addition, as used in the present invention, an element disposed on another element generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the connection, coupling, cooperation or transmission between the two elements may be direct or indirect through an intermediate element, and it cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, one element may be in any orientation such as inside, outside, above, below or on one side of another element, unless otherwise clearly indicated in the content. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

The inventors have found that conventional H-bridge circuits need to integrate several devices, and during use, the heat generated by the MOS tube in a non-ideal switching state will increase sharply, seriously affecting the life of the MOS tube or even directly damaging the MOS tube.

Based on this, the core idea of the present invention is to reduce the use of discrete devices by integrating MOS tubes and freewheeling diodes. At the same time, a temperature measuring resistor is set inside the integrated device, which optimizes the number of devices in the application scenario, reduces the cost and system space occupied, and can monitor the internal temperature of the device.

Specifically, please refer to Figures 1 to 8, which are schematic diagrams of embodiments of the present invention. An H-bridge device structure integrating NMOS transistors includes a substrate 1, a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, and a fourth NMOS transistor Q4, wherein an N-type heavily doped region 2 and an N-type lightly doped region 3 are formed in the substrate 1, wherein the N-type lightly doped region 3 is located on the top of the N-type heavily doped region 2, wherein the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4 are formed in the substrate 1 to form an H-bridge circuit, wherein the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4 share the N-type heavily doped region 2 and the N-type lightly doped region 3, wherein a composite insulating layer 7 is formed on the front side of the substrate 1, wherein the top of the composite insulating layer 7 is covered with a heat conductive metal layer 31, wherein a temperature measuring resistor 32 is formed on the top of the heat conductive metal layer 31, and the bottom surface of the temperature measuring resistor 32 is in contact with the heat conductive metal layer 31.

The NMOS tube is integrated on a substrate to form an H-bridge circuit, which improves the device integration and reduces discrete devices. The temperature measuring resistor 32 is embedded in the front insulating packaging layer 34 of the integrated device, and a thermal conductive metal layer 31 is made under the temperature measuring resistor 32 to connect to the inside of the integrated device. In this way, the temperature measurement is closer to the temperature inside the device, and the measurement is more accurate. In combination with an external temperature acquisition and control circuit, it can monitor the device temperature. If the temperature is over, the internal MOS tube can be shut down in time to avoid thermal damage to the device.

Among them, the first NMOS tube Q1, the second NMOS tube Q2, the third NMOS tube Q3 and the fourth NMOS tube Q4 and the freewheeling diodes D1, D2, D3, and D4 formed in each MOS tube are arranged on the substrate 1, and the constructed H-bridge circuit is shown in Figure 1. It should be noted that no load motor M is set on the substrate 1. In Figure 1, the drain of the first NMOS tube Q1 and the drain of the second NMOS tube Q2 are externally connected to Vbat (load power supply), the load motor M is set between the source of the first NMOS tube Q1 and the source of the second NMOS tube Q2, and the source of the fourth NMOS tube Q4 and the source of the third NMOS tube Q3 are connected to the ground.

In one embodiment, a heat-conducting metal body 29 is further provided at the bottom of the temperature-measuring resistor 32. The top of the heat-conducting metal body 29 penetrates the composite insulating layer 7 and contacts the heat-conducting metal layer 31, and the bottom extends into the N-type lightly doped region 3. The bottom and sidewalls of the heat-conducting metal body 29 are provided with an external insulating layer 30 for isolating the N-type lightly doped region 3 and the composite insulating layer 7. It also includes a bottom metal layer 35 and an insulating packaging layer 34. The insulating packaging layer 34 is arranged around the temperature-measuring resistor 32 to surround and fix the temperature-measuring resistor 32. The bottom metal layer 35 is located at the bottom of the N-type heavily doped region 2 for heat dissipation and conduction. An electrical pin 33 is led out from the temperature-measuring resistor 32, and the electrical pin 33 is located at the top of the insulating packaging layer 34. The insulating packaging layer 34 uses an insulating packaging material to surround and fix the temperature-measuring resistor 32 and protect the entire device.

As shown in FIG6 , a heat-conducting metal body 29 is arranged in the N-type lightly doped region 3, and an external insulating layer 30 is provided on the heat-conducting metal body 29, so that the heat generated by the substrate 1 and the composite insulating layer 7 can be transferred to the temperature measuring resistor 32 via the heat-conducting metal layer 31, and the temperature measuring resistor 32 is connected to an external device, such as a temperature control circuit, through an electrical pin 33 connected to the temperature measuring resistor 32, so that the internal MOS tube can be shut down in time in case of overtemperature to avoid thermal damage to the device.

Specifically, the first NMOS transistor Q1 includes two first P-type heavily doped regions 4, the first P-type heavily doped regions 4 are located at the top of the N-type lightly doped region 3, the first N-type heavily doped regions 5 are formed at the top of the first P-type heavily doped regions 4, the first source metal lead wires 9 are led out from the top of the first N-type heavily doped regions 5, a first gate 6 is arranged in the composite insulating layer 7 between the two first source metal lead wires 9, a gap exists between the bottom of the first gate 6 and the substrate 1, and a first gate metal lead wire 25 is connected to the top of the first gate 6. The first NMOS transistor Q1 also includes a first drain metal layer 8, the first drain metal layer 8 is located at the bottom of the N-type heavily doped region 2, and a gap exists between the first drain metal layer 8 and the bottom metal layer 35.

As shown in FIG2 , the first P-type heavily doped region 4 in the first NMOS transistor Q1 also serves as the P-pole of the freewheeling diode D1, and the first drain metal layer 8 in the first NMOS transistor Q1 also serves as the N-pole metal layer of the freewheeling diode D1, and is connected to the second drain metal layer 13 of the second NMOS transistor Q2. By optimizing the range and P-type doping concentration of the well region of the MOS transistor to serve as the P-pole of the freewheeling diode, and by optimizing the N-type doping concentration and range of the substrate to serve as the N-pole of the freewheeling diode, the optimized MOS transistor body diode has better withstand voltage freewheeling capability than the body diode of the traditional MOS transistor, and can directly replace the traditional external freewheeling diode.

Specifically, the first NMOS transistor Q1 , the second NMOS transistor Q2 , the third NMOS transistor Q3 and the fourth NMOS transistor Q4 have the same structure. It can be understood that, as shown in Figures 3 to 5, the second NMOS tube Q2 also has two second P-type heavily doped regions 10, a second N-type heavily doped region 11 is arranged in the second P-type heavily doped region 10, a second source metal lead 14 is connected to the top of the second N-type heavily doped region 11, a second gate 12 and a second gate metal lead 26 are formed between the second source metal lead 14, and a second drain metal layer 13 is also provided at the N-type heavily doped region 2 on the back side of the second NMOS tube Q2. Similarly, the third NMOS tube Q3 has a third P-type heavily doped region 15, a third N-type heavily doped region 16, a third source metal lead 19, a third gate 17, a third gate metal lead 27 and a third drain metal layer 18; the fourth NMOS tube Q4 has a fourth P-type heavily doped region 20, a fourth N-type heavily doped region 21, a fourth source metal lead 24, a fourth gate 22 and a fourth gate metal lead 28.

It can be understood that the first source metal lead line 9 of the first NMOS tube Q1 is connected to the fourth drain metal layer 23 of the fourth NMOS tube Q4, the first drain metal layer 8 of the first NMOS tube Q1 is interconnected with the second drain metal layer 13 of the second NMOS tube Q2, the second source metal lead line 14 of the second NMOS tube Q2 is connected to the third drain metal layer 18 of the third NMOS tube Q3, and the third source metal lead line 19 of the third NMOS tube Q3 is connected to the fourth source metal lead line 24 of the fourth NMOS tube Q4.

Specifically, the first gate metal lead line 25 of the first NMOS tube Q1 is connected to the first gate control signal G1, the second gate metal lead line 26 of the second NMOS tube Q2 is connected to the second gate control signal G2, the third gate metal lead line 27 of the third NMOS tube Q3 is connected to the third gate control signal G3, and the fourth gate metal lead line 28 of the fourth NMOS tube Q4 is connected to the fourth gate control signal G4.

As shown in Figures 7 and 8, the first NMOS tube Q1, the second NMOS tube Q2, the third NMOS tube Q3 and the fourth NMOS tube Q4 are arranged in a rectangular array. The first NMOS tube Q1, the second NMOS tube Q2, the third NMOS tube Q3 and the fourth NMOS tube Q4 are arranged around the temperature measuring resistor 32. The temperature measuring resistor 32 is located on the top of the substrate 1 and is slightly higher than each NMOS tube, which is helpful for connecting other devices in the subsequent process and expanding the function of the H-bridge device structure. It can be understood that the temperature measuring resistor 32 in Figures 7 and 8 is the same as the temperature measuring resistor 32 in Figure 6. The lower part of the temperature measuring resistor 32 in Figure 8 also has a heat-conducting metal body 29 (not marked), an electrical pin 33 (not shown) and other structures, which will not be repeated here.

The first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3 and the fourth NMOS transistor Q4 are arranged in a 2*2 rectangular array. The temperature measuring resistor 32 is located on the composite insulating layer 7 in the center of the array and receives heat transferred from the substrate 1 through the thermal conductive metal layer 31 and the thermal conductive metal body 29 at the bottom thereof.

The H-bridge device structure of the integrated NMOS tube provided by the present invention combines 4 NMOS tubes and 4 equivalent freewheeling diodes, and at the same time adds a heat-conducting metal area inside the device, and a temperature measuring resistor is embedded in the front package insulation layer of the device. By optimizing the N-type doping concentration and range of the substrate as the N pole of the freewheeling diode, the optimized MOS tube body diode has better voltage resistance and freewheeling ability than the body diode of the traditional MOS tube, and can directly replace the traditional external freewheeling diode. The temperature measuring resistor is embedded in the front package protection layer of the integrated device, and a heat-conducting metal layer is made under the temperature measuring resistor and connected to the inside of the integrated device, so that the temperature measurement is closer to the temperature control inside the device, and the measurement is more accurate. It can monitor the temperature of the device in combination with the external temperature acquisition and control circuit, and the internal MOS tube can be shut down in time in case of overtemperature to avoid thermal damage to the device.

The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims (10)

1. An H-bridge device structure integrating NMOS tubes, characterized in that it comprises a substrate, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube, wherein an N-type heavily doped region and an N-type lightly doped region are formed in the substrate, and the N-type lightly doped region is located on the top of the N-type heavily doped region, and the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are formed in the substrate to form an H-bridge circuit, wherein the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube share the N-type heavily doped region and the N-type lightly doped region, a composite insulating layer is formed on the front side of the substrate, the top of the composite insulating layer is covered with a heat conductive metal layer, a temperature measuring resistor is formed on the top of the heat conductive metal layer, and the bottom surface of the temperature measuring resistor is in contact with the heat conductive metal layer. 2. According to the H-bridge device structure of the integrated NMOS tube in claim 1, it is characterized in that a heat-conducting metal body is also arranged at the bottom of the temperature measuring resistor, the top of the heat-conducting metal body penetrates the composite insulating layer and contacts the heat-conducting metal layer, and the bottom extends into the N-type lightly doped region, and an external insulating layer is arranged at the bottom and side walls of the heat-conducting metal body for isolating the N-type lightly doped region and the composite insulating layer. 3. The H-bridge device structure of the integrated NMOS tube according to claim 2 is characterized in that it also includes a bottom metal layer and an insulating packaging layer, the insulating packaging layer is arranged around the temperature measuring resistor to surround and fix the temperature measuring resistor, the bottom metal layer is located at the bottom of the N-type heavily doped region, and the temperature measuring resistor is led out with an electrical pin, and the electrical pin is located on the top of the insulating packaging layer. 4. The H-bridge device structure of the integrated NMOS tube according to claim 1 is characterized in that the first NMOS tube includes two first P-type heavily doped regions, the first P-type heavily doped region is located on the top of the N-type lightly doped region, a first N-type heavily doped region is formed on the top of the first P-type heavily doped region, a first source metal lead wire is led out from the top of the first N-type heavily doped region, a first gate is arranged in the composite insulating layer between the two first source metal lead wires, a gap is formed between the bottom of the first gate and the substrate, and a first gate metal lead wire is connected to the top of the first gate. 5. The H-bridge device structure of the integrated NMOS tube according to claim 3 is characterized in that the first NMOS tube further includes a first drain metal layer, the first drain metal layer is located at the bottom of the N-type heavily doped region, and there is a gap between the first drain metal layer and the bottom metal layer. 6 . The H-bridge device structure of integrated NMOS tubes according to claim 4 , wherein the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube have the same structure. 7. The H-bridge device structure of integrated NMOS tubes according to claim 6 is characterized in that the first source metal lead-out line of the first NMOS tube is connected to the fourth drain metal layer of the fourth NMOS tube, the first drain metal layer of the first NMOS tube is interconnected with the second drain metal layer of the second NMOS tube, the second source metal lead-out line of the second NMOS tube is connected to the third drain metal layer of the third NMOS tube, and the third source metal lead-out line of the third NMOS tube is connected to the fourth source metal lead-out line of the fourth NMOS tube. 8. The H-bridge device structure of integrated NMOS tubes according to claim 1 is characterized in that the first gate metal lead wire of the first NMOS tube is connected to a first gate control signal, the second gate metal lead wire of the second NMOS tube is connected to a second gate control signal, the third gate metal lead wire of the third NMOS tube is connected to a third gate control signal, and the fourth gate metal lead wire of the fourth NMOS tube is connected to a fourth gate control signal. 9 . The H-bridge device structure of integrated NMOS tubes according to claim 1 , wherein the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are arranged in a rectangular array. 10 . The H-bridge device structure integrating NMOS transistors according to claim 9 , wherein the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are arranged around the temperature measuring resistor.