CN118171023A - Data signal processing method and device, electronic equipment, chip and storage medium - Google Patents
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Abstract
The present disclosure provides a data signal processing method, a device, an electronic apparatus, a chip and a storage medium, wherein current frame data is input into a first-stage processing module, and an intermediate processing result is output after processing, wherein the first-stage processing module comprises a first storage module, a first base four module and a second base four module; the intermediate processing result is input into a second-stage processing module, and the data processing result is output after the intermediate processing result is processed, wherein the second-stage processing module comprises a second storage module, a third base four module, a fourth base four module and a base two module, an FFT (fast Fourier transform) implementation scheme is provided, a 512-point base four-type FFT architecture is adopted, compared with the base two architecture, the data butterfly operation level is reduced, the data throughput rate is improved by using a pipeline structure, the storage module is optimized, resources and power consumption are further optimized greatly, meanwhile, the scheme is completely based on an integrated circuit, and the operation rate is far greater than that of software taking an embedded processor as a core.
Description
Technical Field
The present disclosure relates to the field of information processing, and in particular, to a data signal processing method and apparatus, an electronic device, a chip, and a storage medium.
Background
In complex communication systems, the problem of processing complex and variable data signals is always a crucial component module in the communication system. FFT (Fast Fourier Transform ) is an important means for signal analysis and processing in digital signal processing, which is an indispensable module in communication systems, especially in chip-level implementations and applications. At present, the base two implementation is used as a main implementation of FFT with ultra-long points (above 2048), long points are divided into a plurality of blocks (such as a plurality of 512 point cascading), and then FFT operation among the blocks is completed, wherein an embedded processor (such as an arm processor or an x86 processor) is used as a basis, the FFT is implemented on the basis of software, and a fixed point adder/multiplier is used in the FFT implementation to optimize the loss of resources and improve the running speed.
Disclosure of Invention
The present disclosure provides a data signal processing method, apparatus, electronic device, chip and storage medium, which can improve the data throughput rate, greatly optimize the power consumption of resources, and meanwhile, the scheme design is based on an integrated circuit, and the operation rate is far greater than that of a software implementation using an embedded processor as a core.
An embodiment of a first aspect of the present disclosure proposes a data signal processing method, the method comprising: inputting the current frame data into a first-stage processing module, and outputting an intermediate processing result after processing, wherein the first-stage processing module comprises a first storage module, a first base four module and a second base four module; and inputting the intermediate processing result into a second-stage processing module, and outputting a data processing result after processing, wherein the second-stage processing module comprises a second storage module, a third base four module, a fourth base four module and a base two module.
In some embodiments of the present disclosure, the current frame data includes four input segments, wherein inputting the current frame data into the first stage processing module, and outputting the intermediate processing result after processing includes: sequentially and completely storing four input sections of the current frame data into addresses of corresponding digits in a first storage module; the method comprises the steps of taking current frame data out of a first storage module, and processing the current frame data through a first base four module to obtain a first base four result, wherein the first base four result comprises result sections corresponding to four input sections of the current frame data; processing the first result segment of the first base four result through the second base four module to obtain a first result segment of the second base four result, and simultaneously writing the second result segment, the third result segment and the fourth result segment of the first base four result back to the original address in the first storage module; when the next frame data is written into the address of the first input section for storing the current frame data in the first storage module, the second result section of the first base four result is processed through the second base four module to obtain the second result section of the second base four result until the first base four result is completely processed through the second base four module to obtain the second base four result as an intermediate processing result.
In some embodiments of the present disclosure, processing by the first base four module includes: and writing the first input section of the next frame data into the first storage module, and processing four input sections of the current frame data through the first base four module.
In some embodiments of the present disclosure, the number of acquisition points of the current frame data is 512, the first input segment of the current frame data is 0-127 th symbol, the second input segment is 128-255 th symbol, the third input segment is 256-383 th symbol, and the fourth input segment is 384-511 th symbol.
In some embodiments of the present disclosure, inputting the intermediate processing result into the second stage processing module, and outputting the data processing result after processing includes: writing the second base four result into the address of the corresponding bit number in the second storage module; reading the second base four result from the second storage module while writing the second base four result into the second storage module, and processing the second base four result by a third base four module to obtain a third base four result; and sequentially processing the third base four result through a fourth base four module and a base two module to obtain a data processing result.
In some embodiments of the present disclosure, reading the second base four result from the second memory module while writing the second base four result to the second memory module and processing by the third base four module to obtain a third base four result comprises: writing a first result segment of the second base four result into an address after the second storage module, and writing a second result segment of the second base four result; reading a first result segment of the second base four result from the second storage module while writing the second result segment of the second base four result into the second storage module, and processing the first result segment of the second base four result through the third base four module to obtain four result segments of the third base four result; and when the third result segment of the second base four result is written into the second storage module, reading the second result segment of the second base four result from the second storage module, and processing the second result segment of the second base four result through the third base four module until the second base four result is completely processed through the third base four module.
In some embodiments of the present disclosure, sequentially processing, by the fourth base four module and the base two module, the third base four result to obtain a data processing result includes: processing the first parts of the four result sections of the third base four results respectively through a fourth base four module, and writing the second parts of the four result sections of the third base four results back to the original addresses in the second storage module respectively; sequentially reading second parts of four result segments of the third base four result from the second storage module respectively, and processing the second parts through the fourth base four module; and inputting a fourth base four result obtained by processing the third base four result by the fourth base four module into the base two module, and processing the fourth base four result to obtain a data processing result.
An embodiment of a second aspect of the present disclosure proposes a data signal processing apparatus, the apparatus comprising: the first-stage processing unit is used for inputting the current frame data into the first-stage processing module and outputting an intermediate processing result after processing, wherein the first-stage processing module comprises a first storage module, a first base four module and a second base four module; the secondary processing unit is used for inputting the intermediate processing result into the secondary processing module and outputting the data processing result after processing, wherein the secondary processing module comprises a second storage module, a third base four module, a fourth base four module and a base two module.
An embodiment of a third aspect of the present disclosure proposes a communication device, including: a transceiver; a memory; and a processor, respectively connected with the transceiver and the memory, configured to control wireless signal transceiving of the transceiver by executing computer executable instructions on the memory, and capable of realizing the method described in the embodiment of the first aspect of the disclosure.
An embodiment of a fourth aspect of the present disclosure proposes a computer storage medium, in which computer-executable instructions are stored; the computer-executable instructions, when executed by the processor, enable the implementation of the method described in embodiments of the first aspect of the present disclosure.
A fifth aspect embodiment of the present disclosure proposes a chip comprising one or more interface circuits and one or more processors; the interface circuit is for receiving a signal from a memory of the electronic device and sending the signal to the processor, the signal comprising computer instructions stored in the memory, which when executed by the processor, cause the electronic device to perform the method described in the embodiments of the first aspect of the disclosure.
In summary, in the data signal processing method provided by the present disclosure, current frame data is input into a first stage processing module, and an intermediate processing result is output after the processing, where the first stage processing module includes a first storage module, a first base four module and a second base four module; the intermediate processing result is input into the second-stage processing module, and the data processing result is output after the processing, wherein the second-stage processing module comprises a second storage module, a third base four module, a fourth base four module and a base two module, so that the data throughput rate can be improved, the power consumption of resources is greatly optimized, meanwhile, the scheme design is based on an integrated circuit, and the running rate is far greater than that of software taking an embedded processor as a core.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure and do not constitute an undue limitation on the disclosure.
Fig. 1 is a schematic view of an application scenario provided in an embodiment of the present disclosure;
fig. 2 is a flowchart of a data signal processing method according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a data signal processing method according to an embodiment of the disclosure;
fig. 4 is an implementation block diagram of a radix-four FFT theoretical butterfly graph provided in an embodiment of the present disclosure;
fig. 5 is a flowchart of a data signal processing method according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of a scheme of a data signal processing method according to an embodiment of the disclosure;
Fig. 7 is a first level radix-four butterfly diagram provided in an embodiment of the disclosure;
fig. 8 is a second-stage radix-four butterfly diagram provided in an embodiment of the disclosure;
Fig. 9 is a third-stage radix-four butterfly diagram provided in an embodiment of the disclosure;
Fig. 10 is a fourth-stage radix-four butterfly diagram provided in an embodiment of the disclosure;
FIG. 11 is a radix-two butterfly diagram provided in an embodiment of the disclosure;
FIG. 12 is a detailed view of the operation of the 0 th-127 th symbol RAM0 provided by embodiments of the present disclosure;
FIG. 13 is a timing diagram of the operation of the 0 th-127 th symbol RAM0 according to one embodiment of the present disclosure;
FIG. 14 is a data flow diagram of a first and second level base four provided by an embodiment of the present disclosure;
FIG. 15 is a detailed view of the operation of the 128-159 th symbol RAM1 provided by embodiments of the present disclosure;
FIG. 16 is a timing diagram of the operation of the 128-159 th symbol RAM1 provided by an embodiment of the present disclosure;
FIG. 17 is a data flow diagram of a third fourth base four and base two provided by an embodiment of the present disclosure;
Fig. 18 is a schematic structural diagram of a data signal processing apparatus according to an embodiment of the disclosure;
fig. 19 is a schematic structural diagram of a communication device according to an embodiment of the present disclosure;
fig. 20 is a schematic structural diagram of a chip according to an embodiment of the disclosure.
Detailed Description
Embodiments of the present disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended for the purpose of explaining the present disclosure and are not to be construed as limiting the present disclosure.
In complex communication systems, the problem of processing complex and variable data signals is always a crucial component module in the communication system. The core of the method is the analysis and processing of signals in the fields of 4G/5G communication, artificial intelligence, IOT, big data, and the like, especially in the fields of industrial detection and the like, and the signal processing under the superposition of a plurality of complex environments. With the development of integrated circuits, chips are used as a high-precision instrument, and after the chips are integrated with information processing, the chips have wider application scenes, which means that the information processing at the chip level is faced with more complex application scenes and more stringent energy indexes.
At present, the base two implementation is used as the main implementation of the FFT with ultra-long points (more than 2048), the long points are mainly divided into a plurality of blocks (such as a plurality of 512 point cascade), and then the FFT operation among the blocks is completed. And a fixed point number adder/multiplier is used in FFT implementation, so that the loss of resources is optimized and the running speed is improved. The FFT is implemented on an embedded processor (e.g., an arm processor or an x86 processor) basis with software as a core. In the existing FFT implementation scheme, the throughput of data is smaller, the power consumption optimization amplitude of resources is smaller, and the running rate is still lower.
In order to solve the problems in the related art, the present disclosure provides a data signal processing method, and the present disclosure provides an FFT implementation scheme, which can improve the data throughput rate, and greatly optimize the power consumption of resources, and meanwhile, the scheme design is based on an integrated circuit, and the running rate is far greater than that of a software implementation using an embedded processor as a core.
Before introducing the detailed scheme of the present disclosure, a description is given of a scenario to which the scheme of the present disclosure is applied. Fig. 1 is an application scenario diagram of a data signal processing method in one embodiment. The present disclosure is mainly applied to digital signal processing in a communication system, as shown in fig. 1, taking a receiving end in wireless communication as an example, after receiving a signal, the receiving end needs to perform operations such as corresponding modulation and demodulation or equalization on the received signal in a digital domain after receiving the signal by using an ADC (Analog to Digital Converter, analog-to-digital converter), and such operations are complex to understand in a time domain, so that a fourier tool is required to convert the time domain signal into a frequency domain signal, and then analyze and process the time domain signal.
It should be appreciated that the foregoing is an example of a main application scenario of the present solution, and is not limited to applications of the present solution in other fields besides communication systems.
Fig. 2 is a flowchart of a data signal processing method according to an embodiment of the present disclosure. As shown in fig. 2, the data signal processing method includes steps S101-102. For ease of understanding, fig. 3 shows a schematic diagram of a data signal processing method.
S101, inputting the current frame data into a first-stage processing module, and outputting an intermediate processing result after processing.
The first-stage processing module comprises a first storage module, a first base four module and a second base four module.
S102, inputting the intermediate processing result into a second stage processing module, and outputting a data processing result after processing.
The second-stage processing module comprises a second storage module, a third base four module, a fourth base four module and a base two module.
In the present disclosure, the acquired data signal is processed, and the current frame data refers to a frame of data currently being processed, and is described differently from the previous frame of data and the next frame of data.
In the present disclosure, the first storage module and the second storage module are modules for storing data signals in the system, and RAM (Random Access Memory ) may be used for storing frame data and processing results. The first base four module, the second base four module, the third base four module and the fourth base four module are used for executing FFT algorithm based on the base four scheme. The radix-two module is used for executing a radix-two FFT algorithm.
In one embodiment of the disclosure, as shown in fig. 3, a structural block diagram of an entire system is shown, which includes two RAMs, RAM0 is used as a first storage module, RAM1 is used as a second storage module, and the RAM includes 4 base four modules S1-S4 respectively including a first base four module, a second base four module, a third base four module and a fourth base four module, and further includes 1 base two module S5, where RAM0, S1, S2 are first stage processing modules, and RAM1, S3, S4, S5 are second stage processing modules.
In one embodiment of the present disclosure, a theoretical formula for radix-four can be obtained according to the theoretical principle of FFT, as follows:
Wherein N is the number of points of the time domain discrete signals, N is the number of the time domain discrete signals (the value range is 0-N-1), m is the number of the frequency domain signals (the value range is O-N-1), the number of points of the frequency domain signals is also N, Is butterfly coefficient
It should be understood that the present scheme is mainly applied to transforming a time domain signal into a frequency domain signal using a fourier tool, and the essence of the FFT algorithm is to divide a long sequence of DFT (Discrete Fourier Transform ) computation into a shorter sequence of DFT computation, where the basic four FFT is divided by a division method that can be divided into 4 points of DFT, where the input of DFT is N discrete points (time domain signal) and output is N discrete points (frequency domain signal, each point of the frequency domain signal is represented by a complex number).
According to the theoretical formula, the implementation manner of the theoretical butterfly graph can be obtained, as shown in fig. 4, each basic four module comprises four inputs, and is divided into three parts, wherein the first two parts are summation units of butterfly operation, the third part is a complex part of butterfly operation, and the basic four modules input four data at one time, so that four results are calculated at one time.
It should be noted that, in the present embodiment, based on the base four scheme, 4 base four modules and 1 base two modules are divided into two stages of processing modules, so that the fourier computation can calculate the corresponding complex frequency domain result faster with fewer stages, and the FFT computation formula in the above embodiment is taken as an example, and other base four formulas based on the theoretical principle of FFT can be used, which is not limited.
In the embodiment of the disclosure, based on the two-stage processing modules, the RAM is utilized to dynamically allocate data, so that the results of the first-stage base four module and the second-stage base four module and the results of the third-stage base four module, the fourth-stage base four module and the fifth-stage base two module can be calculated at one time, the resource loss is reduced, and the FFT calculation process is accelerated.
In summary, according to the data signal processing method provided by the disclosure, current frame data is input into a first-stage processing module, and an intermediate processing result is output after processing, wherein the first-stage processing module comprises a first storage module, a first base four module and a second base four module; the intermediate processing result is input into a second-stage processing module, and the data processing result is output after the processing, wherein the second-stage processing module comprises a second storage module, a third base four module, a fourth base four module and a base two module, an FFT (fast Fourier transform) implementation scheme is provided, the corresponding complex frequency domain result can be calculated more quickly by Fourier calculation with fewer stages, the resource loss is reduced, and the FFT calculation process is quickened.
Based on the embodiment shown in fig. 2, fig. 5 further shows a detailed flowchart of a data signal processing method proposed by the present disclosure. Based on the embodiment shown in fig. 2, fig. 5 includes the following steps.
Steps S201 to S204 are further disclosed for inputting the current frame data into the first stage processing module in step S101, and outputting the intermediate processing result after processing. Step S205-SS207 is further disclosed for inputting the intermediate processing result to the second stage processing module in step S102, and outputting the data processing result after processing.
The first-stage processing module comprises a first storage module, a first base four module and a second base four module. The second-stage processing module comprises a second storage module, a third base four module, a fourth base four module and a base two module.
In the embodiment of the present disclosure, as shown in fig. 3, the first memory module and the second memory module use RAM, RAM0 as the first memory module, and RAM1 as the second memory module. S1-S4 are respectively a first base four module, a second base four module, a third base four module and a fourth base four module. RAM0, S1, S2 are first stage processing modules, and RAM1, S3, S4, S5 are second stage processing modules.
Wherein the current frame data includes four input segments.
In an embodiment of the present disclosure, the first base four module, the second base four module, the third base four module, and the fourth base four module are configured to perform an FFT algorithm based on a base four scheme. The theoretical formula of the base four architecture shown in fig. 4 is adopted in the base four model, and in particular, referring to the embodiment shown in fig. 2, the disclosure will not be repeated. Each base four module comprises four inputs, so that the current frame data is divided into four input segments, and the corresponding four result segments can be obtained by processing the input base four modules.
In some embodiments of the present disclosure, the number of acquisition points of the current frame data is 512, the first input segment of the current frame data is 0-127 th symbol, the second input segment is 128-255 th symbol, the third input segment is 256-383 th symbol, and the fourth input segment is 384-511 th symbol.
It should be noted that, the embodiment of the present disclosure adopts the architecture shown in fig. 3, and the theoretical formulas of the first base four module, the second base four module, the third base four module and the fourth base four module adopt the following base four architecture:
Wherein N is the number of points of the time domain discrete signals, N is the number of the time domain discrete signals (the value range is 0-N-1), m is the number of the frequency domain signals (the value range is O-N-1), the number of points of the frequency domain signals is also N, Is butterfly coefficient
In the embodiment of the present disclosure, the number of collection points of the current frame data is 512, that is, N in the formula is 512, which is taken as an example, and the scheme of the present disclosure is described in detail, but other embodiments of the present disclosure are not limited thereto.
S201, sequentially storing all four input segments of the current frame data into addresses of corresponding digits in the first storage module.
In the embodiment of the present disclosure, the acquisition point number of the current frame data is 512, and as shown in fig. 6, a simplified operation diagram of RAM0 and RAM1 is shown. Wherein the first frame data refers to the current frame data and the second frame data refers to the next frame data. First, the first input segment, the second input segment, the third input segment, and the fourth input segment, namely, the 0 th to 511 th symbols of the current frame are all stored in the 0 th to 511 th addresses of the RAM 0.
S202, the current frame data is taken out from the first storage module and is processed through the first base four module, so that a first base four result is obtained.
Wherein the first base four results include result segments corresponding to four input segments of the current frame data.
In an embodiment of the present disclosure, a general butterfly diagram architecture of 512-point FFT radix-four may be obtained according to the theoretical formula of the radix-four architecture shown in fig. 4, fig. 7 shows a first-stage radix-four butterfly diagram, four input segments of current frame data are input, corresponding to X [0:127], X [128:255], X [256:383] and X [383:511] shown in fig. 7, to obtain a first radix-four result, where the first radix-four result includes result segments X 1[0:127]、X1[128:255]、X1 [256:383] and X 1 [383:511] corresponding to the four input segments of the current frame data.
In some embodiments of the present disclosure, processing by the first base four module includes: and writing the first input section of the next frame data into the first storage module, and processing four input sections of the current frame data through the first base four module.
In the embodiment of the present disclosure, as shown in fig. 6, 128 data input in the first input segment 0-127 symbols of the next frame data are written into the addresses 511-639 of the RAM0, and at the same time, the four input segments of the current frame data, that is, the 0-511 data in the current RAM0, all complete the first level base four processing by the first base four module, as shown in fig. 7, and the first base four result is obtained.
S203, processing the first result segment of the first base four result through the second base four module to obtain the first result segment of the second base four result, and simultaneously writing the second result segment, the third result segment and the fourth result segment of the first base four result back to the original address in the first storage module.
In the embodiment of the disclosure, the X 1 [0:127] in the output result of the first base four is sorted, the butterfly diagram of the second base four is shown in fig. 8, and as shown in fig. 6, the first result segment X 2 [0:31] of the second base four result can be obtained by processing the data of the first result segment X1[0:127] of the first base four result by the second base four module. At the same time, the second, third and fourth result segments, i.e., the 128-511 data original addresses, in the results of the first level base four are written back to RAM0, as shown in FIG. 6, in the 127-511 addresses of RAM 0.
And S204, when the next frame data is written into the address of the first input section for storing the current frame data in the first storage module, processing the second result section of the first base four result through the second base four module to obtain a second result section of the second base four result until the first base four result is completely processed through the second base four module, and obtaining the second base four result as an intermediate processing result.
In the embodiment of the present disclosure, referring to fig. 6 and 8, the data inputted in the second input segment of the next frame data, i.e., the 128-255 symbol, is written into the 0-127 address of RAM0, and at the same time, the second result segment of the first base four stored in the 128-255 address of RAM0 is read out, and processed by the second base four module, to obtain the second result segment X 2 [32:63] of the second base four result.
Similarly, the data input in the third input segment of the next frame data, namely 255-383 symbols, is written into the 128-255 addresses of the RAM0, and simultaneously the third result segment of the first-level base four stored in the 255-383 addresses of the RAM0 is read out and processed by the second-level base four module to obtain the third result segment X 2 [64:95] of the second-level base four result.
The fourth input segment of the next frame data, i.e. the data input in 383-511 symbols, is written into 255-383 addresses of RAM0, and at the same time the second result segment of the first-level base four stored in 383-511 addresses of RAM0 is read out and processed by the second-level base four module to obtain the fourth result segment X 2 [96:127] of the second-level base four result.
Finally, the first base four results are all processed through the second base four module, and the second base four results are obtained as intermediate processing results.
In the embodiment of the present disclosure, as shown in fig. 12, a detailed diagram of RAM0 read/write in 0-127 symbols is shown, and since the first input segment of the current frame, i.e., the 0-127 data read from RAM0, needs to calculate the primary base four and the secondary base four at a time, the order of reading RAM0 per path is a skip order.
Specifically, for the skip RAM0 read mode in which the first level base four and the second level base four need to be calculated once for the 0-127 data in fig. 13, fig. 14 provides Xu Tu for this mode, the first addresses of 0, 128, 256 and 384 of RAM0 are read, and the second clock rising edge reads the addresses of 32, 160, 288 and 416 of RAM0, so that the first level base four and the second level base four of the RAM1 are sequentially and circularly read 128 symbols and the first level base four and the second level base four of the 0-127 data are calculated. At the same time, the newly input data will be stored in 512 th-639 th addresses of RAM0 of FIG. 13 in this segment of symbols as starting point, then in each segment of symbols (128-255, 256-383, 384-511), the 0-127, 128-255 and 256-383 addresses of RAM0 will be emptied in turn, and the input data will be stored in these addresses in turn, and the new data calculation will be started after the current data calculation is completed.
FIG. 15 shows a data flow diagram of the first level base four and the second level base four within 0-127 symbols according to the timing diagram of FIG. 14. Firstly, the first-stage base four calculates the result according to the specific data flow, and when the corresponding result is obtained, the data belonging to the [127:0] section immediately carries out the second-stage base four calculation, and the calculated result is stored in the RAM 1. While other results for the first level base four store the source address back into RAM 0. In addition, the results of the first level base four stored in RAM0 will be read out sequentially and passed through the second level base four in 128-511 symbols.
According to the scheme, the RAM is utilized to dynamically allocate data in the operation process, so that the results of the first-stage base four module and the second-stage base four module can be calculated at one time, the resource loss is reduced, and the FFT calculation process is quickened.
S205, writing the second base four result into the address of the corresponding bit number in the second storage module.
In the embodiment of the disclosure, in the 0-127 symbol, as can be seen from fig. 14, the first level second level base four completes the calculation of [127:0] data, and the second base four result X 2 [127:0] is written into the RAM1, in the 128-159 symbol, as shown in fig. 15, the data stored in the RAM1 is read out, and the operations of the third level base four, the fourth level base four and the base two are performed by the third level base four, the fourth level base four and the base two modules through the following steps.
S206, reading the second base four result from the second storage module while writing the second base four result into the second storage module, and processing the second base four result through the third base four module to obtain a third base four result.
In some embodiments of the present disclosure, reading the second base four result from the second memory module while writing the second base four result to the second memory module and processing by the third base four module to obtain a third base four result comprises: writing a first result segment of the second base four result into an address after the second storage module, and writing a second result segment of the second base four result; reading a first result segment of the second base four result from the second storage module while writing the second result segment of the second base four result into the second storage module, and processing the first result segment of the second base four result through the third base four module to obtain four result segments of the third base four result; and when the third result segment of the second base four result is written into the second storage module, reading the second result segment of the second base four result from the second storage module, and processing the second result segment of the second base four result through the third base four module until the second base four result is completely processed through the third base four module.
In an embodiment of the present disclosure, the first result segment X 2 [0:31] of the second base four result is written into the 128-159 address of RAM1, while the second result segment X 2 [32:63] of the second base four result is written into RAM1, at the same time, the first result segment of the second base four result is read from the 128-159 address of RAM1 and processed by the third base four module, as shown in FIG. 9, which illustrates a third base four butterfly graph, four result segments X 3[0:7]、X3[8:15]、X3 [16:23] of the third base four can be obtained, and X 3 [24:31], after which 8-31 segments of data writing the source address back into RAM1,0-7 segments of data will perform the processing of the fourth base four and base two modules.
Similarly, when the third result X 2 [32:63] of the second base four result is written to RAM1, and at the same time, the second result segment X 2 [32:63] of the second base four result is read from RAM1 and processed by the third base four module, four result segments X 3[32:39]、X3[40:47]、X3 [48:55] and X 3 [56:63] of the third base four result can be obtained, after which 40-63 segments of data write the source address back to RAM1, and 32-39 segments of data will perform the processing of the fourth base four and base two modules. The third result segment and the fourth result segment of the second base four are processed in the same way, after that, 73-95, 104-127 segments of data source addresses are written back to the RAM1, and 64-71, 96-103 segments of data are processed by the fourth base four and base two modules.
It will be appreciated that in the above procedure, newly entered data will be stored in the 128-159 addresses of RAM1, and the 0-7, 32-39, 64-71, 96-103 segment addresses of RAM1 will be cleared for storing the next segment of entered data.
S207, sequentially processing the third base four result by the fourth base four module and the base two module to obtain a data processing result
In some embodiments of the present disclosure, sequentially processing, by the fourth base four module and the base two module, the third base four result to obtain a data processing result includes: processing the first parts of the four result sections of the third base four results respectively through a fourth base four module, and writing the second parts of the four result sections of the third base four results back to the original addresses in the second storage module respectively; sequentially reading second parts of four result segments of the third base four result from the second storage module respectively, and processing the second parts through the fourth base four module; and inputting a fourth base four result obtained by processing the third base four result by the fourth base four module into the base two module, and processing the fourth base four result to obtain a data processing result.
In the embodiment of the disclosure, taking the fourth processing of the first part of the first result segment of the third base four as an example, as shown in fig. 11, a fourth-stage base four butterfly graph is shown, four result segments of the corresponding fourth base four result can be obtained, and similarly, as shown in fig. 15, through a fourth base four module, the first result segments 0-7, 32-39, 64-71, 96-103 in the four result segments X 3 of the third base four are sequentially processed respectively, 8-31, 40-63, 73-95, 104-127 segments of data write the source address back to RAM1, taking the fourth base four processing of 0-7 segments as an example, input X 3[0:1]、X3[2:3]、X3 [4:5] and X 3 [6:7] can obtain the result X 4[0:1]、X4[2:3]、X4 [4:5] and X 4 [6:7], the rest 2-7 segments of data are sequentially processed after the first segment data are sequentially retained, and the base two processing of 0-1 segments as an example is performed, as shown in fig. 12, and the fourth base four butterfly graph can be sequentially processed according to the fourth base four processing of the fourth base four result segments, and the fourth base four butterfly graph can be performed according to the fourth base four processing of the fourth base four stages of the fourth base four, and the fourth base four processing of the fourth base four can be obtained.
In the embodiment of the present disclosure, similar to the one-time execution of the first base four and the second base four, the one-time execution of the operations of the third base four, the fourth base four, and the second base four also requires specific operations for the data reading sequence of the RAM1, and fig. 16 is a drawing of the 128-159 symbol RAM1 operation timing chart. As shown in fig. 16, the third-level base four module, the fourth-level base four module and the base two module complete the calculation of the data of 0-7, 32-38, 64-70, 96-102 of 512 points of the current frame and output the same within 129-159 symbols. According to fig. 17, a data flow chart of 128-159 symbols can be obtained, as shown in fig. 17, in the above steps S206 and S207, first, all data are fetched from the RAM1, then, a third-stage radix-four operation is performed, the data which are not written back (such as the above first result segment) will immediately perform a fourth-stage radix-four and radix-two operation, after completion, the data are directly output, part of the data in the operation result (such as the above remaining result segments) are written back by the source address, and the written back data will be read out within the next 32 symbols of the next segment, thus completing the fourth-stage radix-four and radix-two operation, and further completing the whole 512-point FFT operation.
According to the scheme, the RAM is utilized to dynamically allocate data in the operation process, so that the results of the third-level base four module, the fourth-level base four module and the base two module can be calculated at one time, the resource loss is reduced, and the FFT calculation process is quickened.
In summary, in the data signal processing method provided by the present disclosure, current frame data is input into a first stage processing module, and an intermediate processing result is output after the processing, where the first stage processing module includes a first storage module, a first base four module and a second base four module; the intermediate processing result is input into a second-stage processing module, and the data processing result is output after the processing, wherein the second-stage processing module comprises a second storage module, a third base four module, a fourth base four module and a base two module, the base four scheme is used as a base four scheme, a 512-point FFT scheme is provided, compared with the base two architecture, the data butterfly operation level is reduced, the data throughput rate is improved by using a pipeline structure, the optimal use of RAM is realized, the resources and the power consumption are further greatly optimized, meanwhile, the scheme is completely based on an integrated circuit, and the operation rate is far greater than that of software taking an embedded processor as a core.
Therefore, the present disclosure has the following beneficial effects:
1. Based on the base four scheme, a 512-point FFT scheme is provided, 4 base four modules and 1 base two modules are consumed altogether, the scheme is divided into two stages, wherein the first and second base four modules are combined into one stage, the third and fourth base four modules and the fifth base two modules are combined into one stage, and the Fourier calculation can calculate the corresponding complex frequency domain result faster by fewer stages.
2. The RAM is utilized to carry out dynamic allocation operation of data, so that the result of the first-stage base four module and the second-stage base four module and the result of the third-stage base four module, the fourth-stage base four module and the fifth-stage base two module can be calculated at one time, the resource loss is reduced, and the FFT calculation process is quickened.
3. By utilizing the dynamic read-write operation of the RAM, a continuous pipeline mode is realized among 512 points of each frame, among modules and inside each module, and the problem of low throughput rate of FFT (fast Fourier transform) when processing data is solved.
4. Based entirely on integrated circuits, the operating speed is much greater than for software implementations with embedded processors as cores.
Fig. 18 is a schematic structural diagram of a data signal processing apparatus 300 according to an embodiment of the disclosure. As shown in fig. 18, the data signal processing apparatus includes: the first-stage processing unit 310 is configured to input the current frame data into a first-stage processing module, and output an intermediate processing result after processing, where the first-stage processing module includes a first storage module, a first base four module, and a second base four module; the secondary processing unit 320 is configured to input the intermediate processing result to the secondary processing module, and output the data processing result after processing, where the secondary processing module includes a second storage module, a third base four module, a fourth base four module, and a base two module.
In some embodiments, the current frame data includes four input segments, wherein the primary processing unit 310 is specifically configured to: sequentially and completely storing four input sections of the current frame data into addresses of corresponding digits in a first storage module; the method comprises the steps of taking current frame data out of a first storage module, and processing the current frame data through a first base four module to obtain a first base four result, wherein the first base four result comprises result sections corresponding to four input sections of the current frame data; processing the first result segment of the first base four result through the second base four module to obtain a first result segment of the second base four result, and simultaneously writing the second result segment, the third result segment and the fourth result segment of the first base four result back to the original address in the first storage module; when the next frame data is written into the address of the first input section for storing the current frame data in the first storage module, the second result section of the first base four result is processed through the second base four module to obtain the second result section of the second base four result until the first base four result is completely processed through the second base four module to obtain the second base four result as an intermediate processing result.
In some embodiments, processing by the first base four module includes: and writing the first input section of the next frame data into the first storage module, and processing four input sections of the current frame data through the first base four module.
In some embodiments, the number of acquisition points of the current frame data is 512, the first input segment of the current frame data is 0-127 th symbol, the second input segment is 128-255 th symbol, the third input segment is 256-383 th symbol, and the fourth input segment is 384-511 th symbol.
In some embodiments, the secondary processing unit 320 is specifically configured to: writing the second base four result into the address of the corresponding bit number in the second storage module; reading the second base four result from the second storage module while writing the second base four result into the second storage module, and processing the second base four result by a third base four module to obtain a third base four result; and sequentially processing the third base four result through a fourth base four module and a base two module to obtain a data processing result.
In some embodiments, reading the second base four result from the second memory module while writing the second base four result to the second memory module and processing by the third base four module to obtain a third base four result comprises: writing a first result segment of the second base four result into an address after the second storage module, and writing a second result segment of the second base four result; reading a first result segment of the second base four result from the second storage module while writing the second result segment of the second base four result into the second storage module, and processing the first result segment of the second base four result through the third base four module to obtain four result segments of the third base four result; and when the third result segment of the second base four result is written into the second storage module, reading the second result segment of the second base four result from the second storage module, and processing the second result segment of the second base four result through the third base four module until the second base four result is completely processed through the third base four module.
In some embodiments, sequentially processing the third base four result by the fourth base four module and the base two module to obtain a data processing result comprises: processing the first parts of the four result sections of the third base four results respectively through a fourth base four module, and writing the second parts of the four result sections of the third base four results back to the original addresses in the second storage module respectively; sequentially reading second parts of four result segments of the third base four result from the second storage module respectively, and processing the second parts through the fourth base four module; and inputting a fourth base four result obtained by processing the third base four result by the fourth base four module into the base two module, and processing the fourth base four result to obtain a data processing result.
Since the apparatus provided by the embodiments of the present disclosure corresponds to the methods provided by the above-described several embodiments, implementation manners of the methods are also applicable to the apparatus provided by the present embodiment, and will not be described in detail in the present embodiment.
In summary, according to the data signal processing device provided by the present disclosure, current frame data is input into a first-stage processing module, and an intermediate processing result is output after processing, where the first-stage processing module includes a first storage module, a first base four module and a second base four module; the intermediate processing result is input into a second-stage processing module, and the data processing result is output after the processing, wherein the second-stage processing module comprises a second storage module, a third base four module, a fourth base four module and a base two module, an FFT (fast Fourier transform) implementation scheme is provided, the corresponding complex frequency domain result can be calculated more quickly by Fourier calculation with fewer stages, the resource loss is reduced, and the FFT calculation process is quickened.
In the embodiment provided by the application, the method and the device provided by the embodiment of the application are introduced. In order to implement the functions in the method provided by the embodiment of the present application, the electronic device may include a hardware structure, a software module, and implement the functions in the form of a hardware structure, a software module, or a hardware structure plus a software module. Some of the functions described above may be implemented in a hardware structure, a software module, or a combination of a hardware structure and a software module.
The embodiment of the application also provides a communication system, which comprises the data signal processing device shown in the embodiment of fig. 18 and used for executing the data signal processing method shown in the embodiments of fig. 2 and 5.
Referring to fig. 19, fig. 19 is a schematic structural diagram of a communication device 400 according to an embodiment of the present application. The communication device 400 may be a network device, a user device, a chip system, a processor or the like that supports the network device to implement the above method, or a chip, a chip system, a processor or the like that supports the user device to implement the above method. The device can be used for realizing the method described in the method embodiment, and can be particularly referred to the description in the method embodiment.
The communication device 400 may include one or more processors 401. The processor 401 may be a general purpose processor or a special purpose processor or the like. For example, a baseband processor or a central processing unit. The baseband processor may be used to process communication protocols and communication data, and the central processor may be used to control communication devices (e.g., base stations, baseband chips, terminal devices, terminal device chips, DUs or CUs, etc.), execute computer programs, and process data of the computer programs.
Optionally, the communication device 400 may further include one or more memories 402, on which a computer program 404 may be stored, and the processor 401 executes the computer program 404, so that the communication device 400 performs the method described in the above method embodiments. Optionally, the memory 402 may also have data stored therein. The communication device 400 and the memory 402 may be provided separately or may be integrated.
Optionally, the communication device 400 may further comprise a transceiver 405, an antenna 406. The transceiver 405 may be referred to as a transceiver unit, a transceiver circuit, or the like, for implementing a transceiver function. The transceiver 405 may include a receiver, which may be referred to as a receiver or a receiving circuit, etc., for implementing a receiving function, and a transmitter; the transmitter may be referred to as a transmitter or a transmitting circuit, etc., for implementing a transmitting function.
Optionally, one or more interface circuits 404 may also be included in the communication device 400. The interface circuit 404 is used to receive code instructions and transmit them to the processor 401. The processor 401 runs code instructions to cause the communication device 400 to perform the method described in the above method embodiments.
In one implementation, a transceiver for implementing the receive and transmit functions may be included in the processor 401. For example, the transceiver may be a transceiver circuit, or an interface circuit. The transceiver circuitry, interface or interface circuitry for implementing the receive and transmit functions may be separate or may be integrated. The transceiver circuit, interface or interface circuit may be used for reading and writing codes/data, or the transceiver circuit, interface or interface circuit may be used for transmitting or transferring signals.
In one implementation, the processor 401 may store a computer program 403, and the computer program 403 runs on the processor 401, which may cause the communication device 400 to perform the method described in the above method embodiment. The computer program 403 may be solidified in the processor 401, in which case the processor 401 may be implemented in hardware.
In one implementation, the communication device 400 may include circuitry that may implement the functions of transmitting or receiving or communicating in the foregoing method embodiments. The processors and transceivers described in this application may be implemented on integrated circuits (INTEGRATED CIRCUIT, ICs), analog ICs, radio frequency integrated circuits RFICs, mixed signal ICs, application SPECIFIC INTEGRATED Circuits (ASICs), printed Circuit boards (Printed Circuit Board, PCBs), electronic devices, and the like. The processor and transceiver may also be fabricated using a variety of IC process technologies such as complementary metal Oxide Semiconductor (Complementary Metal Oxide Semiconductor, CMOS), N-type metal Oxide Semiconductor (NMOS), P-type metal Oxide Semiconductor (PMOS), bipolar junction transistor (Bipolar Junction Transistor, BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.
The communication device described in the above embodiment may be a network device or a user device, but the scope of the communication device described in the present application is not limited thereto, and the structure of the communication device may not be limited by fig. 11. The communication device may be a stand-alone device or may be part of a larger device. For example, the communication device may be:
(1) A stand-alone integrated circuit IC, or chip, or a system-on-a-chip or subsystem;
(2) A set of one or more ICs, optionally including storage means for storing data, a computer program;
(3) An ASIC, such as a Modem (Modem);
(4) Modules that may be embedded within other devices;
(5) A receiver, a terminal device, an intelligent terminal device, a cellular phone, a wireless device, a handset, a mobile unit, a vehicle-mounted device, a network device, a cloud device, an artificial intelligent device, and the like;
(6) Others, and so on.
For the case where the communication device may be a chip or a chip system, reference may be made to the schematic structural diagram of the chip shown in fig. 20. The chip shown in fig. 20 includes a processor 501 and an interface 502. Wherein the number of processors 501 may be one or more, and the number of interfaces 502 may be a plurality.
Optionally, the chip further comprises a memory 503, the memory 503 being used for storing the necessary computer programs and data.
Those of skill in the art will further appreciate that the various illustrative logical blocks (illustrative logical block) and steps (steps) described in connection with the embodiments of the application may be implemented by electronic hardware, computer software, or combinations of both. Whether such functionality is implemented as hardware or software depends upon the particular application and design requirements of the overall system. Those skilled in the art may implement the functionality in a variety of ways for each particular application, but such implementation should not be construed as beyond the scope of the embodiments of the present application.
The application also provides a readable storage medium having stored thereon instructions which when executed by a computer perform the functions of any of the method embodiments described above.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer programs. When the computer program is loaded and executed on a computer, the flow or functions according to embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer program may be stored in or transmitted from one computer readable storage medium to another, e.g., from one website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc., that contain an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a high-density digital video disc (Digital Video Disc, DVD)), or a semiconductor medium (e.g., a Solid state disk (Solid STATE DISK, SSD)), or the like.
Those of ordinary skill in the art will appreciate that: the first, second, etc. numbers referred to in the present application are merely for convenience of description and are not intended to limit the scope of the embodiments of the present application, but also to indicate the sequence.
At least one of the present application may also be described as one or more, and a plurality may be two, three, four or more, and the present application is not limited thereto. In the embodiment of the application, for a technical feature, the technical features of the technical feature are distinguished by a first, a second, a third, a, B, a C, a D and the like, and the technical features described by the first, the second, the third, the a, the B, the C, the D are not in sequence or in order of magnitude.
As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and/or device (e.g., magnetic discs, optical disks, memory, programmable Logic Devices (PLDs)) used to provide machine instructions and/or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal used to provide machine instructions and/or data to a programmable processor.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.
The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.
Furthermore, it is to be understood that the various embodiments of the application may be practiced alone or in combination with other embodiments as the scheme permits.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
The foregoing is merely illustrative embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present application, and the application should be covered. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (11)
1. A method of data signal processing, the method comprising:
Inputting current frame data into a first-stage processing module, and outputting an intermediate processing result after processing, wherein the first-stage processing module comprises a first storage module, a first base four module and a second base four module;
And inputting the intermediate processing result into a second-stage processing module, and outputting a data processing result after processing, wherein the second-stage processing module comprises a second storage module, a third base four module, a fourth base four module and a base two module.
2. The method of claim 1, wherein the current frame data includes four input segments, wherein the inputting the current frame data into the first stage processing module, the outputting the intermediate processing result after the processing, includes:
Sequentially and completely storing four input sections of the current frame data into addresses of corresponding digits in the first storage module;
The current frame data is taken out from the first storage module and is processed through the first base four module to obtain a first base four result, wherein the first base four result comprises result segments corresponding to four input segments of the current frame data;
Processing a first result segment of the first base four result through the second base four module to obtain a first result segment of a second base four result, and simultaneously writing back a second result segment, a third result segment and a fourth result segment of the first base four result to the original address in the first storage module;
When the next frame data is written into the address of the first input section used for storing the current frame data in the first storage module, the second result section of the first base four result is processed through the second base four module to obtain a second result section of a second base four result until the first base four result is completely processed through the second base four module to obtain a second base four result serving as the intermediate processing result.
3. The method of claim 2, wherein the processing by the first base four module comprises:
And writing the first input section of the next frame data into the first storage module, and processing the four input sections of the current frame data through the first base four module.
4. The method of claim 2, wherein the number of acquisition points of the current frame data is 512, the first input segment of the current frame data is 0-127 th symbol, the second input segment is 128-255 th symbol, the third input segment is 256-383 th symbol, and the fourth input segment is 384-511 th symbol.
5. The method according to any one of claims 2 to 4, wherein inputting the intermediate processing result to a second stage processing module, and outputting the data processing result after processing comprises:
Writing the second base four result into an address of a corresponding bit number in the second storage module;
Reading the second base four result from the second storage module while writing the second base four result into the second storage module, and processing the second base four result through the third base four module to obtain a third base four result;
And sequentially processing the third base four result through the fourth base four module and the base two module to obtain the data processing result.
6. The method of claim 5, wherein reading the second base four result from the second memory module while writing the second base four result to the second memory module and processing by the third base four module to obtain a third base four result comprises:
Writing a first result segment of the second base four result into an address after the second storage module, and writing a second result segment of the second base four result;
Reading a first result segment of the second base four result from the second storage module while writing the second result segment of the second base four result into the second storage module, and processing the first result segment of the second base four result by the third base four module to obtain four result segments of a third base four result;
And reading the second result segment of the second base four result from the second storage module while writing the third result segment of the second base four result into the second storage module, and processing the second result segment of the second base four result through the third base four module until the second base four result is completely processed through the third base four module.
7. The method of claim 6, wherein sequentially processing the third base four result by the fourth base four module and the base two module to obtain the data processing result comprises:
processing the first parts of the four result segments of the third base four results respectively and sequentially through the fourth base four module, and writing the second parts of the four result segments of the third base four results back to the original addresses in the second storage module respectively and sequentially;
Sequentially reading second parts of four result segments of the third base four result from the second storage module respectively, and processing the second parts through the fourth base four module;
And inputting a fourth base four result obtained by processing the third base four result by the fourth base four module into the base two module, and processing the fourth base four result to obtain the data processing result.
8. A data signal processing apparatus, the apparatus comprising:
The first-stage processing unit is used for inputting the current frame data into the first-stage processing module and outputting an intermediate processing result after processing, wherein the first-stage processing module comprises a first storage module, a first base four module and a second base four module;
the secondary processing unit is used for inputting the intermediate processing result into the secondary processing module and outputting a data processing result after processing, wherein the secondary processing module comprises a second storage module, a third base four module, a fourth base four module and a base two module.
9. A communication device, comprising: a transceiver; a memory; a processor, coupled to the transceiver and the memory, respectively, configured to control wireless signal transceiving of the transceiver and to enable the method of any one of claims 1-7 by executing computer-executable instructions on the memory.
10. A computer storage medium, wherein the computer storage medium stores computer-executable instructions; the computer executable instructions, when executed by a processor, are capable of implementing the method of any of claims 1-7.
11. A chip comprising one or more interface circuits and one or more processors; the interface circuit is configured to receive a signal from a memory of an electronic device and to send the signal to the processor, the signal comprising computer instructions stored in the memory, which when executed by the processor, cause the electronic device to perform the method of any of claims 1-7.
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