CN118170705A

CN118170705A - Bus instruction control method and related equipment

Info

Publication number: CN118170705A
Application number: CN202410564448.XA
Authority: CN
Inventors: 钟澔; 王一博; 王峰
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2024-05-09
Filing date: 2024-05-09
Publication date: 2024-06-11

Abstract

The application discloses a bus instruction control method and related equipment. The method may be applied to an IC device. One end of the IC device is connected with one or more hosts through SPMI buses, and the other end of the IC device is connected with the corresponding slaves. According to the method, when the address of the slave in the SPMI bus instruction received by the IC device is the same as the address of the target slave, the instruction comprises a preset register address, and the instruction is a write instruction, the IC device can modify the data corresponding to the preset register address in the instruction, and then the modified instruction is sent to the target slave. The target slave of the IC device is the slave connected with the IC device. The method can realize the adjustment of data such as power supply voltage carried by SPMI bus instructions, and improves the operability and the flexibility of power supply voltage adjustment.

Description

Bus instruction control method and related equipment

Technical Field

The present application relates to the field of terminal technologies, and in particular, to a bus instruction control method and related devices.

Background

The System Power management interface (System Power MANAGEMENT INTERFACE, SPMI) is a two-wire serial interface that can be used to accurately monitor and control the processor performance level required for a given workload or application and dynamically control the various Power supply voltages in real time based on the performance level. The SPMI bus supports multiple masters (or masters) and multiple slaves (or slaves), up to 4 masters and 16 slaves. However, the master-slave system of the existing SPMI bus directly realizes control of the power supply voltage based on SPMI protocol, the specific control strategy is not disclosed, and the terminal manufacturer cannot modify the control strategy and naturally cannot control adjustment of the power supply voltage.

Disclosure of Invention

The application provides a bus instruction control method and related equipment. The method may be applied to an IC device. One end of the IC device is connected with one or more hosts through SPMI buses, and the other end of the IC device is connected with a corresponding slave. Under the condition that the IC device receives a SPMI writing instruction which is to be sent to the target slave and contains a preset register address, the IC device can modify data corresponding to the preset register address in the instruction and then send the modified instruction to the target slave, so that the adjustment of data such as power supply voltage carried by SPMI bus instructions is realized, and the operability and the flexibility of power supply voltage adjustment are improved.

In a first aspect, the present application provides a bus instruction control method. The method may be applied to an integrated circuit device. One end of the integrated circuit device may be connected to one or more hosts via SPMI buses and the other end may be connected to a first slave. The method may include: the integrated circuit device may monitor a first instruction sent by the host to the SPMI bus; when the address of the slave machine included in the first instruction is the same as the address of the first slave machine, the first instruction includes a preset register address, and the first instruction is a write instruction, the integrated circuit device may modify first data in the first instruction to obtain second data, and then send the second instruction including the second data to the first slave machine. The first data is data corresponding to a preset register address included in the first instruction, and the second data is data corresponding to a preset register address included in the second instruction.

In the scheme provided by the application, the integrated circuit device can monitor the instruction sent by the host to the SPMI bus, after monitoring the instruction sent by the host to the SPMI bus, the target address of the instruction (namely the slave address included by the instruction) is the same as the address of the target slave, the instruction comprises the preset register address, and the integrated circuit device can modify the data corresponding to the preset register address in the instruction under the condition that the instruction is a write instruction, and send the instruction obtained after the data modification to the target slave. The method can realize control of SPMI bus instructions, including adjustment of data (such as power supply voltage) carried by SPMI bus instructions, solves the problem that a voltage regulation strategy cannot be modified due to unpublished voltage regulation mechanism, and improves operability and flexibility of power supply voltage regulation.

It is understood that the first slave refers to a slave to which the integrated circuit device corresponds, or a slave to which the integrated circuit device is correspondingly connected. For example, as shown in fig. 4, in the case where the integrated circuit device is an ICN, the first slave is a slave N, and N is a positive integer not greater than 16.

In some embodiments of the present application, in the case of SPMI systems comprising multiple integrated circuit devices, the slaves to which the multiple integrated circuit devices are correspondingly connected are different from each other.

It should be noted that, the first slave may be understood as a target slave of the integrated circuit device, and the description of the target slave may be specifically referred to below, which is not described herein.

It is understood that the integrated circuit device is referred to hereinafter as an IC device (as shown in fig. 4, 5, 6, and 8). The first instruction may be the SPMI bus instruction mentioned below and the second instruction may be the modified SPMI bus instruction mentioned below.

With reference to the first aspect, in one possible implementation manner, after the integrated circuit device listens for a first instruction sent by the host to the SPMI bus, the method may further include: the integrated circuit device may parse the first instruction; in the process of resolving the first instruction, the integrated circuit device may determine whether the address of the slave included in the first instruction is the same as the address of the first slave; in the case where the first instruction includes a slave address that is the same as the address of the first slave, the integrated circuit device may determine whether the first instruction includes a preset register address; in the case where the first instruction includes a preset register address, it is determined whether the first instruction is a write instruction.

In the scheme provided by the application, after the integrated circuit device monitors the instruction sent to the SPMI bus by the host, the instruction can be analyzed, firstly, whether the target address of the instruction is identical to the address of the target slave (namely, whether the instruction is the instruction sent to the target slave or not is determined), if the target address of the instruction is identical to the address of the target slave, the instruction is sent to the target slave, in this case, the integrated circuit device continuously determines whether the instruction comprises a preset register address or not, however, if the target address of the instruction is not identical to the address of the target slave, the instruction is not sent to the target slave, and in this case, the integrated circuit device does not continuously analyze the instruction. If the integrated circuit determines that the instruction includes the preset register address, the integrated circuit device may continue to determine the instruction type of the instruction, process the instruction according to the instruction type, and respond accordingly to the instruction, however, if the integrated circuit determines that the instruction includes the preset register address, the integrated circuit device may directly send the instruction to the target slave without resolving and processing the instruction. In this way, the integrated circuit device can parse the SPMI bus instruction monitored by the integrated circuit device step by step, and stop parsing in time (refer to fig. 7) when the instruction is found not to meet the corresponding condition, so that the program is saved, and the power consumption can be reduced to a certain extent.

With reference to the first aspect, in one possible implementation manner, the preset register address may be an address of a power supply register, and the first data includes a first voltage value. The integrated circuit device modifies the first data in the first instruction may specifically include: under the condition that the first voltage value is smaller than a first voltage threshold value, the integrated circuit device can reduce the first voltage value by a1 to obtain second data; when the first voltage value is greater than or equal to the first voltage threshold and less than the second voltage threshold, the integrated circuit device may reduce the first voltage value by a2 to obtain second data; and when the first voltage value is greater than or equal to the second voltage threshold value, reducing the first voltage value by a3 to obtain second data. Wherein a1 is less than a2, and a2 is less than a3.

In the scheme provided by the application, the integrated circuit device can modify the data according to the data size corresponding to the preset register address carried by the SPMI instruction, for example, the data can be reduced in a relatively larger step size under the condition that the data corresponding to the preset register address is relatively large, and the data can be reduced in a relatively smaller step size under the condition that the data corresponding to the preset register address is relatively small, so that the data is not increased or reduced in a fixed step size, and the data corresponding to the preset register address carried by the SPMI bus instruction can be modified more reasonably.

In some embodiments of the application, the first data may include a supply voltage. I.e. the first voltage value, is to be understood as the supply voltage carried by the first command.

With reference to the first aspect, in one possible implementation manner, after the integrated circuit device listens for a first instruction sent by the host to the SPMI bus, the method may further include: when the slave address included in the first instruction is the same as the address of the first slave, the first instruction includes a preset register address, and the first instruction is a read instruction, the integrated circuit device may acquire third data; the integrated circuit device may emulate a first slave preemption SPMI bus and send third data to the master. The third data is original configuration data corresponding to a preset register address.

In the scheme provided by the application, the integrated circuit device can monitor the instruction sent by the host to the SPMI bus, after monitoring the instruction sent by the host to the SPMI bus, the integrated circuit device can acquire the original configuration data corresponding to the preset register address and send the original configuration data to the host when the target address of the instruction (namely the slave address included by the instruction) is the same as the address of the target slave and the instruction includes the preset register address and the instruction is a read instruction. The method can avoid inconsistent data of the slave register read by the host and data originally written into the slave register caused by the modification of SPMI bus instructions by the integrated circuit device, namely, the problem of inconsistent read-write data caused by the modification of the data is avoided, so that the stability of SPMI system voltage regulation is maintained, and the method can complete reading and response (send the read original configuration data to the host) by the integrated circuit device without notifying the slave read and response, saves the flow to a certain extent and can control the power consumption.

In some embodiments of the present application, before or after the integrated circuit device listens that the target address (i.e., the slave address included in the instruction) is the same as the address of the target slave and includes the SPMI read instruction of the preset register address, the integrated circuit device may listen that the target address (i.e., the slave address included in the instruction) is the same as the address of the target slave and includes the SPMI write instruction of the preset register address, and modify the supply voltage carried by the SPMI write instruction.

With reference to the first aspect, in one possible implementation manner, the integrated circuit device may include one or more ROM partitions, where different kinds of original configuration data are stored. The one or more ROM partitions may include a first partition storing raw configuration data of the same class as data corresponding to a preset register address. The acquiring of the third data by the integrated circuit device may specifically include: the integrated circuit device may obtain third data from the first partition.

In the scheme provided by the application, the integrated circuit device can comprise one or more ROM partitions, and in this case, if the integrated circuit device monitors that the target address is the same as the address of the target slave and comprises a SPMI read instruction of a preset register address, the integrated circuit device can search the corresponding ROM partition for the original configuration data of the same category based on the category of the data corresponding to the preset register address. By the method, the integrated circuit device can store different types of original configuration data in different ROM partitions respectively, and the ROM partition storing the corresponding type of original configuration data can be searched based on the addresses of the ROM partitions, so that the specific type of original configuration data can be acquired from various types of original configuration data more quickly and conveniently.

It can be understood that the third data is original configuration data corresponding to the preset register address. The third data may be the raw data mentioned below, and may also be the raw register data mentioned below.

With reference to the first aspect, in one possible implementation manner, after the integrated circuit device listens for a first instruction sent by the host to the SPMI bus, the method may further include: when the first instruction includes a slave address that is the same as the address of the first slave, and the first instruction includes a preset register address, and the first instruction is a write instruction, the integrated circuit device may determine whether the first slave needs to respond to the first instruction; in the case where the first slave needs to respond to the first instruction, the integrated circuit device may emulate the first slave preemption SPMI bus and reply to the host that the first instruction has been received.

In the scheme provided by the application, the integrated circuit device can monitor the instruction sent by the host to the SPMI bus, after monitoring the instruction sent by the host to the SPMI bus, the target address of the instruction (namely the address of the slave included in the instruction) is the same as the address of the target slave, the instruction comprises a preset register address, and the integrated circuit device can determine whether to answer or not under the condition that the instruction is a write instruction, if so, the integrated circuit device can simulate the slave to preempt the bus and answer to the host after receiving the corresponding instruction, the slave is not required to be informed to answer the host, the flow can be simplified to a certain extent, and the power consumption is controlled.

With reference to the first aspect, in one possible implementation manner, the integrated circuit device is connected with a central processing unit CPU. After the integrated circuit device sends the second instruction to the first slave, the method may further include: the integrated circuit device may receive a third instruction sent by the CPU; based on the third instruction, the integrated circuit device may switch the operating mode from the first mode to the second mode; after switching the mode of operation to the second mode, the integrated circuit device may listen for instructions sent by the host to the SPMI bus and send instructions sent by the host to the SPMI bus to the first slave.

In the solution provided in the present application, in the case that the operation mode of the integrated circuit device is the first mode, the integrated circuit device may respond to and process the monitored SPMI bus command according to any one of the possible implementations of the first aspect and the first aspect, and in the case that the operation mode of the integrated circuit device is the second mode, the integrated circuit device is only responsible for transmitting the monitored SPMI bus command without processing it. And, the CPU can control the working mode adopted by the integrated circuit device, in particular can control the integrated circuit device to switch the working mode by sending an instruction for indicating to switch the working mode. In this way, the integrated circuit device can process the monitored SPMI bus instruction only in part of the scene (for example, in combination with power consumption, use condition of a user and the like), and is only responsible for transparent transmission in other scenes, so that the power consumption can be reduced to a certain extent.

It is understood that the third instruction may be an instruction to instruct switching of the operation mode, which is mentioned below.

With reference to the first aspect, in one possible implementation manner, before the integrated circuit device may snoop the first instruction sent by the host to the SPMI bus, the method may further include: the integrated circuit device may receive a fourth instruction sent by the CPU; based on the fourth instruction, the integrated circuit device may switch the operating mode from the second mode to the first mode. It will be appreciated that after switching the mode of operation to the first mode, the integrated circuit device may parse and process the SPMI bus instruction if it is heard (see for details the above description of the first aspect).

In some embodiments of the application, the operating mode employed by default by the integrated circuit device is the second mode.

With reference to the first aspect, in one possible implementation manner, the third instruction may include an address of the integrated circuit device. The address of the integrated circuit device is determined by the pull-up or pull-down resistor itself connected through one or more pins.

In the scheme provided by the application, the instruction sent by the CPU to the integrated circuit device for indicating to switch the working mode can comprise the address of the integrated circuit device. It will be appreciated that the address of the integrated circuit device may be determined based on the pull-up or pull-down resistance of its pin connections, and reference may be made in particular to the following.

In some embodiments of the application, SPMI systems may include multiple integrated circuit devices.

In a second aspect, the present application provides an integrated circuit device. The integrated circuit device may include a processing module, the integrated circuit device coupled with a memory in the electronic device. The memory may be used to store program instructions and the processing module may be used to read and execute the program instructions such that the integrated circuit device performs the method as described above in the first aspect or any implementation of the first aspect.

In some embodiments of the application, the processing module may include a protocol parsing module and an IC configuration module.

In some embodiments of the present application, the processing module may include a bus snoop module, a register corresponding module, a bus acknowledge module, and a protocol conversion module.

In some embodiments of the application, the integrated circuit device may include a communication module. The communication module can be used for communicating with other devices and is responsible for forwarding data.

In some embodiments of the application, the communication module may include ports (e.g., a master port, a slave port, and other ports, etc.) and a data forwarding control module.

In some embodiments of the application, the communication module may include ports (e.g., a master port, a slave port, and other ports, etc.).

In some embodiments of the application, the integrated circuit device may further comprise a memory module. The memory module may be used to store raw configuration data for the integrated circuit device and/or its corresponding connected slaves.

In some embodiments of the application, the storage module may include a slave data cache module.

In a third aspect, the present application provides a SPMI system. The SPMI system may include one or more hosts, SPMI buses, one or more integrated circuit devices as described in the second aspect above, and one or more slaves. The one or more hosts are each coupled to SPMI the bus, and each of the one or more integrated circuit devices may be coupled to SPMI the bus at one end and to their respective slaves at the other end.

In the scheme provided by the application, in the case that the SPMI system comprises a plurality of slaves and a plurality of integrated circuit devices, each integrated circuit device can be respectively connected with one slave, and the slaves correspondingly connected with the integrated circuit devices can be mutually different. In this way, each integrated circuit device in the SPMI system can parse the monitored SPMI bus command and respond to and process the SPMI bus command sent to its corresponding connected slave.

With reference to the third aspect, in a possible implementation manner, in a case that the SPMI system includes a plurality of integrated circuit devices as described in the second aspect, an address of each of the plurality of integrated circuit devices may be determined by a pull-up resistor or a pull-down resistor connected by itself through one or more pins, and addresses of the plurality of integrated circuit devices are different from each other.

In the scheme provided by the application, when the SPMI system comprises a plurality of slaves and a plurality of integrated circuit devices, the plurality of integrated circuit devices can be connected with the CPU through one communication interface of the CPU, and in this case, the plurality of integrated circuit devices can configure mutually different addresses through connecting a pull-up circuit or a pull-down resistor, so that the CPU can accurately send the instruction (or notification) to the corresponding integrated circuit devices when sending the instruction (or notification) to the integrated circuit devices, and because the plurality of integrated circuit devices only use one communication interface of the CPU, the CPU interface can be saved, and the layout difficulty of the plurality of integrated circuit devices is reduced to a certain extent.

In a fourth aspect, the present application provides an electronic device. The electronic device may comprise a SPMI system and a memory as described in the third aspect. The SPMI system is coupled to the memory, which may be used to store program instructions.

In a fifth aspect, the present application provides a computer storage medium. The computer storage medium stores program instructions which, when run on an integrated circuit device, cause the integrated circuit device to perform the bus instruction control method as described above in the first aspect or any implementation of the first aspect.

In a sixth aspect, the application provides a computer program product comprising instructions. The computer program product, when run on an electronic device, causes an integrated circuit device in the electronic device to perform the method as described in the first aspect or any implementation of the first aspect.

It will be appreciated that the integrated circuit device provided in the second aspect, the SPMI system provided in the third aspect, the electronic device provided in the fourth aspect, the computer storage medium provided in the fifth aspect, and the computer program product provided in the sixth aspect are all configured to perform the method as described in the first aspect or any implementation of the first aspect. Thus, reference may be made to the advantages of any one of the possible implementation manners of the first aspect, and the description is omitted here.

Drawings

FIG. 1 is a schematic diagram of a SPMI bus architecture according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a SPMI bus instruction cycle according to one embodiment of the present application;

Fig. 3 is a schematic hardware structure of an electronic device according to an embodiment of the present application;

fig. 4 is a schematic diagram of a SPMI system according to an embodiment of the present application;

fig. 5 is a schematic diagram of address configuration of an IC device according to an embodiment of the present application;

FIG. 6 is a schematic diagram illustrating interaction of SPMI systems according to an embodiment of the present application;

FIG. 7 is a block diagram illustrating a method for controlling a bus command according to an embodiment of the present application;

fig. 8 is a schematic diagram of software module interaction in an IC device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Wherein, in the description of the embodiments of the present application, unless otherwise indicated, "/" means or, for example, a/B may represent a or B; the text "and/or" is merely an association relation describing the associated object, and indicates that three relations may exist, for example, a and/or B may indicate: the three cases where a exists alone, a and B exist together, and B exists alone, and furthermore, in the description of the embodiments of the present application, "plural" means two or more than two.

It should be understood that the terms first, second, and the like in the description and in the claims and drawings are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the described embodiments of the application may be combined with other embodiments.

The present application relates to the SPMI bus field and, in order to facilitate an understanding of the method provided by the present application, some terms of the SPMI bus field are described below.

1. SPMI bus

The mobile industry processor interface (Mobile Industry Processor Interface, MIPI) alliance defines a set of standards for standardizing interfaces within electronic devices (e.g., camera interfaces, display screen interfaces, radio frequency/baseband interfaces, etc.), while increasing design flexibility, while reducing cost, design complexity, power consumption, etc. The MIPI alliance defines a hardware interface between a baseband or applications processor and peripheral components to support advanced power management techniques. For example SPMI is a two-wire serial interface for power management defined by the MIPI alliance.

SPMI buses are commonly used for power management and may be used to accurately monitor and control the processor performance level required for a given workload or application and to dynamically control various power supply voltages in real time according to the performance level. SPMI the bus is an asynchronous bus that can connect multiple masters and multiple slaves. Wherein a master refers to a device that initiates transmission, generates a clock signal, and terminates transmission, and a slave refers to a device addressed by the master. It is understood that SPMI bus is a bi-directional transmission bus, and thus, both the master and the slave to which SPMI bus is connected may be a transmitter (i.e., a device that transmits data) and a receiver (i.e., a device that receives data).

Illustratively, as shown in FIG. 1, the SPMI bus may connect 4 hosts (i.e., host 1, host 2, host 3, and host 4 shown in FIG. 1) and N slaves. Wherein N is a positive integer less than or equal to 16. Note that, the SPMI bus may include two signal lines, and connect 4 masters and N slaves through the two signal lines, which are a serial clock signal line and a serial data signal line, respectively. The Serial Clock signal line may transmit a Serial Clock Signal (SCLK), and the Serial data signal line may transmit a Serial data signal (SERIAL DATA, SDATA). It is understood that the serial clock signal may be simply referred to as a clock signal and the serial data signal may be simply referred to as a data signal.

It can be understood that the 4 hosts and the N slaves can perform data interaction through SPMI buses. In some embodiments of the application, the master and slaves may perform bus preemption via arbitration to resolve the conflict problem. When the bus is in an idle state, multiple hosts or slaves can access the bus through bus arbitration requests, and the host of the bus monitors the bus arbitration requests and grants the bus to a requester.

2. SPMI bus instruction cycles

Further, one cycle of data interaction between the master and the slave may be referred to as SPMI bus instruction cycles.

SPMI bus instruction cycles can be divided into several phases: a bus arbitration phase (bus arbitration as shown in fig. 2), a sequence start phase (sequence start as shown in fig. 2), a bus frame sequence phase (frame sequence as shown in fig. 2), and a bus stop period (as shown in fig. 2).

When a plurality of masters or a plurality of slaves connected by SPMI bus initiate data exchange (or communication/data transfer), a bus arbitration phase is first entered, which typically requires 9 clock cycles. In the bus arbitration phase, the host currently controlling SPMI the bus may determine which device initiating the communication transfer on the SPMI bus has a higher priority, and determine an arbitration result, i.e., a result of bus preemption (which may also be understood as a device that obtains ownership of the bus) according to the priority of the device. After preempting SPMI the bus and becoming the master of the SPMI bus, the device may gain control of the clock signal (i.e., SCLK) of the SPMI bus and provide SCLK of the SPMI bus. In some embodiments of the present application, devices connected to the SPMI bus may implement bus preemption by pulling the data signal line of the SPMI bus high.

A sequence start phase (also known as a bus buffer phase) may then be entered, during which a start sequence (Sequence Start Condition, SSC) is generated. In some embodiments of the present application, during the start-up phase of the sequence, the device that gains SPMI bus control may generate a start sequence by pulling down SCLK while controlling the data signal line to pull high the data signal (i.e., SDATA) first and then pulling down SDATA.

A receiver (or receiver device) on SPMI bus, such as a Power MANAGEMENT INTEGRATED Circuit (PMIC), detects the start timing and then proceeds to the bus frame sequence stage where a receiver on SPMI bus may be ready to receive a subsequent frame sequence. In the bus frame sequence stage, the device obtaining the bus ownership can perform operations such as host read-write or slave read-write. During the bus frame sequence phase, the master/slave may send SPMI bus instructions to the master/slave to implement operations such as reading from and writing to the master or reading from and writing to the slave. After execution SPMI of the bus instruction, a bus stall cycle may be entered.

In some embodiments of the application, SPMI bus instructions may include information on instruction type, destination address, data, and so on. It is understood that the data interaction process on SPMI buses may include, but is not limited to: and a process of reading the slave by the host and a process of writing the slave by the host. Accordingly, instruction types may include, but are not limited to: the host reads the slave (i.e., the host reads the slave register) and the host writes the slave (i.e., the host writes the slave register).

In some embodiments of the present application, the data interaction process on SPMI bus may also include a process of writing from the host. Accordingly, the instruction type may also include a slave-to-master write instruction.

In some embodiments of the present application, the target address includes an address of the slave (which may be simply referred to as a slave address), an address of a register of the slave (which may be simply referred to as a register address). For example, a specific SPMI bus instruction may be a command that the master writes a voltage value to a register of 0110 corresponding to a slave of 1111. The slave with address 1111 may be a PMIC, and the voltage may be a power management unit (Power Management Unit, PMU) voltage.

In some embodiments of the application, PMU and PMIC may be understood by different names of the same device.

In the SPMI system shown in fig. 1, both the master and the slave need to support the SPMI protocol, and both the master and the slave need to be connected by a SPMI bus. For example, the master 1 and the slave 1 both support SPMI protocols, and the master 1 and the slave 1 are connected in advance through a SPMI bus, so that the master 1 and the slave 1 can communicate through a SPMI bus and the master 1 can write data into the slave 1 or read data of the slave 1. That is, only the master and the slave, which support SPMI protocols and are connected through the SPMI bus, can perform data interaction. It should be noted that, the SPMI bus instruction transmitted by the SPMI bus is obtained based on the SPMI protocol, the data in the SPMI bus instruction is also obtained based on the SPMI protocol, and the device receiving the SPMI bus instruction cannot modify the SPMI bus instruction. For example, the voltage regulation mechanism involved in SPMI systems (e.g., a system including a SPMI bus and a slave and a host connected to a SPMI bus) is not disclosed, cannot be modified, and the device receiving the SPMI bus command in SPMI system can only regulate the voltage according to the voltage value in the SPMI bus command, cannot regulate the voltage by itself, and has problems of low operability and poor flexibility.

Based on the foregoing, the embodiment of the application provides a bus instruction control method and related equipment. The method may be applied to any integrated circuit (INTEGRATED CIRCUIT, IC) device in the SPMI system. It is understood that the master in SPMI system is connected to SPMI bus and each slave in SPMI system may be connected to one IC device and each IC device may also be connected to SPMI bus. For any IC device in the SPMI system, when the address of the slave in the SPMI bus instruction received by the IC device is the same as the address of the target slave, and the SPMI bus instruction includes a preset register address, and the SPMI bus instruction is a write instruction, the IC device may modify data corresponding to the preset register address, and then send the SPMI bus instruction (i.e., the modified SPMI bus instruction) obtained after modifying the data to the target slave, however, when the address of the slave in the SPMI bus instruction received by the IC device is the same as the address of the target slave, and the SPMI bus instruction includes the preset register address, and when the SPMI bus instruction is a read instruction, the IC device may read the original register data of the target slave, and then send the original register data to the host. The target slave of the IC device is the slave connected with the IC device. The original register data is original data configured by a preset register address (or called original configuration data corresponding to the preset register address). The method can realize control of SPMI bus instructions, including adjustment of data (such as power supply voltage) carried by SPMI bus instructions, solves the problem that a voltage regulation strategy cannot be modified due to unpublished voltage regulation mechanism, and improves operability and flexibility of power supply voltage regulation.

The following first describes an apparatus according to an embodiment of the present application.

It can be appreciated that the electronic device related to the embodiment of the present application may be a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device, an augmented Reality (Augmented Reality, AR)/Virtual Reality (VR) device, a notebook computer, an Ultra-Mobile Personal Computer (UMPC), a netbook, a Personal digital assistant (Personal DIGITAL ASSISTANT, PDA), or a special camera (such as a single-lens reflex camera, a card-type camera), etc., and the embodiment of the present application does not limit the specific type of the electronic device.

The following describes a hardware structure of an electronic device provided by an embodiment of the present application.

Referring to fig. 3, fig. 3 is a schematic hardware structure of an electronic device according to an embodiment of the application.

As shown in fig. 3, the electronic device may include: processor, memory, universal serial bus (Universal Serial Bus, USB) interface, charge management module, power management module, battery, etc.

It should be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device. It is to be understood that the illustrated components may be implemented in hardware, software, or a combination of software and hardware. In some embodiments of the application, the electronic device may include more components than illustrated. By way of example, the electronic device may include an audio module, a sensor module, an antenna 1, an antenna 2, a mobile communication module, a wireless communication module, a sensor module, keys, a motor, an indicator, a camera, a display screen, a subscriber identity module (Subscriber Identity Module, SIM) card slot, and the like. The audio module may include a speaker, a receiver, a microphone, an earphone interface, etc., and the sensor module may include a pressure sensor, a gyroscope sensor, a barometric sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, etc. In still other embodiments of the application, the electronic device may include fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components. The electronic device may include a processor and a memory, for example. The interface connection relation between the modules illustrated in the embodiment of the present application is only illustrated schematically, and does not limit the structure of the electronic device.

The processor may include one or more processing units, such as: the processors may include a central Processor (Central Processing Unit, CPU), an application Processor (Application Processor, AP), a Modem Processor (Modem, also referred to as baseband Processor), a graphics Processor (Graphics Processing Unit, GPU), an image signal Processor (IMAGE SIGNAL Processor, ISP), a controller, a video codec, a digital signal Processor (DIGITAL SIGNAL Processor, DSP), and/or a neural network Processor (Neural-network Processing Unit, NPU), etc. Wherein the AP is the processor responsible for running the operating system and applications. Modem is the processor responsible for handling the various communication protocols.

In some embodiments of the application, the processing unit comprised by the processor may also be understood as a chip. In this case, the processor may include one or more chips. For example, a System on Chip (SoC), a micro control unit (Microcontroller Unit, MCU). SoCs are also known as systems on chip, and mainly refer to a chip circuit that integrates critical components of a system on a chip and is capable of implementing complete system functions. The SoC can process digital signals, analog signals, mixed signals, and even radio frequency signals, and is often used in embedded systems, for example, in smart devices such as mobile phones, tablets, smart home appliances, and the like, and is a core chip that constitutes the devices. An MCU is a small computer on a single IC that contains a processor core, memory, programmable input/output (I/O) peripherals, timers, counters, etc. It provides minimal memory, interfaces and processing power. The peripherals contained on the MCU are less specific than SoC packages. MCUs are commonly used in small embedded control systems or control applications.

The charge management module is to receive a charge input from a charger. The charger can be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module may receive a charging input of the wired charger through the USB interface. In some wireless charging embodiments, the charging management module may receive wireless charging input through a wireless charging coil of the electronic device. The charging management module can also supply power to the electronic equipment through the power management module while charging the battery.

The power management module is used for connecting the battery, the charging management module and the processor. The power management module receives the input of the battery and/or the charging management module and supplies power to the processor, the internal memory, the external memory, the display screen, the camera, the wireless communication module and the like. The power management module may also be used to monitor parameters such as battery capacity, battery cycle times, and battery state of health (e.g., leakage conditions, impedance, etc.). In some embodiments of the application, the power management module may also be provided in the processor. In still other embodiments of the present application, the power management module and the charge management module may also be provided in the same device.

In some embodiments of the application, the power management module may include one or more PMICs. In still other embodiments of the present application, one or more PMICs in an electronic device may be provided independently, and not in a power management module or in a processor.

PMIC is an application specific integrated circuit that primarily functions to manage power for the host system. The PMIC may be used to control the charge management module. PMIC is commonly used for devices that use a battery as a power source, such as a mobile phone or a portable media player. Since such devices typically have more than one power source (e.g., battery and USB power source), the system requires multiple power sources of different voltages, and the need to control the charging and discharging of the battery, which would conventionally take up much space and increase product development time, has resulted in the advent of PMICs.

In some embodiments of the present application, an electronic device may include and connect a SoC with a PMIC via SPMI bus, which may be used to accurately monitor and control the processor performance level required for a given workload or application, and dynamically control various power supply voltages in real time according to the performance level.

The Memory may include one or more RAMs and one or more nonvolatile memories (NVM). Random access memory may be read directly from and written to by a processor, may be used to store executable programs (e.g., machine instructions) for an operating system or other on-the-fly programs, may also be used to store data for users and applications, and the like. The nonvolatile memory may also store executable programs, store data of users and application programs, and the like, and may be loaded into the random access memory in advance for the processor to directly read and write.

In some embodiments of the application, the electronic device may also include an external memory interface. The external memory interface may be used to connect to an external non-volatile memory to enable expansion of the memory capabilities of the electronic device.

In some embodiments of the application, the electronic device may include a SPMI system and the monitoring and regulation of the supply voltage is accomplished by a SPMI system that it contains.

The architecture of SPMI systems provided by embodiments of the present application is described below.

As shown in fig. 4, the SPMI system may include a SPMI bus, one or more hosts (e.g., one or more of hosts 1-4), one or more slaves (e.g., one or more of slaves 1-N), and one or more IC devices (e.g., one or more of ICs 1-ICN), and the one or more hosts are connected to the one or more IC devices via a SPMI bus and each IC device is connected to a slave, i.e., the number of IC devices in the SPMI system is equal to the number of slaves. That is, each slave is connected to the master through one IC device. It is also understood that one or more hosts and one or more IC devices are mounted on the SPMI bus, and that each IC device mounted on the SPMI bus is correspondingly connected to a slave.

It should also be noted that one or more IC devices in SPMI systems may be connected to the CPU of the electronic device. In some embodiments of the application, the one or more IC devices may be connected to the CPU of the electronic device through a communication interface (e.g., an IC configuration interface as shown in fig. 4) of the CPU.

For ease of understanding, the relationship between the master, slave and IC devices in the SPMI system may also be described and understood in series and parallel. Specifically, one or more hosts in SPMI systems are connected to the SPMI bus in parallel with each other, and similarly, one or more IC devices in SPMI systems are connected to the SPMI bus in parallel with each other, and each IC device is connected in series with a slave. That is, the hosts in SPMI are connected in parallel, the IC devices in SPMI are connected in parallel, the slaves in SPMI are connected in parallel, and the IC devices in SPMI are connected in series with their corresponding slaves.

It is understood that SPMI buses may include serial clock signal lines and serial data signal lines, in accordance with the above.

In some embodiments of the application, one or more socs in the electronic device may include one or more hosts in the SPMI system and one or more PMICs in the electronic device may include one or more slaves in the SPMI system.

In some embodiments of the application, one or more MCUs in the electronic device may include one or more hosts in the SPMI system and one or more PMICs in the electronic device may include one or more slaves in the SPMI system.

It is understood that in the case of SPMI systems comprising multiple hosts, the multiple hosts may be modules in one SoC or may be modules in a different SoC. Similarly, where SPMI system includes multiple hosts, the multiple hosts may be modules in one MCU or modules in different MCUs. Similarly, where SPMI system includes multiple slaves, the slaves may be modules in one PMIC or may be modules in a different PMIC.

In some embodiments of the present application, the IC devices in SPMI systems may be understood as devices that are provided independently of the SoC, MCU, and PMIC. In still other embodiments of the present application, the IC devices in the SPMI system may also be provided in other modules (e.g., power management modules) of the electronic device, as the application is not limited in this regard.

It is understood that the CPU of the electronic device and one or more hosts in its SPMI system may be in one SoC or may be in separate socs.

In some embodiments of the application, the IC device may be any of the following: a field programmable array (Field Programmable GATE ARRAY, FPGA), an MCU, an active device Circuit, an Application SPECIFIC INTEGRATED Circuit (ASIC). The relevant meaning of FPGA, MCU, active device circuit and ASIC may be referred to the relevant technical documents, and the present application is not described here. Of course, the IC device may be any other type of integrated circuit device, and the present application is not limited to the specific type thereof.

Further, based on the SPMI system architecture shown in fig. 4, the address configuration method of the IC device provided by the embodiment of the present application is specifically described below.

According to the above, in some embodiments of the present application, the plurality of IC devices may be connected to the CPU through one communication interface of the CPU (as shown in fig. 4), so that the communication between the plurality of IC devices and the CPU is realized, so that the communication between the CPU and the plurality of IC devices can be realized through only one communication interface, occupation of the communication interface of the CPU is reduced, and it is more convenient to arrange SPMI the system in the electronic device. In this case, the plurality of IC devices may be configured with different addresses, thereby ensuring normal communication with the CPU.

In some embodiments of the present application, as shown in fig. 5, the IC device may set the address of the IC device by setting the level value corresponding to the 4 GPIOs (General Purpose Input/Output ports, i.e., general purpose input Output ports) of its pins (GPIOs 1-GPIOs 4 as shown in fig. 5). Specifically, the 4 GPIOs of the IC device may be respectively connected to a pull-up resistor (R1-R4 shown in fig. 5) or a pull-down resistor (R5-R8 shown in fig. 5), after the GPIOs are connected to the pull-up resistor, they correspond to high levels and may be represented by 1, and after the GPIOs are connected to the pull-down resistor, they correspond to low levels and may be represented by 0, so that the levels corresponding to the 4 GPIOs of the corresponding pins (i.e., pins configured with addresses) of the IC device may be represented by 0000-1111, which means that 16 addresses may be configured for the IC device in this way, and the 16 addresses may be represented by 0000-1111 in binary, and converted into hexadecimal values may be represented by 0x 0-0 xf.

It will be appreciated that pins of the configuration address of the IC device may be set according to actual needs, and the present application is not particularly limited thereto. It is understood that the number of GPIOs set by the IC device configuration address may be determined based on the number of IC devices in the SPMI system. For convenience of description, the present application refers to the number of GPIOs set by the configuration address of the IC device as m. Wherein the power of 2 to m is not less than the number of IC devices in SPMI systems. It is understood that the power of 2 to the m indicates the number of configurable addresses of the IC device. For example, as shown in fig. 5, the IC device is provided with 4 GPIOs, which means that the number of configurable addresses of the IC device is 16, in which case the number of slaves in the SPMI system is no greater than 16. It is understood that m is an integer no greater than 4.

In some embodiments of the present application, the number of GPIOs set per IC device configuration address in the SPMI system may be set based on the number of slaves in the SPMI system (equal to the number of IC devices). For example, in the case where the number of slaves of the SPMI system is not greater than 8, the number of GPIOs set by each IC device configuration address in the SPMI system may be 3. For another example, in the case where the number of slaves of the SPMI system is not greater than 4, the number of GPIOs set by each IC device configuration address in the SPMI system may be 2. For another example, in the case where the number of slaves of the SPMI system is not greater than 2, the number of GPIOs set by each IC device configuration address in the SPMI system may be 1.

In some embodiments of the application, the number of GPIOs set by each IC device configuration address in the SPMI system is the same.

It is understood that the resistance values of the pull-up resistor and the pull-down resistor connected to the IC device may be set according to actual needs, which is not particularly limited by the present application. That is, the resistance values of R1 to R8 shown in FIG. 5 may be the same or different, and may be specifically set according to actual needs.

The following describes a bus command control method provided by the embodiment of the application from the perspective of device interaction in SPMI systems.

Referring to fig. 6, fig. 6 is a schematic diagram illustrating interaction of SPMI systems according to an embodiment of the present application. Fig. 6 illustrates an example of interaction between an IC device and a master or slave in SPMI systems, to describe a bus command control method according to an embodiment of the present application.

As shown in fig. 6, the host may send SPMI a bus instruction to the SPMI bus, the IC device may receive SPMI a bus instruction on the SPMI bus (or snoop SPMI a bus instruction), and identify the SPMI bus instruction, the IC device may identify whether the SPMI bus instruction relates to specific data of the target slave, and whether the SPMI bus instruction is a write instruction or a read instruction. In the case where the IC device determines that the SPMI bus instruction it receives relates to specific data of the target slave and the SPMI bus instruction is a Read instruction, the IC device may Read the original data from a corresponding Read-Only Memory (ROM) partition and transmit the original data to the host. In the case where the IC device determines that the SPMI bus instruction it receives relates to specific data of the target slave and that the SPMI bus instruction is a write instruction, the IC device may further determine whether the SPMI bus instruction needs to be modified, if the IC device needs to modify the SPMI bus instruction, the IC device may modify the SPMI bus and send the modified SPMI bus instruction to the slave to which it is connected, and if the IC device does not need to modify the SPMI bus instruction, the IC device may directly pass the SPMI bus instruction it receives through to the slave to which it is connected (i.e., the target slave).

It is understood that for an IC device, its corresponding connected slave is its target slave. Illustratively, as shown in FIG. 4, the target slave of IC1 is slave 1, the target slave of IC2 is slave 2, the target slave of IC3 is slave 3, and the target slave of ICN is slave N.

In some embodiments of the application, the particular data may be data stored by a particular register. In this case, the specific data of the target slave is data stored in the specific register of the target slave, and the original data is original configuration data (or standard configuration data, that is, original register data mentioned below) corresponding to the specific register of the target slave.

In some embodiments of the application, the particular data may be a particular type of data. Such as a supply voltage. In this case, the raw data is the standard supply voltage to which the target slave corresponds.

In some embodiments of the present application, the specific manner in which the IC device identifies SPMI devices may refer to steps S102-S103, and the present application is not described herein.

In some embodiments of the present application, the specific manner in which the IC device determines SPMI whether the bus instruction relates to specific data of the target slave may refer to step S104, and the present application is not described herein.

In some embodiments of the application, the IC device may determine whether the SPMI bus instructions need to be modified according to preset configuration rules. In some embodiments of the present application, the IC device may not modify SPMI the bus instruction if the specific data of the target slave to which the SPMI bus instruction relates is within a preset range. In some embodiments of the present application, if the specific data of the target slave to which the SPMI bus instruction relates is less than threshold 1 (or not greater than threshold 1), the IC device may raise the corresponding data in the SPMI bus instruction, and if the specific data of the target slave to which the SPMI bus instruction relates is greater than threshold 2 (or not less than threshold 2), the IC device may lower the corresponding data in the SPMI bus instruction.

In some embodiments of the present application, the minimum value of the preset range may be a threshold value 1, and the maximum value of the preset range may be a threshold value 2.

It will be appreciated that the threshold 1 and the threshold 2 may be set according to actual needs, and the present application is not limited thereto. In some embodiments of the application, threshold 1 and threshold 2 may be equal.

It is understood that other implementations of the preset configuration rules may be referred to below, and the present application is not described herein.

In some embodiments of the present application, in the event that it is determined SPMI that the bus instruction relates to specific data of the target slave and that the SPMI bus instruction is a write instruction, the IC device may directly modify SPMI the bus instruction (e.g., modify SPMI the bus instruction according to a preset configuration rule) without first determining whether the SPMI bus instruction needs to be modified, as may be referred to in step S106 for a specific implementation.

In some embodiments of the application, the IC device may be connected to the CPU and the operating mode of the IC device may be configured and controlled by the CPU. The connection manner of the IC device and the CPU may be specifically referred to above (as shown in fig. 4), and the present application is not described herein.

In some embodiments of the application, the CPU may control the IC device to switch modes of operation via an integrated circuit bus (Inter-INTEGRATED CIRCUIT, I2C). In still other embodiments of the application, the CPU may control the IC device to switch modes of operation via a serial peripheral interface (SERIAL PERIPHERAL INTERFACE, SPI) bus. In some embodiments of the application, the CPU may send instructions to the IC device over a corresponding bus (e.g., I2C or SPI) to inform the IC device to switch modes of operation.

In some embodiments of the application, the modes of operation of the IC device may include a first mode and a second mode. In the case of the IC device employing the first mode, the IC device may recognize SPMI the bus and process SPMI the bus instruction (e.g., modify SPMI the bus instruction), the specific procedure of which may be referred to above. In the case where the IC device adopts the second mode, as shown in fig. 6, the IC device may transparently transmit a corresponding instruction, for example, the IC device may directly transmit the SPMI bus instruction, which is transmitted from the host to the SPMI bus, to the slave (i.e., the target slave) to which the IC device is connected, without identifying and processing the same.

In some embodiments of the present application, the first mode may be a normal mode and the second mode may be a low power mode.

In some embodiments of the present application, the CPU may determine an operation mode that the IC device needs to employ, and notify the IC device to switch the operation mode in the case where the IC device needs to switch the operation mode. In some embodiments of the application, the CPU may determine the mode of operation that the IC device needs to employ based on the power consumption of the electronic device. Of course, the CPU may also determine the operation mode that needs to be adopted by the IC device in combination with other factors (for example, the on/off screen condition of the electronic device, whether the electronic device is in a specific mode such as a night mode or a flight mode, etc.), which is not limited by the present application.

In some embodiments of the application, the IC device defaults to the second mode. That is, after the user triggers the electronic device to start up, the IC device in the electronic device first adopts the second mode.

In some embodiments of the present application, as shown in fig. 6, the IC device may be connected to a resistor to configure its address, and the specific implementation may refer to the above (related description in fig. 5), which is not repeated herein.

A specific implementation of the above embodiment is described below.

Referring to fig. 7, fig. 7 is a schematic diagram of a bus instruction control method according to an embodiment of the application. The method may be applied to each of the IC devices connected to the slaves in the SPMI system. The method may include, but is not limited to, the steps of:

s101: and monitoring SPMI bus instructions sent by the host.

The IC device may snoop the command sent by the host onto the SPMI bus, i.e., the SPMI bus command.

S102: it is determined SPMI whether the slave address in the bus instruction is the same as the address of the target slave.

If the IC device monitors the SPMI bus command sent by the host, the SPMI bus command may be identified, specifically, whether the SPMI bus command is a SPMI bus command sent to the target slave, that is, whether the SPMI bus command is a command sent to the slave to which the IC device is correspondingly connected may be identified. Specifically, the IC device may parse SPMI the bus instruction, obtain the slave address in the SPMI bus instruction, and determine whether the slave address in the SPMI bus instruction is the address of the target slave. If the slave address in the SPMI bus instruction is the same as the address of the target slave, the IC device may continue to perform steps S103-S112. If the slave address in the SPMI bus instruction is not the same as the address of the target slave, it means that the SPMI bus instruction is not an instruction to the slave to which the IC device is connected, in which case the IC device does not need to process the SPMI bus instruction.

It is understood that the slave address in the SPMI bus instruction may be the target address in the SPMI bus instruction mentioned above.

S103: and resolving SPMI register addresses and data carried by the bus instruction.

In accordance with the above, in some embodiments of the application, SPMI bus instructions may include the register address and data of the slave. It will be appreciated that in the event that the IC device determines that the slave address in the SPMI bus instruction it listens to is the same as the address of the target slave, the IC device may resolve SPMI the register address (the register address of the slave referred to above) and the data (including the data to which the register address corresponds) carried by the bus instruction.

S104: it is determined SPMI whether the bus instruction carries a preset register address.

After the IC device parses the register address and data carried by the SPMI bus instruction, it may be determined whether the SPMI bus instruction carries a preset register address, and specifically, it may be determined whether the register address in the parsed SPMI bus instruction includes the preset register address. If the register address in the SPMI bus instruction obtained by the IC device parsing includes the preset register address, it indicates that the SPMI bus instruction carries the preset register address, in which case the IC device may execute step S105. If the register address in the SPMI bus instruction obtained by the IC device parsing does not include the preset register address, it indicates that the SPMI bus instruction does not carry the preset register address, in this case, the IC device may execute step S112, that is, the IC device may directly send the SPMI bus instruction to the target slave.

In some embodiments of the present application, the preset register address may be set according to actual needs, which is not particularly limited by the present application. For example, the preset register address may be a register address corresponding to the slave machine, where specific data is stored. It is understood that, in accordance with the above, the specific data may be a specific type (or class) of data, such as a supply voltage.

It is understood that the preset register address in each IC device may be set based on the register address of the slave to which it is connected. In some embodiments of the present application, in the SPMI system, the register addresses corresponding to different slaves storing specific data may be different from each other, in which case the preset register addresses set in the respective IC devices are also different from each other.

S105: it is determined SPMI whether the bus instruction is a write instruction or a read instruction.

In the case where the SPMI bus instruction that the IC device monitors carries a preset register address, the IC device may determine the instruction type of the SPMI bus instruction, i.e., determine whether the SPMI bus instruction is a write instruction or a read instruction. In the case where the SPMI bus instruction is a write instruction, the IC device may perform steps S106 to S109, and in the case where the SPMI bus instruction is a read instruction, the IC device may perform steps S110 to S111.

In some embodiments of the present application, in the case where the SPMI bus instruction that is monitored by the IC device carries a preset register address, the IC device may determine the instruction type of the SPMI bus instruction, and in particular may determine whether the SPMI bus instruction is a write instruction. If the SPMI bus command is a write command, the IC device may perform steps S106 to S109, and if the SPMI bus command is not a write command, the SPMI bus command is a read command, in which case the IC device may perform steps S110 to S111.

S106: and modifying data corresponding to a preset register address in the SPMI bus instruction according to a preset configuration rule to obtain a modified SPMI bus instruction.

In the case that the SPMI bus instruction monitored by the IC device is a write instruction, the IC device may modify, according to a preset configuration rule, data corresponding to a preset register address in the SPMI bus instruction, to obtain a modified SPMI bus instruction.

In some embodiments of the present application, the preset register may be a register used by the target slave to store the power supply voltage (i.e., a power supply register of the target slave), and the data corresponding to the preset register address may be the power supply voltage.

In some embodiments of the present application, the preset configuration rules may include: the power supply voltage is adjusted according to the first voltage threshold and the second voltage threshold. Specifically, the power supply voltage is reduced by a1 in the case where the power supply voltage is smaller than the first voltage threshold, reduced by a2 in the case where the power supply voltage is larger than or equal to the first voltage threshold and smaller than the second voltage threshold, and reduced by a3 in the case where the power supply voltage is larger than or equal to the second voltage threshold.

That is, the IC device modifies, according to a preset configuration rule, data corresponding to a preset register address in the SPMI bus instruction, which may specifically include: under the condition that the data corresponding to the preset register in the SPMI bus instruction is smaller than the first voltage threshold, the IC device may decrease a1 on the basis of the data to obtain a modified SPMI bus instruction, that is, the data corresponding to the preset register address in the modified SPMI bus instruction is lower than the corresponding data in the original SPMI bus instruction by a1, and under the condition that the data corresponding to the preset register in the SPMI bus instruction is larger than or equal to the first voltage threshold and smaller than the second voltage threshold, the IC device may decrease a2 on the basis of the data to obtain a modified SPMI bus instruction, that is, the data corresponding to the preset register address in the modified SPMI bus instruction is lower than the corresponding data in the original SPMI bus instruction by a2, and under the condition that the data corresponding to the preset register in the SPMI bus instruction is larger than or equal to the second voltage threshold, the IC device may decrease a3 on the basis of the data to obtain a modified SPMI bus instruction, that is, the data corresponding to the corresponding data corresponding to the preset register address in the modified SPMI bus instruction is lower than the corresponding data in the original SPMI.

It is understood that the first voltage threshold is less than the second voltage threshold. The first voltage threshold and the second voltage threshold may be set according to actual needs, which is not limited in the present application. For example, the first voltage threshold may be 2 volts (V) and the second voltage threshold may be 3V.

It will be appreciated that a1, a2 and a3 may be set according to actual needs, and the application is not limited thereto. In some embodiments of the application, a1 is less than a2, and a2 is less than a3. For example, a1 may be 100 millivolts (mV), a2 may be 200 mV, and a3 may be 300 mV.

In some embodiments of the present application, the preset configuration rules may include: the supply voltage is regulated according to the third voltage threshold and the fourth voltage threshold. Specifically, in the case where the power supply voltage is smaller than the third voltage threshold, the power supply voltage is increased, in the case where the power supply voltage is greater than or equal to the third voltage threshold and smaller than the fourth voltage threshold, the power supply voltage is not adjusted, and in the case where the power supply voltage is greater than or equal to the fourth voltage threshold, the power supply voltage is decreased. In one possible implementation, the preset configuration rule may further include: the voltage threshold is further set to increase the power supply voltage, for example, one or more ranges are set, the power supply voltage falls in different ranges, the step sizes of the corresponding increases of the power supply voltage are different, and the implementation manner of reducing the power supply voltage by referring to the above set ranges can be referred to. Similarly, the preset configuration rules may further include: the voltage threshold is further set to reduce the power supply voltage, for example, one or more ranges are set, the power supply voltage falls in different ranges, and the step sizes of the corresponding reduced power supply voltages are different.

It is understood that the third voltage threshold is less than the fourth voltage threshold. The third voltage threshold and the fourth voltage threshold may be set according to actual needs, which is not limited by the present application.

S107: and sending the modified SPMI bus instruction to the target slave as the host.

After the IC device obtains the modified SPMI bus instruction, the modified SPMI bus instruction may be sent as a master to the target slave, i.e., the slave to which the IC device is connected.

For example, the address of the slave (i.e., the target slave) to which the IC device is correspondingly connected may be 0x2, the address of the power register of the slave is 0x1234, and the preset register address in the IC device is the address of the power register of the target slave thereof, i.e., 0x1234. After the IC device monitors a SPMI bus command, the IC device may parse (or identify) the SPMI bus command, first parse DEVICEADDR address bits and determine that the content thereof is 0x2, which means that the SPMI bus command is a command sent to a slave with an address of 0x2, the IC device may determine that the address is the same as the address of the target slave of the IC device, further, the IC device may continue parsing CMD command bits and determine that the instruction type of the SPMI bus command is a write command, further, the IC device may continue parsing DataAddr register address bits and determine that the content thereof is 0x1234, which means that the SPMI bus command is an instruction for a register with an address of 0x1234, the IC device may determine that the content of the register address is the same as a preset register address, further, the IC device may continue parsing 07062 Data bits and determine that the content thereof is h' 8, at this time, the parsing of the SPMI bus command is completed. After the IC device has completed parsing, the voltage value in the SPMI bus command may be determined. It will be appreciated that h'0708 is converted to 1800 decimal, so the IC device can determine that the data corresponding to the power register in the SPMI bus command is 1800mV, i.e., the voltage value (i.e., power supply voltage) carried by the SPMI bus command is 1800mV. Further, the IC device may determine that the voltage value in the SPMI bus command is less than 2V, and then the IC device may decrease the voltage value by 100mV to obtain a new voltage value, i.e., 1700mV, and send a SPMI bus command carrying the new voltage value to the slave with address 0x 2.

In some embodiments of the present application, the slave to which the IC device is correspondingly connected is a third party device that supports only other third party protocols and does not support the SPMI protocol. In this case, the IC device may convert the modified SPMI bus instruction into an instruction supported by the third party protocol, and then send the converted instruction to its corresponding connected slave.

S108: it is determined whether the target slave needs to respond SPMI to the bus instruction.

In the case where the SPMI bus instruction that the IC device monitors is a write instruction, the IC device may determine whether the target slave needs to respond to SPMI bus instruction. If the target slave needs to answer SPMI the bus command, the IC device needs to perform not only step S106-step S107, but also step S109, i.e. the IC device may simulate the target slave to preempt the SPMI bus and answer SPMI bus command sent by the target slave to the host. It will be appreciated that the relevant description of the preemption bus may be made with reference to the above and other relevant technical documents, and the present application is not described herein. If the target slave does not need to respond SPMI to the bus command, the IC device only needs to execute steps S106 to S107, and step S109 is not required to be executed.

S109: the emulated target slave preempts SPMI the bus and acknowledges to the host that it has received the SPMI bus instruction it sent.

In the case where the target slave needs to respond SPMI to the bus instruction, the IC device may emulate the target slave preempting SPMI bus and reply to the host that it has received the SPMI bus instruction it sent.

S110: and acquiring original register data corresponding to the target slave machine from the corresponding ROM partition. The original register data is original configuration data corresponding to a preset register address.

In the case that the SPMI bus instruction monitored by the IC device is a read instruction, the IC device may obtain the original register data corresponding to the target slave from the corresponding ROM partition. Wherein the corresponding ROM partition can be understood as: ROM partitions storing original configuration data corresponding to preset register addresses are stored in the IC device. It is understood that the raw configuration data may include raw register data corresponding to the target slave.

In some embodiments of the application, the raw register data may be a standard supply voltage of the configuration (or referred to as the original/raw configuration supply voltage).

It is understood that the IC device may include a memory module that may be used to store raw configuration data. In some embodiments of the application, the memory module may include one or more ROM partitions, where the memory module includes multiple ROM partitions, the multiple ROM partitions may each store different raw configuration data (e.g., different categories of raw configuration data).

By way of example, as shown in table 1, the IC device may include any one or more of the following ROM partitions: ROM partition 1, ROM partition 2, ROM partition 3, ROM partition 4, ROM partition 5, ROM partition 6. Wherein the address of ROM partition 1 is 0x00, the address of ROM partition 2 is 0x01, the address of ROM partition 3 is 0x02, the address of ROM partition 4 is 0x03, the address of ROM partition 5 is 0x04, and the address of ROM partition 6 is 0x05. The ROM partition 1 stores therein chip version information, the ROM partition 2 stores therein chip software version information, the ROM partition 3 stores therein chip operation state information (e.g., standby, abnormal, operating, etc.), the ROM partition 4 stores therein chip operation mode information (e.g., normal mode, low power consumption mode, etc.), the ROM partition 5 stores therein power supply information (e.g., power supply voltage), and the ROM partition 6 stores therein power supply operation mode information.

TABLE 1

For example, the address of the slave (i.e., the target slave) to which the IC device is correspondingly connected may be 0x2, the address of the power register of the slave is 0x1234, and the preset register address in the IC device is the address of the power register of the target slave thereof, i.e., 0x1234. After the IC device monitors a SPMI bus command, the IC device may parse (or identify) the SPMI bus command, first parse DEVICEADDR address bits and determine that the content thereof is 0x2, which means that the SPMI bus command is a command sent to a slave with an address of 0x2, the IC device may determine that the address is the same as the address of the target slave of the IC device, further, the IC device may continue parsing CMD command bits and determine that the instruction type of the SPMI bus command is a read command, further, the IC device may continue parsing to DataAddr register address bits and determine that the content thereof is 0x1234, which means that the SPMI bus command is an instruction for a register with an address of 0x1234, and the IC device may determine that the register address is the same as a preset register address, which means that the SPMI bus command is to read data in a power register of the target slave, that is, reading the power supply voltage stored in the power supply register of the target slave, at this time, complete parsing the SPMI bus command. After the IC device has completed the parsing, the IC device can read the power supply voltage from the ROM partition 5, since the power supply information is stored in the ROM partition 5. It will be appreciated that the supply voltage read by the IC device from the ROM partition 5 is a configured standard supply voltage.

S111: the simulation target slave preempts SPMI the bus and sends the original register data to the host.

After the IC device obtains the original register data, the target slave may be modeled to preempt the SPMI bus and send the original register data to the host.

S112: and directly sending SPMI bus instructions to the target slave.

Under the condition that SPMI bus instructions monitored by the IC device do not carry preset register addresses, the IC device can directly send the SPMI bus instructions to the target slave, namely, the SPMI bus instructions are transmitted to the target slave.

The following exemplarily describes software modules in an IC device, and describes a specific implementation of the above embodiment based on the software modules in the IC device.

In some embodiments of the application, as shown in fig. 8, an IC device may include ports (e.g., a master port, a slave port, and other ports, etc.), a protocol resolution module, a data forwarding control module, an IC configuration module, and a memory module. A port may be understood as a communication port of an IC device with other modules (e.g., CPU, host, slave, etc.), in particular, an IC device may communicate with a host through a host port and an IC device may communicate with a slave through a slave port. The protocol parsing module may be used to parse instructions (e.g., SPMI bus instructions) that the IC device listens for or receives. The data forwarding control module may be used to forward instructions or other data to other modules. The IC configuration module may be used to configure the operating mode of the IC device and modify instructions (e.g., SPMI bus instructions) that the IC device listens to or receives, and may also include other configuration information. The storage module may be used to store raw configuration data (e.g., raw configuration data of a power register of a target slave).

In some embodiments of the application, the IC configuration module may include a slave configuration module and a slave data forwarding module. The slave configuration module may be configured to configure an operation mode of the IC device and modify an instruction (e.g., SPMI bus instruction) that the IC device listens to or receives, and the slave data forwarding module may be configured to control forwarding of the instruction sent by the slave.

In some embodiments of the application, the IC configuration module may be divided into a plurality of software modules, each responsible for different configuration information. For example, the IC configuration module shown in fig. 8 may be divided into two software modules, one of which may be referred to as an IC operation mode control module, and the other of which may use the original name, i.e., the IC configuration module. In this case, the IC operation mode control module may be used to configure the operation mode of the IC device, modify instructions, and control data forwarding from the slave to the host, and the IC configuration module may include other configuration information.

As shown in fig. 8, the IC device may receive SPMI the bus instruction through the host port, and after receiving SPMI the bus instruction through the host port, a protocol parsing module in the IC device may parse the SPMI bus instruction. Specifically, when the address of the slave in the SPMI bus instruction is the same as the address of the target slave and the SPMI bus instruction carries the preset register address, the protocol parsing module may send the data corresponding to the preset register address to the IC configuration module in the IC device. In some embodiments of the present application, the protocol parsing module may send the data corresponding to the preset register address and SPMI bus instructions to the IC configuration module together.

When the SPMI bus instruction is a write instruction, after receiving the data corresponding to the preset register address, the IC configuration module may modify the data corresponding to the preset register address carried by the SPMI bus instruction to obtain modified data corresponding to the preset register address and a modified SPMI bus instruction. In some embodiments of the present application, the IC device may modify data corresponding to the preset register address carried by SPMI through a slave configuration module in the IC configuration module. After the IC configuration module obtains the modified SPMI bus instruction, the modified SPMI bus instruction may be sent to a data forwarding control module in the IC device. After receiving the modified SPMI bus instruction, the data forwarding control module may send the modified SPMI bus instruction to the target slave through the slave port.

When the SPMI bus instruction is a read instruction, after receiving the data corresponding to the preset register address, the IC configuration module may read the original register data from the corresponding ROM partition of the storage module, and send the original register data to the data forwarding control module. After the data forwarding control module receives the original register data, the original register data can be sent to the host through the host port.

In some embodiments of the application, the IC device may configure its mode of operation through an IC configuration module. According to the above, the operation modes of the IC device may include the first mode and the second mode. In the case of the IC device adopting the first mode, the IC device may process the received command according to the above, and in the case of the IC device adopting the second mode, after the IC device receives the SPMI bus command through the host port, the SPMI bus command may be directly sent to the target slave through the slave port by the data forwarding control module, without parsing it by the protocol parsing module, and without processing it by the IC configuration module.

In some embodiments of the application, the operating mode that the IC device defaults to may be the second mode.

In some embodiments of the present application, the IC device may receive instructions sent by the CPU via other ports indicating to switch modes of operation. After the IC device receives the instruction, a protocol parsing module in the IC device may parse the instruction, and then send the parsing result to the IC configuration module. After the IC configuration module receives the analysis result, the working mode after switching can be configured. After the IC configuration module configures the switched operating mode, the IC device may employ the switched operating mode to process the received instruction (e.g., directly forward the instruction, or forward the instruction after processing it accordingly).

It will be appreciated that specific trigger conditions for the CPU to send instructions to the IC device to switch modes of operation may be referred to above, as the application is not limited in this regard.

In some embodiments of the application, the IC device may include a port, a bus snoop module, a register response module, a bus acknowledge module, a slave data cache module, and a protocol conversion module. Reference may be made to the above for a description of ports, and the description of the present application is not repeated here. The bus monitoring module can realize monitoring analysis of SPMI bus instructions and trigger other modules to work under the condition that the addresses of the slaves in the SPMI bus instructions are the same as the addresses of the target slaves. The register response module is used for addressing original configuration data prestored in the corresponding ROM and sending the data to the host computer through SPMI buses. It is understood that the register response module is triggered by a read instruction. That is, if the bus snoop module snoops the SPMI bus command including the target slave address and the command is a read command, the register response module in the IC device does not perform the above (i.e. obtain and send the corresponding original configuration data). The bus response module is used for simulating the slave to preempt the bus and responding to the host. It will be appreciated that the bus response module in the IC device does not perform this in the event that the IC device determines SPMI that the bus command needs to be responded to. The slave data caching module is used for caching the write instruction, triggering the protocol conversion module to analyze SPMI bus instructions and modifying the carried data. The protocol parsing module may also be used to perform protocol conversion, such as converting instructions supporting SPMI protocols to instructions supporting other protocols.

The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. A bus command control method, applied to an integrated circuit device, one end of the integrated circuit device being connected to one or more hosts through a system power management interface SPMI bus, and the other end being connected to a first slave, the method comprising:

Monitoring a first instruction sent to the SPMI bus by the host;

When the slave address included in the first instruction is the same as the address of the first slave, the first instruction includes a preset register address, and the first instruction is a write instruction, modifying first data in the first instruction to obtain second data;

sending a second instruction to the first slave;

The first data are data corresponding to the preset register address included in the first instruction; the second data is data corresponding to the preset register address included in the second instruction.

2. The method of claim 1, wherein after the listening for the first instruction sent by the host to the SPMI bus, the method further comprises:

analyzing the first instruction;

In the process of analyzing the first instruction, determining whether the address of the slave machine included in the first instruction is the same as the address of the first slave machine; determining whether the first instruction comprises the preset register address or not under the condition that the slave address included in the first instruction is the same as the address of the first slave; in the case that the first instruction includes the preset register address, determining whether the first instruction is a write instruction.

3. The method of claim 1 or 2, wherein the preset register address is an address of a power supply register, and the first data includes a first voltage value; the modifying the first data in the first instruction includes:

Under the condition that the first voltage value is smaller than a first voltage threshold value, reducing the first voltage value by a1 to obtain the second data;

when the first voltage value is larger than or equal to the first voltage threshold value and smaller than a second voltage threshold value, reducing the first voltage value by a2 to obtain the second data;

reducing the first voltage value by a3 under the condition that the first voltage value is larger than or equal to the second voltage threshold value to obtain the second data;

Wherein a1 is smaller than a2 and a2 is smaller than a3.

4. The method of claim 1 or 2, wherein after the listening for the first instruction sent by the host to the SPMI bus, the method further comprises:

Acquiring third data when the slave machine address included in the first instruction is the same as the address of the first slave machine, the first instruction includes the preset register address, and the first instruction is a read instruction; the third data is original configuration data corresponding to the preset register address;

And simulating the first slave to preempt the SPMI bus and sending the third data to the host.

5. The method of claim 4, wherein the integrated circuit device comprises one or more ROM partitions, the one or more ROM partitions storing different categories of raw configuration data; the one or more ROM partitions comprise a first partition, and the category of original configuration data stored by the first partition is the same as the category of data corresponding to the preset register address;

the acquiring third data includes: the third data is obtained from the first partition.

6. The method of claim 1 or 2, wherein after the listening for the first instruction sent by the host to the SPMI bus, the method further comprises:

Determining whether the first slave needs to answer the first instruction or not under the condition that the slave address included in the first instruction is the same as the address of the first slave, the first instruction includes a preset register address and the first instruction is a write instruction;

and under the condition that the first slave needs to answer the first instruction, simulating the first slave to preempt the SPMI bus and answer that the first instruction is received to the host.

7. The method of claim 1 or 2, wherein the integrated circuit device is connected to a central processing unit CPU; after the sending the second instruction to the first slave, the method further includes:

Receiving a third instruction sent by the CPU;

Switching the working mode from the first mode to the second mode based on the third instruction;

After the working mode is switched to the second mode, monitoring an instruction sent to the SPMI bus by the host, and sending an instruction sent to the SPMI bus by the host to the first slave.

8. The method of claim 7, wherein the third instruction comprises an address of the integrated circuit device; the address of the integrated circuit device is determined by a pull-up resistor or a pull-down resistor connected to the integrated circuit device via one or more pins.

9. An integrated circuit device, wherein the integrated circuit device may include a processing module, the integrated circuit device coupled with a memory in an electronic device; the memory is used for storing program instructions; the processing module is configured to read and execute the program instructions, so that the integrated circuit device performs the bus instruction control method according to any one of claims 1 to 8.

10. A SPMI system, wherein said SPMI system includes one or more hosts, a SPMI bus, one or more integrated circuit devices as claimed in claim 9, and one or more slaves, said one or more hosts being respectively connected to said SPMI bus, one end of each of one or more of said integrated circuit devices being connected to said SPMI bus, the other end being connected to a respective slave.

11. The SPMI system of claim 10, wherein in the case where the SPMI system includes a plurality of integrated circuit devices as in claim 9, the address of each of the plurality of integrated circuit devices is determined by a pull-up resistor or a pull-down resistor itself connected through one or more pins; the addresses of the plurality of integrated circuit devices are different from each other.

12. An electronic device comprising the SPMI system and memory of claim 10; the SPMI system is coupled to the memory; the memory is used for storing program instructions.

13. A computer storage medium storing program instructions which, when run on an integrated circuit device, cause the integrated circuit device to perform the bus instruction control method of any one of claims 1 to 8.