CN1181625A - Method for making alignment mark with high staging - Google Patents
Method for making alignment mark with high staging Download PDFInfo
- Publication number
- CN1181625A CN1181625A CN 96120504 CN96120504A CN1181625A CN 1181625 A CN1181625 A CN 1181625A CN 96120504 CN96120504 CN 96120504 CN 96120504 A CN96120504 A CN 96120504A CN 1181625 A CN1181625 A CN 1181625A
- Authority
- CN
- China
- Prior art keywords
- wellblock
- silicon nitride
- implanting ions
- photoresistance pattern
- alignment mark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 61
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 34
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 34
- 150000002500 ions Chemical class 0.000 claims abstract description 32
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 30
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 235000012239 silicon dioxide Nutrition 0.000 claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 2
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 6
- 239000007789 gas Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- 235000019994 cava Nutrition 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
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- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
A method for making align mark of IC includes forming silicon oxide bed and silicon nitride on P-silicon substrate, forming photoresist pattern of align mark as etching mask, etching silicon nitride to form silicon nitride layer forming photoresist pattern of N well area as ion implanation mask, forming N-doping area on P-silicon substrate, removing the pattern, forming photoresist pattern of P well area as ion implanation mask, forming P-doping area on P-silicon substrate, removing the pattern, forming N and P well areas by well area drive, and removing hot SiOs to form a pit as align mark.
Description
The invention relates to the manufacture method of the alignment mark (alignment mark) in the integrated circuit preparation process, particularly about the manufacture method of alignment mark with high ladder.
In the manufacture process of integrated circuit, can produce up-and-down surface topography, these up-and-down surface topographies mark (mark) seemingly on silicon semiconductor substrate can utilize mark as the take second place aligning (alignment) of light shield of the different layers of little shadow exposure manufacture process.For example, isolate between about 1000 to 3000 dusts in field oxide outstanding silicon semiconductor substrate surface of electrical components, just can be used as the alignment mark of little shadow exposure manufacture process.In addition, at twin-well district integrated circuit manufacture process (twin-well p rocess), remove the wellblock and drive in the thermal silicon dioxide that process forms and also can form ladder, so this ladder provides alignment mark, with the usefulness of the aligning that exposes as follow-up little shadow.
In order to obtain enough high alignment mark to obtain comparatively ideal little shadow exposure manufacture process, usually need to increase the time that the people is driven in the wellblock, make to remove and to form highly higher ladder after the wellblock drives in the thermal silicon dioxide that process forms, problem is that it is oversize that some integrated circuit manufacture process does not allow the wellblock to drive in the time.
The present invention's main purpose provides the manufacture method of the alignment mark (alignment mark) that a kind of short wellblock drives in the integrated circuit manufacture process of time.
Another purpose of the present invention provides a kind of manufacture method with alignment mark (high step alignment mark) of high ladder.
The method at first forms silica bed course and silicon nitride on P type silicon semiconductor substrate, then, utilize little shadow technology to form alignment mark photoresistance pattern (alignment mark photoresist pattern), except " alignment mark photoresistance pattern ", all the other are clear zone (clear field), and with described " alignment mark photoresistance pattern " as etching mask (etching mask), utilize the described silicon nitride of electric paste etching technology etching off to form " silicon nitride layer ".
Then, utilize little shadow technology to form N wellblock photoresistance pattern, and with described N wellblock photoresistance pattern as implanting ions mask (implantation mask), see through described " silica bed course " and carry out N type implanting ions, forming N doped region (N-doped region), and soon remove described N wellblock photoresistance pattern at described P type silicon semiconductor substrate.
Then, utilize little shadow technology to form P wellblock photoresistance pattern, and with described P wellblock photoresistance pattern as the implanting ions mask, see through described " silica bed course " and carry out P type implanting ions, forming P doped region (P-doped region), and soon remove described P wellblock photoresistance pattern at described P type silicon semiconductor substrate.
Then, under the environment of high temperature, carry out the wellblock and drive in step, to activate described N doped region and P doped region, to form the N wellblock respectively with P wellblock (N-well and P-well), and drive in process in the wellblock, can form thermal silicon dioxide on " surface, N wellblock ", " surface, P wellblock " and " between the silicon nitride layer ".
Then, the thermal silicon dioxide of removing described " surface, N wellblock ", " surface, P wellblock " and " between the silicon nitride layer " is to form depression (recess) in described " wellblock ", also form depression at " between the silicon nitride layer ", the height of described " silicon nitride layer " adds that " depression between the silicon nitride layer " provides quite high ladder, form an alignment mark (alignment mark), as the usefulness of follow-up little shadow exposure aligning, this is the present invention's a key.
Brief description of drawings is as follows:
Fig. 1 is the processing procedure generalized section of the present invention's embodiment to Fig. 8.
Fig. 1 is the generalized section behind formation silica bed course and the silicon nitride.
Fig. 2 is the generalized section of utilizing after little shadow technology forms alignment mark photoresistance pattern.
Fig. 3 is the generalized section of utilizing behind the described silicon nitride of electric paste etching technology etching off.
Fig. 4 utilizes little shadow technology to form N wellblock photoresistance pattern in " zone, wellblock ", and with described N wellblock photoresistance pattern as the implanting ions mask, see through described " silicon nitride layer " and " silica bed course " and carry out N type implanting ions, with the generalized section after forming the N doped region at described P type silicon semiconductor substrate.
Fig. 5 utilizes little shadow technology to form P wellblock photoresistance pattern in " zone, wellblock ", and with described P wellblock photoresistance pattern as the implanting ions mask, see through described " silicon nitride layer " and " silica bed course " and carry out P type implanting ions, with the generalized section after forming the P doped region at described P type silicon semiconductor substrate.
Fig. 6 is the generalized section behind the photoresistance pattern of the described P of removal wellblock.
Fig. 7 is the generalized section of carrying out after the wellblock drives in, and described wellblock drives in and form thermal silicon dioxide.
Fig. 8 is the generalized section of removing behind the described thermal silicon dioxide of residue.
Below utilize P type silicon semiconductor substrate the present invention's method to be described, but the present invention's method can be extended and is generalized to N type silicon semiconductor substrate as embodiment.
Please refer to Fig. 1, Fig. 2 and Fig. 3.At first on P type silicon semiconductor substrate 1, form silica bed course 3 and silicon nitride 5, as shown in Figure 1, then, utilize little shadow technology to form alignment mark photoresistance pattern 7 (alignment mark photoresist pattern), except " alignment mark photoresistance pattern 7 ", all the other are clear zone (clear field), as shown in Figure 2, and with described " alignment mark photoresistance pattern 7 " as etching mask (etchingmask), utilize the described silicon nitride 5 of electric paste etching technology etching off to form " silicon nitride layer 5A ", after utilizing oxygen plasma and sulfuric acid solution to remove described " alignment mark photoresistance pattern 7 ", as shown in Figure 3.
Described " silica bed course 3 " normally forms with thermal oxidation technique, about 1000 ℃ of oxidizing temperature, and its thickness is between 320 to 380 dusts.Described " silicon nitride 5 " is to form with Low Pressure Chemical Vapor Deposition, about 760 ℃ of its reaction temperature, and the about 350 millitorrs that of reaction pressure, reacting gas is SiH
2Cl
2And NH
3, its thickness is between 1350 to 1650 dusts.In addition, electric paste etching to described " silicon nitride 5 ", can utilize magnetic field enhanced active ion formula electric paste etching technology (MERIE) or electron cyclotron resonace electric paste etching technology (ECR) or traditional active ion formula electric paste etching technology (RIE), normally utilize magnetic field enhanced active ion formula electric paste etching technology, its electricity slurry reacting gas is CF
4, CHF
3, Ar and O
2Gas.
Please refer to Fig. 4.Then, utilize little shadow technology to form N wellblock photoresistance pattern 9, and see through " silica bed course 3 " with described N wellblock photoresistance pattern 9 as the implanting ions mask and carry out N type implanting ions 11, to form N doped region 13, as shown in Figure 4 at described P type silicon semiconductor substrate 1.Usually, the N type ion of formation N doped region 13 is phosphorus (P
31), between 1E13 atom/square centimeter, the implanting ions energy is between 50 to 150Kev between 1E11 for its implanting ions dosage.
Please refer to Fig. 5 and Fig. 6.After utilizing oxygen plasma and sulfuric acid solution to remove described N wellblock photoresistance pattern 9, then, utilize little shadow technology to form P wellblock photoresistance pattern 15, and with described P wellblock photoresistance pattern 15 as the implanting ions mask, see through described " silica bed course 3 " and carry out P type implanting ions 17, to form P doped region 19 (P-doped region), as shown in Figure 5 at described P type silicon semiconductor substrate 1.At last, utilize oxygen plasma and sulfuric acid solution to remove described P wellblock photoresistance pattern 15, as shown in Figure 6.The P type ion that forms described P doped region 19 is boron (B normally
11), also can be boron difluoride (BF
2), between 1E13 atom/square centimeter, its ion implantation energy is then between 10 to 80Kev between 1E12 for its implanting ions dosage.
Please refer to Fig. 7.Then, under the hot environment that contains nitrogen and oxygen, carry out the wellblock and drive in step (we1l drive-in), to activate described N doped region 13 and P doped region 19, to form N wellblock 13A respectively with P wellblock 19A (N-well and P-well), on the other hand, drive in the process in the wellblock, can form thermal silicon dioxide 21A on described " N wellblock 13A " surface and " P wellblock 19A " surface, also between described " silicon nitride layer 5A ", form thermal silicon dioxide 21B, its thickness is between 2000 to 2400 dusts, as shown in Figure 7.
Please refer to Fig. 8.Then, the thermal silicon dioxide 21A that removes described " N wellblock 13A " surface and " P wellblock 19A " surface is to form depression 88 (recess) in described " wellblock ", the thermal silicon dioxide 21B that also removes simultaneously between described " silicon nitride layer 5A " caves in 99 to form between described " silicon nitride layer 5A ", make described silica bed course 3 become silica bed course 3A, as shown in Figure 8.
Please note, the height of described " silica bed course 3A " and " silicon nitride layer 5A " adds the depression 99 between the above " silicon nitride layer 5A ", quite high ladder is provided, form an alignment mark (alignment mark), as the usefulness of follow-up little shadow exposure aligning, this is the present invention's a key.Because of the existence of described " silicon nitride layer 5A ", the time that the wellblock drives in does not need oversize, that is to say, need not form too thick thermal silicon dioxide, so the present invention's method particularly suitable does not allow the wellblock to drive in oversize integrated circuit manufacture process of time at some yet.
After finishing the manufacturing of described alignment mark, can utilize the standard processing procedure to continue follow-up separation process (isolation).
More than be to set forth the present invention, and unrestricted the present invention, and the personage who knows semiconductor technology all can understand, suitably do change slightly and adjust, will not lose the present invention's main idea place, also not break away from the present invention's spirit and scope with preferred embodiment.
Claims (7)
1, a kind of manufacture method of alignment mark of integrated circuit comprises:
(a) on P type silicon semiconductor substrate, form silica bed course and silicon nitride;
(b) utilize little shadow technology to form alignment mark photoresistance pattern;
(c) with described " alignment mark photoresistance pattern " as etching mask, utilize the described silicon nitride of etching technique etching off to form " silicon nitride layer ";
(d) utilize little shadow technology to form N wellblock photoresistance pattern;
(e) with described N wellblock photoresistance pattern as the implanting ions mask, see through " silica bed course " and carry out N type implanting ions, to form the N doped region, remove described N wellblock photoresistance pattern then at described P type silicon semiconductor substrate;
(f) utilize little shadow technology to form P wellblock photoresistance pattern;
(g) with described P wellblock photoresistance pattern as the implanting ions mask, see through " silica bed course " and carry out the P implanting ions, to form the P doped region, remove described P wellblock photoresistance pattern then at described P type silicon semiconductor substrate;
(h) carry out the wellblock and drive in, to form N wellblock and P wellblock, described wellblock drives in and forms thermal silicon dioxide on " surface, N wellblock ", " surface, P wellblock " and " between the silicon nitride layer ";
(i) remove described " thermal silicon dioxide ", to form depression between described " silicon nitride layer ", the height of described " silicon nitride layer " adds that the depression between " silicon nitride layer " provides quite high ladder, forms an alignment mark.
2, manufacture method according to claim 1 is characterized in that: described silica bed course is to form in being rich in the hot environment of oxygen, and temperature is between 800 ℃ to 1000 ℃, and thickness is between 320 to 380 dusts.
3, the manufacture method as described in wanting 1 as right is characterized in that: described silicon nitride, and utilize Low Pressure Chemical Vapor Deposition to form, its thickness is between 320 to 380 dusts.
4, manufacture method as claimed in claim 1 is characterized in that: described N doped region, and utilize the implanting ions technology to form, its ionic species is phosphorus (P
31), between 1E13 atom/square centimeter, the implanting ions energy is between 50 to 150Kev between 1E11 for its implanting ions dosage.
5, manufacture method according to claim 1, wherein said P doped region utilizes the implanting ions technology to form, and its ionic species is boron (B
11) or boron difluoride (BF
2), between 1E13 atom/square centimeter, its implanting ions energy is then between 10 to 80Kev between 1E12 for its implanting ions dosage.
6, manufacture method according to claim 1, wherein said it " alignment mark photoresistance pattern " zone in addition is the clear zone.
7, manufacture method according to claim 1, wherein said P type silicon semiconductor substrate can substitute it with N type silicon semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN96120504A CN1053995C (en) | 1996-11-05 | 1996-11-05 | Method for making alignment mark with high staging |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN96120504A CN1053995C (en) | 1996-11-05 | 1996-11-05 | Method for making alignment mark with high staging |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1181625A true CN1181625A (en) | 1998-05-13 |
| CN1053995C CN1053995C (en) | 2000-06-28 |
Family
ID=5126384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96120504A Expired - Lifetime CN1053995C (en) | 1996-11-05 | 1996-11-05 | Method for making alignment mark with high staging |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1053995C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100449686C (en) * | 2007-08-31 | 2009-01-07 | 江苏宏微科技有限公司 | Manufacturing method of power semi-conductor discrete device first floor photolithography para-position making |
| CN101866119B (en) * | 2009-04-14 | 2012-02-22 | 上海华虹Nec电子有限公司 | Formation method of zero object |
| CN103367251A (en) * | 2012-03-29 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| WO2021008040A1 (en) * | 2019-07-12 | 2021-01-21 | Tcl华星光电技术有限公司 | Dry etching method for film layer structure, and film layer structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4558508A (en) * | 1984-10-15 | 1985-12-17 | International Business Machines Corporation | Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step |
-
1996
- 1996-11-05 CN CN96120504A patent/CN1053995C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100449686C (en) * | 2007-08-31 | 2009-01-07 | 江苏宏微科技有限公司 | Manufacturing method of power semi-conductor discrete device first floor photolithography para-position making |
| CN101866119B (en) * | 2009-04-14 | 2012-02-22 | 上海华虹Nec电子有限公司 | Formation method of zero object |
| CN103367251A (en) * | 2012-03-29 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| WO2021008040A1 (en) * | 2019-07-12 | 2021-01-21 | Tcl华星光电技术有限公司 | Dry etching method for film layer structure, and film layer structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1053995C (en) | 2000-06-28 |
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| C53 | Correction of patent for invention or patent application | ||
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Free format text: CORRECT: PATENTEE; FROM: HETAI SEMICONDUCTOR CO., LTD. TO: LIANHUA ELECTRONICS CO., LTD. |
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| CP01 | Change in the name or title of a patent holder |
Patentee after: United Microelectronics Corporation Patentee before: Hetai Semiconductor Co., Ltd. |
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