CN118160103A - 源晶片、方法和光电子器件 - Google Patents

源晶片、方法和光电子器件 Download PDF

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CN118160103A
CN118160103A CN202280067393.0A CN202280067393A CN118160103A CN 118160103 A CN118160103 A CN 118160103A CN 202280067393 A CN202280067393 A CN 202280067393A CN 118160103 A CN118160103 A CN 118160103A
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wafer
layer
etch stop
release layer
substrate
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杨华
M·德尔奈卡
F·皮特斯
余国民
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Rockley Photonics Ltd
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Abstract

用于微转移印刷工艺中的源晶片。所述源晶片包含：晶片衬底；在器件试样中提供的光子组件，所述器件试样经由释放层附接到所述晶片衬底；和一个或多个蚀刻停止层，其位于所述光子组件和所述晶片衬底之间。

Description

源晶片、方法和光电子器件
发明领域
本发明涉及源晶片、方法和光电子器件。
背景
微转移印刷(MTP)是将由一种材料体系制造的器件集成到由不同材料体系形成的衬底上的新兴技术。例如，将基于III-V族半导体的器件集成到硅平台或主晶片上。在可印刷器件的制造过程期间，与非MTP工艺相比值得注意的步骤是通过除去外延层和衬底之间的牺牲或释放层而从衬底剥离外延层(例如器件试样(device coupon))。这通常通过湿化学蚀刻进行，所述湿化学蚀刻选择性地蚀刻牺牲层并因此除去牺牲层，在试样的底部和衬底之间留下间隙。
一方面，获得试样的平坦或光滑的底表面对于将剥离的试样印刷到目标衬底例如硅上是重要的。表面的平坦度取决于对于从试样的背面(例如下表面)上的层湿法蚀刻牺牲层的选择性。通常，这种选择性不够高，或需要额外的复杂性来提供相关条件(例如非常低的温度)。这导致器件试样的最底表面的弓弯，其可对器件试样与主晶片的结合产生负面影响。
另一方面，MTP工艺的优点之一在于，衬底在器件试样/外延试样剥离之后可以再使用，以降低成本。为了使得这一点能够实现，衬底的表面应该非常平坦和光滑以促进外延生长。
概述
因此，在第一方面中，本发明的实施方案提供用于微转移印刷工艺中的源晶片，所述源晶片包含：
晶片衬底；
在器件试样中提供的光子组件，所述器件试样经由释放层附接到所述晶片衬底；和
一个或多个蚀刻停止层，其位于所述光子组件和所述晶片衬底之间。
提供这样的蚀刻停止层提供了用于微转移印刷工艺中的改进的源晶片。
现在将阐述本发明的任选特征。这些可单独适用或与本发明的任何方面以任何组合适用。
所述一个或多个蚀刻停止层中的蚀刻停止层，例如第一蚀刻停止层，可以位于光子组件和释放层之间。通过在这些层之间提供蚀刻停止层，可以使器件试样的最底表面(即，最靠近晶片衬底的那个表面)更平坦，这可以改进在将器件试样印刷到平台晶片上时的产率。源晶片可以进一步包含位于蚀刻停止层和释放层之间的中间半导体层。该中间半导体层允许衬底再生。通过用湿法蚀刻法蚀刻掉该层，其上具有蚀刻停止层的衬底可以立即再使用且无任何进一步的CMP工艺。这减少了衬底再生成本和加工时间。
所述一个或多个蚀刻停止层中的蚀刻停止层，例如第二蚀刻停止层，可以位于释放层和晶片衬底之间。通过在这些层之间提供蚀刻停止层，可以在已除去器件试样之后保留晶片衬底，并因此可以在其上提供另外的器件试样。源晶片可包含位于释放层和蚀刻停止之间的中间衬底层。原始器件试样正是从该中间衬底层可以已生长。中间衬底层可为至少50nm厚，或至少500nm厚，和/或不大于800nm厚。
释放层可为至少450nm厚，和/或不大于550nm厚，并且可为500nm厚或约500nm厚。
所述蚀刻停止层或各个蚀刻停止层可由多个子层形成，所述多个子层中的两个或更多个子层分别由不同材料形成。在一些实施方案中，各个子层分别由与其它子层不同的材料形成。
所述蚀刻停止层或各个蚀刻停止层可为至少15nm厚和/或不大于25nm厚，并且可为20nm厚或约20nm厚。
所述蚀刻停止层或各个蚀刻停止层可由III-V族半导体形成。所述蚀刻停止层或各个蚀刻停止层可由以下各项中的一种形成：InGaAsP、InGaAs、AlInGeaAs和InP。当所述蚀刻停止层或各个蚀刻停止层由多个子层形成时，所述多个子层中的两个或更多个子层分别由不同的III-V族半导体或III-V族半导体的组合形成。
光子组件可包含多个半导体层，并且可包含一个或多个掺杂层和一个或多个有源层。半导体层可以是III-V族半导体层。光子组件可以是光电子器件，例如调制器、激光器或光电二极管。光子组件可以是波导，并且可以是有源波导(例如其中穿过其的光的性质被有源改变的那种波导)或无源波导(例如其中穿过其的光的性质未被有源改变的那种波导)。光子组件可以至少部分由III-V族半导体形成。
晶片衬底可以由III-V族半导体形成。
在第二方面中，本发明的实施方案提供加工用于微转移印刷工艺的源晶片的方法，所述源晶片包含：
晶片衬底；
在器件试样中提供的光子组件，所述器件试样经由释放层附接到所述晶片衬底；和
在所述器件试样中提供的蚀刻停止层，其位于所述光子组件和所述释放层之间；
所述方法包括蚀刻掉所述释放层的步骤，以从所述晶片衬底释放所述器件试样。
有利地，所述蚀刻停止层起到使所述器件试样的最底表面(即，最靠近所述晶片衬底的那个表面，其可以是或可以不是所述蚀刻停止层)更平坦的作用。
该方法可进一步包括将光子组件从晶片衬底剥离，并将其沉积到平台晶片上以提供光电子器件。
所述源晶片可具有第一方面的源晶片的任选特征中的任何一个或任何组合，前提是它们是相容的。
在第三方面中，本发明的实施方案提供光电子器件，其使用第二方面的方法生产。
可以通过以下方式确定第三方面的光电子器件是使用第二方面的方法生产的，例如：从横截面研究光电子器件的层结构、次级离子质谱分析以识别外延层；x-射线衍射分析以分析外延层晶体结构；源晶片的x-射线光电子能谱分析；和/或研究器件试样的最下表面的平坦度。
在第四方面中，本发明的实施方案提供加工源晶片的方法，所述源晶片包含：
晶片衬底；
在器件试片中提供的光子组件，所述器件试片经由释放层附接到所述晶片衬底；和
蚀刻停止层，其位于所述释放层和所述晶片衬底之间；
所述方法包括以下步骤：
蚀刻掉所述释放层；
剥离所述器件试片；和
蚀刻掉所述蚀刻停止，以暴露所述晶片衬底。
有利地，所述蚀刻停止层起到保留所述晶片衬底的结构的作用(例如，确保其是平坦的，而不需要抛光)，以使该晶片可以再使用。
所述源晶片可具有第一方面的源晶片的任选特征中的任何一个或任何组合，前提是它们是相容的。
所述源晶片可进一步包含位于所述释放层和所述蚀刻停止层之间的中间衬底层；并且该方法可进一步包括在已经剥离所述器件试样之前或之后蚀刻掉所述中间衬底层。
该方法可进一步包括将所述器件试样沉积到平台晶片上以提供光电子器件。
该方法可进一步包括在暴露的晶片衬底上生长另外的释放层，并且在所述另外的释放层上生长另外的器件试样，所述另外的器件试样包含另外的光子组件。该方法可进一步包括蚀刻掉所述另外的释放层，剥离所述另外的器件试样，和将所述另外的器件试样沉积到平台晶片上以提供另外的光电子器件。
该方法可进一步包括生长以下各项：
首先，在所述晶片衬底上方的替换蚀刻停止层；
第二，在所述替换蚀刻停止上方的替换释放层；和
第三，在所述替换释放层上方的包含新光子组件的新器件试样。
该方法可进一步包括在所述替换蚀刻停止层上方生长替换中间衬底层的步骤，其在第一和第二步骤之间进行。
该方法可进一步包括蚀刻掉所述替换释放层，剥离所述新器件试样，和将所述新器件试样沉积到平台晶片上。
在本文中，上方可以指远离晶片衬底的方向，例如垂直于晶片衬底的延伸并远离它。类似地，下方可以指朝向晶片衬底的方向。
在第五方面中，本发明的实施方案提供光电子器件，其使用第四方面的方法生产。
可以通过以下方式确定第五方面的光电子器件是使用第四方面的方法生产的，例如：从横截面研究光电子器件的层结构、次级离子质谱分析以识别外延层；x-射线衍射分析以分析外延层晶体结构；源晶片的x-射线光电子能谱分析；和/或研究器件试样的最下表面的平坦度。
在第六方面中，本发明的实施方案提供光电子器件，其包含：
平台晶片；和
在器件试样中提供的光子组件，所述光子组件结合到所述平台晶片；
其中在所述器件试样中提供的蚀刻停止层位于所述光子组件和所述平台晶片之间。
有利地，所述蚀刻停止层起到使所述器件试样的最底表面(即，最靠近所述平台衬底的那个表面，其可以是或可以不是所述蚀刻停止层)更平坦的作用并因此改进粘附。
所述源晶片可具有第一方面的源晶片的任选特征中的任何一个或任何组合，前提是它们是相容的。
在第七方面中，本发明的实施方案提供制备源晶片的方法，该方法包括以下步骤：在晶片衬底上生长包含光子组件的器件试样，所述器件试样经由释放层附接到所述晶片衬底；和
在所述光子组件和所述晶片衬底之间生长一个或多个蚀刻停止层。
所述源晶片可具有第一方面的源晶片的任选特征中的任何一个或任何组合，前提是它们是相容的。所述一个或多个蚀刻停止层中的蚀刻停止层，例如第一蚀刻停止层，可以生长在所述光子组件和所述释放层之间。所述一个或多个蚀刻停止层中的蚀刻停止层，例如第二蚀刻停止层，可以生长在所述释放层和晶片衬底之间。在本文中，生长可以指外延晶体生长。生长所述一个或多个蚀刻停止层的步骤可以在生长所述器件试样的步骤之前、之后或作为生长所述器件试样的步骤的一部分进行。在其中第二蚀刻停止层生长于所述释放层和所述衬底之间的实施方案中，生长该蚀刻层的步骤在生长所述器件试样之前进行。在其中第一蚀刻停止层生长于所述光子组件和所述释放层之间的实施方案中，生长该蚀刻层的步骤作为生长所述器件试样的一部分进行。在其中生长第一蚀刻停止层和第二蚀刻停止层的实施例中，这些蚀刻停止层可以在不同的时间生长。
在本文中，蚀刻停止层可以指耐受用于蚀刻晶片衬底和/或释放层的蚀刻剂的层。例如，蚀刻停止层可以由与用于制造晶片衬底和/或释放层的材料所不同的材料制造。
本发明包括所描述的方面和优选特征的组合，除这样的组合是明显不可允许或明确避免的情况以外。
本发明的进一步的方面提供：包括代码的计算机程序，所述代码在计算机上运行时造成所述计算机执行第一方面、第四和/或第七方面的方法；计算机可读介质，所述计算机可读介质存储包括代码的计算机程序，所述代码在计算机上运行时造成所述计算机执行第一方面、第四和/或第七方面的方法；和计算机系统，所述计算机系统被编程为执行第一方面、第四和/或第七方面的方法。
附图简述
现在将参考附图就举例而言描述本发明的实施方案，其中：
图1显示了源晶片的横截面视图；
图2显示了变体源晶片的横截面视图，所述变体源晶片具有部分蚀刻的释放层；
图3显示了另外的变体源晶片的横截面视图；
图4显示了变体蚀刻停止层；
图5显示了另外的变体源晶片的横截面视图；和
图6显示了光电子器件。
详述和进一步的任选特征
现在将参考附图讨论本发明的方面和实施方案。进一步的方面和实施方案将对本领域技术人员而言是显而易见的。
图1显示了源晶片100的横截面视图。源晶片包括器件试样120，在该实施方案中其由三个半导体层形成：p掺杂InP层104、有源层(例如，四元有源、MQW或类似物)106和n掺杂InP层108，它们一起提供光子组件(例如电吸收调制器、相位调制器或光电二极管)。p掺杂InP层104被p掺杂InGaAs层102覆盖，层102提供较低的金属接触电阻。在器件试样120下方是释放层110。在该实施方案中，该释放层由InAlAs形成，并且为约500nm厚。在释放层110下方是中间衬底112，其可以由或可以不由与晶片衬底116相同的材料(例如本征/未掺杂的InP)制造。在释放层110下方是蚀刻停止层114。在该实施方案中蚀刻停止层由InGaAsP形成，其耐受用于湿法蚀刻衬底和/或释放层的蚀刻剂。在加工期间，蚀刻深度将被限制在所述释放层和所述蚀刻停止层之间的中间衬底层112中。在所述器件试样已经释放并剥离之后，剩余的中间衬底层112可以用湿法蚀刻除去以暴露蚀刻停止层114。然后，如果需要，则蚀刻停止层114的第二湿法蚀刻步骤可以以对晶片衬底116具有选择性的方式进行(即，使用不与形成衬底116的材料相互作用或不与形成衬底116的材料强相互作用的蚀刻剂)。剩余源晶片的顶表面平坦且光滑，并且处于准备好用于进一步外延生长的状态而不需要抛光。在该实施方案中，蚀刻停止层114为约20nm厚，且所述中间衬底层为500nm至800nm之间厚。
图2显示了具有部分蚀刻的释放层的变体源晶片200的横截面视图。在其与源晶片100共有特征的情况下，类似的特征由类似的附图标记表示。源晶片200与源晶片100的不同之处在于，器件试样620不仅包括层104、106和108，还包括蚀刻停止层202。在该实施方案中蚀刻停止层202由InGaAsP形成。在蚀刻停止层202下方是中间半导体层204，在该实施方案中它是夹在蚀刻停止层202和释放层110(先前讨论的类型)之间的另外的n掺杂InP层。在释放蚀刻(release etch)以除去释放层(这通过底切湿法蚀刻进行)期间，尽管蚀刻剂在所述另外的n掺杂InP层204和释放层110之间具有高蚀刻选择性，但层204仍将被部分蚀刻。此外，由于层204的边缘上的InP将比中心更早地暴露于蚀刻剂，因此层204将因边缘部分比中心蚀刻得更久/更多而在下侧最终呈圆(例如弓弯)形，尤其是在长时间底切释放蚀刻工艺例如用于较大试样的长时间底切释放蚀刻工艺中。箭头206显示该蚀刻的方向。借助在n掺杂InP层108和另外的n掺杂InP层204之间插入的蚀刻停止层202，在释放层110已经完全除去后，可以使用蚀刻停止层202作为硬蚀刻停止快速蚀刻掉另外的n掺杂InP层204。试样的下表面将因此非常平坦，并且可以确保印刷术时改进的产率。可以根据需要保留或选择性除去蚀刻停止层。当除去时，器件试样将不包含蚀刻停止层202。在该实施方案中，蚀刻停止层202为约20nm厚，其中中间半导体层为100nm至300nm之间厚。释放层110为约500nm厚。
图3显示了另外的变体源晶片300的横截面视图。在它与源晶片100和200共有特征的情况下，类似的特征由类似的附图标记表示。实质上，源晶片300是源晶片100和200的组合，因为它包括第一蚀刻停止层202和第二蚀刻停止层114。源晶片300因此同时提供以下二者：器件试样620/120的底面的改进的平坦度以及晶片衬底116的改进的可再使用性。如上所述，蚀刻停止层可以各自为约20nm厚。中间衬底层可以为500nm至800nm之间厚，其中中间半导体层(在该实施方案中是未掺杂的InP)304为100nm至300nm之间厚。释放层为约500nm厚。
图4显示了变体蚀刻停止层。在图1至3中所示的先前实施例中，蚀刻停止层一直是仅由单一材料形成的单个层。然而，这些蚀刻停止层中的任一个可以被多个子层替代，例如第一蚀刻停止子层402和第二蚀刻停止子层404，其组合可用作先前讨论的类型的蚀刻停止层114或202。这为更大范围的湿法蚀刻剂提供保护。在该实施方案中，第一子层由InGaAsP形成，且第二子层由InGaAs形成，尽管可以使用其它III-V族半导体材料。此外，可存在多于两个子层。在一个实施例中，存在四个子层，其具有的组成为：InGaAsP/InP/InGaAsP/InP。
图5显示了另外的变体源晶片500的横截面视图。在它与源晶片100、200和300共有特征的情况下，类似的特征由类似的附图标记表示。源晶片500与源晶片300的不同之处在于，它既不包括中间衬底层也不包括中间半导体层。作为替代，第一蚀刻停止层202直接位于n掺杂InP层108和释放层之间，且第二蚀刻停止层114直接位于释放层110和衬底层116之间。借助这种另外的变型，不需要提供中间层，这意味着不需要蚀刻掉中间层。这意味着更短的外延生长时间和因此更低的成本。
图6显示了光电子器件600。光电子器件600包括位于平台晶片的空腔内的图2、3或5的器件试样620。所述平台晶片包括：器件层606、绝缘体层604和衬底层602。所述器件层可以由硅形成，所述绝缘体层可以由隐埋氧化物形成，以及所述衬底层可以由硅形成。尽管在该实施方案中空腔仅部分延伸穿过器件层，但在其它实施方案中，空腔可以完全延伸穿过器件层，且在又另外的实施方案中，它可以完全延伸穿过器件层和绝缘体层以接触衬底层602。
在本说明书或以下权利要求书或附图中公开的、以其特定形式或就用于执行所公开的功能的手段或用于获得所公开的结果的方法或工艺而言所表达的特征在适当情况下可以单独地或以此类特征的任何组合用于以其多种形式实现本发明。
尽管已经结合上述示例性实施方案描述了本发明，但是当给出本公开时，许多等同的修改和变化将是对本领域技术人员而言显而易见的。因此，上文阐述的本发明的示例性实施方案被认为是说明性的而非限制性的。可以对所描述的实施方案作出各种改变而不脱离本发明的精神和范围。
为避免任何疑问，本文提供的任何理论解释出于改善读者的理解的目的而提供。本发明人不希望受任何这些理论解释的束缚。
本文使用的任何章节标题仅出于组织目的，并且不应被解释为限制所描述的主题。
在本说明书通篇，包括随后的权利要求书中，除非上下文另有要求，否则词语“包含/包括(comprise)”和“包含/包括(include)”以及变型(例如“包含/包括(comprises)”、“包含/包括(comprising)”和“包含/包括(including)”)将被理解为暗示包括指定的整数或步骤或整数或步骤的组，但不排除任何其它整数或步骤或整数或步骤的组。
必须注意，除非上下文另有明确指定，否则如本说明书和所附权利要求书中所用，单数形式“一(a/an)”和“该”包括复数个提及物。范围在本文中可以表示为从“约”一个特定值，和/或至“约”另一个特定值。当表达这样的范围时，另一实施方案包括从一个特定值和/或至另一个特定值。类似地，当通过使用先行词“约(about)”或“约(around)”将值表示为近似值时，将理解的是，该特定值形成另一实施方案。与数值相关的术语“约(about)”或“约(around)”是任选的，并且意指例如+/-10％。
特征的清单
100、200、300、500 源晶片
102 P掺杂InGaAs层
104 P掺杂InP层
106 有源层
108 N掺杂InP层
110 释放层
112 中间衬底
114 蚀刻停止层
116 衬底
120 器件试样
202 蚀刻停止层
204 N掺杂InP层
206 蚀刻方向
302 InP层
620 器件试样
402 第一蚀刻停止子层
404 第二蚀刻停止子层
600 平台晶片
602 衬底
604 绝缘体
606 侧壁

Claims (26)

1.一种用于微转移印刷工艺中的源晶片，所述源晶片包含：
晶片衬底；
在器件试样中提供的光子组件，所述器件试样经由释放层附接到所述晶片衬底；和
一个或多个蚀刻停止层，其位于所述光子组件和所述晶片衬底之间。
2.前述权利要求中任一项所述的源晶片，其中所述一个或多个蚀刻停止层中的蚀刻停止层位于所述释放层和所述晶片衬底之间。
3.权利要求2所述的源晶片，其中中间衬底层位于所述释放层和所述蚀刻停止之间。
4.权利要求3所述的源晶片，其中所述中间衬底层为至少500nm厚且不大于800nm厚。
5.前述权利要求中任一项所述的源晶片，其中所述一个或多个蚀刻停止层中的蚀刻停止层位于所述光子组件和所述释放层之间。
6.权利要求5所述的源晶片，其中所述源晶片进一步包含位于所述蚀刻停止层和所述释放层之间的中间半导体层。
7.前述权利要求中任一项所述的源晶片，其中所述释放层为至少450nm厚且不大于550nm厚。
8.前述权利要求中任一项所述的源晶片，其中所述蚀刻停止层或各个蚀刻停止层由多个子层形成，所述多个子层中的两个或更多个子层分别由不同材料形成。
9.前述权利要求中任一项所述的源晶片，其中所述蚀刻停止层或各个蚀刻停止层为至少15nm厚且不大于25nm厚。
10.前述权利要求中任一项所述的源晶片，其中所述蚀刻停止层或各个蚀刻停止层由以下各项中的一种形成：InGaAsP、InGaAs、AlInGaAs和InP。
11.前述权利要求中任一项所述的源晶片，其中所述光子组件包含多个半导体层。
12.前述权利要求中任一项所述的源晶片，其中所述晶片衬底由III-V族半导体形成。
13.前述权利要求中任一项所述的源晶片，其中所述光子组件至少部分由III-V族半导体形成。
14.一种加工用于微转移印刷工艺的源晶片的方法，所述源晶片包含：
晶片衬底；
在器件试样中提供的光子组件，所述器件试样经由释放层附接到所述晶片衬底；和
在所述器件试样中提供的蚀刻停止层，其位于所述光子组件和所述释放层之间；
所述方法包括蚀刻掉所述释放层的步骤，以从所述晶片衬底释放所述器件试样。
15.权利要求14所述的方法，其进一步包括将所述光子组件从所述晶片衬底剥离，并将其沉积到平台晶片上以提供光电子器件。
16.一种光电子器件，其使用权利要求15所述的方法生产。
17.一种加工源晶片的方法，所述源晶片包含：
晶片衬底；
在器件试片中提供的光子组件，所述器件试片经由释放层附接到所述晶片衬底；和
蚀刻停止层，其位于所述释放层和所述晶片衬底之间；
所述方法包括以下步骤：
蚀刻掉所述释放层；
剥离所述器件试片；和
蚀刻掉所述蚀刻停止，以暴露所述晶片衬底。
18.权利要求17所述的方法，其中所述源晶片进一步包含位于所述释放层和所述蚀刻停止之间的中间衬底层；并且所述方法进一步包括在已经剥离所述器件试样之后蚀刻掉所述中间衬底层。
19.权利要求17或18所述的方法，其进一步包括将所述器件试样沉积到平台晶片上以提供光电子器件。
20.权利要求17、18或19所述的方法，其进一步包括在暴露的晶片衬底上生长另外的释放层，并且在所述另外的释放层上生长另外的器件试样，所述另外的器件试样包含另外的光子组件。
21.权利要求20所述的方法，其进一步包括蚀刻掉所述另外的释放层，剥离所述另外的器件试样，和将所述另外的器件试样沉积到平台晶片上以提供光电子器件。
22.权利要求17所述的方法，其进一步包括生长以下各项：
首先，在所述晶片衬底上方的替换蚀刻停止层；
第二，在所述替换蚀刻停止上方的替换释放层；和
第三，在所述替换释放层顶部的包含新光子组件的新器件试样。
23.权利要求22所述的方法，其进一步包括：
蚀刻掉所述替换释放层，剥离所述新器件试样，和将所述新器件试样沉积到平台晶片上以提供光电子器件。
24.一种光电子器件，其使用权利要求19、21或23所述的方法生产。
25.一种光电子器件，其包含：
平台晶片；和
在器件试样中提供的光子组件，所述光子组件结合到所述平台晶片；
其中在所述器件试样中提供的蚀刻停止层位于所述光子组件和所述平台晶片之间。
26.一种制备源晶片的方法，其包括以下步骤：
在晶片衬底上生长包含光子组件的器件试样，所述器件试样经由释放层附接到所述晶片衬底；和
在所述光子组件和所述晶片衬底之间生长一个或多个蚀刻停止层。
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