CN118157632A - Clock signal generating circuit and clock signal generating method - Google Patents
Clock signal generating circuit and clock signal generating method Download PDFInfo
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Abstract
The embodiment of the application provides a clock signal generating circuit and a clock signal generating method, wherein the circuit comprises a current generating circuit, a voltage regulating circuit, an oscillator and a switch control circuit; the voltage regulating circuit comprises an integrator, a first switch, a second switch, a third switch and a capacitor; outputting a clock signal through the second output terminal of the oscillator; the switch control circuit is respectively connected with the first switch, the second switch and the third switch, and is used for controlling the on or off of the first switch, the second switch and the third switch so as to charge the capacitor with the current generated by the current generation circuit, and then discharge the integrator through the capacitor to make the input voltage of the first input end of the integrator equal to the reference voltage of the second input end of the integrator; the application realizes the frequency output of the oscillating circuit by using the integrator through the loop modulation of the switch control circuit, simultaneously realizes the clamping of the input voltage of the integrator through the charge and discharge of the capacitor, and adjusts the output frequency of the oscillating circuit through the first frequency dividing circuit and the second frequency dividing circuit.
Description
Technical Field
The embodiments of the present application relate to the technical field of oscillating circuits, and in particular, to a clock signal generating circuit and a clock signal generating method.
Background
With the development of industry and automotive electronics, systems provided on chips place increasing demands on the clocks they use. As shown in fig. 1, a relaxation oscillation circuit based on a comparator a in the prior art generates a clock signal, and the working principle is as follows: when the circuit is in phase1, the capacitor C1 is charged through the current Icharge, when the voltage of the upper polar plate of the capacitor reaches vrefh, the comparator turns over, and the control logic B of the later stage switches control signals phase1 and phase2 to enable the circuit to enter phase2; when the circuit is in phase2, the capacitor C1 discharges through the current IDISCHARGE, when the voltage of the upper polar plate of the capacitor is lower than vrefl, the comparator turns over, and the control logic B of the later stage switches the control signals phase1 and phase2 to enable the circuit to return to phase1; thus, one period T is completed, where the control signals phase1 and phase2 are clock signals with period T. The circuit can generate stable clock signals by circulating and reciprocating in this way. Ideally, the clock period is T= (vrefh-vrefl) C1/Icharge+ (vrefh-vrefl) C1/IDISCHARGE.
There are two main disadvantages to comparator-based relaxation oscillators: the period T of the relaxation oscillator is determined by vrefh, vrefl, C1, icharge and IDISCHARGE, and in terms of practical engineering implementation, the flip delay of the comparator and the delay of the post-stage control logic also need to be considered, if the clock period is to be reduced, the relaxation oscillator cannot be realized in a low-power consumption mode; secondly, the offset voltage voffset exists in the comparator, so that the comparator can be inverted only when the differential input end of the comparator is larger than the voffset, the error is converted into the output frequency of the oscillator, the voffset can change along with the temperature, and the output precision of the oscillator is affected.
Disclosure of Invention
An object of the present invention is to solve or alleviate the technical problems in the prior art, and in a first aspect, an embodiment of the present invention provides a clock signal generating circuit, including: a current generation circuit, a voltage regulation circuit, an oscillator and a switch control circuit;
the voltage regulating circuit comprises an integrator, a first switch, a second switch, a third switch and a capacitor;
The current generating circuit is connected with one end of the first switch, one end of the second switch and one end of the capacitor are respectively connected with a common end between the other end of the first switch and one end of the third switch, and the other end of the capacitor and the other end of the second switch are connected with a grounding end;
The first input end of the integrator is connected with the other end of the third switch, the output end of the integrator is connected with the grid electrode of the PMOS tube, the drain electrode of the PMOS tube is connected with the oscillator, and the source electrode of the PMOS tube is connected with the current source;
the first output end of the oscillator is connected with the switch control circuit so as to output the input signal of the switch control circuit, and the clock signal is output through the second output end of the oscillator;
The switch control circuit is respectively connected with the first switch, the second switch and the third switch, and is used for controlling the on or off of the first switch, the second switch and the third switch through the switch control circuit so as to charge the capacitor through the current generated by the current generating circuit and discharge the integrator through the capacitor, so that the input voltage of the first input end of the integrator is equal to the reference voltage of the second input end of the integrator.
As a preferred embodiment of the present application, the circuit generating circuit includes an operational amplifier, an NMOS transistor, a first resistor, and a current mirror;
The first input end of the operational amplifier is connected with the output end of the negative temperature coefficient voltage generating circuit, the negative temperature coefficient voltage is generated to be input into the operational amplifier through the negative temperature coefficient voltage, the second input end of the operational amplifier is connected with the common end between the source electrode of the NMOS tube and the first resistor, the output end of the operational amplifier is connected with the grid electrode of the NMOS tube, the drain electrode of the NMOS tube is connected with the current mirror, and the current is output through the current mirror.
As a preferred embodiment of the application, a second resistor is arranged between the source electrode of the PMOS tube and the current source.
As a preferred embodiment of the present application, the switch control circuit includes a first switch control sub-circuit, a second switch control sub-circuit, and a third switch control sub-circuit;
The first switch control sub-circuit comprises a signal processing circuit and a first frequency dividing circuit which are connected with each other in sequence; the input end of the signal processing circuit is connected with the first output end of the oscillator, and an output signal of the output end of the first frequency dividing circuit is transmitted to the first switch to control the turn-off and turn-on of the first switch;
The third switch control sub-circuit comprises a delay circuit and a first AND gate; the output signal of the output end of the signal processing circuit is transmitted to the input end of the delay circuit and the first input end of the first and the gate, the output signal of the output end of the delay circuit is transmitted to the second input end of the first and the gate, the output signal of the output end of the first frequency dividing circuit is transmitted to the third input end of the first and the gate through the output signal of the output end of the inverting circuit, and the output signal of the output end of the first and the gate is transmitted to the third switch for controlling the turn-off and turn-on of the third switch;
The second switch control sub-circuit comprises a NOR gate and a second AND gate; the output signal of the output end of the signal processing circuit is transmitted to the first input end of the NOR gate, the output signal of the output end of the delay circuit is transmitted to the second input end of the NOR gate, the output signal of the output end of the NOR gate is transmitted to the first input end of the second AND gate, the output signal of the output end of the inverting circuit is transmitted to the second input end of the second AND gate, and the output signal of the output end of the second AND gate is transmitted to the second switch for controlling the turn-off and turn-on of the second switch.
As a preferred embodiment of the present application, the signal processing circuit includes a first buffer, a second frequency dividing circuit, and a first level converting circuit connected to each other in this order;
the first buffer input end is connected with the first output end of the oscillator, and the first level conversion circuit output end is connected with the first frequency division circuit input end.
As a preferred embodiment of the present application, the first buffer and the second frequency dividing circuit are further connected to the drain electrode of the NMOS transistor;
The first level conversion circuit, the first frequency division circuit, the inverting circuit, the delay circuit, the AND gate, the NOR gate and the AND gate are also connected with the second buffer.
As a preferred embodiment of the present application, the second output terminal of the oscillator is provided with a second level shifter circuit.
Compared with the prior art, the embodiment of the application provides a clock signal generating circuit, which comprises a current generating circuit, a voltage regulating circuit, an oscillator and a switch control circuit; the voltage regulating circuit comprises an integrator, a first switch, a second switch, a third switch and a capacitor; outputting a clock signal through the second output terminal of the oscillator; the switch control circuit is respectively connected with the first switch, the second switch and the third switch, and is used for controlling the on or off of the first switch, the second switch and the third switch so as to charge the capacitor with the current generated by the current generation circuit, and then discharge the integrator through the capacitor to make the input voltage of the first input end of the integrator equal to the reference voltage of the second input end of the integrator; according to the application, the frequency output of the oscillator is realized by using the integrator through the loop modulation of the switch control circuit, meanwhile, the input voltage of the integrator is clamped through the charge and discharge of the capacitor, and the output frequency of the oscillator is regulated through the first frequency dividing circuit and the second frequency dividing circuit.
In a second aspect, an embodiment of the present application further provides a clock signal generating method, which is implemented by the clock signal generating circuit in the first aspect, where the method includes:
Acquiring current output by a current generating circuit;
the first switch is controlled to be turned on through the first switch control sub-circuit, the second switch is controlled to be turned off through the second switch control sub-circuit, the third switch is controlled to be turned off through the third switch control sub-circuit, and the capacitor is charged;
the first switch is controlled to be turned off through the first switch control sub-circuit, the second switch is controlled to be turned off through the second switch control sub-circuit, the third switch is controlled to be turned on through the third switch control sub-circuit, and the capacitor discharges the integrator to achieve that the voltage of the first input end and the voltage of the second input end of the integrator are equal;
After the voltage is output by the integrator, the power supply voltage of the oscillator is regulated by the PMOS tube;
And controlling the oscillator to output a clock signal through the regulated voltage.
As a preferred embodiment of the present application, the method further comprises:
The first switch is controlled to be turned off through the first switch control sub-circuit, the second switch is controlled to be turned on through the second switch control sub-circuit, the third switch is controlled to be turned off through the third switch control sub-circuit, and the electric charge on the capacitor is cleared.
Compared with the prior art, the clock signal generating method provided in the second aspect has the same advantages as those provided in the first aspect, and is not described herein.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. Some specific embodiments of the application will be described in detail hereinafter by way of example and not by way of limitation with reference to the accompanying drawings. The same reference numbers in the drawings denote the same or similar parts or portions, and it will be understood by those skilled in the art that the drawings are not necessarily drawn to scale, in which:
FIG. 1 is a schematic diagram of a prior art clock signal generation circuit;
FIG. 2 is a schematic diagram of a clock signal generating circuit according to an embodiment of the present application;
FIG. 3 is a waveform diagram of a control signal generated by loop modulation according to an embodiment of the present application;
fig. 4 is a graph of the power-on waveform after being enabled according to the embodiment of the present application.
Detailed Description
In order to enable those skilled in the art to better understand the present application, the following description will make clear and complete descriptions of the technical solutions according to the embodiments of the present application with reference to the accompanying drawings. It will be apparent that the described embodiments are merely some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
As shown in fig. 2, an embodiment of the present application provides a clock signal generating circuit, including: a current generation circuit, a voltage adjustment circuit, an oscillator 12, and a switch control circuit;
The voltage regulating circuit comprises an integrator 08, a first switch 05, a second switch 06, a third switch 07 and a capacitor 04;
The current generating circuit is connected with one end of the first switch 05, one end of the second switch 06 is connected with one end of the capacitor 04 and a common end between the other end of the first switch 05 and one end of the third switch 07 respectively, and the other end of the capacitor 04 and the other end of the second switch 06 are connected with a grounding end;
The first input end of the integrator 08 is connected with the other end of the third switch 07, the output end of the integrator 08 is connected with the grid electrode of the PMOS tube 11, the drain electrode of the PMOS tube 11 is connected with the input end of the oscillator 12, and the source electrode of the PMOS tube 11 is connected with the current source 10;
The first output end of the oscillator 12 is connected with the switch control circuit so as to output the input signal of the switch control circuit, and the clock signal is output through the second output end of the oscillator 12;
The switch control circuit is respectively connected with the first switch 05, the second switch 06 and the third switch 07, and controls the on or off of the first switch 05, the second switch 06 and the third switch 07 through the switch control circuit, so that after the capacitor 04 is charged by the current generated by the current generating circuit and the integrator 08 is discharged through the capacitor 04, the input voltage of the first input end of the integrator 08 is equal to the reference voltage of the second input end of the integrator 08.
In the embodiment of the application, the current generating circuit is mainly used for generating the current of the voltage regulating circuit, and the current generating circuit is equivalent to the current source of the voltage regulating circuit, generates the current through the current generating circuit and inputs the current into the voltage regulating circuit.
Specifically, the first switch 05 is controlled to be turned on by the control switch control circuit, the second switch 06 is controlled to be turned off by the switch control circuit, the third switch 07 is controlled to be turned off by the switch control circuit, and the capacitor 04 is charged; then the first switch 05 is controlled to be turned off by a switch control circuit, the second switch 06 is controlled to be turned off by a switch control circuit, the third switch 07 is controlled to be turned on by a switch control circuit, and the capacitor 04 discharges the integrator 08 to realize that the voltages of the first input end and the second input end of the integrator 08 are equal; the first switch 05 is controlled to be turned off by the switch control circuit, the second switch 06 is controlled to be turned on by the switch control circuit, the third switch 07 is controlled to be turned off by the switch control circuit, and the charge on the capacitor 04 is reset and then the charge and discharge process of the capacitor 04 in the next period is carried out. The application realizes the frequency output of the oscillator 12 through the loop modulation of the switch control circuit by utilizing the integrator 08, and simultaneously realizes the method of equalizing the voltage of the second input end of the integrator 08 and the first input end of the integrator 08 through the charge and discharge of the capacitor 04. In the embodiment of the present application, the first input end of the integrator 08 is a positive input end, and the second input end of the integrator 08 is a negative input end.
In the embodiment of the present application, the first input terminal of the integrator 08 inputs the voltage with the reference voltage of 1V, the second input terminal of the integrator 08 receives the regulated voltage outputted by the voltage regulating circuit, the integrator 08 is also connected to the second buffer circuit 22, so that the electronic device can be mainly operated under low voltage, and the PMOS transistor 11 is mainly used for outputting a controlled voltage to the oscillator 12, that is, the output voltage of the integrator 08 can be regulated.
In the embodiment of the present application, a second resistor 02 is disposed between the source of the PMOS transistor 11 and the current source 10, and the second resistor 02 is mainly used to make the output voltage variation of the integrator 08 more linear.
In a preferred embodiment of the present application, the circuit generating circuit includes an operational amplifier 01, an NMOS tube 03, a first resistor 09 and a current mirror;
the first input end of the operational amplifier 01 is connected with the output end of the negative temperature coefficient voltage generating circuit, the negative temperature coefficient voltage is input to the operational amplifier 01 through the negative temperature coefficient voltage generating circuit, the second input end of the operational amplifier 01 is connected with a common end between the source electrode of the NMOS tube 03 and the first resistor 09, the output end of the operational amplifier 01 is connected with the grid electrode of the NMOS tube 03, the drain electrode of the NMOS tube 03 is connected with the current mirror, and current is output through the current mirror.
Specifically, the negative temperature coefficient voltage is mainly obtained through the difference between the reference voltage on the chip and the positive temperature coefficient voltage of the chip, so that the first input end of the operational amplifier 01 has a fixed negative temperature coefficient voltage, the voltage of the first input end and the voltage of the second input end of the operational amplifier 01 are the same, the voltage of the circuit where the second resistor 02 is located is also the input voltage of the first input end of the operational amplifier 01, the current is obtained according to ohm law through the input voltage of the first input end of the operational amplifier 01 and the second resistor 02, the charging current of the capacitor 04 is obtained after the current is mirrored through the current mirror, the first output end of the operational amplifier 01 is the positive input end, and the second input end of the operational amplifier 01 is the negative input end.
The switch control circuit comprises a first switch control sub-circuit, a second switch control sub-circuit and a third switch control sub-circuit;
The first switch control sub-circuit comprises a signal processing circuit and a first frequency dividing circuit 16 which are sequentially connected with each other; the input end of the signal processing circuit is connected with the first output end of the oscillator 12, and the output signal of the output end of the first frequency dividing circuit 16 is transmitted to the first switch 05 to control the turn-off and turn-on of the first switch 05;
The third switch control sub-circuit comprises a delay circuit 18 and a first and gate 19; an output signal of the output end of the signal processing circuit is sent to an input end of a delay circuit 18 and a first input end of a first and gate 19, an output signal of the output end of the delay circuit 18 is sent to a second input end of the and gate, an output signal of the output end of the inverting circuit 17 is sent to a third input end of the first and gate 19, and an output signal of the output end of the first and gate 19 is sent to a third input end of the first and gate 19, and the second switch 06 is used for controlling the turn-off and turn-on of the third switch 07;
The second switch control sub-circuit comprises a nor gate 20 and a second and gate 21; the output signal of the output end of the signal processing circuit is sent to the first input end of the or second NOT gate, the output signal of the output end of the delay circuit 18 is sent to the second input end of the NOR gate 20, the output signal of the output end of the NOR gate 20 is sent to the first input end of the second AND gate 21, the output signal of the output end of the first frequency dividing circuit 16 is sent to the second input end of the second AND gate 21 through the output signal of the inverting circuit 17, and the output signal of the output end of the second AND gate 21 is sent to the second switch 06 for controlling the turn-off and turn-on of the second switch 06.
As a preferred embodiment of the present application, the signal processing circuit includes a first buffer 13, a second frequency dividing circuit 14, and a first level converting circuit 15, which are sequentially connected to each other;
the input end of the first buffer 13 is connected with the first output end of the oscillator 12, and the output end of the first level conversion circuit 15 is connected with the input end of the first frequency division circuit 16.
In the embodiment of the present application, the signal processing circuit in the first switch control sub-circuit firstly shapes and delays the signal output from the first output end of the oscillator 12 through the first buffer 13, then performs the frequency division processing through the second frequency dividing circuit 14, and the main function of the second frequency dividing circuit 14 makes the output signal frequency be the electronic circuit of the integral fraction of the input signal frequency. For any one of the divide-by-N frequency dividers, the output signal may have a phase of 2pi/N, with the input signal unchanged. In the embodiment of the present application, the second frequency dividing circuit 14 is mainly used for performing frequency division processing on the signal output by the first buffer 13, the signal processed by the second frequency dividing circuit 14 then converts the analog signal into a digital signal through the first level converting circuit 15, the digital signal is output to the inverting circuit 17 for performing phase inversion processing on the signal after being subjected to frequency division again by the first frequency dividing circuit 16, and the inverted digital signal is a control signal of the first switch 05 to further control the turn-off and turn-on of the first switch 05. In addition, the first buffer 13 and the second frequency dividing circuit 14 are also connected to the drain of the NMOS 03, so as to supply power.
In the third switch control sub-circuit, the signal output by the first level conversion circuit 15 is received through the delay circuit 18, then the signal is delayed and output to the first and gate 19, whether the output signal is high or low is determined by the first and gate 19 according to whether the signals input by the first input end, the second input end and the third input end are high or low, and then the control signal of the third switch 07 is output through the first and gate 19 to further control the turn-off and turn-on of the third switch 07.
In the second switch control sub-circuit, whether the output signal is high level or low level is determined by whether the signals of the first input end, the second input end and the third input end of the nor gate are high level or low level, then the output signal is transmitted to the second and gate 21 through the nor gate, the second and gate 21 determines whether the output signal is high level or low level according to whether the signals of the first input end, the second input end and the second input end are high level or low level, and then the control signal of the second switch 06 is output through the second and gate 21 so as to control the turn-off and turn-on of the second switch 06.
In the embodiment of the present application, in order to make the whole circuit work in the low power consumption mode, the first level conversion circuit 15, the first frequency division circuit 16, the inverting circuit 17, the delay circuit 18, the first and gate 19, the nor gate 20 and the second and gate 21 are further connected to the second buffer 22, and the second buffer 22 can make the oscillating circuit of the embodiment of the present application use the internal power supply, so that the function of the clock signal generating circuit can be realized with lower power consumption.
As a preferred embodiment of the present application, the second output terminal of the oscillating circuit is provided with a second level shifter 23, and the level signal output by the second output terminal of the oscillator can be shifted by the second level shifter 23, so as to output a clock signal.
In the embodiment of the application, negative temperature coefficient voltage vbg-vptat (vbg refers to the output voltage of a band gap reference, the band gap reference is a circuit for generating zero temperature voltage reference, the output value generated by the band gap reference is generally 1.2V, vptat (ptat is proportional to absolute temperature for short) refers to positive temperature coefficient voltage, the operational amplifier 01 can enable the second input end of the operational amplifier 01 to be clamped at the negative temperature coefficient voltage vbg-vptat, the current of the current generating circuit is I= (vbg-vptat)/R0, wherein R0 is the resistance value of a first resistor 09, a current mirror is used for mirroring the current I by k times to obtain Ichg=k (vbg-vptat)/R0, the current generated by the current generating circuit is used for periodically charging and discharging the capacitor 04, the specific time sequence control logic is that the first switch 05 controlled by the first switch 05 outputs a p 1-pre signal, the third switch 07 controls the sub-circuit to output a rsw signal, and the second switch 07 controls the current to turn-off the second switch circuit to turn-off the capacitor 04, and the third switch 07 controls the current to turn-off the capacitor 3706; the first switch 05 is controlled to be turned off by the output p1_pre signal of the first switch 05, the third switch 07 is controlled to be turned on by the output sw signal of the third switch 07, the second switch 06 is controlled to be turned off by the output rst signal of the second switch 06, the vcap voltage is discharged to the integrator 08, the discharging voltage is vint _n, the first switch 05 is controlled to be turned off by the output p1_pre signal of the first switch 05, the third switch 07 is controlled to be turned off by the output sw signal of the third switch 07, the second switch 06 controls the second switch 06 controlled by the rst signal output by the sub-circuit to be turned on, so that the charge on the capacitor 04 is discharged, and one period is completed.
The output end of the integrator 08 controls the grid electrode of one PMOS tube 11 to generate the internal power supply voltage vctrl1 of the oscillator 12; vco output frequency f is the output frequency of the oscillator 12; the third switch 07 control signal sw, the second switch 06 control signal rst and the first switch 05 control signal p1_pre are generated after the frequency is divided by the second frequency dividing circuit 14N, for example, when vcap voltage is higher than vref_1v (the reference voltage input to the first input terminal of the integrator 08), vctrl1 increases, the oscillation frequency of the oscillator 12 increases, the charging time of the capacitor 04 in the next modulation period decreases, and vcap voltage decreases. After such negative feedback loop modulation vint _n will eventually be clamped at a voltage of vref=1v.
To reduce the frequency sensitivity to voltage, a second buffer 22 is added to convert the input power vdd_in to a 3.2V regulated power supply avdd to power the oscillating circuit.
The use of ichg=k (vbg-vptat)/R0 is mainly to compensate the negative temperature coefficient of the second resistor 02, and the voltage of vptat can be appropriately adjusted to compensate the influence of the temperature coefficient of the leakage current of the capacitor 04 and the NMOS 03. Wherein the temperature coefficient of the second resistor 02 is about +/-2.5% (negative temperature coefficient); the temperature coefficient of the capacitor 04 is about-0.16% -0.39% (positive temperature coefficient), and the temperature coefficient of the leakage current contribution of the NMOS tube 03 affecting the output frequency is about 0.35%.
The output frequency f_out of the oscillating circuit can be obtained by the following formula:
f_out＝N*Ichg/C0/Vref_1V,Ichg＝k*(vbg-vptat)/R0,f_out＝N*k*(vbg-vptat)/R0/C0/Vref_1V；
As shown in fig. 3, y0 is an output of the output clock signal after divided by N by the second frequency dividing circuit 14; y0_d is a signal processed by y0 through a delay circuit; p1_pre is a signal obtained by dividing y0 by the first frequency dividing circuit 16; p1_pre_b is a signal after passing through the inverting circuit 17, and p1_pre_b is an inverted signal of p1_pre; sw is the output signal of p1_pre_b, y0 and y0_d after passing through the first AND gate 1919; rst is the output of y0 and y0_d through the NOR gate and p1_pre_b through the second AND gate. Where sw and rst are non-overlapping signals to ensure that the charge at node vint _n is not drained via the switches controlled by the sw and rst signals.
As shown in fig. 4, when the en_osc signal goes high from low, the internal second buffer 22 starts outputting the internal power voltage avdd of 3.2V; the en_osc is delayed by 25us by a delay circuit to generate a signal ena, so that the internal power supply voltage avdd can be completely established; delaying ena by 45us to generate a signal enc by using a delay circuit, so that the internal Ichg current and the integrator 08 can be completely established; enabling vco after enc is turned high, starting oscillation of the oscillator 12, outputting a clock signal, and keeping the output frequency stable after a period of time. The clock signal output with high precision is realized, namely, the power supply voltage and the temperature are changed, and the oscillator circuit can still output stable and accurate clock signals within a certain range.
According to the embodiment of the application, the temperature coefficient of the output frequency of the clock signal generating circuit can be effectively adjusted by adjusting the temperature coefficient of the Ichg current, and the output frequency of the clock signal generating circuit can be stabilized between 39.42MHz and 40.09MHz by changing the power supply voltage and the temperature after the clock signal generating circuit is adjusted at normal temperature, and the precision is +0.225% to-1.45%; the power consumption is 162.5 uA-202.2 uA; a maximum of about 95.8us is required from the enabling of the clock signal generating circuit to the completion of the clock output frequency establishment.
In a second aspect, an embodiment of the present application further provides a clock signal generating method, implemented by the clock signal generating circuit in any one of the first aspect, where the method includes:
Acquiring current output by a current generating circuit;
The first switch 05 is controlled to be turned on through a first switch 05 control sub-circuit, the second switch 06 is controlled to be turned off through a second switch control sub-circuit, the third switch 07 is controlled to be turned off through a third switch control sub-circuit, and the capacitor 04 is charged;
the first switch 05 is controlled to be turned off through the first switch control sub-circuit, the second switch 06 is controlled to be turned off through the second switch control sub-circuit, the third switch 07 is controlled to be turned on through the third switch control sub-circuit, and the capacitor 04 discharges the first input end of the integrator 08 to achieve equal voltage of the first input end and the second input end of the integrator 08;
After the voltage is output by the integrator 11, the power supply voltage of the oscillator 12 is regulated by the PMOS tube 11;
And controlling the oscillating circuit to output a clock signal through the regulating voltage.
The method further comprises the steps of:
The first switch 05 is controlled to be turned off through the first switch control sub-circuit, the second switch 06 is controlled to be turned on through the second switch control sub-circuit, the third switch 07 is controlled to be turned off through the third switch control sub-circuit, and the electric charge on the capacitor 04 is reset.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (9)
1. A clock signal generation circuit, comprising: a current generation circuit, a voltage regulation circuit, an oscillator and a switch control circuit;
the voltage regulating circuit comprises an integrator, a first switch, a second switch, a third switch and a capacitor;
The current generating circuit is connected with one end of the first switch, one end of the second switch and one end of the capacitor are respectively connected with a common end between the other end of the first switch and one end of the third switch, and the other end of the capacitor and the other end of the second switch are connected with a grounding end;
The first input end of the integrator is connected with the other end of the third switch, the output end of the integrator is connected with the grid electrode of the PMOS tube, the drain electrode of the PMOS tube is connected with the oscillator, and the source electrode of the PMOS tube is connected with the current source;
the first output end of the oscillator is connected with the switch control circuit so as to output the input signal of the switch control circuit, and the clock signal is output through the second output end of the oscillator;
The switch control circuit is respectively connected with the first switch, the second switch and the third switch, and is used for controlling the on or off of the first switch, the second switch and the third switch through the switch control circuit so as to charge the capacitor through the current generated by the current generating circuit and discharge the integrator through the capacitor, so that the input voltage of the first input end of the integrator is equal to the reference voltage of the second input end of the integrator.
2. The clock signal generation circuit of claim 1, wherein the circuit generation circuit comprises an operational amplifier, an NMOS transistor, and a first resistor and a current mirror;
The first input end of the operational amplifier is connected with the output end of the negative temperature coefficient voltage generating circuit, negative temperature coefficient voltage is input to the operational amplifier through the negative temperature coefficient voltage input circuit, the second input end of the operational amplifier is connected with a common end between the source electrode of the NMOS tube and the first resistor, the output end of the operational amplifier is connected with the grid electrode of the NMOS tube, the drain electrode of the NMOS tube is connected with the current mirror, and current is output through the current mirror.
3. The clock signal generating circuit according to claim 1, wherein a second resistor is arranged between the source of the PMOS transistor and the current source.
4. The clock signal generation circuit of claim 1, wherein the switch control circuit comprises a first switch control sub-circuit, a second switch control sub-circuit, and a third switch control sub-circuit;
The first switch control sub-circuit comprises a signal processing circuit and a first frequency dividing circuit which are connected with each other in sequence; the input end of the signal processing circuit is connected with the first output end of the oscillator, and an output signal of the output end of the first frequency dividing circuit is transmitted to the first switch to control the turn-off and turn-on of the first switch;
The third switch control sub-circuit comprises a delay circuit and a first AND gate; ; the output signal of the output end of the signal processing circuit is transmitted to the input end of the delay circuit and the first input end of the first and the gate, the output signal of the output end of the delay circuit is transmitted to the second input end of the first and the gate, the output signal of the output end of the first frequency dividing circuit is transmitted to the third input end of the first and the gate through the output signal of the output end of the inverting circuit, and the output signal of the output end of the first and the gate is transmitted to the third switch for controlling the turn-off and turn-on of the third switch;
The second switch control sub-circuit comprises a NOR gate and a second AND gate; the output signal of the output end of the signal processing circuit is transmitted to the first input end of the NOR gate, the output signal of the output end of the delay circuit is transmitted to the second input end of the NOR gate, the output signal of the output end of the NOR gate is transmitted to the first input end of the second AND gate, the output signal of the output end of the inverting circuit is transmitted to the second input end of the second AND gate, and the output signal of the output end of the second AND gate is transmitted to the second switch for controlling the turn-off and turn-on of the second switch.
5. The clock signal generation circuit of claim 4, wherein the signal processing circuit comprises a first buffer, a second frequency dividing circuit, and a first level shifting circuit connected to each other in order;
the first buffer input end is connected with the first output end of the oscillator, and the first level conversion circuit output end is connected with the first frequency division circuit input end.
6. The clock signal generation circuit of claim 5, wherein the first buffer and the second frequency divider are further connected to the drain of the PMOS transistor;
The first level conversion circuit, the first frequency division circuit, the inverting circuit, the delay circuit, the AND gate, the NOR gate and the AND gate are also connected with the second buffer.
7. A clock signal generation circuit according to claim 1, wherein the oscillator second output is provided with a second level shift circuit.
8. A clock signal generation method realized by the clock signal generation circuit according to any one of claims 1 to 7, the method comprising:
Acquiring current output by a current generating circuit;
the first switch is controlled to be turned on through the first switch control sub-circuit, the second switch is controlled to be turned off through the second switch control sub-circuit, the third switch is controlled to be turned off through the third switch control sub-circuit, and the capacitor is charged;
the first switch is controlled to be turned off through the first switch control sub-circuit, the second switch is controlled to be turned off through the second switch control sub-circuit, the third switch is controlled to be turned on through the third switch control sub-circuit, and the capacitor discharges the integrator to achieve that the voltage of the first input end and the voltage of the second input end of the integrator are equal;
After the voltage is output by the integrator, the power supply voltage of the oscillator is regulated by the PMOS tube;
And controlling the oscillator to output a clock signal through the regulated voltage.
9. The clock signal generation method of claim 8, wherein the method further comprises:
The first switch is controlled to be turned off through the first switch control sub-circuit, the second switch is controlled to be turned on through the second switch control sub-circuit, the third switch is controlled to be turned off through the third switch control sub-circuit, and the electric charge on the capacitor is cleared.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311779570.0A CN118157632A (en) | 2023-12-21 | 2023-12-21 | Clock signal generating circuit and clock signal generating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311779570.0A CN118157632A (en) | 2023-12-21 | 2023-12-21 | Clock signal generating circuit and clock signal generating method |
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| Publication Number | Publication Date |
|---|---|
| CN118157632A true CN118157632A (en) | 2024-06-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311779570.0A Pending CN118157632A (en) | 2023-12-21 | 2023-12-21 | Clock signal generating circuit and clock signal generating method |
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| Country | Link |
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| CN (1) | CN118157632A (en) |
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- 2023-12-21 CN CN202311779570.0A patent/CN118157632A/en active Pending
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