CN118139472A - Display panel, preparation method of display panel and display device - Google Patents

Abstract

The embodiment of the disclosure provides a display panel, a preparation method of the display panel and a display device, and relates to the technical field of display. The display panel comprises a substrate, a pixel definition layer, a light-emitting functional layer and a partition structure. The pixel defining layer is located on one side of the substrate. The pixel definition layer is provided with a plurality of pixel openings, and the pixel openings comprise a first pixel opening and a second pixel opening which are adjacently arranged. The light-emitting functional layer is positioned on one side of the pixel definition layer far away from the substrate, and comprises a first light-emitting layer, a charge generation layer and a second light-emitting layer. The partition structure is located between the first pixel opening and the second pixel opening. At least the charge generation layer in the light emitting functional layer is disconnected at the partition structure. The partition structure is far away from the surface of the substrate, and is close to the substrate compared with the surface of the pixel definition layer far away from the substrate; or the surface of the partition structure away from the substrate is flush with the surface of the pixel defining layer away from the substrate. The display panel is used for displaying images.

Description

Display panel, preparation method of display panel and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a display panel, a preparation method of the display panel and a display device.

Background

With the continuous development of display technology, display devices have been gradually spread throughout the life of people. Among them, an Organic Light-Emitting Diode (OLED) display panel has advantages of self-luminescence, low power consumption, wide viewing angle, fast response speed, high contrast ratio, etc., so it is widely used in display devices such as mobile phones, televisions, notebook computers, etc.

Disclosure of Invention

An embodiment of the disclosure is directed to a display panel, a manufacturing method of the display panel, and a display device, which are used for avoiding crosstalk between a first sub-pixel and a second sub-pixel caused by a charge generation layer with high conductivity and improving a display effect of the display panel.

In order to achieve the above object, the embodiments of the present disclosure provide the following technical solutions:

In one aspect, a display panel is provided. The display panel comprises a substrate, a pixel definition layer, a light-emitting functional layer and a partition structure.

The pixel defining layer is located at one side of the substrate. The pixel definition layer is provided with a plurality of pixel openings, and the pixel openings comprise a first pixel opening and a second pixel opening which are adjacently arranged.

A light emitting function layer located at one side of the pixel defining layer away from the substrate, wherein a part of the light emitting function layer is located in the first pixel opening and the second pixel opening; the light-emitting functional layer comprises a first light-emitting layer, a charge generation layer and a second light-emitting layer which are sequentially stacked along a direction far away from the substrate, and at least part of the charge generation layer in the light-emitting functional layer is positioned between the first pixel opening and the second pixel opening.

A blocking structure is located between the first pixel opening and the second pixel opening. In the light-emitting functional layer, at least the charge generation layer is disconnected at the partition structure.

The partition structure is far away from the surface of the substrate and is close to the substrate compared with the surface of the pixel definition layer, which is far away from the substrate; or the partition structure is away from the surface of the substrate and is flush with the surface of the pixel defining layer away from the substrate.

In the display panel, the partition structure is arranged between the first sub-pixel and the second sub-pixel which are adjacently arranged, and at least the charge generation layer in the luminous functional layer is disconnected at the partition structure, so that crosstalk between the first sub-pixel and the second sub-pixel caused by the charge generation layer with high conductivity is avoided, and the display effect of the display panel is improved.

In some embodiments, the display panel further comprises a first dielectric layer between the partition structure and the substrate.

The surface of the first dielectric layer, which is far away from the substrate, is provided with an opening, and at least part of the partition structure is positioned in the opening.

In some embodiments, the first dielectric layer is further from a surface of the substrate than the partition structure is from the surface of the substrate.

In some embodiments, the partition structure is provided with an undercut structure on a side close to the first pixel opening; and/or, an undercut structure is arranged on one side of the partition structure, which is close to the second pixel opening.

The undercut structure is located within the opening with a spacing between the undercut structure and a sidewall of the opening.

In the light emitting functional layer, at least the charge generating layer is disconnected at the undercut structure.

In some embodiments, the partition structure is provided with an undercut structure near a side of one of the first pixel opening and the second pixel opening.

The partition structure is close to one side of the other one of the first pixel opening and the second pixel opening, and at least part of the partition structure is attached to the side wall of the opening.

In some embodiments, a side of the partition structure adjacent to the other of the first pixel opening and the second pixel opening partially overlaps a surface of the first dielectric layer remote from the substrate.

In some embodiments, the portion of the partition structure overlapping the surface of the first dielectric layer remote from the substrate includes a first side surface proximate to the other of the first pixel opening and the second pixel opening. The first side surface and the surface of the first dielectric layer, which is far away from the substrate, are provided with a first included angle, the first included angle faces the opening, and the first included angle is an acute angle.

In some embodiments, the partition structure has a closed loop shape surrounding the first pixel opening or the second pixel opening.

In some embodiments, the display panel further includes a common electrode layer located at a side of the second light emitting layer remote from the substrate. The common electrode layer is continuous at the partition structure.

In some embodiments, the partition structure is disposed around the first pixel opening or the second pixel opening, and the partition structure has at least one notch.

In some embodiments, the display panel further includes a common electrode layer located at a side of the second light emitting layer remote from the substrate. The common electrode layer is broken at the partition structure and continuous at the at least one notch.

In some embodiments, the partition structure includes a plurality of block-shaped partitions, and a plurality of the partitions are spaced around the first pixel opening or the second pixel opening.

In some embodiments, the partition structure comprises a negative photosensitive material.

In some embodiments, the slope of the side wall of the opening proximate to the undercut structure is greater than the slope of the side wall of the opening distal to the undercut structure.

In some embodiments, the depth of the opening is less than the thickness of the first dielectric layer.

In another aspect, a method for manufacturing a display panel is provided, including the steps of:

a partition structure is formed on a substrate.

And forming a pixel defining layer on the substrate on which the partition structure is formed. The pixel definition layer is provided with a plurality of pixel openings, each pixel opening comprises a first pixel opening and a second pixel opening which are adjacently arranged, and the partition structure is located between the first pixel opening and the second pixel opening. The partition structure is far away from the surface of the substrate and is close to the substrate compared with the surface of the pixel definition layer, which is far away from the substrate; or the partition structure is away from the surface of the substrate and is flush with the surface of the pixel defining layer away from the substrate.

And forming a light-emitting functional layer on one side of the pixel definition layer away from the substrate. The light-emitting functional layer comprises a first light-emitting layer, a charge generation layer and a second light-emitting layer which are sequentially stacked along a direction away from the substrate; in the light-emitting functional layer, at least the charge generation layer is disconnected at the partition structure.

The manufacturing method of the display panel has the same structure and beneficial technical effects as those of the display panel provided in some embodiments, and is not described herein.

In some embodiments, before the forming of the partition structure on the substrate, the method further includes the steps of:

a first dielectric layer is formed on a substrate.

And forming an opening on the surface of the first dielectric layer, which is far away from the substrate.

Wherein at least part of the partition structure is located within the opening.

In some embodiments, the forming the partition structure on the substrate includes the steps of:

And forming a separation layer on one side of the first dielectric layer away from the substrate.

And exposing the target area of the isolating layer to form an isolating structure.

Wherein a portion of the target region overlaps the opening with a spacing from a sidewall of the opening; another portion of the target area is located outside the opening and proximate to the other of the first pixel opening and the second pixel opening.

In some embodiments, the material of the barrier layer comprises a negative photosensitive material.

In yet another aspect, a display device is provided, including a display panel and a cover plate as described in any of the embodiments above. The cover plate is arranged on the light emitting side of the display panel.

The display device has the same structure and beneficial technical effects as those of the display panel provided in some embodiments described above, and will not be described in detail herein.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings that need to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic diagrams, not limiting the actual size of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure.

FIG. 1 is a block diagram of a display device according to some embodiments;

FIG. 2 is a cross-sectional view of the display device of FIG. 1 along section line B-B;

FIG. 3 is a block diagram of a display panel according to some embodiments;

FIG. 4 is a partial plan view of a display panel according to some embodiments;

FIG. 5A is a film layer structure diagram of a pixel layer of a display panel according to some embodiments;

FIG. 5B is another film layer structure diagram of a pixel layer of a display panel according to some embodiments;

FIG. 6 is a further film layer structure diagram of a pixel layer of a display panel according to some embodiments;

FIG. 7 is another block diagram of a display panel according to some embodiments;

FIG. 8 is yet another block diagram of a display panel according to some embodiments;

FIG. 9 is a block diagram of a partition structure of a display panel according to some embodiments;

FIG. 10 is another block diagram of a partition structure of a display panel according to some embodiments;

FIG. 11 is yet another block diagram of a partition structure of a display panel according to some embodiments;

FIG. 12A is yet another block diagram of a partition structure of a display panel according to some embodiments;

FIG. 12B is yet another block diagram of a partition structure of a display panel according to some embodiments;

FIG. 12C is yet another block diagram of a partition structure of a display panel according to some embodiments;

FIG. 13A is yet another block diagram of a partition structure of a display panel according to some embodiments;

FIG. 13B is yet another block diagram of a partition structure of a display panel according to some embodiments;

FIG. 13C is yet another block diagram of a partition structure of a display panel according to some embodiments;

FIG. 14A is another partial plan view of a display panel according to some embodiments;

FIG. 14B is yet another partial plan view of a display panel according to some embodiments;

FIG. 15 is yet another partial plan view block diagram of a display panel according to some embodiments;

FIG. 16 is a further partial plan view of a display panel according to some embodiments;

FIG. 17 is a cross-sectional view of a display panel according to some embodiments;

FIG. 18 is a flow chart of a method of manufacturing a display panel according to some embodiments;

Fig. 19 is a structural diagram corresponding to step S1 in the manufacturing method of the display panel according to the embodiment shown in fig. 18;

Fig. 20 is a structural diagram corresponding to step S2 in the manufacturing method of the display panel according to the embodiment shown in fig. 18;

fig. 21 is a structural diagram corresponding to step S3 in the manufacturing method of the display panel according to the embodiment shown in fig. 18;

fig. 22 is a structural diagram corresponding to step S0 in the manufacturing method of the display panel according to the embodiment shown in fig. 18;

fig. 23 is another structural diagram corresponding to step S1 in the manufacturing method of the display panel according to the embodiment shown in fig. 18.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

Throughout the specification and claims, unless the context requires otherwise, the word "comprise" and its other forms such as the third person referring to the singular form "comprise" and the present word "comprising" are to be construed as open, inclusive meaning, i.e. as "comprising, but not limited to. In the description of the specification, the terms "one embodiment", "some embodiments (some embodiments)", "exemplary embodiment (exemplary embodiments)", "example (example)", "specific example (some examples)", etc. are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing some embodiments, expressions of "coupled" and "connected" and their derivatives may be used. The term "coupled" is to be interpreted broadly, as referring to, for example, a fixed connection, a removable connection, or a combination thereof; can be directly connected or indirectly connected through an intermediate medium. The term "coupled" for example, indicates that two or more elements are in direct physical or electrical contact. The term "coupled" or "communicatively coupled (communicatively coupled)" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

At least one of "A, B and C" has the same meaning as at least one of "A, B or C" and includes the following combinations of A, B and C: a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.

"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.

As used herein, the term "if" is optionally interpreted to mean "when … …" or "at … …" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if determined … …" or "if a [ stated condition or event ] is detected" is optionally interpreted to mean "upon determination … …" or "in response to determination … …" or "upon detection of a [ stated condition or event ]" or "in response to detection of a [ stated condition or event ], depending on the context.

The use of "adapted" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

As used herein, "about," "approximately" or "approximately" includes the stated values as well as average values within an acceptable deviation range of the particular values as determined by one of ordinary skill in the art in view of the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

As used herein, "parallel", "perpendicular", "equal" includes the stated case as well as the case that approximates the stated case, the range of which is within an acceptable deviation range as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, where the acceptable deviation range for approximately parallel may be, for example, a deviation within 5 °; "vertical" includes absolute vertical and near vertical, where the acceptable deviation range for near vertical may also be deviations within 5 °, for example. "equal" includes absolute equal and approximately equal, where the difference between the two, which may be equal, for example, is less than or equal to 5% of either of them within an acceptable deviation of approximately equal.

It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present between the layer or element and the other layer or substrate.

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

For convenience of the following description, an XYZ coordinate system is established. The third direction Z is the thickness direction of the display device, the XY plane is perpendicular to the Z direction, and the first direction X and the second direction Y are intersected. For example, the first direction X and the second direction Y are perpendicular to each other.

It should be noted that, for example, 91/9 appearing in the drawings of the present disclosure indicates that the component is both 9 and 91, and that other similar reference numerals appearing in the drawings also follow the above description.

As shown in fig. 1, some embodiments of the present disclosure provide a display device 100.

Illustratively, the display device 100 may be any device that displays images, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual or pictorial. More particularly, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal Data Assistants (PDAs), hand-held or portable computers, GPS receivers/navigators, cameras, MP4 video players, video cameras, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), navigators, cabin controllers and/or displays, displays of camera views (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry), and the like. In fig. 1, a display device 100 is illustrated as a mobile phone.

The display device 100 may be an electroluminescent display device or a photoluminescent display device, for example. In the case where the display device 100 is an electroluminescent display device, the electroluminescent display device may be an Organic Light-Emitting Diode (OLED) or a Quantum Dot LIGHT EMITTING Diodes (QLED). In the case where the display device 100 is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

In the following, some embodiments of the present disclosure will be schematically described using the display device 100 as an Organic Light-Emitting Diode (OLED) as an example, but the embodiments of the present disclosure include, but are not limited to, any other display device may be considered as long as the same technical ideas are applied.

In some embodiments, as shown in fig. 2, fig. 2 is a cross-sectional view of the display device 100 of fig. 1 along the section line B-B. The display device 100 includes a display panel 10 and a cover plate 20. The cover 20 is disposed on the light-emitting side of the display panel 10.

The cover plate 20 may isolate the display panel 10 from the external environment, providing protection for the display panel 10.

The cover 20 may be a single-layer cover, or may be a multi-layer cover 20 covered together by glue.

Illustratively, the cover plate 20 may be a silicate glass cover plate, for example, curved glass or ultra-thin glass.

The cover 20 may be a flexible polymer film cover, for example, transparent polyimide, PET, polyurethane, or the like.

The cover plate 20 may be a combination of the above flexible polymer films or a combination of the flexible polymer film and silicate glass.

In some embodiments, the display device 100 may further include a circuit board (not shown). The circuit board is electrically connected to the display panel 10 and configured to drive the display panel 10 to display an image.

Illustratively, the circuit boards include, but are not limited to, PCBs (Printed Circuit Board, printed circuit boards) and FPCs (Flexible Printed Circuit Board, flexible printed circuit boards).

In some embodiments, the display device 100 may further include an under-screen camera, an under-screen fingerprint recognition sensor, and the like, so that the display device 100 can implement a plurality of different functions such as photographing, video recording, fingerprint recognition, or face recognition. The present disclosure is not limited in any way, and may be adaptively designed according to actual requirements.

The display panel 10 is described in detail below.

In some embodiments, as shown in fig. 3, fig. 3 is a block diagram of the display panel 10 according to some embodiments. The display panel 10 may have a rectangular structure.

The "rectangular structure" mentioned above means that the shape of the border of the display panel 10 is rectangular in shape as a whole, but is not limited to a standard rectangle. That is, the "rectangular" herein includes not only a standard rectangular shape but also a rectangular-like shape in consideration of process conditions. For example, as shown in fig. 3, the long side and the short side of the rectangle are curved at each intersecting position (i.e., corner G), i.e., corner G is smooth, so that the boundary of the display panel 10 has a rounded rectangle shape in a plan view.

In other embodiments, the display panel 10 may have a circular structure, or other shapes with corners.

Some embodiments of the present disclosure will be schematically described below taking the display panel 10 as an example of a rectangular structure, but the embodiments of the present disclosure include, but are not limited to, any other shape of the display panel 10 may be considered.

In some embodiments, referring to fig. 3, the display panel 10 has a display area AA for displaying AN image, and a peripheral area AN located at least on one side of the display area AA.

For example, the peripheral area AN is located at one side of the display area AA.

For another example, the peripheral area AN is located at opposite sides of the display area AA.

As another example, as shown in fig. 3, the peripheral area AN surrounds the display area AA.

The specific arrangement of the peripheral area AN is related to the specific design of the display panel 10, and may be designed according to actual needs, and is only illustrated here as AN example, and is not intended to limit the present disclosure.

In some embodiments, referring to fig. 3, a plurality of sub-pixels 9 are disposed in a display area AA of the display panel 10, and the sub-pixels 9 are the smallest light emitting units in the display area AA.

Illustratively, the plurality of sub-pixels 9 in the display area AA of the display panel 10 may emit light of the same color, and the display panel 10 may further include a color film layer disposed on the light emitting side of the plurality of sub-pixels 9. For example, the plurality of sub-pixels 9 each emit white light, red light, green light, or blue light, and in this case, the color light emitted from the sub-pixels 9 passes through the color film layer and then is emitted in the same color, or is converted into other color light, so that the display panel 10 can realize multi-color light emission when the plurality of sub-pixels 9 emit the same color light.

Or a plurality of sub-pixels 9 within the display area AA of the display panel 10 emit light of different colors, for example, the plurality of sub-pixels 9 include red sub-pixels emitting red light, green sub-pixels emitting green light, and blue sub-pixels emitting blue light, thereby realizing multicolor light emission of the display panel 10.

In some embodiments, referring to fig. 2, the display panel 10 includes a substrate 1, a driving layer 2, a pixel layer D, and an encapsulation layer 8 sequentially stacked.

The pixel layer D is used for disposing a plurality of sub-pixels 9 in the display area AA of the display panel 10, and the plurality of sub-pixels 9 include a first sub-pixel 91 and a second sub-pixel 92 disposed adjacently.

The "first subpixel 91 and second subpixel 92 disposed adjacently" means that no other subpixel 9 is disposed between the first subpixel 91 and the second subpixel 92.

The driving layer 2 is used for driving the plurality of sub-pixels 9 in the pixel layer D to emit light.

The packaging layer 8 is used for packaging the pixel layer D, plays a role in protecting the pixel layer D, and avoids corrosion caused by external water and oxygen.

The first subpixel 91 may be, for example, a red subpixel emitting red light, a green subpixel emitting green light, or a blue subpixel emitting blue light. The second subpixel 92 may also be a red subpixel that emits red light, a green subpixel that emits green light, or a blue subpixel that emits blue light.

It is understood that the colors of the light emitted by the first and second sub-pixels 91, 92 may be the same, for example, the first and second sub-pixels 91, 92 may each be a red sub-pixel that emits red light.

For another example, the first subpixel 91 and the second subpixel 92 may be green subpixels that emit green light.

For another example, the first subpixel 91 and the second subpixel 92 may each be a blue subpixel emitting blue light.

The colors of the light emitted by the first and second sub-pixels 91, 92 may also be different, for example, the first sub-pixel 91 may be a red sub-pixel emitting red light, and the second sub-pixel 92 may be a green sub-pixel emitting green light or a blue sub-pixel emitting blue light.

For another example, the first subpixel 91 may be a green subpixel that emits green light, and the second subpixel 92 may be a red subpixel that emits red light or a blue subpixel that emits blue light.

For another example, the first subpixel 91 may be a blue subpixel emitting blue light, and the second subpixel 92 may be a red subpixel emitting red light or a green subpixel emitting green light.

Illustratively, the material used to form the substrate 1 may include an inorganic material, for example, a glass material such as soda lime glass, quartz glass, sapphire glass, or the like.

The material used to form the substrate 1 may also include an organic material, for example, one or more of polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate.

The material used to form the substrate 1 may also include both organic and inorganic materials.

Illustratively, a plurality of pixel driving circuits may be disposed within the driving layer 2. The pixel driving circuit and the sub-pixel 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92) are electrically connected, and the sub-pixel 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92) can emit light under the driving of the pixel driving circuit.

The pixel driving circuit may include a Thin Film Transistor (TFT) and a storage capacitor.

The encapsulation layer 8 may include an inorganic encapsulation layer and an organic encapsulation layer, for example.

The pixel layer D will be described in detail below.

In some embodiments, referring to fig. 2, the pixel layer D of the display panel 10 includes a pixel electrode layer 4, a light emitting functional layer 6, and a common electrode layer 7 sequentially stacked along a third direction Z. The pixel electrode layer 4 and the common electrode layer 7 may supply carriers such as electrons, holes, and the like to the light emitting functional layer 6 to cause the light emitting functional layer 6 to emit light.

A plurality of pixel electrodes 41 are provided within the pixel electrode layer 4, and the light emitting functional layer 6 includes a plurality of light emitting portions 6a, each of the light emitting portions 6a and one of the pixel electrodes 41 overlapping in the third direction Z.

The common electrode layer 7 may serve as a common electrode for a plurality of sub-pixels 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92) within the pixel layer D. Each of the sub-pixels 9 (e.g., the first sub-pixel 91 or the second sub-pixel 92) in the pixel layer D may include a pixel electrode 41 and a common electrode which are stacked, and a light emitting portion 6a between the pixel electrode 41 and the common electrode.

For example, referring to fig. 2, the pixel electrode layer 4 may be closer to the driving layer 2 than the common electrode layer 7.

Illustratively, one of the pixel electrode 41 and the common electrode may serve as an anode of the sub-pixel 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92), and the other may serve as a cathode of the sub-pixel 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92).

For example, the pixel electrode 41 may serve as an anode of the sub-pixel 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92), and the common electrode may serve as a cathode of the sub-pixel 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92).

Illustratively, the material used to form the pixel electrode 41 may include a metal material, such as any one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo).

The material for forming the pixel electrode 41 may also include an alloy material of the above-described metal material, such as an aluminum neodymium alloy (AlNd) or a molybdenum niobium alloy (MoNb).

The pixel electrode 41 may be a single-layer structure, for example.

Or the pixel electrode 41 may be a multi-layered composite structure. For example, the pixel electrode 41 may be a Ti/Al/Ti structure or the like. For another example, the pixel electrode 41 may be a stack structure formed of a metal material and a transparent conductive material, such as ITO/Ag/ITO, mo/AlNd/ITO, or the like.

Illustratively, the material used to form the common electrode layer 7 may include any one or more of magnesium (Mg), silver (Ag), aluminum (Al), and the like.

The material for forming the common electrode layer 7 may also include an alloy made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), and the like.

The material for forming the common electrode layer 7 may further include a transparent conductive material, for example, indium Tin Oxide (ITO).

In some embodiments, as shown in fig. 4, in combination with fig. 2, fig. 4 is a partial plan view block diagram of the display panel 10 according to some embodiments. The display panel 10 further includes a Pixel Defining Layer (PDL) 5 between the pixel electrode layer 4 and the light emitting function layer 6. A plurality of pixel openings K are formed in the Pixel Defining Layer (PDL) 5, the pixel openings K and the pixel electrodes 41 being disposed correspondingly, each pixel opening K exposing at least a partial area of one pixel electrode 41. The light emitting portion 6a in the light emitting functional layer 6 is provided in the pixel opening K, and is electrically connected to the pixel electrode 41 and the common electrode layer 7, respectively.

By exposing at least a partial area of one pixel electrode 41 per pixel opening K, the Pixel Defining Layer (PDL) 5 can effectively define the actual effective area of the pixel electrode 41 (i.e., the area where the pixel electrode 41 is directly electrically connected to the light emitting portion 6a in the light emitting functional layer 6), thereby defining the light emitting area and the light emitting area of the sub-pixel 9.

For example, referring to fig. 4, a Pixel Defining Layer (PDL) 5 may cover an edge of the pixel electrode 41, and the pixel opening K exposes a portion of an inner region of the pixel electrode 41.

Illustratively, the material used to form the Pixel Defining Layer (PDL) 5 may include an organic material, such as polyimide, acryl, or polyethylene terephthalate, or the like.

For example, with continued reference to fig. 4, the plurality of pixel openings K in the pixel defining layer 5 includes a first pixel opening K1 and a second pixel opening K2 disposed adjacently. The first pixel opening K1 is disposed corresponding to the pixel electrode 41 in the first subpixel 91, and exposes at least a partial region of the pixel electrode 41 in the first subpixel 91. The second pixel opening K2 is disposed corresponding to the pixel electrode 41 in the second subpixel 92, and exposes at least a partial region of the pixel electrode 41 in the second subpixel 92.

The "first pixel opening K1 and the second pixel opening K2 disposed adjacently" means that no other pixel opening K is disposed between the first pixel opening K1 and the second pixel opening K2.

In some embodiments, as shown in fig. 5A and 5B, fig. 5A and 5B are each a film layer structure diagram of the pixel layer D of the display panel 10 according to some embodiments. The light emitting functional layer 6 in the pixel layer D includes a light emitting layer 61.

For example, with continued reference to fig. 5A, the display panel 10 may be a QLED display panel. Based on the display panel 10 being a QLED display panel, the light emitting layer 61 may include a Quantum Dot Layer (QDL). For example, a Quantum Dot Layer (QDL) may have quantum dot particles that may be interconnected by surface modifying groups.

Alternatively, referring to fig. 5B, the display panel 10 may be an OLED display panel. The light emitting layer 61 may include an organic light emitting layer (EML) based on the display panel 10 being an OLED display panel. For example, the organic light emitting layer EML may include a light emitting layer host material and a light emitting layer guest material, which may be a fluorescent dopant or a phosphorescent dopant.

Some embodiments of the present disclosure will be schematically described below taking the display panel 10 as an OLED display panel as an example, but the embodiments of the present disclosure include, but are not limited to, any other type of display panel may be considered as long as the same technical ideas are applied.

In some embodiments, referring to fig. 5B, the light emitting functional layer 6 further includes one or more of a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL).

Illustratively, the material used to form the Hole Injection Layer (HIL) may include an oxide. The material used to form the Hole Injection Layer (HIL) may also include an organic material.

Illustratively, the material for forming the Hole Transport Layer (HTL) may include an arylamine, dimethylfluorene, or carbazole material having hole transport characteristics.

Illustratively, the material used to form the Electron Transport Layer (ETL) may include an aromatic heterocyclic compound.

Illustratively, the material used to form the Electron Injection Layer (EIL) may include an alkali metal or a metal and a compound thereof.

In some embodiments, referring to fig. 5B, the light emitting functional layer 6 in the pixel layer D may include a single light emitting layer 61.

In other embodiments, as shown in fig. 6, fig. 6 is a film layer structure diagram of the pixel layer D of the display panel 10 according to some embodiments. The light emitting functional layer 6 within the pixel layer D may include a plurality of light emitting layers 61.

For example, referring to fig. 6, the light emitting functional layer 6 may include two light emitting layers 61, a first light emitting layer 61a and a second light emitting layer 61b, respectively.

Wherein the second light emitting layer 61b may be closer to the common electrode layer 7 than the first light emitting layer 61a, and the common electrode layer 7 may be located at a side of the second light emitting layer 61b away from the substrate 1.

Some embodiments of the present disclosure will be schematically described below with an example in which the light-emitting functional layer 6 includes two light-emitting layers 61.

With continued reference to fig. 6, the light emitting functional layer 6 further includes a charge generating layer (Charge Generation Layer, CGL) 62 between the first light emitting layer 61a and the second light emitting layer 61 b. The Charge Generation Layer (CGL) 62 may connect the first light emitting layer 61a and the second light emitting layer 61b in series to achieve a stacked light emitting (Tandem EL) design.

On the one hand, since the number of light emitting layers 61 increases and the Charge Generation Layer (CGL) 62 can reduce the driving voltage and generate new carriers, the light emitting efficiency of the light emitting functional layer 6 can be doubled. On the other hand, the display panel 10 of the stacked light emitting (Tandem EL) design has a reduced current density compared to the display panel 10 of the single-layer light emitting design at the same luminance, which is advantageous for prolonging the service life of the display panel 10.

Illustratively, the Charge Generation Layer (CGL) 62 may be configured to generate carriers, transport carriers, and inject carriers.

Illustratively, the Charge Generation Layer (CGL) 62 may include an N-type charge generation layer (N-CGL) and a P-type charge generation layer (P-CGL).

The N-type charge generation layer (N-CGL) may include, for example, an organic Electron Transport Layer (ETL) material doped with a metal material.

The P-type charge generation layer (P-CGL) may include, for example, an organic Hole Transport Layer (HTL) material doped with a P-type light emitting dopant (P-dopant).

In some embodiments, referring to fig. 6, part of the film layer in the light emitting functional layer 6 may be a common layer.

The common layer in the light emitting function layer 6 means that a part of the film layer in the light emitting function layer 6 is formed in both the region where the plurality of sub-pixels 9 (for example, the first sub-pixel 91 and the second sub-pixel 92) are located and the gap region between the plurality of sub-pixels 9 (for example, the gap region J between the first sub-pixel 91 and the second sub-pixel 92). That is, a part of the film layers in the light emitting functional layer 6 is a continuous film layer of the whole layer, and in this case, the plurality of sub-pixels 9 (for example, the first sub-pixel 91 and the second sub-pixel 92) can be considered to share the part of the film layers in the light emitting functional layer 6, and the part of the film layers in the light emitting functional layer 6 can be considered to be a common layer in the light emitting functional layer 6.

For example, it may be that part of the film layers in the light emitting functional layer 6 are common layers due to process reasons. For example, when the partial film layer in the light emitting function layer 6 is formed by using the open mask process, a material for forming the partial film layer of the light emitting function layer 6 may be deposited in the region where the plurality of sub-pixels 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92) are located, specifically, a material for forming the partial film layer of the light emitting function layer 6 may be deposited in the plurality of pixel openings K (e.g., the first pixel opening K1 and the second pixel opening K2), that is, a portion of the light emitting function layer 6 is located in the plurality of pixel openings K (e.g., the first pixel opening K1 and the second pixel opening K2) for forming the light emitting portion 6a (e.g., the light emitting portion 6a of the first sub-pixel 91 and the light emitting portion 6a of the second sub-pixel 92) in the sub-pixel 9; meanwhile, the material for forming the partial film layer (e.g., the Charge Generation Layer (CGL) 62) of the light emitting function layer 6 is also deposited in the gap region (e.g., the gap region J between the first and second sub-pixels 91 and 92) between the plurality of sub-pixels 9, and particularly, the material for forming the partial film layer (e.g., the Charge Generation Layer (CGL) 62) of the light emitting function layer 6 is also deposited in the gap region (e.g., the gap region between the first and second pixel openings K1 and K2) between the plurality of pixel openings K, i.e., the portion of the partial film layer (e.g., the Charge Generation Layer (CGL) 62) of the light emitting function layer 6 is located in the gap region between the plurality of pixel openings K (e.g., the first and second pixel openings K1 and K2) such that the adjacent two sub-pixels 9 (e.g., the first and second sub-pixels 91 and 92) are connected by the light emitting function layer 6 formed in the gap region J. Specifically, the light emitting portions 6a of two adjacent sub-pixels 9 (for example, the light emitting portion 6a of the first sub-pixel 91 and the light emitting portion 6a of the second sub-pixel 92) are connected by the light emitting functional layer 6 formed in the gap region J.

That is, the common layer in the light emitting function layer 6 may cover the region where the plurality of sub-pixels 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92) are located, and the gap region between the plurality of sub-pixels 9 (e.g., the gap region J between the first sub-pixel 91 and the second sub-pixel 92), and the common layer is continuous at the gap region between the plurality of sub-pixels 9 (e.g., the gap region J between the first sub-pixel 91 and the second sub-pixel 92).

When the sub-pixels 9 are operated, carriers easily flow laterally through the common layer in the light emitting functional layer 6 (i.e., carriers flow from one sub-pixel 9 to another sub-pixel 9), resulting in crosstalk between adjacent sub-pixels 9, which is particularly serious at low gray scales.

Particularly when the conductivity of the common layer in the light emitting functional layer 6 is strong, crosstalk between adjacent sub-pixels 9 is liable to be more serious. For example, when the Charge Generation Layer (CGL) 62 is a common layer, crosstalk between adjacent sub-pixels 9 may be more serious due to the Charge Generation Layer (CGL) 62 having a relatively strong conductivity, which may cause color shift.

For example, as shown in fig. 6, when the first subpixel 91 is operated, a signal is input to the first subpixel 91, and the first subpixel 91 is turned on and the second subpixel 92 is also turned on, so that the color purity of the screen of the first subpixel 91 is reduced, the gray scale color gamut is reduced, and the display effect of the display panel 10 is affected.

Based on this, in some embodiments, as shown in fig. 7, fig. 7 is a structural diagram of the display panel 10 according to some embodiments. The display panel 10 further includes a partition structure 32a. The partition structure 32a is located between the first pixel opening K1 and the second pixel opening K2. That is, the partition structure 32a is located between the first subpixel 91 and the second subpixel 92.

Based on the Charge Generation Layer (CGL) 62 being a common layer in the light emitting functional layer 6, at least the Charge Generation Layer (CGL) 62 is disconnected at the partition structure 32 a.

The phrase "at least the Charge Generation Layer (CGL) 62 is disconnected from the light-emitting functional layer 6 at the partition structure 32 a" means that at least the Charge Generation Layer (CGL) 62 is discontinuous or non-integral with the light-emitting functional layer 6 at the partition structure 32 a.

By providing a blocking structure between the first sub-pixel 91 and the second sub-pixel 92 that are adjacently disposed and making at least the Charge Generation Layer (CGL) 62 in the light emitting functional layer 6 break at the blocking structure 32a, crosstalk between the first sub-pixel 91 and the second sub-pixel 92 caused by the Charge Generation Layer (CGL) 62 with higher conductivity is avoided, which is advantageous for improving the display effect of the display panel 10.

Illustratively, the partition structure 32a may include a negative photosensitive material.

Illustratively, in the light emitting functional layer 6, other film layers than the Charge Generation Layer (CGL) 62 may also be common layers in the light emitting functional layer 6. For example, the light emitting functional layer 6 may include one or more of a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL), and may be a common layer in the light emitting functional layer 6.

When some of the other film layers other than the Charge Generation Layer (CGL) 62 in the light emitting functional layer 6 are also common layers in the light emitting functional layer 6, only the Charge Generation Layer (CGL) 62 may be broken at the partition structure 32a, or other film layers as common layers may be broken at the partition structure 32 a.

For example, as shown in fig. 7, all the common layers in the light emitting functional layer 6 are broken at the partition structure 32 a. Namely, a part of the light-emitting functional layer 6 located on the surface 32aa of the partition structure 32a away from the substrate 1 and another part of the light-emitting functional layer 6 are discontinuous or non-integral.

By making all the common layers in the light emitting functional layer 6 open at the partition structure 32a, it is possible to avoid the lateral flow of carriers through the common layers in the light emitting functional layer 6 (i.e., the flow of carriers from one sub-pixel 9 to another sub-pixel 9), thereby avoiding crosstalk between adjacent sub-pixels 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92), which is advantageous for further improving the display effect of the display panel 10.

For ease of explanation, some embodiments of the present disclosure will be schematically described below taking the example that all common layers in the light emitting functional layer 6 are broken at the partition structure 32 a.

In some embodiments, referring to fig. 7, in the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 is greater than the distance d1 between the surface 5aa of the pixel defining layer 5 away from the substrate 1 and the substrate 1.

That is, the pixel defining layer 5 is far from the surface 5aa of the substrate 1, and is closer to the substrate 1 than the partition structure 32a is far from the surface 32aa of the substrate 1.

On the one hand, in forming the light emitting function layer 6 by the vapor deposition process, it is necessary to provide a mask plate on the side of the pixel defining layer 5 and the partition structure 32a away from the substrate 1. Since the pixel defining layer 5 is far away from the surface 5aa of the substrate 1, compared with the partition structure 32a, the surface 32aa of the substrate 1 is far away from the substrate 1, and therefore the partition structure 32a is far away from the surface 32aa of the substrate 1, compared with the surface 5aa of the pixel defining layer 5, the surface 5aa of the substrate 1 is near the mask plate, scratch is likely to occur between the partition structure 32a and the mask plate, the reliability of packaging may be affected by the chippings of the partition structure 32a, and the chippings of the partition structure 32a easily enter the pixel opening K to affect the light emission of the light emitting part 6a in the pixel opening K, which may cause the black spot problem of the display panel 10, and the yield of the display panel 10 may be reduced.

On the other hand, since the pixel defining layer 5 is far from the surface 5aa of the substrate 1, the partition structure 32 is closer to the substrate 1 than the surface 32aa of the partition structure 32a is to the surface 32aa of the substrate 1, and in a side view state, the partition structure 32 is likely to block the sub-pixels 9 and affect the visual experience of the display panel 10.

Based on this, in some embodiments, as shown in fig. 8, fig. 8 is a structural diagram of the display panel 10 according to some embodiments. In the third direction Z, the separation structure 32a is distant from the distance d2 between the surface 32aa of the substrate 1 and the substrate 1, which is smaller than or equal to the distance d1 between the surface 5aa of the pixel defining layer 5 distant from the substrate 1 and the substrate 1.

That is, the partition structure 32a is away from the surface 32aa of the substrate 1, which is shown in fig. 8, as compared to the pixel defining layer 5 being closer to the substrate 1 than the surface 5aa of the substrate 1; or the partition structure 32a is away from the surface 32aa of the substrate 1 and flush with the surface 5aa of the pixel defining layer 5 away from the substrate 1.

By keeping the partition structure 32a away from the surface 32aa of the substrate 1, it is not higher than the surface 5aa of the pixel defining layer 5 away from the substrate 1. On the one hand, when the light emitting functional layer 6 is formed by the vapor deposition process, scratch between the partition structure 32a and the mask plate can be avoided, so that scraps of the partition structure 32a formed by scratch can be avoided, normal light emission of the light emitting part 6a in the pixel opening K is ensured, the packaging reliability is improved, and the yield of the display panel 10 is improved.

On the other hand, since the partition structure 32a is not higher than the surface 32aa of the pixel defining layer 5 away from the substrate 1 and is away from the surface 5aa of the substrate 1, the shielding of the sub-pixels 9 by the partition structure 32 can be avoided in the side view state, and the visual experience of the display panel 10 is improved.

In some embodiments, please continue to refer to fig. 8 in conjunction with fig. 9, fig. 9 is a block diagram of a partition structure 32a of the display panel 10 according to some embodiments. The display panel 10 further comprises a first dielectric layer 31 between the partition structure 32a and the substrate 1. The surface 31a of the first dielectric layer 31 remote from the substrate 1 is provided with an opening T, at least part of the partition structure 32a being located in the opening T.

With continued reference to fig. 9, by disposing at least a portion of the partition structure 32a in the opening T, while ensuring that the partition structure 32a is not higher than the surface 5aa of the pixel definition layer 5 away from the substrate 1, the dimension g1 of the partition structure 32a along the third direction Z (hereinafter, for convenience of description, the height g1 of the partition structure 32a is generally referred to as "the height g 1") may be increased, that is, the distance between the surface 32aa of the partition structure 32a away from the substrate 1 and the surface 32ad of the partition structure 32a near the substrate 1 is increased, so that the edge of the partition structure 32a has a larger break difference, which is beneficial to improving the partition effect of the partition structure 32a on the light emitting functional layer 6, and avoiding the light emitting functional layer 6 from being continuous at the partition structure 32 a.

Illustratively, the first dielectric layer 3 may comprise a planar layer. The flat layer is mainly used for blocking water and oxygen and blocking alkaline ions.

The first dielectric layer 3 may be obtained by coating PI (Polyimide) by a spin coating process, or may be obtained by depositing silicon nitride, silicon oxide or silicon oxynitride by a PECVD process.

The opening T may extend through the first dielectric layer 3, for example.

Alternatively, as shown in fig. 9, the opening T may not penetrate the first dielectric layer 3. I.e. the depth g2 of the opening T is smaller than the thickness g3 of the first dielectric layer 31.

The "depth g2 of the opening T" refers to a dimension g2 of the opening T along the third direction Z. The "thickness g3 of the first dielectric layer 31" refers to the dimension g3 of the first dielectric layer 31 along the third direction Z.

In some embodiments, referring to fig. 9, the partition structure 32a may be provided with an undercut structure (undercut) near one side 32ac of the second pixel opening K2.

Or as shown in fig. 10, fig. 10 is a block diagram of a partition structure 32a of the display panel 10 according to some embodiments. The partition structure 32a may be provided with an undercut structure (undercut) near one side 32ab of the first pixel opening K1.

As also shown in fig. 11, fig. 11 is a block structure 32a of the display panel 10 according to some embodiments. One side 32ac of the partition structure 32a near the second pixel opening K2 and one side 32ab of the partition structure 32a near the first pixel opening K1 may be provided with undercut structures.

The "undercut" is formed by retracting the partition structure 32a to a certain distance from the side 32ac of the partition structure 32a near the second pixel opening K1 and/or the side 32ab of the partition structure 32a near the first pixel opening K1.

In the above-described "in the light emitting functional layer 6, at least the Charge Generation Layer (CGL) 62 is disconnected at the partition structure 32 a", specifically, in the light emitting functional layer 6, at least the charge generation layer 62 may be disconnected at the undercut structure (undercut) of the partition structure 32 a.

By providing the undercut structure (undercut), and in the light emitting functional layer 6, at least the charge generation layer 62 is disconnected at the undercut structure (undercut), at least crosstalk between the first subpixel 91 and the second subpixel 92 caused by the Charge Generation Layer (CGL) 62 with relatively high conductivity can be avoided, which is beneficial to improving the display effect of the display panel 10.

For example, with continued reference to fig. 9, 10 and 11, an undercut structure (undercut) is located within the opening T, with a spacing d4 between the undercut structure (undercut) and the sidewalls of the opening T. That is, the undercut structure (undercut) and the sidewall of the opening T are not contacted.

In some embodiments, as shown in fig. 9, 12A, 12B and 12C, fig. 12A, 12B and 12C are each a structural diagram of a partition structure 32A of a display panel 10 according to some embodiments. Based on the side 32ac of the partition structure 32a near the second pixel opening K2, an undercut structure (undercut) is provided, and the side 32ab of the partition structure 32a near the first pixel opening K1 is at least partially attached to the side wall of the opening T.

For example, with continued reference to fig. 9, 12A, 12B and 12C, the slope of the side wall of the opening T near the undercut structure (undercut) is greater than the slope of the side wall of the opening T away from the undercut structure (undercut). Since the undercut structure is provided near the side 32ac of the second pixel opening K2 in the embodiment shown in fig. 9, 12A, 12B and 12C, the opening T is near the side 32ac of the partition structure 32A, and the slope of the side wall is larger than the slope of the side wall of the side 32ab of the partition structure 32A near the opening T.

That is, the opening T is close, the slope of the side wall of the side 32ab of the partition structure 32a is small, the side wall is relatively gentle, and when the partition structure 32a is formed in the opening T, the side 32ab close to the first pixel opening K1 is easily attached to the side wall, which is advantageous to attach the side wall to the side 32ab of the first pixel opening K1.

Illustratively, as shown in fig. 12A, in the third direction Z, a distance d2 between the surface 32aa of the partition structure 32A away from the substrate 1 and the substrate 1 may be smaller than a distance d3 between the surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. That is, the first dielectric layer 31 is far from the surface 31a of the substrate 1, and far from the substrate 1 than the partition structure 32aa is far from the surface 32aa of the substrate 1.

Based on the surface 31a of the first dielectric layer 31 far from the substrate 1, the partition structure 32a is far from the substrate 1 than the surface 32aa of the partition structure 32aa far from the substrate 1, and the partition structure 32a near one side 32ab of the first pixel opening K1 can be bonded to the side wall of the opening T entirely.

Or as shown in fig. 12B, in the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 may be equal to the distance d3 between the surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. That is, the first dielectric layer 31 is away from the surface 31a of the substrate 1, and the partition structure 32aa is flush away from the surface 32aa of the substrate 1.

Based on the fact that the first dielectric layer 31 is away from the surface 31a of the substrate 1 and the partition structure 32aa is away from the surface 32aa of the substrate 1 and is flush, the partition structure 32a is close to the side 32ab of the first pixel opening K1, and can be attached to the side wall of the opening T entirely.

Further alternatively, as shown in fig. 12C, in the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 may be larger than the distance d3 between the surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. That is, the first dielectric layer 31 is far from the surface 31a of the substrate 1, and is closer to the substrate 1 than the partition structure 32aa is far from the surface 32aa of the substrate 1.

Based on the surface 31a of the first dielectric layer 31 away from the substrate 1, the surface 32aa of the partition structure 32aa away from the substrate 1 is closer to the substrate 1 than the surface 32aa of the partition structure 32aa is, a part of the partition structure 32a near the first pixel opening K1 may be attached to a sidewall of the opening T, another part extends out of the opening T, and the part of the partition structure 32a near the first pixel opening K1 extending out of the opening T is not in contact with the surface 31a of the first dielectric layer 31 away from the substrate 1.

Further alternatively, as shown in fig. 9, in the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 may be greater than the distance d3 between the surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. That is, the first dielectric layer 31 is far from the surface 31a of the substrate 1, and is closer to the substrate 1 than the partition structure 32aa is far from the surface 32aa of the substrate 1.

Based on the surface 31a of the first dielectric layer 31 far away from the substrate 1, the surface 32aa of the partition structure 32aa far away from the substrate 1 is closer to the substrate 1 than the surface 32aa of the partition structure 32aa, a part of the partition structure 32a near the first pixel opening K1 may be attached to a side wall of the opening T, another part of the partition structure extends out of the opening T, and a part of the partition structure 32a near the side 32ab of the first pixel opening K1 extending out of the opening T is attached to the surface 31a of the first dielectric layer 31 far away from the substrate 1.

For example, as shown in fig. 9, a portion of the partition structure 32a overlapping on the surface 31a of the first dielectric layer 31 away from the substrate 1 includes a first side surface 32ae, based on a portion of the partition structure 32a extending beyond the opening T near a side 32ab of the first dielectric layer 31 away from the substrate 1 near the first pixel opening K1, the first side surface 32ae is adjacent to the first pixel opening K1, and belongs to a side 32ab of the partition structure 32a near the first pixel opening K1.

The first side surface 32ae and the surface 31a of the first dielectric layer 31 remote from the substrate 1 have a first included angle R1. The first included angle R1 faces the opening T, and the first included angle R1 is an acute angle. That is, the first side surface 32ae is an inclined surface, so that the first dielectric layer 31 is away from the surface 31a of the substrate 1, and the first side surface 32ae can smoothly transition to the surface 32aa of the partition structure 32a away from the substrate 1.

In forming the Pixel Defining Layer (PDL) 5, the Pixel Defining Layer (PDL) 5 is formed on the surface 31a of the first dielectric layer 31 remote from the substrate 1, the first side surface 32ae, and the surface 32aa of the partition structure 32a remote from the substrate 1. Since the first dielectric layer 31 is far from the surface 31a of the substrate 1 and can be smoothly transited from the first side surface 32ae to the surface 32aa of the partition structure 32a far from the substrate 1, the Pixel Definition Layer (PDL) 5 can be continuously formed between the surface 31a of the first dielectric layer 31 far from the substrate 1, the first side surface 32ae and the surface 32aa of the partition structure 32a far from the substrate 1, so that the Pixel Definition Layer (PDL) 5 can be prevented from being broken at the partition structure 32a, and the stress to which the Pixel Definition Layer (PDL) 5 is subjected in the transition region (i.e., the first side surface 32 ae) between the surface 31 of the first dielectric layer 31 far from the substrate 1 and the surface 32aa of the partition structure 32a far from the substrate 1 can be reduced, which is beneficial to improving the stability of the display panel 10.

In other embodiments, as shown in fig. 10, 13A, 13B and 13C, fig. 13A, 13B and 13C are each a structural diagram of a partition structure 32a of the display panel 10 according to some embodiments. Based on the side 32ab of the partition structure 32a near the first pixel opening K1, an undercut structure (undercut) is provided, and the side 32ac of the partition structure 32a near the second pixel opening K2 is at least partially attached to the side wall of the opening T.

For example, with continued reference to fig. 10, 13A, 13B and 13C, the slope of the side wall of the opening T near the undercut structure (undercut) is greater than the slope of the side wall of the opening T away from the undercut structure (undercut). Since the undercut structure (undercut) is provided near the side 32ab of the first pixel opening K1 in the embodiment shown in fig. 10, 13A, 13B and 13C, the inclination of the side wall of the side 32ab of the partition structure 32a near the opening T is larger than the inclination of the side wall of the side 32ac of the partition structure 32a near the opening T.

That is, the opening T is close, the side wall of the side 32ac of the partition structure 32a is relatively gentle, and the side wall is easily attached to the side wall of the side 32ac close to the first pixel opening K1 when the partition structure 32a is formed in the opening T, so that the side wall is easily attached to the side wall of the side 32ac of the first pixel opening K1.

Illustratively, as shown in fig. 13A, in the third direction Z, a distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 may be smaller than a distance d3 between the surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. That is, the first dielectric layer 31 is far from the surface 31a of the substrate 1, and far from the substrate 1 than the partition structure 32aa is far from the surface 32aa of the substrate 1.

Based on the surface 31a of the first dielectric layer 31 far from the substrate 1, the surface 32aa of the partition structure 32aa far from the substrate 1 is far from the substrate 1, and the side 32ac of the partition structure 32a near the second pixel opening K2 can be bonded to the side wall of the opening T entirely.

Or as shown in fig. 13B, in the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 may be equal to the distance d3 between the surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. That is, the first dielectric layer 31 is away from the surface 31a of the substrate 1, and the partition structure 32aa is flush away from the surface 32aa of the substrate 1.

Based on the fact that the surface 31a of the first dielectric layer 31 far from the substrate 1 and the surface 32aa of the partition structure 32aa far from the substrate 1 are flush, one side 32ac of the partition structure 32a near the second pixel opening K2 can be fully attached to the side wall of the opening T.

Further alternatively, as shown in fig. 13C, in the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 may be larger than the distance d3 between the surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. That is, the first dielectric layer 31 is far from the surface 31a of the substrate 1, and is closer to the substrate 1 than the partition structure 32aa is far from the surface 32aa of the substrate 1.

Based on the surface 31a of the first dielectric layer 31 away from the substrate 1, the surface 32aa of the partition structure 32aa away from the substrate 1 is closer to the substrate 1 than the surface 32aa of the partition structure 32aa is, a part of the partition structure 32a near the second pixel opening K2 may be attached to a sidewall of the opening T, another part extends out of the opening T, and the part of the partition structure 32a near the second pixel opening K2 extending out of the opening T is not in contact with the surface 31a of the first dielectric layer 31 away from the substrate 1.

Further, or as shown in fig. 10, in the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 may be greater than the distance d3 between the surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. That is, the first dielectric layer 31 is far from the surface 31a of the substrate 1, and is closer to the substrate 1 than the partition structure 32aa is far from the surface 32aa of the substrate 1.

Based on the surface 31a of the first dielectric layer 31 far away from the substrate 1, the surface 32aa of the partition structure 32aa far away from the substrate 1 is closer to the substrate 1, and one side 32ac of the partition structure 32a near the second pixel opening K2 may be attached to a side wall of the opening T, and another portion extends out of the opening T, and the portion of the partition structure 32a near the side 32ac of the second pixel opening K2 extending out of the opening T is attached to the surface 31a of the first dielectric layer 31 far away from the substrate 1.

For example, as shown in fig. 10, a portion of the partition structure 32a overlapping on the surface 31a of the first dielectric layer 31 away from the substrate 1 includes a first side surface 32ae, based on a portion of the partition structure 32a extending beyond the opening T near the side 32ac of the second pixel opening K2, overlapping on the surface 31a of the first dielectric layer 31 away from the substrate 1, the first side surface 32ae near the second pixel opening K2, and belonging to the side 32ac of the partition structure 32a near the second pixel opening K2.

The first side surface 32ae and the surface 31a of the first dielectric layer 31 remote from the substrate 1 have a first included angle R1. The first included angle R1 faces the opening T, and the first included angle R1 is an acute angle. That is, the first side surface 32ae is an inclined surface, so that the first dielectric layer 31 is away from the surface 31a of the substrate 1, and the first side surface 32ae can smoothly transition to the surface 32aa of the partition structure 32a away from the substrate 1.

In forming the Pixel Defining Layer (PDL) 5, the Pixel Defining Layer (PDL) 5 is formed on the surface 31a of the first dielectric layer 31 remote from the substrate 1, the first side surface 32ae, and the surface 32aa of the partition structure 32a remote from the substrate 1. Since the first dielectric layer 31 is far from the surface 31a of the substrate 1 and can be smoothly transited from the first side surface 32ae to the surface 32aa of the partition structure 32a far from the substrate 1, the Pixel Definition Layer (PDL) 5 can be continuously formed between the surface 31a of the first dielectric layer 31 far from the substrate 1, the first side surface 32ae and the surface 32aa of the partition structure 32a far from the substrate 1, so that the Pixel Definition Layer (PDL) 5 can be prevented from being broken at the partition structure 32a, and the stress to which the Pixel Definition Layer (PDL) 5 is subjected in the transition region (i.e., the first side surface 32 ae) between the surface 31 of the first dielectric layer 31 far from the substrate 1 and the surface 32aa of the partition structure 32a far from the substrate 1 can be reduced, which is beneficial to improving the stability of the display panel 10.

In some embodiments, as shown in fig. 14A and 14B, fig. 14A and 14B are both partial plan view block diagrams of the display panel 10 according to some embodiments. The partition structure 32a is disposed around the first pixel opening K1 or the second pixel opening K2, and the partition structure 32a has at least one notch Q.

Based on the partition structure 32a being disposed around the first pixel opening K1, and the partition structure 32a having at least one notch Q, at least the Charge Generation Layer (CGL) 62 in the light emitting function layer 6 can be disconnected at the partition structure 32a around the first pixel opening K1 and continuous at the notch Q, that is, at least the Charge Generation Layer (CGL) 62 of the light emitting function layer 6, a portion located within the first pixel opening K1 and other portions (for example, at least the Charge Generation Layer (CGL) 62 of the light emitting function layer 6, a portion located within the second pixel opening K2) are connected only at the notch Q, so that crosstalk between the first sub-pixel 91 and other sub-pixels 9 (for example, the second sub-pixel 92) caused by at least the Charge Generation Layer (CGL) 62 in the light emitting function layer 6 can be reduced, which is advantageous for improving the display effect of the display panel 10.

Based on the partition structure 32a being disposed around the second pixel opening K2, and the partition structure 32a having at least one notch Q, at least the Charge Generation Layer (CGL) 62 in the light emitting functional layer 6 can be disconnected at the partition structure 32a around the second pixel opening K2 and continuous at the notch Q, that is, at least the Charge Generation Layer (CGL) 62 of the light emitting functional layer 6, a portion located in the second pixel opening K2 and other portions (for example, at least the Charge Generation Layer (CGL) 62 of the light emitting functional layer 6, a portion located in the first pixel opening K1) are connected only at the notch Q, so that crosstalk between the second sub-pixel 92 and other sub-pixels 9 (for example, the first sub-pixel 91) caused by at least the Charge Generation Layer (CGL) 62 in the light emitting functional layer 6 can be reduced, which is advantageous for improving the display effect of the display panel 10.

For example, referring to fig. 14A, the partition structure 32a is disposed around the first pixel opening K1 or the second pixel opening K2, and the partition structure 32a has a notch Q.

Alternatively, referring to fig. 14B, the partition structure 32a is disposed around the first pixel opening K1 or the second pixel opening K2, and the partition structure 32a has a plurality of notches Q.

It will be appreciated that when the partition structure 32a has a plurality of notches Q, the partition structure 32a is divided into a plurality of block-shaped partition portions 32a ', i.e., the partition structure 32a includes a plurality of block-shaped partition portions 32a'. The plurality of partition parts 32a' are spaced apart around the first pixel opening K1 or the second pixel opening K2.

In other embodiments, as shown in fig. 15, fig. 15 is a partial plan view structural diagram of the display panel 10 according to some embodiments. The partition structure 32a has a closed loop shape surrounding the first pixel opening K1 or the second pixel opening K2.

Based on the partition structure 32a having a closed loop shape surrounding the first pixel opening K1, at least the Charge Generation Layer (CGL) 62 in the light emitting function layer 6 can be disconnected at the partition structure 32a surrounding the first pixel opening K1, i.e., at least the Charge Generation Layer (CGL) 62 of the light emitting function layer 6, the portion located within the first pixel opening K1 and the other portion (e.g., at least the Charge Generation Layer (CGL) 62) of the light emitting function layer 6, the portion located within the second pixel opening K2) are not connected, so that crosstalk between the first sub-pixel 91 and the other sub-pixels 9 (e.g., the second sub-pixel 92) caused by at least the Charge Generation Layer (CGL) 62 in the light emitting function layer 6 can be avoided, which is advantageous for further improving the display effect of the display panel 10.

Based on the partition structure 32a having a closed loop shape surrounding the second pixel opening K2, at least the Charge Generation Layer (CGL) 62 in the light emitting function layer 6 can be disconnected at the partition structure 32a surrounding the second pixel opening K2, i.e., at least the Charge Generation Layer (CGL) 62 of the light emitting function layer 6, the portion located within the second pixel opening K2 and the other portion (e.g., at least the Charge Generation Layer (CGL) 62 of the light emitting function layer 6, the portion located within the first pixel opening K1) are not connected, so that crosstalk between the second sub-pixel 92 and the other sub-pixels 9 (e.g., the first sub-pixel 91) caused by at least the Charge Generation Layer (CGL) 62 in the light emitting function layer 6 can be avoided, which is advantageous for further improving the display effect of the display panel 10.

In some embodiments, referring to fig. 14A, 14B and 15, the partition structure 32a includes a third sub-partition structure 323 located between the first sub-pixel 91 and the second sub-pixel 92, and the third sub-partition structure 323 may be a part of the partition structure 32a surrounding the first pixel opening K1 or a part of the partition structure 32a surrounding the second pixel opening K2, that is, only one partition structure 32a (i.e., the third sub-partition structure 323) is disposed between the first sub-pixel 91 and the second sub-pixel 92, and the third sub-partition structure 323 may be a common partition structure surrounding the first pixel opening K1 and the partition structure 32a surrounding the second pixel opening K2. The pitches of the first sub-pixel 91 and the second sub-pixel 92 can be reduced, so that the layout of the plurality of sub-pixels 9 in the display panel 10 is more compact, which is advantageous for improving the pixel density of the display panel 10.

In other embodiments, as shown in fig. 16, fig. 16 is a partial plan view block diagram of the display panel 10 according to some embodiments. The partition structure 32a surrounding the first pixel opening K1 includes a first sub-partition structure 321, and the partition structure 32a surrounding the second pixel opening K2 includes a second sub-partition structure 322. The first sub-partition structure 321 and the second sub-partition structure 322 are located between the first sub-pixel 91 and the second sub-pixel 92, and are sequentially disposed along the arrangement direction of the first sub-pixel 91 and the second sub-pixel 92.

That is, two partition structures 32a (i.e., a first sub-partition structure 321 and a second sub-partition structure 322) are provided between the first sub-pixel 91 and the second sub-pixel 92, and when at least the Charge Generation Layer (CGL) 62 in the light emitting function layer 6 is at one of the first sub-partition structure 321 and the second sub-partition structure 322, at least the Charge Generation Layer (CGL) 62 in the light emitting function layer 6 may be disconnected at the other of the first sub-partition structure 321 and the second sub-partition structure 322 when it is not disconnected or not completely disconnected. For example, when at least the Charge Generation Layer (CGL) 62 in the light emitting functional layer 6 is not disconnected or is not completely disconnected at the first sub-partition structure 321, at least the Charge Generation Layer (CGL) 62 in the light emitting functional layer 6 may be disconnected at the second sub-partition structure 322.

Therefore, by providing the first sub-blocking structure 321 and the second sub-blocking structure 322 in this order along the arrangement direction of the first sub-pixel 91 and the second sub-pixel 92 between the first sub-pixel 91 and the second sub-pixel 92, at least the Charge Generation Layer (CGL) 62 in the light emitting functional layer 6 can be completely disconnected at the blocking structure 32a, thereby further avoiding crosstalk between the first sub-pixel 91 and the second sub-pixel 92 caused by the Charge Generation Layer (CGL) 62 having relatively high conductivity, and facilitating improvement of the display effect of the display panel 10.

It should be noted that, in fig. 16, only the closed loop shape of the partition structure 32a surrounding the first pixel opening K1 or the second pixel opening K2 is taken as an example, the arrangement of the partition structure 32a between the first sub-pixel 91 and the second sub-pixel 92 is schematically illustrated, and the corresponding arrangement may be performed based on the case that the partition structure 32a is arranged around the first pixel opening K1 or the second pixel opening K2 and the partition structure 32a has at least one notch Q, which is not described herein again.

In some embodiments, the common electrode layer 7 may be continuous at the partition structure 32 a.

Or as shown in fig. 17, fig. 17 is a cross-sectional view of the display panel 10 according to some embodiments. The common electrode layer 7 may also be disconnected at the partition structure 32 a.

For example, referring to fig. 17, and in conjunction with fig. 14A and 14B, based on the partition structure 32a being disposed around the first pixel opening K1 or the second pixel opening K2, and the partition structure 32a having at least one notch Q, the common electrode layer 7 may be continuous at the at least one notch Q, so as to facilitate the transfer of a common electrode (e.g., cathode) signal between the first sub-pixel 91 and the second sub-pixel 92.

Alternatively, referring to fig. 17 in combination with fig. 15, based on the partition structure 32a having a closed loop shape surrounding the first pixel opening K1 or the second pixel opening K2, in order to ensure continuity of the common electrode layer 7 between the first sub-pixel 91 and the second sub-pixel 92, a connection structure may be added so that the common electrode layer 7 between the first sub-pixel 91 and the second sub-pixel 92 is continuous, so that a common electrode (e.g., cathode) signal is transferred between the first sub-pixel 91 and the second sub-pixel 92.

The method of manufacturing the display panel 10 will be described in detail below.

In some embodiments, as shown in fig. 18, fig. 18 is a flowchart of a method of manufacturing the display panel 10 according to some embodiments. The manufacturing method of the display panel 10 includes steps S1 to S3.

S1: as shown in fig. 19, fig. 19 is a structural diagram corresponding to step S1 in the manufacturing method of the display panel 10 according to the embodiment shown in fig. 18. A partition structure 32a is formed on the substrate 1.

S2: as shown in fig. 20, fig. 20 is a structural diagram corresponding to step S2 in the manufacturing method of the display panel 10 according to the embodiment shown in fig. 18. A pixel defining layer 5 is formed on the substrate 1 on which the partition structure 32a is formed.

The pixel defining layer 5 is provided with a plurality of pixel openings K. The plurality of pixel openings K include a first pixel opening K1 and a second pixel opening K2 that are adjacently disposed, and the partition structure 32a is located between the first pixel opening K1 and the second pixel opening K2.

The partition structure 32a is far from the surface 32aa of the substrate 1, and is closer to the substrate 1 than the surface 5aa of the pixel defining layer 5, which is far from the substrate 1; or the partition structure 32a is away from the surface 32aa of the substrate 1 and flush with the surface 5aa of the pixel defining layer 5 away from the substrate 1. That is, in the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 is smaller than or equal to the distance d1 between the surface 5aa of the pixel defining layer 5 away from the substrate 1 and the substrate 1.

S3: as shown in fig. 21, fig. 21 is a structural diagram corresponding to step S3 in the manufacturing method of the display panel 10 according to the embodiment shown in fig. 18. A light emitting functional layer 6 is formed on the side of the pixel defining layer 5 remote from the substrate 1.

With continued reference to fig. 6, the light-emitting functional layer 6 includes a first light-emitting layer 61a, a Charge Generation Layer (CGL) 62, and a second light-emitting layer 61b, which are sequentially stacked in a direction away from the substrate 1. The light-emitting functional layer 6, at least the Charge Generation Layer (CGL) 62 is broken at the partition structure 32 a.

By providing the partition structure 32a between the first pixel opening K1 and the second pixel opening K2 (i.e., between the first sub-pixel 91 and the second sub-pixel 92) and making at least the Charge Generation Layer (CGL) 62 in the light emitting functional layer 6 break at the partition structure 32a, crosstalk between the first sub-pixel 91 and the second sub-pixel 92 caused by the Charge Generation Layer (CGL) 62 with higher conductivity is avoided, which is beneficial to improving the display effect of the display panel 10.

Further, by keeping the partition structure 32a away from the surface 32aa of the substrate 1, it is not higher than the surface 5aa of the pixel defining layer 5 away from the substrate 1. On the one hand, when the light emitting functional layer 6 is formed by the vapor deposition process, scratch between the partition structure 32a and the mask plate can be avoided, so that scraps of the partition structure 32a formed by scratch can be avoided, normal light emission of the light emitting part 6a in the pixel opening K is ensured, the packaging reliability is improved, and the yield of the display panel 10 is improved.

On the other hand, since the partition structure 32a is not higher than the surface 32aa of the pixel defining layer 5 away from the substrate 1 and is away from the surface 5aa of the substrate 1, the shielding of the sub-pixels 9 by the partition structure 32 can be avoided in the side view state, and the visual experience of the display panel 10 is improved.

In some embodiments, referring to fig. 18, the method for manufacturing the display panel 10 further includes step S0 before the step S1.

S0: as shown in fig. 22, fig. 22 is a structural diagram corresponding to step S0 in the manufacturing method of the display panel 10 according to the embodiment shown in fig. 18. A first dielectric layer 31 is formed on the substrate 1. An opening T is formed in a surface 31a of the first dielectric layer 31 remote from the substrate 1.

For example, referring to fig. 22, forming an opening T on a surface 31a of the first dielectric layer 31 away from the substrate 1 may include the following steps:

A surface 31a of the first dielectric layer 31 remote from the substrate 1 is coated with a Photoresist (PR).

The first dielectric layer 31 is exposed using a Mask (Mask), and then subjected to a developing reaction to form an opening T.

In some embodiments, please continue to refer to fig. 18 in combination with fig. 23, fig. 23 is a structural diagram corresponding to step S1 in the manufacturing method of the display panel 10 according to the embodiment shown in fig. 18. Based on the above step S0, step S1 in the manufacturing method of the display panel 10 includes step S11 and step S12.

S11: a spacer layer 32 is formed on the side of the first dielectric layer 31 remote from the substrate 1.

S12: the target region M of the barrier layer 32 is subjected to exposure treatment to form a barrier structure 32a. At least part of the partition structure 32a is located within the opening T.

By arranging at least part of the partition structure 32a in the opening T, the height g1 of the partition structure 32a can be increased while ensuring that the partition structure 32a is not higher than the surface 5aa of the pixel definition layer 5 away from the substrate 1, which is to say, the distance between the surface 32aa of the partition structure 32a away from the substrate 1 and the surface 32ad of the partition structure 32a close to the substrate 1 is increased, so that the edge of the partition structure 32a has larger break difference, which is beneficial to improving the partition effect of the partition structure 32a on the light-emitting functional layer 6 and avoiding the light-emitting functional layer 6 from being continuous at the partition structure 32 a.

Illustratively, the material of barrier layer 32 includes a negative photosensitive material. The material of the barrier layer 32 may include, for example, a negative photoresist.

The portion of the negative photoresist that is irradiated with light (i.e., the exposed portion) is not dissolved in the photoresist developer, and the portion that is not irradiated with light (i.e., the portion other than the exposed portion) is dissolved in the photoresist developer or dissolved very slowly.

With continued reference to fig. 23, after forming the isolation layer 32 on the side of the first dielectric layer 31 away from the substrate 1 based on the material of the isolation layer 32 including negative photoresist, a Mask (Mask) may be used to expose the target area M of the isolation layer 32, and then a developing reaction may be performed to form the isolation structure 32a.

For example, with continued reference to fig. 23, a portion of the target area M overlaps the opening T, there is an overlap region J1, and a distance d5 is provided between the target area M and the sidewall of the opening T. At least part of the resulting partition structure 32a may be located within the opening T after the exposure process is performed on the target area M.

Another portion M1 of the target area M is located outside the opening T and is close to one of the first pixel opening K1 and the second pixel opening K2. After the exposure treatment is performed on the target area M, a portion of the obtained partition structure 32a may be overlapped on the surface 31a of the first dielectric layer 32 remote from the substrate 1.

For example, with continued reference to fig. 23, a dimension h1 of the portion of the partition layer 32 located within the opening T along the third direction Z (hereinafter, for convenience of description, collectively referred to as a thickness h1 of the portion of the partition layer 32 located within the opening T) is greater than a dimension h2 of the portion of the partition layer 32 not located within the opening T along the third direction Z (hereinafter, for convenience of description, collectively referred to as a thickness h2 of the portion of the partition layer 32 not located within the opening T).

In the exposure process of the target area M of the partition layer 32, since the thickness h1 of the portion of the target area M located in the opening T is large, the side of the portion of the target area M located in the opening T away from the Mask may be underexposed, and easily dissolved in the photoresist developer, forming an undercut structure (undercut).

When the exposure process is performed on the target area M of the partition layer 32, since the thickness h2 of the portion of the target area M not located in the opening T is small, the portion of the target area M not located in the opening T can be sufficiently exposed, and after the development process is performed, the portion of the first dielectric layer 32 overlapping the surface 31a of the substrate 1, which is far from the undercut structure (undercut), may be beveled.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art who is skilled in the art will recognize that changes or substitutions are within the technical scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (20)

1. A display panel, comprising:

The substrate is provided with a plurality of grooves,

A pixel defining layer located at one side of the substrate; the pixel definition layer is provided with a plurality of pixel openings, and the pixel openings comprise a first pixel opening and a second pixel opening which are adjacently arranged;

A light emitting function layer located at one side of the pixel defining layer away from the substrate, wherein a part of the light emitting function layer is located in the first pixel opening and the second pixel opening; the light-emitting functional layer comprises a first light-emitting layer, a charge generation layer and a second light-emitting layer which are sequentially stacked along the direction far away from the substrate, wherein at least part of the charge generation layer in the light-emitting functional layer is positioned between the first pixel opening and the second pixel opening;

A blocking structure located between the first pixel opening and the second pixel opening, in which at least the charge generation layer is broken at the blocking structure;

the partition structure is far away from the surface of the substrate and is close to the substrate compared with the surface of the pixel definition layer, which is far away from the substrate; or the partition structure is away from the surface of the substrate and is flush with the surface of the pixel defining layer away from the substrate.

2. The display panel of claim 1, further comprising a first dielectric layer between the partition structure and the substrate;

The surface of the first dielectric layer, which is far away from the substrate, is provided with an opening, and at least part of the partition structure is positioned in the opening.

3. The display panel of claim 2, wherein the first dielectric layer is further from the surface of the substrate than the partition structure is from the surface of the substrate.

4. The display panel according to claim 2, wherein the partition structure is provided with an undercut structure at a side close to the first pixel opening; and/or, one side of the partition structure, which is close to the second pixel opening, is provided with an undercut structure;

the undercut structure is positioned in the opening, and a space is reserved between the undercut structure and the side wall of the opening;

in the light emitting functional layer, at least the charge generating layer is disconnected at the undercut structure.

5. The display panel according to claim 4, wherein the partition structure is provided with an undercut structure near one side of one of the first pixel opening and the second pixel opening;

The partition structure is close to one side of the other one of the first pixel opening and the second pixel opening, and at least part of the partition structure is attached to the side wall of the opening.

6. The display panel of claim 5, wherein a side of the partition structure adjacent to the other of the first pixel opening and the second pixel opening partially overlaps a surface of the first dielectric layer remote from the substrate.

7. The display panel of claim 6, wherein the portion of the partition structure overlapping the surface of the first dielectric layer remote from the substrate comprises a first side surface proximate the other of the first pixel opening and the second pixel opening, the first side surface and the surface of the first dielectric layer remote from the substrate having a first included angle; the first included angle faces the opening, and the first included angle is an acute angle.

8. The display panel of claim 1, wherein the partition structure has a closed loop shape surrounding the first pixel opening or the second pixel opening.

9. The display panel of claim 8, further comprising a common electrode layer located on a side of the second light emitting layer remote from the substrate; the common electrode layer is continuous at the partition structure.

10. The display panel of claim 1, wherein the partition structure is disposed around the first pixel opening or the second pixel opening, and the partition structure has at least one notch.

11. The display panel of claim 10, further comprising a common electrode layer located on a side of the second light emitting layer remote from the substrate; the common electrode layer is broken at the partition structure and continuous at the at least one notch.

12. The display panel of claim 10, wherein the partition structure includes a plurality of block-shaped partitions, the plurality of partitions being spaced around the first pixel opening or the second pixel opening.

13. The display panel according to any one of claims 1 to 12, wherein the partition structure comprises a negative photosensitive material.

14. The display panel of any one of claims 5-7, wherein a slope of a side wall of the opening proximate to the undercut structure is greater than a slope of a side wall of the opening distal from the undercut structure.

15. The display panel according to any one of claims 2 to 7, wherein a depth of the opening is smaller than a thickness of the first dielectric layer.

16. A method for manufacturing a display panel, comprising:

forming a partition structure on a substrate;

Forming a pixel defining layer on the substrate on which the partition structure is formed; the pixel definition layer is provided with a plurality of pixel openings, each pixel opening comprises a first pixel opening and a second pixel opening which are adjacently arranged, and the partition structure is positioned between the first pixel opening and the second pixel opening; the partition structure is far away from the surface of the substrate and is close to the substrate compared with the surface of the pixel definition layer, which is far away from the substrate; or the partition structure is away from the surface of the substrate and is flush with the surface of the pixel definition layer away from the substrate;

Forming a light emitting function layer on one side of the pixel defining layer away from the substrate; the light-emitting functional layer comprises a first light-emitting layer, a charge generation layer and a second light-emitting layer which are sequentially stacked along a direction away from the substrate; in the light-emitting functional layer, at least the charge generation layer is disconnected at the partition structure.

17. The method of manufacturing a display panel according to claim 16, wherein before the forming of the partition structure on the substrate, further comprising:

Forming a first dielectric layer on a substrate;

forming an opening on the surface of the first dielectric layer, which is far away from the substrate;

wherein at least part of the partition structure is located within the opening.

18. The method of manufacturing a display panel according to claim 17, wherein the forming a partition structure on the substrate comprises:

Forming a separation layer on one side of the first dielectric layer away from the substrate;

Exposing the target area of the isolating layer to form an isolating structure;

wherein a portion of the target region overlaps the opening with a spacing from a sidewall of the opening; another portion of the target area is located outside the opening and proximate to the other of the first pixel opening and the second pixel opening.

19. The method of claim 18, wherein the material of the insulating layer comprises a negative photosensitive material.

20. A display device, comprising:

the display panel according to any one of claims 1 to 15;

and the cover plate is arranged on the light emitting side of the display panel.