CN114335122A - Display panel and display device - Google Patents

Abstract

The disclosure relates to the technical field of display, in particular to a display panel and a display device, which are used for improving the display effect of the display device. The display panel comprises a substrate, an anode layer, a pixel definition layer, a light-emitting functional layer and at least one conductive pattern. The anode layer includes a plurality of anodes; the pixel defining layer is provided with a plurality of openings, and one opening is arranged corresponding to one anode; the light-emitting functional layer is in contact with the anode through the opening; the at least one conductive pattern is arranged on one side, close to the substrate, of the light-emitting functional layer, orthographic projections of the conductive patterns on the substrate are located between orthographic projections of two adjacent anodes on the substrate, the conductive patterns are in contact with the light-emitting functional layer, the conductive patterns are configured to transmit blocking voltage, and the blocking voltage is smaller than working voltage transmitted by the anodes adjacent to the conductive patterns. By arranging the conductive patterns, crosstalk current generated between adjacent sub-pixels in the display panel is reduced, so that the display effect of the display device is improved.

Description

Display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

With the continuous development of the display technology field, the Organic Light-Emitting Diode (OLED) display device is widely used by virtue of its characteristics of full-screen, narrow frame, high resolution, curling, wearing, folding, etc.

The display effect of the display device is one of the most important performances of electronic products, and how to reduce the crosstalk current generated between adjacent sub-pixels, thereby improving the display effect of the display device and enhancing the image quality of the electronic products is a problem which is continuously researched in the industry.

Disclosure of Invention

Embodiments of the present disclosure provide a display panel and a display device, which aim to reduce crosstalk current generated between adjacent sub-pixels in the display panel and improve a display effect of the display device.

In order to achieve the purpose, the embodiment of the disclosure adopts the following technical scheme:

in one aspect, a display panel is provided, the display panel including: the display device comprises a substrate, an anode layer, a pixel definition layer, a light-emitting functional layer and at least one conductive pattern.

Wherein the anode layer is disposed on the substrate, the anode layer including a plurality of anodes. The pixel defining layer is arranged on one side of the anode layer far away from the substrate, the pixel defining layer is provided with a plurality of openings, and one opening is arranged corresponding to one anode. The light-emitting function layer is arranged on one side, far away from the substrate, of the pixel defining layer, and the light-emitting function layer is in contact with the anode through the opening. The at least one conductive pattern is arranged on one side of the light-emitting functional layer close to the substrate; the orthographic projection of the conductive pattern on the substrate is positioned between the orthographic projections of two adjacent anodes on the substrate, the conductive pattern is in contact with the light-emitting functional layer, and the conductive pattern is configured to transmit a blocking voltage which is smaller than an operating voltage transmitted by the anodes adjacent to the conductive pattern.

According to the display panel provided by some embodiments of the present disclosure, by providing the conductive pattern, a part of carriers in the light emitting functional layer corresponding to the anode adjacent to the conductive pattern is received, the carriers in the part of the light emitting functional layer corresponding to one anode are interrupted, and flow to the transmission path of the part corresponding to the other anode, so that crosstalk current is prevented from being generated between sub-pixels corresponding to two anodes, thereby preventing the sub-pixels from generating a problem of poor display under the influence of the crosstalk current, and improving the display effect of the display device.

In some embodiments, the at least one conductive pattern is disposed between the pixel defining layer and the substrate.

In some embodiments, the at least one conductive pattern is provided on the anode layer; the pixel defining layer is provided with at least one first through hole, the first through hole is arranged between two adjacent openings of the pixel defining layer, and the light-emitting function layer is in contact with the conductive pattern through the first through hole.

In some embodiments, the display panel further comprises: at least one conductive layer and an insulating layer. The at least one conducting layer is arranged between the substrate and the anode layer, the conducting layer closest to the anode layer in the at least one conducting layer is a target conducting layer, and the conducting pattern is arranged on the target conducting layer; the insulating layer is disposed between the target conductive layer and the anode layer.

The pixel defining layer is provided with at least one first through hole, and the first through hole is arranged between two adjacent openings of the pixel defining layer. The insulating layer is provided with at least one second via hole, and the second via hole is communicated with the first via hole. The light-emitting functional layer is in contact with the conductive pattern through a first via hole and a second via hole which are communicated.

In some embodiments, the display panel includes a source-drain conductive layer disposed between the substrate and the anode layer, and the source-drain conductive layer is the target conductive layer; or, the display panel comprises a source-drain conducting layer arranged between the substrate and the anode layer, and at least one switching conducting layer arranged between the source-drain conducting layer and the anode layer, wherein the switching conducting layer closest to the anode layer in the at least one switching conducting layer is a target conducting layer.

In some embodiments, the at least one conductive pattern is disposed between the pixel defining layer and the light emitting functional layer.

In some embodiments, the display panel further comprises: a first power supply line and/or an initialization signal line disposed between the substrate and the anode layer. The first power line is configured to transmit a low-level voltage signal, and the initialization signal line is configured to transmit an initialization signal. Wherein at least one of the conductive patterns is electrically connected to the first power line; and/or at least one conductive pattern is electrically connected with the initialization signal line.

In some embodiments, a first conductive pattern and a second conductive pattern are disposed between two adjacent anodes; and the first conductive pattern and the second conductive pattern are arranged side by side along the direction of a central connecting line of the two adjacent anodes.

In some embodiments, the two adjacent anodes are a first anode and a second anode, respectively, the first anode is adjacent to the first conductive pattern, and the second anode is adjacent to the second conductive pattern. The first conductive pattern is configured to transmit a first blocking voltage, the second conductive pattern is configured to transmit a second blocking voltage, and the first blocking voltage is greater than the second blocking voltage. The first anode is configured to transmit an operating voltage greater than or equal to a first initial lighting voltage, and the second anode is configured to transmit an operating voltage greater than or equal to a second initial lighting voltage, the second initial lighting voltage being greater than the first initial lighting voltage.

In some embodiments, the light emitting function layer includes a plurality of light emitting patterns, and one light emitting pattern is disposed corresponding to one anode. The light emitting pattern disposed corresponding to the first anode can emit green light, and the light emitting pattern disposed corresponding to the second anode can emit red light.

In some embodiments, the display panel further comprises: a first power line and an initialization signal line disposed between the substrate and the anode layer. The first power line is configured to transmit a low-level voltage signal, and the initialization signal line is configured to transmit an initialization signal, a voltage of the low-level voltage signal being greater than a voltage of the initialization signal. Wherein the first conductive pattern is electrically connected to the first power line, and the second conductive pattern is electrically connected to the initialization signal line.

In some embodiments, the display panel further comprises: an initialization signal line disposed between the substrate and the anode layer, the initialization signal line including a first initialization signal line and a second initialization signal line. The first initialization signal line is configured to transmit a first initialization signal, the second initialization signal line is configured to transmit a second initialization signal, and a voltage of the first initialization signal is greater than a voltage of the second initialization signal. Wherein the first conductive pattern is electrically connected to the first initialization signal line, and the second conductive pattern is electrically connected to the second initialization signal line.

In some embodiments, the conductive pattern has a shape of a strip, and a length extending direction of the conductive pattern coincides with an extending direction of a side of the opening adjacent to the conductive pattern.

In some embodiments, the display panel includes a plurality of sub-pixels, each sub-pixel including an anode. In two sub-pixels to which two anodes adjacent to the conductive pattern belong, light that one of them can emit is light of a different color from light that the other can emit.

In some embodiments, the light emitting functional layer comprises: the light-emitting device comprises a first sub light-emitting functional layer, a heterojunction structure layer and a second sub light-emitting functional layer which are stacked along the thickness direction of the substrate, wherein the heterojunction structure layer is positioned between the first sub light-emitting functional layer and the second sub light-emitting functional layer.

The display panel comprises a plurality of sub-pixels, each sub-pixel comprises a first light-emitting pattern and a second light-emitting pattern, the first light-emitting pattern is arranged on the first sub-light-emitting functional layer, the second light-emitting pattern is arranged on the second sub-light-emitting functional layer, and the first light-emitting pattern and the second light-emitting pattern are arranged corresponding to the same opening of the pixel defining layer.

In another aspect, there is provided a display device including: the display panel of any preceding embodiment.

It can be understood that the beneficial effects achieved by the display device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the display panel in the foregoing, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic and are not intended to limit the actual size of products to which embodiments of the disclosure relate.

FIG. 1 is a block diagram of a display device provided in accordance with some embodiments;

FIG. 2 is a top view of a display panel provided in accordance with some embodiments;

FIG. 3 is a cross-sectional view taken along section line A-A' of FIG. 2;

FIG. 4 is a schematic illustration of a transport of carriers provided according to some embodiments;

FIG. 5 is a schematic illustration of another transport of carriers provided according to some embodiments;

FIG. 6 is another cross-sectional view taken along section line A-A' of FIG. 2;

FIG. 7 is another cross-sectional view taken along section line A-A' of FIG. 2;

FIG. 8 is another cross-sectional view taken along section line A-A' of FIG. 2;

FIG. 9 is a structural diagram corresponding to the area B in FIG. 3;

FIG. 10 is a schematic view of another transport of carriers provided in accordance with some embodiments;

FIG. 11 is another structural diagram corresponding to the area B in FIG. 3;

FIG. 12 is another structural diagram corresponding to the area B in FIG. 3;

FIG. 13 is a block diagram of an arrangement of sub-pixels according to some embodiments;

FIG. 14 is a block diagram of another arrangement of subpixels provided in accordance with some embodiments;

figure 15 is a cross-sectional view of a light emitting functional layer provided according to some embodiments.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "electrically connected" and "connected" and derivatives thereof may be used. For example, the term "electrically connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Fig. 1 shows a top view of a display device 100. As shown in fig. 1, some embodiments of the present disclosure provide a display device 100, which display device 100 may be any device that displays images, whether in motion (e.g., video) or stationary (e.g., still images), and whether textual or textual. More particularly, it is contemplated that embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, Personal Data Assistants (PDAs), hand-held or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), navigators, cockpit controls and/or displays, displays of camera views (e.g., of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., a display of images for a piece of jewelry), and so forth. Fig. 1 illustrates the display device 100 as a mobile phone.

As shown in fig. 1, the display device 100 includes a display panel 200. The display panel 200 may be an electroluminescent display panel. In the case where the display panel 200 is an electroluminescent display panel, the electroluminescent display panel may be an Organic Light-Emitting Diode (OLED) display panel.

Fig. 2 shows a top view of the display panel 200 of fig. 1. As shown in fig. 2, the display panel 200 includes a plurality of subpixels P. The plurality of subpixels P includes at least a subpixel capable of emitting a first color light, a subpixel capable of emitting a second color, and a subpixel capable of emitting a third color. The first, second and third colors are three primary colors (e.g., red, green and blue).

Fig. 3 shows a cross-sectional view of the display panel 200 in fig. 2 at a section line a-a'. As shown in fig. 3, some embodiments of the present disclosure provide a display panel 200, the display panel 200 includes a substrate 10, an anode layer 301, a pixel defining layer 302, a light emitting function layer 303, and at least one conductive pattern R.

Illustratively, the substrate 10 may have a single-layer structure or a multi-layer structure. For example, as shown in fig. 3, the substrate 10 may include a flexible base layer 101 and a buffer layer 102, which are sequentially stacked. For another example, the substrate 10 may include a plurality of flexible base layers 101 and a plurality of buffer layers 102 alternately arranged. The material of the flexible base layer 101 may include polyimide, and the material of the buffer layer 102 may include silicon nitride and/or silicon oxide, so as to achieve the effects of blocking water and oxygen and blocking alkali ions.

As shown in fig. 3, the anode layer 301 is provided on the substrate 10, and the anode layer 301 includes a plurality of anodes L1. Anode L1 is configured to transmit an operating voltage.

Illustratively, the anode L1 transmits a high level voltage, for example, the operating voltage is greater than 0V, and different operating voltages correspond to different gray levels, so as to drive the light-emitting function layer 303 to emit light with different brightness.

Illustratively, the anode layer 301 may be a stacked structure of a transparent conductive oxide-metal-transparent conductive oxide. The transparent conductive oxide material is, for example, indium tin oxide or indium zinc oxide, and the metal material is, for example, gold, silver, nickel, or platinum. For example, the anode layer 301 is an indium tin oxide-silver-indium zinc oxide stack structure.

Illustratively, the display panel 200 includes a driving circuit layer 20 disposed between the substrate 10 and the anode layer 301, the driving circuit layer 20 being electrically connected to the anode L1 to supply a voltage to the anode L1.

As shown in fig. 3, the pixel defining layer 302 is disposed on a side of the anode layer 301 away from the substrate 10, and the pixel defining layer 301 is provided with a plurality of openings K, one opening K corresponding to one anode L1.

It will be appreciated that each opening K exposes at least a portion of the anode L1, i.e. the orthographic projection of opening K on substrate 10 is within the range of the orthographic projection of anode L1 on substrate 10.

Illustratively, the material of the pixel defining layer 302 may include an organic material.

As shown in fig. 3, the light-emitting function layer 303 is provided on the side of the pixel defining layer 302 away from the substrate 10, and the light-emitting function layer 303 is in contact with the anode L1 through the opening K.

For example, at least a part of the light-emitting functional layer 303 is located in the opening K of the pixel defining layer 302 and is in contact with the anode L1 located on the side of the pixel defining layer 302 close to the substrate 10.

Illustratively, the light emitting function layer 303 includes a light emitting pattern L3, and the light emitting pattern L3 may include a small molecule organic material or a polymer molecule organic material, may be a fluorescent light emitting material or a phosphorescent light emitting material, may emit red light, blue light, green light, or white light, or the like.

Illustratively, the material of the light emitting pattern L3 capable of emitting light of different colors is different.

As shown in fig. 3, the display panel 200 further includes a cathode layer 304, serving as a cathode L2, disposed on a side of the light emitting function layer 303 away from the substrate 10 and configured to supply a low-level voltage, for example, a voltage of 0V, to the light emitting function layer 303. The light emitting pattern L3 is provided between the anode layer 301 and the cathode layer 304, and a high level voltage applied to the anode layer 301 (i.e., the anode L1) and a low level voltage applied to the cathode layer 304 (i.e., the cathode L2) form an electric field, thereby driving holes in the anode L1 and electrons in the cathode L2 to migrate to the light emitting function layer 303 and recombine in the light emitting pattern L3, so that the light emitting layer L3 emits light.

Illustratively, the cathode layer 304 is made of a metal or alloy material. The metal material is, for example, a metal such as aluminum, silver, or magnesium, and the alloy material is, for example, a magnesium-silver alloy or a silver-lithium alloy.

Illustratively, the light emitting function Layer 303 further includes a common Layer 305, and the common Layer 305 includes one or more of an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), a Hole Blocking Layer (HBL), a Hole Transport Layer (HTL), a Hole Injection Layer (HIL), and an Electron Blocking Layer (EBL).

The common layer 305 serves as a transition medium for carriers (including the aforementioned electrons and holes) to migrate to the light emitting pattern L3, thereby reducing the barrier height to be overcome for carrier transition and improving the light emitting efficiency of the display panel 200. The higher the conductivity of the common layer 305, the higher the light emitting efficiency of the display panel 200.

Illustratively, the common layer 305 is a structure in which the entire layers are connected, that is, the common layer 305 is shared by the light emitting patterns L3 emitting different colors.

As shown in fig. 3, at least one conductive pattern R is provided on the side of the light-emitting functional layer 303 close to the substrate 10; the orthographic projection of the conductive pattern R on the substrate 10 is located between the orthographic projections of the adjacent two anodes L1 on the substrate 10, and the conductive pattern R is in contact with the light-emitting functional layer 303, and the conductive pattern R is configured to transmit a blocking voltage that is smaller than an operating voltage transmitted by the anode L1 adjacent to the conductive pattern R.

The term "adjacent" in the "anode L1 adjacent to the conductive pattern R" means that the orthographic projection of the anode L1 on the substrate 10 is adjacent to the orthographic projection of the conductive pattern R on the substrate 10.

Exemplarily, the conductive pattern R is in contact with the common layer 305 in the light emitting function layer 303. For example, as shown in fig. 3, the conductive pattern R is in contact with the hole transport layer HTL in the light emitting function layer 303.

Illustratively, the blocking voltage conveys a low level voltage, e.g., the blocking voltage is 0V, -1V, -2V, etc.

In the related art, in order to improve the light emitting efficiency of the display panel, the material of the common layer is usually selected to have higher conductivity, which causes a charge transfer phenomenon (i.e., the flow and transmission of carriers between adjacent sub-pixels) in the common layer between adjacent sub-pixels; moreover, with the improvement of the resolution of the display panel, the distance between adjacent sub-pixels is closer and closer, the charge transfer difficulty of the common layer between adjacent sub-pixels is reduced, and the charge transfer phenomenon is aggravated; in addition, the two parts of the common layer corresponding to the two adjacent sub-pixels emitting different colors have different carrier densities, and the carriers easily flow from the side with higher density to the side with lower density, so that the charge transfer phenomenon is aggravated; in addition, when the luminance of two adjacent sub-pixels is different, that is, the working voltage of the anode is different, a weak electric field is formed between the two adjacent sub-pixels, and the electric charges in the common layer are more easily transferred under the driving of the electric field.

As shown in fig. 4, the inventors of the present disclosure have studied and found that a charge transfer phenomenon easily occurs between the sub-pixels P' adjacently disposed, so that a crosstalk current (arrow Z is a carrier transmission direction) is generated, and a display effect of the display panel is affected. For example, when one of two adjacent sub-pixels P 'needs to emit light and the other does not need to emit light, the sub-pixel P' which does not need to emit light is slightly bright due to crosstalk current caused by a charge transfer phenomenon, and poor display occurs; for another example, the sub-pixel P 'needs to emit light meeting the brightness requirement, and when crosstalk current is generated due to charge migration, the luminance of the sub-pixel P' may deviate, so that it cannot display accurate color.

In the display panel 200 according to some embodiments of the present disclosure, by disposing the conductive pattern R between the adjacent sub-pixels P and contacting (i.e., electrically connecting) the conductive pattern R with the light emitting function layer 303, the transmission of carriers in the common layer 305 between the adjacent sub-pixels P can be blocked under the condition that the blocking voltage transmitted by the conductive pattern R is less than the operating voltage transmitted by the anode L1 of the sub-pixel P adjacent to the conductive pattern R.

For example, as shown in fig. 5, charges diffused between two adjacent sub-pixels P are transferred toward the conductive pattern R (the first arrow Z1 and the second arrow Z2 are the transmission direction of carriers), so that the charge transfer between the two adjacent sub-pixels P is interrupted, a crosstalk current is prevented from being generated between the two sub-pixels P, problems such as poor display caused by the crosstalk current are prevented, the accuracy of the display luminance of the sub-pixels P is improved, and the display effect of the display panel 200 is improved.

As shown in fig. 3, the driving circuit layer 20 illustratively includes an active layer 201, a first gate insulating layer 202, a first gate conductive layer 203, a second gate insulating layer 204, a second gate conductive layer 205, an interlayer dielectric layer 206, a source-drain conductive layer 21, and a planarization layer 22, which are sequentially stacked and disposed on the substrate 10. An anode layer 301 is disposed over the planarization layer 22.

Alternatively, only one layer or a plurality of layers may be provided for the source-drain conductive layer 21. In the case where the source-drain conductive layer 21 is provided in a plurality of layers, the planarization layer 22 is also provided in a plurality of layers.

Alternatively, the driver circuit layer 20 may be provided with only one gate conductive layer (e.g., only the first gate conductive layer 203 or only the second gate conductive layer 205), in which case, accordingly, the gate insulating layer is also provided with only one layer (e.g., only the first gate insulating layer 202).

Illustratively, the driving circuit layer 20 is provided with a plurality of thin film transistors and a plurality of capacitive structures Cst.

Alternatively, the thin film transistor may be a top gate type, a bottom gate type, or a double gate type structure.

The thin film transistor includes a gate electrode T1, a source electrode T2, a drain electrode T3, and an active layer pattern T4. The gate electrode T1 is disposed on the first gate conductive layer 203, the source electrode T2 and the drain electrode T3 are disposed on the source drain conductive layer 21, and the active layer pattern T4 is disposed on the active layer 201.

For example, the source electrode T2 or the drain electrode T3 of the thin film transistor may be electrically connected to the anode L1.

The capacitive structure Cst includes a first plate Cst1 and a second plate Cst2, wherein the first plate Cst1 is located on the first gate conductive layer 203, and the second plate Cst2 is located on the second gate conductive layer 205.

Illustratively, the display panel 200 further includes an encapsulation layer 40 disposed on a side of the cathode layer 304 remote from the substrate 10. The encapsulation layer 40 may include a first encapsulation sub-layer 41, a second encapsulation sub-layer 42, and a third encapsulation sub-layer 43, which are sequentially stacked away from the substrate 10. Illustratively, the material of the first and third encapsulation sub-layers 41 and 43 includes an inorganic material, and the material of the second encapsulation sub-layer 42 includes an organic material. The first and third encapsulating sub-layers 41, 43 have a function of blocking water vapor and oxygen, while the second encapsulating sub-layer 42 has a certain flexibility and a function of absorbing water vapor, and the like.

In some embodiments, at least one conductive pattern R is provided between the pixel defining layer 302 and the substrate 10.

As shown in fig. 3, in some embodiments, at least one conductive pattern R is provided on the anode layer 301. The pixel defining layer 302 is provided with at least one first via H1, the first via H1 is provided between two adjacent openings K of the pixel defining layer 302, and the light emitting function layer 303 is in contact with the conductive pattern R through the first via H1.

It should be noted that the conductive pattern R is insulated from the anode L1.

It is understood that the conductive pattern R is disposed in the same layer as the anode L1. The "same layer" refers to a layer structure formed by forming a film layer for forming a specific pattern by the same film formation process and then performing a patterning process once using the same mask plate. Depending on the specific pattern, the single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and the specific patterns may be at different heights or have different thicknesses.

By arranging the conductive pattern R on the anode layer 301, the crosstalk current generated between two adjacent sub-pixels P is blocked, the display effect of the display panel 200 is improved, and meanwhile, the conductive pattern R can be simultaneously manufactured in the process of manufacturing the anode L1 without increasing the process of independently manufacturing the conductive pattern R, so that the difficulty of the manufacturing process of the display panel 200 is reduced, and the process cost is reduced.

As shown in fig. 6, in some embodiments, at least one conductive pattern R is provided between the pixel defining layer 302 and the light emitting function layer 303. The conductive pattern R is in contact with the light emitting functional layer 303.

The conductive pattern R is disposed above the pixel defining layer 302 to block the crosstalk current generated between two adjacent sub-pixels P, so as to improve the display effect of the display panel 200, and meanwhile, the arrangement of the conductive pattern R is not limited by the position of the anode L1, so that the operation space during preparation is increased, and the process difficulty is further reduced.

As shown in fig. 7 and 8, in some embodiments, the display panel 200 further includes at least one conductive layer M and an insulating layer N.

At least one conductive layer M is disposed between the substrate 10 and the anode layer 301, a conductive layer closest to the anode layer 301 among the at least one conductive layer M is a target conductive layer M ', and the conductive pattern R is disposed on the target conductive layer M'; the insulating layer N is disposed between the target conductive layer M' and the anode layer 301.

Wherein, the pixel defining layer 302 is provided with at least one first via H1, and the first via H1 is provided between two adjacent openings K of the pixel defining layer 302; the insulating layer N is provided with at least one second via H2, the second via H2 being in communication with the first via H1. The light emitting function layer 303 is in contact with the conductive pattern R through the first via hole H1 and the second via hole H2 which are communicated.

The conductive pattern R is disposed on a side of the anode layer 301 close to the substrate 10, and is convenient for the conductive pattern R to be electrically connected to a signal line in the driving circuit layer 20 for transmitting a low-level voltage while blocking a crosstalk current generated between two adjacent sub-pixels P, so as to improve a display effect of the display panel 200.

Illustratively, the display panel 200 includes a source-drain conductive layer 21 disposed between the substrate 10 and the anode layer 301, the source-drain conductive layer 21 being a target conductive layer M', and a conductive pattern R disposed on the source-drain conductive layer 21. Wherein the insulating layer N comprises a planarization layer 22 between the anode layer 301 and the source drain conductive layer 21.

Illustratively, in the case where the source-drain conductive layer 21 is provided with a plurality of layers, the layer closest to the anode layer 301 is the target conductive layer M'.

For example, as shown in fig. 7, the source-drain conductive layer 21 includes a first source-drain conductive layer 207 and a second source-drain conductive layer 210, and accordingly, the planarization layer 22 includes a first planarization layer 209 and a second planarization layer 211, the first planarization layer 209 is disposed between the first source-drain conductive layer 207 and the second source-drain conductive layer 210, and the second planarization layer 211 is disposed between the second source-drain conductive layer 210 and the anode layer 301.

With respect to the first source-drain conductive layer 207, the second source-drain conductive layer 210 closer to the anode layer 301 is the target conductive layer M', the conductive pattern R is disposed on the second source-drain conductive layer 210, at this time, the insulating layer N includes a second planarization layer 211 disposed between the anode layer 301 and the second source-drain conductive layer 210, the second planarization layer 211 is provided with a second via hole H2, and the conductive pattern R is electrically connected to the light-emitting function layer 303 through the second via hole H2 and the first via hole H1 of the pixel defining layer 302.

Illustratively, the display panel 200 further includes a passivation layer 208 disposed between the first source-drain conductive layer 207 and the first planarization layer 209.

Illustratively, the second source-drain conductive layer 210 is provided with a connection pattern 210 ', and the anode L1 is electrically connected to the thin film transistor through the connection pattern 210'.

As shown in fig. 8, the display panel 200 further includes at least one via conductive layer 31 and a sub-insulating layer 32. At least one via conductive layer 31 is disposed between the source/drain conductive layer 21 and the anode layer 301, and a sub-insulating layer 32 is disposed between the via conductive layer 31 and the anode layer 301. Illustratively, the anode L1 is electrically connected to the tft through the via conductive layer 31.

The via conductive layer closest to the anode layer 301 of the at least one via conductive layer 31 is the target conductive layer M', and the conductive pattern R is disposed on the via conductive layer 31. The insulating layer N includes a sub-insulating layer 32, the sub-insulating layer 32 is located between the anode layer 301 and the via conductive layer closest to the anode layer 301, the sub-insulating layer 32 is provided with a second via H2, and the conductive pattern R is electrically connected to the light emitting functional layer 303 through the second via H2 and the first via H1 of the pixel defining layer 302.

Illustratively, the material of the switching conductive layer 31 is a transparent material, for example, indium tin oxide.

As shown in fig. 9, in some embodiments, a first conductive pattern R1 and a second conductive pattern R2 are provided between adjacent two anodes L1; the first conductive pattern R1 and the second conductive pattern R2 are arranged side by side in the direction of the center connecting line Li of the adjacent two anodes L1.

That is, the plurality of conductive patterns R include a first conductive pattern R1 and a second conductive pattern R2, and two conductive patterns R are disposed between two adjacent anodes L1, one of the conductive patterns R1 is the first conductive pattern R1, and the other is the second conductive pattern R2.

Wherein the first conductive pattern R1 is configured to transmit a first blocking voltage, and the second conductive pattern R2 is configured to transmit a second blocking voltage, both of which are less than an operating voltage transmitted by the sub-pixel P disposed adjacent to the two conductive patterns R (i.e., an operating voltage transmitted by the anode L1).

For example, as shown in fig. 9, a first conductive pattern R1 and a second conductive pattern R2 are disposed between two adjacent sub-pixels P, and charges diffused by the sub-pixels P relatively closer to the first conductive pattern R1 are transferred toward the first conductive pattern R1, while charges diffused by the sub-pixels P relatively closer to the second conductive pattern R2 are transferred toward the second conductive pattern R2.

The first conductive pattern R1 transmits a first blocking voltage less than the operating voltage of the subpixel P so that charges in the subpixel P light emitting functional layer 303 adjacent to the first conductive pattern R1 may be transferred to the first conductive pattern R1 and may be blocked by the second conductive pattern R2 even if a part of residual charges still exist after the charges are transferred to the first conductive pattern R1 and may be blocked by the other subpixel P, and similarly, the second conductive pattern R2 transmits a second blocking voltage less than the operating voltage of the subpixel P so that charges in the subpixel P light emitting functional layer 303 adjacent to the second conductive pattern R2 may be transferred to the second conductive pattern R2 and may be blocked by the first conductive pattern R1 even if a part of residual charges still exist after the charges are transferred to the second conductive pattern R2 and may be transferred to the other subpixel P. By arranging two conductive patterns R (the first conductive pattern R1 and the second conductive pattern R2) between two adjacent sub-pixels P, the blocking effect of the conductive patterns R on crosstalk current can be further enhanced, the accuracy of the light-emitting brightness of the sub-pixels P is improved, and the display effect of the display panel 200 is enhanced.

It should be noted that the above "the first conductive pattern R1 and the second conductive pattern R2 are provided between two adjacent anodes L1" is not limited to the scheme that the first conductive pattern R1 and the second conductive pattern R2 are provided on the anode layer 301, and may also include the scheme that the first conductive pattern R1 and the second conductive pattern R2 are provided on other film layers (for example, the first conductive pattern R1 and the second conductive pattern R2 are provided on the anode layer 301, the source-drain conductive layer 21, or the via conductive layer 31, etc.), that is, the "the first conductive pattern R1 and the second conductive pattern R2 are provided between two adjacent anodes L1" may mean that the first conductive pattern R1 and the second conductive pattern R2 are provided between two sub-pixels P corresponding to two adjacent anodes L1.

As shown in fig. 9, for example, two adjacent anodes L1 are a first anode L11 and a second anode L12, respectively, the first anode L11 is adjacent to the first conductive pattern R1, and the second anode L12 is adjacent to the second conductive pattern R2, that is, the first anode L11 is closer to the first conductive pattern R1 than the second anode L12, and the second anode L12 is closer to the second conductive pattern R2 than the first anode L11.

Wherein the first conductive pattern R1 is configured to transmit a first blocking voltage, the second conductive pattern R2 is configured to transmit a second blocking voltage, the first blocking voltage is greater than the second blocking voltage; the first anode L11 is configured to transmit an operating voltage greater than or equal to a first initial lighting voltage, and the second anode L12 is configured to transmit an operating voltage greater than or equal to a second initial lighting voltage, the second initial lighting voltage being greater than the first initial lighting voltage.

Note that the "first initial lighting voltage" is a light emission threshold voltage of the light emission pattern L3 corresponding to the first anode L11, that is, a lowest voltage at which the light emission pattern L3 corresponding to the first anode L11 can emit light; the "second initial lighting voltage" is a light emission threshold voltage of the light emission pattern L3 corresponding to the second anode L12, that is, the lowest voltage capable of causing the light emission pattern L3 corresponding to the second anode L12 to emit light.

By arranging the first conductive pattern R1 adjacent to the first anode L11 and the second conductive pattern R2 adjacent to the second anode L12, and the first blocking voltage transmitted by the first conductive pattern R1 is greater than the second blocking voltage transmitted by the second conductive pattern R2, the two conductive patterns R (the first conductive pattern R1 and the second conductive pattern R2) between two adjacent sub-pixels P form an inverter, that is, a blocking current is formed between the first conductive pattern R1 and the second conductive pattern R2, and the transfer direction of charges in the blocking current is opposite to the charge transfer tendency between the two adjacent sub-pixels P, so that the blocking effect on the crosstalk current between the adjacent sub-pixels P is further enhanced, the problems of poor display and the like caused by the crosstalk current are avoided, the accuracy of the light emission luminance of the sub-pixels P is improved, and the display effect of the display panel 200 is enhanced.

For example, as shown in fig. 10, when the operating voltage transmitted by the second anode L12 is greater than the operating voltage transmitted by the first anode L11, an electric field exists between the sub-pixel P corresponding to the second anode L12 and the sub-pixel P corresponding to the first anode L11, so that a phenomenon of charge transfer occurs in the light-emitting functional layer 303, a crosstalk current (arrow Z is a transmission direction of charges in the crosstalk current) directed from the second anode L12 to the first anode L11 is formed, and accuracy of light-emitting luminance of the two sub-pixels P is affected. By providing the first conductive pattern R1 and the second conductive pattern R2 and making the first blocking voltage larger than the second blocking voltage so that an electric field exists between the first conductive pattern R1 and the second conductive pattern R2, a blocking current directed from the first conductive pattern R1 to the second conductive pattern R2 is formed (arrow Z3 is a transfer direction of electric charges in the blocking current), the first conductive pattern R1 is closer to the first anode L11 than the second conductive pattern R2, and the transfer direction of the blocking current is opposite to the transfer direction of the aforementioned crosstalk current, thereby further preventing a charge transfer tendency between adjacent two sub-pixels P and enhancing the blocking effect of the conductive pattern R.

In some embodiments, the display panel 200 further includes a first power line VSS and/or an initialization signal line Vinit disposed between the substrate 10 and the anode layer 301. At least one conductive pattern R is electrically connected to the first power line VSS, and/or at least one conductive pattern R is electrically connected to the initialization signal line Vinit.

Wherein the first power line VSS is configured to transmit a low-level voltage signal, and the initialization signal line Vinit is configured to transmit an initialization signal. The voltage of the low-level voltage signal is greater than the voltage of the initialization signal, for example, the voltage of the low-level voltage signal is 0V, and the voltage of the initialization signal is-1V, -2V, -3V, -4.5V or-5V.

Illustratively, the initialization signal line Vinit includes a first initialization signal line Vinit1 and a second initialization signal line Vinit 2.

Wherein the first initialization signal line Vinit1 is configured to transmit a first initialization signal, and the second initialization signal line Vinit2 is configured to transmit a second initialization signal. The voltage of the first initialization signal is greater than that of the second initialization signal, for example, the voltage of the first initialization signal is-1V, the voltage of the second initialization signal is-2V or-3V, etc.; for example, the voltage of the first initialization signal is-3V, the voltage of the second initialization signal is-4V or-5.5V, etc.

In some embodiments, the first power line VSS is provided on the source drain conductive layer 21. For example, the first power line VSS is disposed on the second source/drain conductive layer 210.

In some embodiments, the initialization signal line Vinit is provided to the gate conductive layer. For example, the first initialization signal line Vinit1 is provided in the second gate conductive layer 205.

In some embodiments, the initialization signal line Vinit is provided to the source-drain conductive layer 21. For example, the second initialization signal line Vinit2 is provided in the first source-drain conductive layer 207.

In some embodiments, the conductive pattern R is electrically connected to the first power line VSS. That is, the first power line VSS provides blocking voltage for the conductive pattern R, and the working voltage of the sub-pixel P is greater than the low level voltage transmitted by the first power line VSS, that is, greater than the blocking voltage transmitted by the conductive pattern R, so that charges in the light emitting functional layer 303 of the sub-pixel P adjacent to the conductive pattern R can be transferred to the conductive pattern R, thereby preventing crosstalk current from being formed between adjacent sub-pixels P, improving accuracy of light emitting luminance of the sub-pixel P, and enhancing display effect of the display panel 200.

In some embodiments, the conductive pattern R is electrically connected to the first initialization signal line Vinit 1. That is, the first initialization signal line Vinit1 provides blocking voltage for the conductive pattern R, and the operating voltage of the sub-pixel P is greater than the voltage of the first initialization signal transmitted by the first initialization signal line Vinit1, that is, greater than the blocking voltage transmitted by the conductive pattern R, so that charges in the light-emitting functional layer 303 of the sub-pixel P adjacent to the conductive pattern R can be transferred to the conductive pattern R, and crosstalk current is prevented from being formed between adjacent sub-pixels P, thereby improving the accuracy of the light-emitting luminance of the sub-pixel P and enhancing the display effect of the display panel 200.

In some embodiments, the conductive pattern R is electrically connected to the second initialization signal line Vinit 2. That is, the second initialization signal line Vinit2 provides blocking voltage for the conductive pattern R, and the operating voltage of the sub-pixel P is greater than the voltage of the second initialization signal transmitted by the second initialization signal line Vinit2, that is, greater than the blocking voltage transmitted by the conductive pattern R, so that charges in the light-emitting functional layer 303 of the sub-pixel P adjacent to the conductive pattern R can be transferred to the conductive pattern R, and crosstalk current is prevented from being formed between adjacent sub-pixels P, thereby improving the accuracy of the light-emitting luminance of the sub-pixel P and enhancing the display effect of the display panel 200.

In some embodiments, the conductive pattern R is electrically connected to the first power line VSS and the initialization signal line Vinit.

Illustratively, the first conductive pattern R1 is electrically connected to the first power line VSS, and the second conductive pattern R2 is electrically connected to the initialization signal line Vinit.

Alternatively, the second conductive pattern R2 is electrically connected to the first initialization signal line Vinit1, or the second conductive pattern R2 is electrically connected to the second initialization signal line Vinit 2.

For example, as shown in fig. 11, the first conductive pattern R1 is electrically connected to the first power line VSS, and the second conductive pattern R2 is electrically connected to the second initialization signal line Vinit 2. That is, the first power line VSS supplies the first blocking voltage to the first conductive pattern R1, and the second initialization signal line Vinit2 supplies the second blocking voltage to the second conductive pattern R2.

The operating voltages of the two sub-pixels P adjacent to the first and second conductive patterns R1 and R2, respectively, are both greater than the low level voltage transmitted by the first power line VSS and also greater than the voltage of the second initialization signal transmitted by the second initialization signal line Vinit2, i.e., both greater than the first blocking voltage and the second blocking voltage. The low-level voltage transmitted by the first power line VSS is greater than the voltage of the second initialization signal transmitted by the second initialization signal line Vinit2, that is, the first blocking voltage is greater than the second blocking voltage, so that the first conductive pattern R1 and the second conductive pattern R2 form an inverter, that is, a blocking current directed from the first conductive pattern R1 to the second conductive pattern R2 is formed between the first conductive pattern R1 and the second conductive pattern R2, and the transmission direction of the blocking current is opposite to the transmission direction of the crosstalk current between two adjacent sub-pixels P, thereby further preventing the charge transfer tendency between the two adjacent sub-pixels P and enhancing the blocking effect of the conductive pattern R.

As shown in fig. 12, the first conductive pattern R1 is electrically connected to the first initialization signal line Vinit1, and the second conductive pattern R2 is electrically connected to the second initialization signal line Vinit2, for example. That is, the first initialization signal line Vinit1 supplies the first blocking voltage to the first conductive pattern R1, and the second initialization signal line Vinit2 supplies the second blocking voltage to the second conductive pattern R2.

The operating voltages of the two sub-pixels P adjacent to the first and second conductive patterns R1 and R2, respectively, are both greater than the voltage of the first initialization signal transmitted by the first initialization signal line Vinit1 and also greater than the voltage of the second initialization signal transmitted by the second initialization signal line Vinit2, that is, both greater than the first blocking voltage and the second blocking voltage. And the voltage of the first initialization signal transmitted by the first initialization signal line Vinit1 is greater than the voltage of the second initialization signal transmitted by the second initialization signal line Vinit2, that is, the first blocking voltage is greater than the second blocking voltage, so that the first conductive pattern R1 and the second conductive pattern R2 form an inverter, that is, a blocking current directed from the first conductive pattern R1 to the second conductive pattern R2 is formed between the first conductive pattern R1 and the second conductive pattern R2, and the transmission direction of the blocking current is opposite to the transmission direction of the crosstalk current between two adjacent sub-pixels P, thereby further preventing the charge transfer tendency between the two adjacent sub-pixels P and enhancing the blocking effect of the conductive pattern R.

In some embodiments, of the two sub-pixels P adjacent to the conductive pattern R (i.e., the two sub-pixels to which the two anodes L1 adjacent to the conductive pattern R belong), the light that one of them can emit is different color light from the light that the other can emit, that is, the light emitting patterns L3 of the two sub-pixels P adjacent to the conductive pattern R are respectively used to emit different color light. For example, one of the two sub-pixels P emits red light and the other emits green or blue light.

It can be understood that, the light emitting threshold voltages of the light emitting patterns L3 of the two sub-pixels P emitting light of different colors are different, that is, the lowest operating voltage provided by the anode L3 and capable of lighting the light emitting pattern L3 is different, and when two adjacent sub-pixels P need to be lighted, the magnitudes of the operating voltages of the two sub-pixels P during the lighting process (for example, at the display luminance of 0 to 3 gray levels) are different, which easily forms an electric field, and causes a crosstalk current to be generated between the two sub-pixels P, thereby affecting the light emitting accuracy of the sub-pixels P. The above embodiments of the present disclosure may effectively block crosstalk current formed between the sub-pixels P by disposing the conductive patterns R between the sub-pixels P for emitting light of different colors, and improve the light emitting accuracy of the sub-pixels P, especially improve the light emitting accuracy of the sub-pixels P in a low gray level light emitting state.

In some embodiments, in the two sub-pixels P adjacent to the conductive pattern R, light that one of them can emit is the same color as light that the other can emit, that is, the light emitting patterns L3 of the two sub-pixels P adjacent to the conductive pattern R are used to emit the same color of light. For example, both the sub-pixels P emit green light.

In some arrangements of the sub-pixels, there are two sub-pixels P emitting light of the same color and disposed adjacent to each other, in this case, when one of the sub-pixels emits no light and the other emits light, or when the luminance of the light emitted by one of the sub-pixels P is lower than the luminance of the light emitted by the other sub-pixel P, that is, the two sub-pixels P have different operating voltages, an electric field is formed between the two sub-pixels P, so that a crosstalk current is formed between the two sub-pixels P, which affects the accuracy of light emission of the sub-pixels P. Through the conductive pattern R arranged between the two adjacent sub-pixels P emitting light with the same color, crosstalk current formed between the sub-pixels P can be effectively prevented, and the light emitting accuracy of the sub-pixels P is improved.

In some embodiments, the conductive pattern R is disposed between the sub-pixel P emitting green light and the sub-pixel P emitting red light.

Exemplarily, in a case where the conductive pattern R includes the first and second conductive patterns R1 and R2, the light emitting pattern L3 of the sub-pixel P adjacent to the first conductive pattern R1 can emit green light, and the light emitting pattern L3 of the sub-pixel P adjacent to the second conductive pattern R2 can emit red light.

In some arrangement of the sub-pixels, the sub-pixel P emitting green light and the sub-pixel P emitting red light are disposed adjacent to each other, and the material of the light emitting functional layer 303 capable of emitting green light and the material of the light emitting functional layer 303 capable of emitting red light have high conductivity, and particularly in a low gray level light emission state, the influence of crosstalk current is significant. By providing the conductive pattern R between the sub-pixel P emitting green light and the sub-pixel P emitting red light, crosstalk current can be effectively blocked, and the light emitting accuracy of the sub-pixel P can be improved.

As shown in fig. 13 and 14, in some embodiments, the planar shapes of the openings K of the pixel defining layers 302 of different sub-pixels P may be different or the same. For example, the arrangement of the plurality of sub-pixels P may be various, for example, the arrangement of the plurality of sub-pixels P may be a conventional RGB arrangement (as shown in fig. 13), and for example, the arrangement of the plurality of sub-pixels P may be an RGBG arrangement.

As shown in fig. 13 and 14, in some embodiments, the conductive pattern R is disposed on at least one side (the side having a positive area with other sub-pixels P) of the sub-pixel P, so that crosstalk current formed between any two sub-pixels P can be effectively blocked, light emitting accuracy of all sub-pixels P is improved, and the whole-screen display effect of the display panel 200 is enhanced.

As shown in fig. 13 and 14, in some embodiments, the shape of the conductive pattern R is a stripe shape, and the length extending direction Y of the conductive pattern R coincides with the extending direction of the side KL of the opening K adjacent to the conductive pattern R.

Illustratively, the length of the conductive pattern R, and the length of the side KL of the opening K adjacent to the conductive pattern R are approximately equal.

In some embodiments, the plurality of conductive patterns P are integrally formed, for example, the film layer on which the conductive pattern R is located is a mesh structure, the sub-pixels P are disposed in a mesh of the mesh structure, a mesh line of the mesh structure passes through between two adjacent sub-pixels P, and the mesh line serves as the conductive pattern R to block a crosstalk current between two adjacent sub-pixels P.

Illustratively, the conductive pattern R is integrally formed on the film layer at only one position to be electrically connected to a signal line (e.g., the first power line VSS or the initialization signal line Vinit) transmitting a low-level voltage. And each conductive pattern R is not required to be connected with a signal wire for transmitting low-level voltage, so that the number of punched holes is reduced, and the process difficulty is reduced.

As shown in fig. 15, in some embodiments, the aforementioned light emission function layer 303 includes: a first sub light emission function layer 303a, a heterojunction structure layer 303b, and a second sub light emission function layer 303c stacked in a thickness direction of the substrate 10 (i.e., a direction perpendicular to the light emission surface of the display panel 200), the heterojunction structure layer 303b being located between the first sub light emission function layer 303a and the second sub light emission function layer 303 c. That is, the light-emitting functional layer 303 corresponding to each sub-pixel P includes two light-emitting devices connected in series, so that the light-emitting current of the sub-pixel P can be greatly reduced under the same light-emitting intensity, the service life of the sub-pixel P is prolonged, and the development, mass production and introduction of high-life new technologies such as vehicle-mounted equipment are facilitated.

As shown in fig. 15, each sub-pixel P illustratively includes a first light-emitting pattern L3a and a second light-emitting pattern L3c, the first light-emitting pattern L3a is provided on the first sub-light-emitting function layer 303a, the second light-emitting pattern L3c is provided on the second sub-light-emitting function layer 303c, and the first light-emitting pattern L3a and the second light-emitting pattern L3c are provided corresponding to the same opening K of the pixel defining layer 302. That is, the light-emitting function layer 303 corresponding to each sub-pixel P includes two layers of light-emitting patterns L3 connected in series.

As shown in fig. 15, for example, in the two-layered light emitting patterns L3 connected in series, each of the light emitting patterns L3 is provided with the common layer 305, for example, the first light emitting pattern L3a is provided with at least one of the common layers 305 on both the side close to the substrate 10 and the side far from the substrate 10, and the second light emitting pattern L3c is provided with at least one of the common layers 305 on both the side close to the substrate 10 and the side far from the substrate 10.

In some embodiments, the heterojunction structure layer 303b includes at least two semiconductor thin films. For example, as shown in fig. 15, the heterojunction structure layer 303b includes a first semiconductor thin film P-CGL and a second semiconductor thin film N-CGL.

Illustratively, the materials of the semiconductor films of different ones of the at least two semiconductor films are different.

The material of the semiconductor thin film is, for example, a compound such as gallium arsenide, and may be a semiconductor alloy such as silicon-germanium.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art will appreciate that changes or substitutions within the technical scope of the present disclosure are included in the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (16)

1. A display panel, comprising:

a substrate;

an anode layer disposed on the substrate, the anode layer comprising a plurality of anodes;

the pixel defining layer is arranged on one side, far away from the substrate, of the anode layer, and is provided with a plurality of openings, and one opening corresponds to one anode;

the light-emitting functional layer is arranged on one side, far away from the substrate, of the pixel defining layer and is in contact with the anode through the opening;

at least one conductive pattern arranged on one side of the light-emitting functional layer close to the substrate; the orthographic projection of the conductive pattern on the substrate is positioned between the orthographic projections of two adjacent anodes on the substrate, the conductive pattern is in contact with the light-emitting functional layer, and the conductive pattern is configured to transmit a blocking voltage which is smaller than an operating voltage transmitted by the anodes adjacent to the conductive pattern.

2. The display panel of claim 1, wherein the at least one conductive pattern is disposed between the pixel defining layer and the substrate.

3. The display panel of claim 2, wherein the at least one conductive pattern is disposed on the anode layer;

the pixel defining layer is provided with at least one first through hole, the first through hole is arranged between two adjacent openings of the pixel defining layer, and the light-emitting function layer is in contact with the conductive pattern through the first through hole.

4. The display panel according to claim 2, characterized in that the display panel further comprises:

at least one conductive layer arranged between the substrate and the anode layer, wherein the conductive layer closest to the anode layer in the at least one conductive layer is a target conductive layer, and the conductive pattern is arranged on the target conductive layer;

an insulating layer disposed between the target conductive layer and the anode layer;

the pixel defining layer is provided with at least one first through hole, and the first through hole is arranged between two adjacent openings of the pixel defining layer;

the insulating layer is provided with at least one second through hole, and the second through hole is communicated with the first through hole;

the light-emitting functional layer is in contact with the conductive pattern through a first via hole and a second via hole which are communicated.

5. The display panel according to claim 4, wherein the display panel comprises a source-drain conductive layer disposed between the substrate and the anode layer, the source-drain conductive layer being the target conductive layer; or,

the display panel comprises a source-drain conducting layer arranged between the substrate and the anode layer and at least one switching conducting layer arranged between the source-drain conducting layer and the anode layer, wherein the switching conducting layer closest to the anode layer in the at least one switching conducting layer is a target conducting layer.

6. The display panel according to claim 1, wherein the at least one conductive pattern is provided between the pixel defining layer and the light emitting function layer.

7. The display panel according to claim 1, characterized in that the display panel further comprises:

a first power supply line and/or an initialization signal line disposed between the substrate and the anode layer; the first power line is configured to transmit a low-level voltage signal, and the initialization signal line is configured to transmit an initialization signal;

wherein at least one of the conductive patterns is electrically connected to the first power line; and/or at least one conductive pattern is electrically connected with the initialization signal line.

8. The display panel according to any one of claims 1 to 7, wherein a first conductive pattern and a second conductive pattern are provided between two adjacent anodes; and the first conductive pattern and the second conductive pattern are arranged side by side along the direction of a central connecting line of the two adjacent anodes.

9. The display panel according to claim 8, wherein the two adjacent anodes are a first anode and a second anode, respectively, the first anode is adjacent to the first conductive pattern, and the second anode is adjacent to the second conductive pattern;

the first conductive pattern is configured to transmit a first blocking voltage, the second conductive pattern is configured to transmit a second blocking voltage, and the first blocking voltage is greater than the second blocking voltage;

the first anode is configured to transmit an operating voltage greater than or equal to a first initial lighting voltage, and the second anode is configured to transmit an operating voltage greater than or equal to a second initial lighting voltage, the second initial lighting voltage being greater than the first initial lighting voltage.

10. The display panel according to claim 9, wherein the light emission function layer includes a plurality of light emission patterns, one light emission pattern being provided corresponding to one anode;

the light emitting pattern disposed corresponding to the first anode can emit green light, and the light emitting pattern disposed corresponding to the second anode can emit red light.

11. The display panel according to claim 8, characterized in that the display panel further comprises:

a first power line and an initialization signal line disposed between the substrate and the anode layer; the first power line is configured to transmit a low-level voltage signal, the initialization signal line is configured to transmit an initialization signal, and a voltage of the low-level voltage signal is greater than a voltage of the initialization signal;

wherein the first conductive pattern is electrically connected to the first power line, and the second conductive pattern is electrically connected to the initialization signal line.

12. The display panel according to claim 8, characterized in that the display panel further comprises:

an initialization signal line disposed between the substrate and the anode layer, the initialization signal line including a first initialization signal line and a second initialization signal line; the first initialization signal line is configured to transmit a first initialization signal, the second initialization signal line is configured to transmit a second initialization signal, and a voltage of the first initialization signal is greater than a voltage of the second initialization signal;

wherein the first conductive pattern is electrically connected to the first initialization signal line, and the second conductive pattern is electrically connected to the second initialization signal line.

13. The display panel according to any one of claims 1 to 7, wherein the conductive pattern has a strip shape, and a length extending direction of the conductive pattern coincides with an extending direction of a side of the opening adjacent to the conductive pattern.

14. The display panel according to any one of claims 1 to 7, wherein the display panel comprises a plurality of sub-pixels, each sub-pixel comprising an anode;

in two sub-pixels to which two anodes adjacent to the conductive pattern belong, light emitted by one of the two sub-pixels is different from light emitted by the other of the two sub-pixels.

15. The display panel according to any one of claims 1 to 7, wherein the light-emitting functional layer comprises: a first sub-light emitting functional layer, a heterojunction structural layer and a second sub-light emitting functional layer which are stacked along the thickness direction of the substrate, wherein the heterojunction structural layer is positioned between the first sub-light emitting functional layer and the second sub-light emitting functional layer;

the display panel comprises a plurality of sub-pixels, each sub-pixel comprises a first light-emitting pattern and a second light-emitting pattern, the first light-emitting pattern is arranged on the first sub-light-emitting functional layer, the second light-emitting pattern is arranged on the second sub-light-emitting functional layer, and the first light-emitting pattern and the second light-emitting pattern are arranged corresponding to the same opening of the pixel defining layer.

16. A display device, comprising:

the display panel according to any one of claims 1 to 15.

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