CN118138030A - Embedded switch system for testing power supply chip - Google Patents
Embedded switch system for testing power supply chip Download PDFInfo
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- CN118138030A CN118138030A CN202410259139.1A CN202410259139A CN118138030A CN 118138030 A CN118138030 A CN 118138030A CN 202410259139 A CN202410259139 A CN 202410259139A CN 118138030 A CN118138030 A CN 118138030A
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- 238000012360 testing method Methods 0.000 title claims abstract description 42
- 238000002955 isolation Methods 0.000 claims description 24
- 229910002601 GaN Inorganic materials 0.000 claims description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 5
- 230000002457 bidirectional effect Effects 0.000 abstract description 9
- 238000011981 development test Methods 0.000 abstract description 4
- 230000008713 feedback mechanism Effects 0.000 abstract description 3
- 238000004891 communication Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
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Abstract
The application provides an embedded switch system for testing a power chip, which comprises: the power module and a plurality of parallelly connected branches, every branch includes: a load and at least one embedded switch in series, wherein the embedded switch comprises: the application can control the on or off of the circuit branch by the driving of the driving unit, the switching unit supports the bidirectional flow of current to meet the requirements of forward and reverse work in the test, and meanwhile, the switching unit is cut off by the driving unit when overcurrent occurs through the feedback mechanism of the overcurrent protection unit to realize the bidirectional overcurrent protection. The application realizes the multi-channel switch through the serial and parallel combination of the embedded switch, realizes the multiplexing of equipment such as a source meter, an electronic load, a digital multimeter and the like in the development test of a power chip, reduces the dependence on instrument equipment and reduces the test input cost.
Description
Technical Field
The application relates to the technical field of power switches, in particular to an embedded switch system for testing a power chip.
Background
With the increase of the complexity of application scenes, the power supply requirement of an electronic system is correspondingly becoming more and more complex. Power chips have evolved from the simplest single-input single-output power chips to power management chips (PMICs) with digital control, supporting multiple inputs and multiple outputs. In the field of power chip development and test, test equipment such as a source meter, an electronic load and a digital multimeter is required to be used for carrying out test, and along with the improvement of the complexity of a tested power chip, relevant instruments and equipment are required to be greatly increased to finish corresponding test, so that the dependence of the power chip development and test on the test equipment such as instruments and meters is high, and the test input cost is high.
Disclosure of Invention
The application provides an embedded switch system for testing a power chip, which can solve the problems of high dependence of power chip development test on test equipment such as instruments and meters and high test input cost.
The embodiment of the application provides an embedded switch system for testing a power chip, which comprises the following components: the power supply module and at least two branches are connected in parallel and then connected with the power supply module, wherein,
Each of the branches includes: a load and at least one embedded switch in series; wherein,
The embedded switch includes:
A driving unit for receiving an initial control signal inputted from the outside and outputting a first voltage signal and a second voltage signal to a rear stage circuit;
the switching unit is used for receiving the first voltage signal and the second voltage signal output by the driving unit and controlling the on-off of each branch according to the pressure difference between the first voltage signal and the second voltage signal;
the overcurrent protection unit is used for acquiring forward current signals or reverse current signals in all the branches, converting the forward current signals or the reverse current signals into intermediate voltage signals, and outputting an intervention signal to the driving unit according to the intermediate voltage signals so as to switch off the switching unit by using the driving unit when the circuit branches are in overcurrent.
Optionally, in the embedded switch system for testing a power chip, the driving unit includes: the photoelectric isolation type switch comprises a first resistor and a photoelectric isolation type gate driver, wherein one end of the first resistor is connected with an initial control signal input from outside, the other end of the first resistor is connected with a positive input end of the photoelectric isolation type gate driver, a negative input end of the photoelectric isolation type gate driver is connected with a ground end, and a positive output end and a negative output end of the photoelectric isolation type gate driver are respectively connected with the switch unit.
Optionally, in the embedded switch system for testing a power chip, the switch unit includes: the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube and is connected with the positive output end of the photoelectric isolation type grid electrode driver together; the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube and is connected with the negative output end of the photoelectric isolation type grid driver together; the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube are respectively connected with a post-stage circuit.
Optionally, in the embedded switch system for testing a power chip, the overcurrent protection unit includes: the positive input end and the negative input end of the first current shunt monitor are respectively connected to two ends of the second resistor, the output end of the first current shunt monitor is connected to the positive electrode of the first diode, the positive input end and the negative input end of the second current shunt monitor are respectively connected to two ends of the second resistor, the positive electrode of the second current shunt monitor is connected to two ends of the second resistor, the output end of the second current shunt monitor is connected to the positive electrode of the second diode, the negative electrode of the first diode is connected to the negative electrode of the second diode, the grid electrode of the third NMOS tube is connected to the grid electrode of the third NMOS tube, the drain electrode of the third NMOS tube is connected to a series node between the positive input end of the photoelectric isolation type grid electrode driver and the first resistor, the source electrode of the third NMOS tube is connected to the ground, and the other end of the third resistor is connected to the ground.
Optionally, in the embedded switch system for testing a power chip, the first NMOS transistor and the second NMOS transistor are gallium nitride NMOS transistors.
Optionally, in the embedded switch system for testing a power chip, when the switch unit is turned on, a current of the circuit loop flows in a forward direction or a reverse direction, wherein a current flow direction of the circuit loop is determined by a potential difference applied across each of the branches.
The technical scheme of the application at least comprises the following advantages:
The application provides an embedded switch system for testing a power chip, which comprises: a plurality of parallel branches, each branch comprising: a load and at least one embedded switch in series, wherein the embedded switch comprises: the application can control the on or off of the circuit branch by the driving of the driving unit, the switching unit supports the bidirectional flow of current, meets the requirements of forward and reverse work in the test, and simultaneously, the switching unit is cut off by the driving unit when in overcurrent through the feedback mechanism of the overcurrent protection unit to realize the bidirectional overcurrent protection. The application realizes the multi-channel switch through the serial and parallel combination of the embedded switch, realizes the multiplexing of the testing equipment such as a source meter, an electronic load, a digital multimeter and the like in the development test of a power chip, obviously reduces the dependence on instrument and equipment, and reduces the test input cost.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic circuit diagram of an embedded switch system applied to a power chip test scenario according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of an embedded switch according to an embodiment of the present invention;
FIG. 3 is a flow chart of the upper computer software of the embedded switch system according to the embodiment of the invention;
FIG. 4 is a flow chart of the lower computer software of the embedded switch system according to the embodiment of the invention;
wherein reference numerals are as follows:
10-power supply module, 21-load one, 22-load two, 31-embedded switch one, 32-embedded switch two, 33-embedded switch three, 34-embedded switch four, 311-driving unit, 312-switching unit, 313-overcurrent protection unit.
Detailed Description
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
The embodiment of the application provides an embedded switch system for testing a power chip, which comprises the following components: the power module and at least two branch circuits are connected in parallel, and then the power module is connected to different branch circuits, wherein each branch circuit comprises: a load and at least one embedded switch in series.
It should be noted that the present application does not limit the type of the load, and the load may be various, may be a power chip to be tested, or may be a source meter, an electronic load, a digital multimeter, or other test equipment. That is, the embedded switching system of the present application can be applied to different power chip test scenarios depending on the type of load.
In this embodiment, a resistor is taken as an example of an application. In this embodiment, taking application of a 4-switch channel as an example, the embedded switch system for testing a power chip provided by the present application is specifically described, referring to fig. 1, fig. 1 is a schematic circuit structure diagram of an embedded switch system applied to a testing scenario of a power chip according to an embodiment of the present application, where the embedded switch system shown in fig. 1 can implement a function that one power module supplies power to two loads to be tested in a time sharing manner, and the embedded switch system includes: the power module 10 and two branches, two the branches connect in parallel the power module 10, wherein, a branch includes: an embedded switch I31, a load I21 and an embedded switch II 32 which are sequentially connected in series; the other branch includes: an embedded switch III 33, a load II 22 and an embedded switch IV 34 which are connected in series in sequence.
In this embodiment, the resistor R7 (load one) and the resistor R14 (load two) are used to simulate the load to be measured on the two branches.
The first embedded switch 31, the second embedded switch 32, the third embedded switch 33 and the fourth embedded switch 34 are identical, and the first embedded switch 31 is taken as an example to describe the embedded switch of the present application in detail, specifically, referring to fig. 2, fig. 2 is a schematic circuit structure diagram of the embedded switch according to the embodiment of the present application, and the embedded switch includes: a driving unit 311, a switching unit 312, and an overcurrent protection unit 313, wherein,
A driving unit 311 for receiving an initial control signal inputted from the outside and outputting a first voltage signal and a second voltage signal to a rear stage circuit;
A switching unit 312, configured to receive the first voltage signal and the second voltage signal output by the driving unit 311, and control on/off of each of the branches according to a voltage difference between the first voltage signal and the second voltage signal; wherein with the switching unit 312 turned on, a forward or reverse flow of current of the circuit loop may be achieved, wherein the current flow direction of the circuit loop is determined by the potential difference applied across each of the branches. After the switch unit 312 is turned on, the current direction is determined by the electric potential at the two ends of the branch, and the current flows from the high electric potential to the low electric potential, and the switch unit 312 does not determine the current direction, but only provides a closed circuit loop for the branch.
The overcurrent protection unit 313 is configured to obtain a forward current signal or a reverse current signal in each of the branches, convert the forward current signal or the reverse current signal into an intermediate voltage signal, and output an intervention signal to the driving unit 311 according to the intermediate voltage signal, so as to turn off the switching unit 312 by using the driving unit 311 when the circuit branches are overcurrent.
Specifically, the driving unit 311 includes: the photoelectric isolation type gate driver comprises a first resistor R1 and a photoelectric isolation type gate driver U1, wherein one end of the first resistor R1 is connected with an externally input initial control signal, the other end of the first resistor R1 is connected with a positive input end of the photoelectric isolation type gate driver U1, a negative input end of the photoelectric isolation type gate driver U1 is connected with a ground end, and a positive output end and a negative output end of the photoelectric isolation type gate driver U1 are respectively connected with the switch unit 312.
In this embodiment, the model of the photo-isolated gate driver U1 may be APV1121SZ.
In this embodiment, the resistance of the first resistor R1 may be 220 ohms.
Preferably, the switching unit 312 includes: the grid electrode of the first NMOS tube M1 is connected with the grid electrode of the second NMOS tube M2 and is connected with the positive output end of the photoelectric isolation type grid electrode driver U1 together; the source electrode of the first NMOS tube M1 is connected with the source electrode of the second NMOS tube M2 and is connected with the negative output end of the photoelectric isolation type grid driver U1 together; the drain electrode of the first NMOS tube M1 and the drain electrode of the second NMOS tube M2 are respectively connected with a post-stage circuit (load and power module).
The first NMOS transistor M1 and the second NMOS transistor M2 are controlled to be turned on or off simultaneously by the photo-isolated gate driver U1, and the switch unit 312 is equivalent to a mechanical switch. In this embodiment, the first NMOS transistor M1 and the second NMOS transistor M2 are both gallium nitride NMOS transistors, where the gallium nitride NMOS transistors have advantages of low on-resistance, high withstand voltage, and the like.
Further, the overcurrent protection unit 313 includes: the second resistor R2, the third resistor R3, the first current shunt monitor U3, the second current shunt monitor U2, the first diode D1, the second diode D2 and the third NMOS tube M3, wherein the second resistor R2 is connected in series in a circuit through which a forward current signal or a reverse current signal flows, the positive input end and the negative input end of the first current shunt monitor U3 are respectively connected to two ends of the second resistor R2, the output end of the first current shunt monitor U3 is connected with the positive electrode of the first diode D1, the second current shunt monitor U2 and the first current shunt monitor U3 are in a symmetrical connection method, the negative input end and the positive input end of the second current shunt monitor U2 are respectively connected to two ends of the second resistor R2, the output end of the second current shunt monitor U2 is connected with the positive electrode of the second diode D2, the negative electrode of the first diode D1 is connected with the negative electrode of the second diode D2, the negative electrode of the second diode D2 is connected with the third NMOS tube is connected with the positive electrode of the third NMOS tube M3, the positive electrode of the third NMOS tube is connected with the third grid electrode 3, and the third NMOS tube is connected with the third grid 3.
In this embodiment, in the serial branch where the first embedded switch 31 is located, the drain of the first NMOS transistor M1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the positive electrode of the power module 10, the drain of the second NMOS transistor M2 is connected to one end of the first load 21, the second embedded switch 32 is symmetrical to the first embedded switch 31, the other end of the first load 21 is connected to the drain of the NMOS transistor M5 (corresponding to the second NMOS transistor M2 in the switch unit of the first embedded switch 31) in the switch unit of the second embedded switch 32, the drain of the NMOS transistor M4 (corresponding to the first NMOS transistor M1 in the switch unit of the first embedded switch 31) is connected to one end of the resistor R4 (corresponding to the second resistor R2 in the over-current protection unit of the first embedded switch 31), and the other end of the resistor R4 is connected to the negative electrode of the power module 10. The connection of the other series branch is the same as the connection of the series branch where the embedded switch 31 is located.
In the circuit of the overcurrent protection unit 313, the first current shunt monitor U3 and the second current shunt monitor U2 output current signals, and the current signals are converted into a voltage signal through the third resistor R3 to control the on-off of the third NMOS transistor M3.
The application uses the first current shunt monitor U3, the second current shunt monitor U2 and the current detection resistor to realize bidirectional current measurement, converts the current signal in the branch into an intermediate voltage signal through the second resistor R2, outputs a current signal through the first current shunt monitor U3 and the second current shunt monitor U2 according to the intermediate voltage signal, converts the current signal into a voltage signal through the third resistor R3 to control the on-off of the third NMOS tube M3, and controls the input of the photoelectric isolation type grid driver U1 through controlling the third NMOS tube M3 to realize bidirectional overcurrent protection function. Specifically, no matter the forward channel current (i+) or the reverse channel current (i-) exceeds a set value, that is, the voltage drop (voltage difference) generated by the forward or reverse current on the second resistor R2 exceeds a preset threshold, the over-current protection unit 313 automatically starts over-current protection within 100 μs, so that the third NMOS transistor M3 is turned on, and the potential of the positive input end of the photo-isolated gate driver U1 is pulled to the ground potential, so that the first NMOS transistor M1 and the second NMOS transistor M2 are turned off, and a bidirectional over-current protection function is implemented.
It should be noted that, the initial control signal that is input from the outside and can turn on the first NMOS transistor M1 and the second NMOS transistor M2 is at a high level, and the current direction is determined by the potential difference applied to the two ends of the main circuit by the power module in practical application, so that the current can flow in both directions. After the first NMOS transistor M1 and the second NMOS transistor M2 are turned on, the first NMOS transistor M1 and the second NMOS transistor M2 may be regarded as mechanical electric shock switches, and when the current in the loop does not flow, the third NMOS transistor M3 is in an off state.
In this embodiment, the models of the first current shunt monitor U3 and the second current shunt monitor U2 may be INA168. The first current shunt monitor U3 and the second current shunt monitor U2 are powered by a direct current power supply, and the power supply voltage is +5V.
In this embodiment, the resistance of the second resistor R2 may be 10mΩ; the resistance value of R3 of the third resistor can be 10KΩ.
IN this embodiment, the model of each of the first diode D1 and the second diode D2 may be IN4001.
In this embodiment, gallium nitride NMOS transistors are used as the first NMOS transistor M1 and the second NMOS transistor M2, the channel on/off speed can be lower than 1 millisecond, and the on-dc impedance of each switching channel is lower than 20 milliohms, so that the embedded switching system provided by the application has fast switching response speed and low impedance.
In the application, the embedded switch of any branch can be driven by the driving unit, so that the switching unit can control the on or off of the circuit branch and support the bidirectional flow of current, the forward or reverse conduction of the circuit in the test is realized, the flexibility of the test is improved, and meanwhile, the switching unit is cut off by the driving unit when in overcurrent through the feedback mechanism of the overcurrent protection unit, so that the bidirectional overcurrent protection is realized.
Furthermore, the application realizes the serial and parallel combination of the embedded switch by the combination of serial connection and parallel connection of a plurality of branches, thereby realizing the multi-channel switch of the system, realizing the multiplexing of testing equipment such as a source meter, an electronic load, a digital multimeter and the like in the development test of a power chip, obviously reducing the dependence on instruments and equipment and reducing the test input cost.
In this embodiment, the operation method of the embedded switch system mainly includes software logic of an upper computer and a lower computer, specifically, referring to fig. 3, fig. 3 is an upper computer software flowchart of the embedded switch system in the embodiment of the present invention, and the method for controlling the embedded switch system to perform a switch operation by the upper computer may specifically include:
Step 1.1: a control communication port is connected;
Step 1.2: the upper computer sends a handshake command to the lower computer through the communication port;
step 1.3: judging whether the lower computer receives the response or not according to the signal fed back by the lower computer;
Step 1.4: if the lower computer is monitored to receive the handshake command, the window prompts that the handshake is successful; if the fact that the lower computer does not receive the handshake command is monitored, the window prompts handshake failure and returns to the step 1.2;
step 1.5: the method comprises the steps of performing turn-off and turn-on operations of an embedded switch according to a first control signal (a switch command) input from the outside and an intervention signal output by a driving unit, or disconnecting a communication port according to a second control signal input from the outside;
Step 1.6: judging whether the communication port is disconnected, if so, ending the switching operation of the system; if the communication port is not disconnected, continuing to judge whether the communication loop is normal or not;
step 1.7: if the communication loop is normal, returning to the step 1.5; if the communication loop is abnormal, returning to the step 1.2.
Further, referring to fig. 4, fig. 4 is a lower computer software flowchart of an embedded switch system according to an embodiment of the present invention, a method for controlling the embedded switch system to perform a switching operation by using the lower computer specifically may include:
Step 2.1: initializing each functional module of MCU (micro control unit);
Step 2.2: waiting for the command of the upper computer to wake up;
Step 2.3: judging whether a correct instruction is received, in this embodiment, step 2.3 may be: judging whether a correct handshake command is received or not;
Step 2.4: if a correct handshake command is received, analyzing the command and executing corresponding switching operation, specifically, turning off and on the embedded switch according to a control signal I (switching command) input from the outside and an intervention signal output by the driving unit; if the correct handshake command is not received, the error command is ignored, and the step 2.2 is returned.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.
Claims (6)
1. An embedded switching system for power chip testing, comprising: the power supply module and at least two branches are connected in parallel and then connected with the power supply module, wherein,
Each of the branches includes: a load and at least one embedded switch in series; wherein,
The embedded switch includes:
A driving unit for receiving an initial control signal inputted from the outside and outputting a first voltage signal and a second voltage signal to a rear stage circuit;
the switching unit is used for receiving the first voltage signal and the second voltage signal output by the driving unit and controlling the on-off of each branch according to the pressure difference between the first voltage signal and the second voltage signal;
the overcurrent protection unit is used for acquiring forward current signals or reverse current signals in all the branches, converting the forward current signals or the reverse current signals into intermediate voltage signals, and outputting an intervention signal to the driving unit according to the intermediate voltage signals so as to switch off the switching unit by using the driving unit when the circuit branches are in overcurrent.
2. The embedded switching system for power chip testing according to claim 1, wherein the driving unit comprises: the photoelectric isolation type switch comprises a first resistor and a photoelectric isolation type gate driver, wherein one end of the first resistor is connected with an initial control signal input from outside, the other end of the first resistor is connected with a positive input end of the photoelectric isolation type gate driver, a negative input end of the photoelectric isolation type gate driver is connected with a ground end, and a positive output end and a negative output end of the photoelectric isolation type gate driver are respectively connected with the switch unit.
3. The embedded switching system for power chip testing according to claim 2, wherein the switching unit comprises: the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube and is connected with the positive output end of the photoelectric isolation type grid electrode driver together; the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube and is connected with the negative output end of the photoelectric isolation type grid driver together; the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube are respectively connected with a post-stage circuit.
4. The embedded switching system for power chip testing according to claim 3, wherein the overcurrent protection unit comprises: the positive input end and the negative input end of the first current shunt monitor are respectively connected to two ends of the second resistor, the output end of the first current shunt monitor is connected to the positive electrode of the first diode, the positive input end and the negative input end of the second current shunt monitor are respectively connected to two ends of the second resistor, the positive electrode of the second current shunt monitor is connected to two ends of the second resistor, the output end of the second current shunt monitor is connected to the positive electrode of the second diode, the negative electrode of the first diode is connected to the negative electrode of the second diode, the grid electrode of the third NMOS tube is connected to the grid electrode of the third NMOS tube, the drain electrode of the third NMOS tube is connected to a series node between the positive input end of the photoelectric isolation type grid electrode driver and the first resistor, the source electrode of the third NMOS tube is connected to the ground, and the other end of the third resistor is connected to the ground.
5. The embedded switching system for power chip testing of claim 1, wherein the first NMOS transistor and the second NMOS transistor are gallium nitride NMOS transistors.
6. The embedded switching system for power chip testing according to claim 1, wherein a current of the circuit loop flows in a forward direction or a reverse direction with the switching unit turned on, wherein the current flow of the circuit loop is determined by a potential difference applied across each of the branches.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410259139.1A CN118138030A (en) | 2024-03-07 | 2024-03-07 | Embedded switch system for testing power supply chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410259139.1A CN118138030A (en) | 2024-03-07 | 2024-03-07 | Embedded switch system for testing power supply chip |
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| CN118138030A true CN118138030A (en) | 2024-06-04 |
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| CN202410259139.1A Pending CN118138030A (en) | 2024-03-07 | 2024-03-07 | Embedded switch system for testing power supply chip |
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