CN118138030A - Embedded Switching System for Power Chip Testing - Google Patents

Abstract

The present application provides an embedded switch system for power chip testing, including: a power module and multiple parallel branches, each branch including: a series load and at least one embedded switch, wherein the embedded switch includes: a drive unit, a switch unit and an overcurrent protection unit. The present application drives the drive unit so that the switch unit can control the conduction or disconnection of the circuit branch. The switch unit supports bidirectional current flow to meet the forward and reverse working requirements in the test. At the same time, through the feedback mechanism of the overcurrent protection unit, the drive unit is used to cut off the switch unit when overcurrent occurs, so as to achieve bidirectional overcurrent protection. The present application realizes multi-channel switching through the series and parallel combination of embedded switches, and realizes the multiplexing of devices such as source meters, electronic loads and digital multimeters in the development and testing of power chips, which reduces the dependence on instruments and equipment and reduces the test investment cost.

Description

Embedded Switching System for Power Chip Testing

Technical Field

The present application relates to the technical field of power switches, and in particular to an embedded switch system for power chip testing.

Background technique

As the complexity of application scenarios increases, the power supply requirements of electronic systems are becoming more and more complex. Power chips have gradually evolved from the simplest single-input single-output power chips to power management chips (PMIC) with digital control and support for multiple inputs and multiple outputs. In the field of power chip development and testing, test equipment such as source meters, electronic loads, and digital multimeters are needed to carry out testing. As the complexity of the power chip being tested increases, a significant increase in related instruments and equipment is required to complete the corresponding tests. It can be seen that the development and testing of power chips is highly dependent on test equipment such as instruments and meters, and the test investment cost is high.

Summary of the invention

The present application provides an embedded switch system for power chip testing, which can solve the problem that power chip development and testing is highly dependent on test equipment such as instruments and meters, and has high test investment costs.

The embodiment of the present application provides an embedded switch system for power chip testing, comprising: a power module and at least two branches, wherein different branches are connected in parallel and then connected to the power module, wherein:

Each branch includes: a load connected in series and at least one embedded switch; wherein,

The embedded switch comprises:

A driving unit, configured to receive an initial control signal input from the outside and output a first voltage signal and a second voltage signal to a subsequent circuit;

a switch unit, configured to receive the first voltage signal and the second voltage signal output by the drive unit, and control the on and off of each of the branches according to a voltage difference between the first voltage signal and the second voltage signal;

An overcurrent protection unit is used to obtain a forward current signal or a reverse current signal in each of the branches, and convert the forward current signal or the reverse current signal into an intermediate voltage signal, and output an intervention signal to the drive unit according to the intermediate voltage signal, so as to use the drive unit to turn off the switch unit when an overcurrent occurs in a circuit branch.

Optionally, in the embedded switch system for power chip testing, the driving unit includes: a first resistor and a photoelectric isolation gate driver, one end of the first resistor is connected to the initial control signal input externally, the other end of the first resistor is connected to the positive input end of the photoelectric isolation gate driver, the negative input end of the photoelectric isolation gate driver is connected to the ground, and the positive output end and the negative output end of the photoelectric isolation gate driver are respectively connected to the switch unit.

Optionally, in the embedded switch system for power chip testing, the switch unit includes: a first NMOS tube and a second NMOS tube, the gate of the first NMOS tube is connected to the gate of the second NMOS tube, and is connected together to the positive output end of the photoelectric isolation gate driver; the source of the first NMOS tube is connected to the source of the second NMOS tube, and is connected together to the negative output end of the photoelectric isolation gate driver; the drain of the first NMOS tube and the drain of the second NMOS tube are respectively connected to the subsequent circuit.

Optionally, in the embedded switch system for power chip testing, the overcurrent protection unit includes: a second resistor, a third resistor, a first current shunt monitor, a second current shunt monitor, a first diode, a second diode and a third NMOS tube, the second resistor is connected in series in a circuit through which a forward current signal or a reverse current signal flows, the positive input terminal and the negative input terminal of the first current shunt monitor are respectively connected to the two ends of the second resistor, the output terminal of the first current shunt monitor is connected to the positive electrode of the first diode, the positive input terminal and the negative input terminal of the second current shunt monitor are respectively connected to the two ends of the second resistor, the output terminal of the second current shunt monitor is connected to the positive electrode of the second diode, the negative electrode of the first diode is connected to the negative electrode of the second diode and is connected together to the gate of the third NMOS tube, the drain of the third NMOS tube is connected to the series node between the positive input terminal of the optoelectronic isolation gate driver and the first resistor, the source of the third NMOS tube is connected to the ground terminal, one end of the third resistor is connected to the gate of the third NMOS tube, and the other end of the third resistor is connected to the ground terminal.

Optionally, in the embedded switch system for power chip testing, the first NMOS tube and the second NMOS tube are both gallium nitride NMOS tubes.

Optionally, in the embedded switch system for power chip testing, when the switch unit is turned on, the current in the circuit loop flows forward or reversely, wherein the current flow direction of the circuit loop is determined by the potential difference applied across each of the branches.

The technical solution of this application has at least the following advantages:

The present application provides an embedded switch system for power chip testing, including: multiple parallel branches, each branch including: a load connected in series and at least one embedded switch, wherein the embedded switch includes: a drive unit, a switch unit and an overcurrent protection unit. The present application drives the drive unit so that the switch unit can control the conduction or disconnection of the circuit branch. The switch unit supports bidirectional current flow to meet the forward and reverse working requirements in the test. At the same time, through the feedback mechanism of the overcurrent protection unit, the drive unit is used to cut off the switch unit when overcurrent occurs, so as to achieve bidirectional overcurrent protection. The present application realizes multi-channel switching through the series and parallel combination of embedded switches, and realizes the multiplexing of test equipment such as source meters, electronic loads and digital multimeters in the development and testing of power chips, which significantly reduces the dependence on instruments and equipment and reduces the test investment cost.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

FIG1 is a schematic diagram of a circuit structure of an embedded switch system applied to a power chip test scenario according to an embodiment of the present invention;

FIG2 is a schematic diagram of a circuit structure of an embedded switch according to an embodiment of the present invention;

3 is a software flow chart of a host computer of an embedded switch system according to an embodiment of the present invention;

4 is a software flow chart of a lower computer of an embedded switch system according to an embodiment of the present invention;

The reference numerals are described as follows:

10-power module, 21-load one, 22-load two, 31-embedded switch one, 32-embedded switch two, 33-embedded switch three, 34-embedded switch four, 311-drive unit, 312-switch unit, 313-overcurrent protection unit.

Detailed ways

The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

An embodiment of the present application provides an embedded switch system for power chip testing, comprising: a power module and at least two branches, wherein different branches are connected in parallel and then connected to the power module, wherein each branch comprises: a load connected in series and at least one embedded switch.

It is worth noting that the present application does not impose any restrictions on the type of load, and the load can be of various types, such as the power chip to be tested, or a source meter, electronic load, digital multimeter and other test equipment. In other words, depending on the type of load, the embedded switch system of the present application can be applied to different power chip test scenarios.

In this embodiment, a resistor is used as a load as an example. This embodiment takes a 4-switch channel application as an example to specifically introduce the embedded switch system for power chip testing provided by this application. Specifically, refer to Figure 1, which is a circuit structure diagram of an embedded switch system applied to a power chip test scenario in an embodiment of the present invention. The embedded switch system shown in Figure 1 can realize the function of a power module supplying power to two loads under test in a time-sharing manner. The embedded switch system includes: a power module 10 and two branches, and the two branches are connected in parallel to the power module 10, wherein one branch includes: an embedded switch 1 31, a load 1 21, and an embedded switch 2 32 connected in series in sequence; the other branch includes: an embedded switch 3 33, a load 22, and an embedded switch 4 34 connected in series in sequence.

In this embodiment, resistor R7 (load one) and resistor R14 (load two) are used to simulate the loads to be measured on the two branches.

Among them, the embedded switch 1 31, the embedded switch 2 32, the embedded switch 3 33 and the embedded switch 4 34 are exactly the same. Next, taking the embedded switch 1 31 as an example, the embedded switch of the present application is described in detail. Specifically, referring to FIG. 2, FIG. 2 is a schematic diagram of the circuit structure of the embedded switch of an embodiment of the present invention. The embedded switch includes: a driving unit 311, a switch unit 312 and an overcurrent protection unit 313, wherein:

The driving unit 311 is used to receive an initial control signal input from the outside and output a first voltage signal and a second voltage signal to a subsequent circuit;

The switch unit 312 is used to receive the first voltage signal and the second voltage signal output by the driving unit 311, and control the on and off of each branch according to the voltage difference between the first voltage signal and the second voltage signal; wherein, when the switch unit 312 is turned on, the current of the circuit loop can flow forward or reversely, wherein the current flow direction of the circuit loop is determined by the potential difference applied to the two ends of each branch. After the switch unit 312 is turned on, the current direction is determined by the potential at both ends of the branch, and the current flows from a high potential to a low potential. The switch unit 312 itself does not determine the current direction, but only provides a closed circuit loop for the branch.

The overcurrent protection unit 313 is used to obtain the forward current signal or the reverse current signal in each branch, and convert the forward current signal or the reverse current signal into an intermediate voltage signal, and output an intervention signal to the driving unit 311 according to the intermediate voltage signal, so as to use the driving unit 311 to turn off the switch unit 312 when the circuit branch is overcurrent.

Specifically, the driving unit 311 includes: a first resistor R1 and a photoelectric isolation gate driver U1, one end of the first resistor R1 is connected to an initial control signal input from the outside, the other end of the first resistor R1 is connected to the positive input end of the photoelectric isolation gate driver U1, the negative input end of the photoelectric isolation gate driver U1 is connected to the ground, and the positive output end and the negative output end of the photoelectric isolation gate driver U1 are respectively connected to the switch unit 312.

In this embodiment, the model of the photoelectric isolation gate driver U1 may be APV1121SZ.

In this embodiment, the resistance value of the first resistor R1 can be selected to be 220 ohms.

Preferably, the switch unit 312 includes: a first NMOS tube M1 and a second NMOS tube M2, the gate of the first NMOS tube M1 and the gate of the second NMOS tube M2 are connected, and are connected together to the positive output end of the photoelectric isolation gate driver U1; the source of the first NMOS tube M1 and the source of the second NMOS tube M2 are connected, and are connected together to the negative output end of the photoelectric isolation gate driver U1; the drain of the first NMOS tube M1 and the drain of the second NMOS tube M2 are respectively connected to the post-stage circuit (load and power supply module).

The first NMOS tube M1 and the second NMOS tube M2 are controlled to be turned on or off simultaneously by the photoelectric isolation gate driver U1, and the switch unit 312 is equivalent to a mechanical switch. In this embodiment, both the first NMOS tube M1 and the second NMOS tube M2 are gallium nitride NMOS tubes, wherein the gallium nitride NMOS tube has the advantages of low on-resistance and high withstand voltage.

Furthermore, the overcurrent protection unit 313 includes: a second resistor R2, a third resistor R3, a first current shunt monitor U3, a second current shunt monitor U2, a first diode D1, a second diode D2 and a third NMOS tube M3, the second resistor R2 is connected in series in a circuit through which a forward current signal or a reverse current signal flows, the positive input terminal and the negative input terminal of the first current shunt monitor U3 are respectively connected to the two ends of the second resistor R2, the output terminal of the first current shunt monitor U3 is connected to the positive electrode of the first diode D1, the second current shunt monitor U2 is symmetrically connected to the first current shunt monitor U3, and the second current shunt monitor U3 is connected to the positive electrode of the first diode D1. The negative input terminal and the positive input terminal of the monitor U2 are respectively connected to the two ends of the second resistor R2, the output terminal of the second current shunt monitor U2 is connected to the anode of the second diode D2, the cathode of the first diode D1 and the cathode of the second diode D2 are connected and connected together to the gate of the third NMOS tube M3, the drain of the third NMOS tube M3 is connected to the series node between the positive input terminal of the photoelectric isolation gate driver U1 and the first resistor R1, the source of the third NMOS tube M3 is connected to the ground, one end of the third resistor R3 is connected to the gate of the third NMOS tube M3, and the other end of the third resistor R3 is connected to the ground.

In this embodiment, in the series branch where the embedded switch 1 31 is located, the drain of the first NMOS transistor M1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the positive electrode of the power module 10, and the drain of the second NMOS transistor M2 is connected to one end of the load 1 21, wherein the embedded switch 2 32 is symmetrical with the embedded switch 1 31, the other end of the load 1 21 is connected to the drain of the NMOS transistor M5 (equivalent to the second NMOS transistor M2 in the switch unit of the embedded switch 1 31) in the switch unit of the embedded switch 2 32, the drain of the NMOS transistor M4 (equivalent to the first NMOS transistor M1 in the switch unit of the embedded switch 1 31) is connected to one end of the resistor R4 (equivalent to the second resistor R2 in the overcurrent protection unit of the embedded switch 1 31), and the other end of the resistor R4 is connected to the negative electrode of the power module 10. The connection of another series branch is similar to the connection mode of the series branch where the embedded switch 1 31 is located.

In the overcurrent protection unit 313 circuit, the first current shunt monitor U3 and the second current shunt monitor U2 output current signals, which are converted into voltage signals through the third resistor R3 to control the on/off of the third NMOS transistor M3.

The present application uses a first current shunt monitor U3, a second current shunt monitor U2 and a current detection resistor to realize bidirectional current measurement. The second resistor R2 converts the current signal in the branch into an intermediate voltage signal, and according to the intermediate voltage signal, a current signal is output through the first current shunt monitor U3 and the second current shunt monitor U2, and the current signal is converted into a voltage signal through the third resistor R3 to control the on and off of the third NMOS tube M3. The input of the opto-isolated gate driver U1 is controlled by controlling the third NMOS tube M3 to realize a bidirectional overcurrent protection function. Specifically, whether the forward channel current (i+) or the reverse channel current (i-) exceeds the set value, that is, the voltage drop (voltage difference) generated by the forward or reverse current on the second resistor R2 exceeds the preset threshold, the overcurrent protection unit 313 will automatically start the overcurrent protection within 100μs, so that the third NMOS tube M3 is turned on, and the potential of the positive input terminal of the opto-isolated gate driver U1 is pulled to the ground potential, thereby turning off the first NMOS tube M1 and the second NMOS tube M2, and realizing the bidirectional overcurrent protection function.

It is worth noting that the initial control signal input externally to turn on the first NMOS tube M1 and the second NMOS tube M2 is at a high level, and the direction of the current is determined by the potential difference applied by the power module at both ends of the main circuit in actual application, and the current can flow in both directions. After the first NMOS tube M1 and the second NMOS tube M2 are turned on, the first NMOS tube M1 and the second NMOS tube M2 can be regarded as mechanical electric shock switches, and when the current in the loop is not over-current, the third NMOS tube M3 is in the off state.

In this embodiment, the first current shunt monitor U3 and the second current shunt monitor U2 may be of the model INA168. The first current shunt monitor U3 and the second current shunt monitor U2 are both powered by a DC power supply with a supply voltage of +5V.

In this embodiment, the resistance value of the second resistor R2 can be selected as 10 mΩ; the resistance value of the third resistor R3 can be selected as 10 KΩ.

In this embodiment, the first diode D1 and the second diode D2 may both be IN4001.

In this embodiment, gallium nitride NMOS tubes are used as the first NMOS tube M1 and the second NMOS tube M2, the channel opening/closing speed can be less than 1 millisecond, and the opening DC impedance of each switch channel is less than 20 milliohms. It can be seen that the embedded switch system provided in the present application has a fast switch response speed and low impedance.

In the present application, the embedded switch of any branch can be driven by a driving unit so that the switch unit can control the conduction or shutdown of the circuit branch and support bidirectional current flow, thereby realizing forward or reverse conduction of the circuit under test, thereby improving the flexibility of the test. At the same time, through the feedback mechanism of the overcurrent protection unit, the driving unit is used to cut off the switch unit when overcurrent occurs, thereby realizing bidirectional overcurrent protection.

Furthermore, the present application realizes the series and parallel combination of embedded switches through the combination of multiple branches in series + parallel, thereby realizing multi-channel switching of the system, and realizing the multiplexing of test equipment such as source meters, electronic loads and digital multimeters in the development and testing of power chips, which significantly reduces the dependence on instruments and equipment and reduces the test investment cost.

In this embodiment, the operation method of the embedded switch system mainly includes software logic of the upper computer and the lower computer. Specifically, referring to FIG. 3 , FIG. 3 is a software flow chart of the upper computer of the embedded switch system of the embodiment of the present invention. The method of the upper computer controlling the embedded switch system to perform switch operation may specifically include:

Step 1.1: Control communication port connection;

Step 1.2: The upper computer sends a handshake command to the lower computer through the communication port;

Step 1.3: According to the signal fed back by the lower computer, determine whether the lower computer has received a response;

Step 1.4: If the lower computer receives the handshake command, the window prompts that the handshake is successful; if the lower computer does not receive the handshake command, the window prompts that the handshake fails and returns to step 1.2;

Step 1.5: Performing the turning-off and turning-on operations of the embedded switch according to the external input control signal 1 (switch command) and the intervention signal output by the drive unit, or disconnecting the communication port according to the external input control signal 2;

Step 1.6: Determine whether the communication port is disconnected. If the communication port is disconnected, end the system switch operation; if the communication port is not disconnected, continue to determine whether the communication circuit is normal;

Step 1.7: If the communication circuit is normal, return to step 1.5; if the communication circuit is abnormal, return to step 1.2.

Further, referring to FIG. 4 , FIG. 4 is a software flow chart of a lower computer of an embedded switch system according to an embodiment of the present invention. The method of the lower computer controlling the embedded switch system to perform a switch operation may specifically include:

Step 2.1: Initialize each functional module of MCU (micro control unit);

Step 2.2: Wait for the command from the host computer to wake up;

Step 2.3: Determine whether a correct instruction is received. In this embodiment, step 2.3 may be: Determine whether a correct handshake command is received;

Step 2.4: If the correct handshake command is received, the command is parsed and the corresponding switch operation is performed. Specifically, the embedded switch is turned off and on according to the external input control signal 1 (switch command) and the intervention signal output by the drive unit; if the correct handshake command is not received, the error command is ignored and the process returns to step 2.2.

Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims (6)

1. An embedded switch system for power chip testing, characterized in that it comprises: a power module and at least two branches, wherein different branches are connected in parallel and then connected to the power module, wherein: Each branch includes: a load connected in series and at least one embedded switch; wherein, The embedded switch comprises: A driving unit, configured to receive an initial control signal input from the outside and output a first voltage signal and a second voltage signal to a subsequent circuit; a switch unit, configured to receive the first voltage signal and the second voltage signal output by the drive unit, and control the on and off of each of the branches according to a voltage difference between the first voltage signal and the second voltage signal; An overcurrent protection unit is used to obtain a forward current signal or a reverse current signal in each of the branches, and convert the forward current signal or the reverse current signal into an intermediate voltage signal, and output an intervention signal to the drive unit according to the intermediate voltage signal, so as to use the drive unit to turn off the switch unit when an overcurrent occurs in a circuit branch. 2. The embedded switch system for power chip testing according to claim 1 is characterized in that the driving unit comprises: a first resistor and a photoelectric isolation gate driver, one end of the first resistor is connected to the initial control signal input externally, the other end of the first resistor is connected to the positive input end of the photoelectric isolation gate driver, the negative input end of the photoelectric isolation gate driver is connected to the ground end, and the positive output end and the negative output end of the photoelectric isolation gate driver are respectively connected to the switch unit. 3. The embedded switch system for power chip testing according to claim 2 is characterized in that the switch unit comprises: a first NMOS tube and a second NMOS tube, the gate of the first NMOS tube is connected to the gate of the second NMOS tube, and is connected to the positive output end of the photoelectric isolation gate driver; the source of the first NMOS tube is connected to the source of the second NMOS tube, and is connected to the negative output end of the photoelectric isolation gate driver; the drain of the first NMOS tube and the drain of the second NMOS tube are respectively connected to the subsequent circuit. 4. The embedded switch system for power chip testing according to claim 3, characterized in that the overcurrent protection unit comprises: a second resistor, a third resistor, a first current shunt monitor, a second current shunt monitor, a first diode, a second diode and a third NMOS tube, the second resistor is connected in series in a circuit through which a forward current signal or a reverse current signal flows, the positive input terminal and the negative input terminal of the first current shunt monitor are respectively connected to the two ends of the second resistor, the output terminal of the first current shunt monitor is connected to the positive electrode of the first diode, the positive input terminal and the negative input terminal of the second current shunt monitor are respectively connected to the two ends of the second resistor, the output terminal of the second current shunt monitor is connected to the positive electrode of the second diode, the negative electrode of the first diode is connected to the negative electrode of the second diode and is connected together to the gate of the third NMOS tube, the drain of the third NMOS tube is connected to the series node between the positive input terminal of the photoelectric isolation gate driver and the first resistor, the source of the third NMOS tube is connected to the ground terminal, one end of the third resistor is connected to the gate of the third NMOS tube, and the other end of the third resistor is connected to the ground terminal. 5 . The embedded switch system for power chip testing according to claim 1 , wherein the first NMOS tube and the second NMOS tube are both gallium nitride NMOS tubes. 6. The embedded switch system for power chip testing according to claim 1 is characterized in that when the switch unit is turned on, the current of the circuit loop flows forward or reversely, wherein the current flow direction of the circuit loop is determined by the potential difference applied across each of the branches.