CN118137781A - Power circuit, direct current converter and power management system - Google Patents

Power circuit, direct current converter and power management system Download PDF

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Publication number
CN118137781A
CN118137781A CN202211535943.5A CN202211535943A CN118137781A CN 118137781 A CN118137781 A CN 118137781A CN 202211535943 A CN202211535943 A CN 202211535943A CN 118137781 A CN118137781 A CN 118137781A
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CN
China
Prior art keywords
power
electrically connected
circuit
switch unit
flying capacitor
Prior art date
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Pending
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CN202211535943.5A
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Chinese (zh)
Inventor
马乔博
张雄杰
江洋
罗文基
麦沛然
马许愿
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University of Macau
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University of Macau
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Application filed by University of Macau filed Critical University of Macau
Priority to CN202211535943.5A priority Critical patent/CN118137781A/en
Publication of CN118137781A publication Critical patent/CN118137781A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The application provides a power circuit, a direct current converter and a power management system, which relate to the technical field of converters and comprise a first flying capacitor, a second flying capacitor, an inductor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a power input end and a power output end, wherein the power input end is connected with the first end of the first flying capacitor through the first switch unit, the first end of the first flying capacitor is sequentially connected with the power output end through the third switch unit and the fourth switch unit, the second end of the first flying capacitor is connected with the first end of a second flying capacitor through the inductor, the second end of the first flying capacitor is grounded through the second switch unit, the first end of the second flying capacitor is grounded through the fifth switch unit, and the second end of the second flying capacitor is connected with the power output end through the sixth switch unit, so that high efficiency and high power density are realized.

Description

Power circuit, direct current converter and power management system
Technical Field
The present application relates to the field of converters, and in particular, to a power circuit, a dc converter, and a power management system.
Background
As data centers, electric vehicles, and industrial robot systems are increasingly functioning, the voltage supplied to a load by a power source is typically managed by millions of power density Switched Capacitor (SC) DC-DC converters.
Millions of power density Switch Capacitor (SC) DC-DC converters have the problem of discontinuous transformation ratio when the system function of a load is complex, in the prior art, the capacitor-inductor hybrid converter designed based on the inductor volt-second balance principle can meet the requirement of transformation ratio continuity under the complex function, but the conduction loss of current in the capacitor-inductor hybrid converter is higher, and the power density is lower. In the prior art, the high direct current resistance of the inductor is reduced to reduce the conduction loss of current, but the volume of the inductor is increased, so that the power density is further reduced.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a power circuit, a direct current converter and a power management system so as to solve the technical problems of reducing the conduction loss of current and reducing the power density in the prior art.
In order to achieve the above purpose, the technical scheme adopted by the embodiment of the application is as follows:
In a first aspect, an embodiment of the present application provides a power circuit, including: the first flying capacitor, the second flying capacitor, the inductor, the first switching unit, the second switching unit, the third switching unit, the fourth switching unit, the fifth switching unit, the sixth switching unit, the power input end and the power output end;
the power input end is electrically connected with a power bus, and the power output end is electrically connected with an electric load; the power input end is electrically connected with the first end of the first flying capacitor through the first switch unit;
The first end of the first flying capacitor is electrically connected with the power output end through the third switch unit and the fourth switch unit in sequence, the second end of the first flying capacitor is electrically connected with the first end of the second flying capacitor through the inductor, the second end of the first flying capacitor is also grounded through the second switch unit, the first end of the second flying capacitor is also electrically connected with the first end of the fourth switch unit, the second end of the second flying capacitor is grounded through the fifth switch unit, and the second end of the second flying capacitor is also electrically connected with the power output end through the sixth switch unit.
Optionally, the first switching unit includes: a first power switch tube, a first driving buffer and a first level shift circuit; the drain electrode of the first power switch tube is electrically connected with the power input end, the source electrode of the first power switch tube is electrically connected with the first end of the first flying capacitor, the grid electrode of the first power switch tube is electrically connected with the output end of the first driving buffer, and the input end of the first driving buffer is electrically connected with the output end of the first level shift circuit; the positive power end of the first driving buffer is electrically connected with a first preset direct current power supply, and the negative power end of the first driving buffer is electrically connected with the source electrode of the first power switch tube;
The third switching unit includes: the third power switch tube, the third driving buffer and the third level shift circuit, wherein the drain electrode of the third power switch tube is electrically connected with the first end of the first flying capacitor, the source electrode of the third power switch tube is electrically connected with the first end of the second flying capacitor, the grid electrode of the third power switch tube is electrically connected with the output end of the third driving buffer, and the input end of the third driving buffer is electrically connected with the output end of the third level shift circuit; the positive power end of the third driving buffer is electrically connected with a third preset direct current power supply, and the negative power end of the third driving buffer is electrically connected with the source electrode of the third power switch tube;
The sixth switching unit includes: the power supply circuit comprises a sixth power switch tube, a sixth driving buffer and a sixth level shift circuit, wherein the drain electrode of the sixth power switch tube is electrically connected with the power supply output end, the source electrode of the sixth power switch tube is electrically connected with the second end of the second flying capacitor, the grid electrode of the sixth power switch tube is electrically connected with the output end of the sixth driving buffer, and the input end of the sixth driving buffer is connected with the output end of the sixth level shift circuit; the positive power end of the sixth driving buffer is electrically connected with a sixth preset direct current power supply, and the negative power end of the sixth driving buffer is electrically connected with the source electrode of the sixth power switch tube;
wherein the first level shift circuit, the third level shift circuit, and the sixth level shift circuit are floating level shift circuits.
Optionally, the fourth switching unit includes: the drain electrode of the fourth power switch tube is electrically connected with the first end of the second flying capacitor, the source electrode of the fourth power switch tube is electrically connected with the power output end, the grid electrode of the fourth power switch tube is electrically connected with the output end of the fourth drive buffer, and the input end of the fourth drive buffer is electrically connected with the output end of the fourth level shift circuit; the positive power end of the fourth driving buffer is electrically connected with a fourth preset direct current power supply, and the negative power end of the fourth driving buffer is electrically connected with the power output end;
wherein the fourth level shift circuit is a fixed level shift circuit.
Optionally, the second switching unit includes: the drain electrode of the second power switch tube is electrically connected with the second end of the first flying capacitor, the source electrode of the second power switch tube is grounded, and the grid electrode of the second power switch tube is electrically connected with the output end of the second drive buffer; the positive power supply end of the second driving buffer is electrically connected with a second preset direct current power supply, and the negative power supply end of the second driving buffer is grounded;
The fifth switching unit includes: the drain electrode of the fifth power switch tube is electrically connected with the second end of the second flying capacitor, the source electrode of the fifth power switch tube is grounded, and the grid electrode of the fifth power switch tube is electrically connected with the output end of the fifth drive buffer; the positive power supply end of the fifth driving buffer is electrically connected with a fifth preset direct current power supply, and the negative power supply end of the fifth driving buffer is grounded.
Optionally, the power circuit further comprises: an output capacitance;
the first end of the output capacitor is electrically connected with the power supply output end, and the second end of the output capacitor is grounded.
Optionally, the voltage of the power bus is 12V or 24V.
In a second aspect, an embodiment of the present application provides a dc converter, including: the power circuit is the power circuit of the first aspect;
The power supply output end of the power circuit is electrically connected with the input end of the voltage sampling module, the output end of the voltage sampling module is also electrically connected with the input end of the output voltage control module, and the output end of the output voltage control module is electrically connected with the control end of each switch unit in the power circuit.
Optionally, the output voltage control module includes: an error amplifier, a triangular wave signal generator, a comparator and a clock signal generator;
The output end of the voltage sampling module is electrically connected with the negative input end of the error amplifier, and the positive input end of the error amplifier is electrically connected with a preset reference power supply; the output end of the error amplifier is electrically connected with the positive input end of the comparator, the output end of the triangular wave signal generator is electrically connected with the negative input end of the comparator, the output end of the comparator is electrically connected with the input end of the clock signal generator, and the output end of the clock signal generator is electrically connected with the control end of each switch unit in the power circuit.
In a third aspect, an embodiment of the present application provides a power management system, including: a power bus, a dc converter according to the second aspect; the power bus is electrically connected with the power input end of the direct current converter, and the power output end of the direct current converter is electrically connected with an electric load.
Compared with the prior art, the application has the following beneficial effects:
The application provides a power circuit, a direct current converter and a power management system, wherein the power circuit comprises: the first end of the first flying capacitor is electrically connected with the power output end through the third switch unit and the fourth switch unit in sequence, the second end of the first flying capacitor is electrically connected with the first end of the second flying capacitor through the inductor, the second end of the first flying capacitor is also grounded through the second switch unit, the first end of the second flying capacitor is also electrically connected with the first end of the fourth switch unit, the second end of the second flying capacitor is also grounded through the fifth switch unit, the second end of the second flying capacitor is also electrically connected with the power output end through the sixth switch unit, and the high-efficiency and high-power-density conduction are realized by reducing the inductance current.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a power circuit according to an embodiment of the present application;
fig. 2 is a schematic diagram of another power circuit according to an embodiment of the present application;
fig. 3 is a schematic diagram of another power circuit according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of another power circuit according to an embodiment of the present application;
Fig. 5 is a schematic diagram of another power circuit according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a power circuit switch state according to an embodiment of the present application;
FIG. 7 is a schematic diagram illustrating another power circuit switch state according to an embodiment of the present application;
fig. 8 is a schematic diagram of a switch conduction loss distribution according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a dc converter according to an embodiment of the present application;
Fig. 10 is a schematic structural diagram of another dc converter according to an embodiment of the present application;
FIG. 11 is a schematic diagram of modeling data analysis according to an embodiment of the present application;
Fig. 12 is a schematic structural diagram of a power management system according to an embodiment of the present application;
fig. 13 is a schematic structural diagram of an electrical device according to an embodiment of the present application.
Icon: a power circuit 100; a first flying capacitor C1; a second flying capacitor C2; an inductance L; a first switching unit S1; a second switching unit S2; a third switching unit S3; a fourth switching unit S4; a fifth switching unit S5; a sixth switching unit S6; a power input VIN; a power supply output end VOUT; a first power switching tube 11; a first drive buffer 12; a first level shift circuit 13; a first preset dc power supply 14; a third power switching tube 31; a third drive buffer 32; a third level shift circuit 33; a third preset dc power supply 34; a sixth power switching tube 61; a sixth drive buffer 62; a sixth level shift circuit 63; a sixth preset dc power supply 64; a fourth power switching tube 41; a fourth drive buffer 42; a fourth level shift circuit 43; a fourth preset dc power supply 44; a second power switching tube 21; a second drive buffer 22; a second preset dc power supply 24; a fifth power switching tube 51; a fifth driving buffer 52; fifth preset dc power supply 54; an output capacitance COUT; a power circuit 100; a voltage sampling module 200; an output voltage control module 300; an error amplifier 310; a triangular wave signal generator 320; a comparator 330; a clock signal generator 340; a first voltage dividing resistor Rf1; a second voltage dividing resistor Rf2; a preset reference power supply 350; a power management system 1; a power bus 2000; a dc converter 1000; and an electric load 2 is used.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present invention, the terms "first," "second," "third," and the like, if any, are used solely for distinguishing between descriptions and should not be construed as indicating or implying a relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
In recent years, the rapidly growing demands for functions and complexity of data centers, electric vehicles and industrial robot systems have presented challenges for low-cost, high-integration and high-power density traditional power management, wherein millions of power density switched capacitor dc-dc converters have hindered the development trend of future diversified power management applications due to discontinuous transformation ratios, and capacitor-inductor hybrid converters designed based on the principle of inductive volt-second balance can cope with the requirements for transformation ratio continuity under complex functions, but the capacitor-inductor hybrid converters face the problems of higher conduction loss and difficulty in improving power density due to high inductance dc resistance. While low conduction losses are guaranteed in the prior art, they sacrifice power density at the same time as low conduction losses.
In order to reduce the influence on the power density while reducing the conduction loss of the current in the converter, i.e. to improve the reduced power density on the basis of the reduction of the conduction loss of the current in the prior art, the present application provides a power circuit, and the explanation of the power circuit provided by the embodiments of the present application is given below by way of specific examples. Fig. 1 is a schematic structural diagram of a power circuit according to an embodiment of the present application, as shown in fig. 1, the power circuit 100 includes: the first flying capacitor C1, the second flying capacitor C2, the inductor L, the first switching unit S1, the second switching unit S2, the third switching unit S3, the fourth switching unit S4, the fifth switching unit S5, the sixth switching unit S6, the power input terminal VIN and the power output terminal VOUT.
The power input terminal VIN is electrically connected to a power bus, through which a supply current and a supply voltage can be provided to the power circuit 100, and the power output terminal VOUT is electrically connected to an electrical load, through which the power circuit 100 can supply power to the electrical load and provide a working voltage.
The power input terminal VIN is electrically connected to the first terminal of the first flying capacitor C1 through the first switching unit S1.
The first end of the first flying capacitor C1 is electrically connected with the power supply output end through the third switch unit S3 and the fourth switch unit S4 in sequence, the second end of the first flying capacitor C1 is electrically connected with the first end of the second flying capacitor C2 through the inductor L, the second end of the first flying capacitor C1 is further grounded through the second switch unit S2, the first end of the second flying capacitor C2 is further connected with the first end of the fourth switch unit S4, the second end of the second flying capacitor C2 is grounded through the fifth switch unit S5, and the second end of the second flying capacitor C2 is further electrically connected with the power supply output end through the sixth switch unit S6.
In the embodiment of the application, in the working process of the power circuit, the withstand voltages of the first switch unit S1 and the second switch unit S2 are Vin-2Vout, wherein Vin is the voltage of the power input end VIN, and Vout is the voltage of the power output end VOUT; the withstand voltage of the third switch unit S1 is Vin-Vout, the withstand voltages of the fourth switch unit S4, the fifth switch unit S5 and the sixth switch unit S6 are Vout, and under the power bus voltage architecture, the output voltage Vout of the power output terminal Vout is far lower than the input voltage Vin of the power input terminal Vin.
When the first switch unit S1, the fourth switch unit S4 and the fifth switch unit S5 are all closed, and when the second switch unit S2, the third switch unit S3 and the sixth switch unit S6 are all opened, the inductor L is connected in parallel with the second flying capacitor C2, and the second flying capacitor C2 plays a role of shunting, so that the current flowing through the inductor L is reduced, and further, the conduction loss of the current in the inductor L is reduced.
When the second switching unit S2, the third switching unit S3 and the sixth switching unit S6 are all closed,
When the first switch unit S1, the fourth switch unit S4 and the fifth switch unit S5 are all turned off, the inductor L is connected in parallel with the first flying capacitor C1, and the first flying capacitor C1 plays a role in shunting, so that the current flowing through the inductor L is reduced, and further, the conduction loss of the current in the inductor L is reduced.
Therefore, in both states of the switch corresponding to the operation of the power circuit 100, there is a fly 5 transcapacitive connected in parallel with the inductance L to reduce the conduction loss for the current in the inductance L, at the power
Under the condition that the output power of the circuit 100 is unchanged, the power circuit 100 reduces the current in the inductance and the conduction loss through the parallel flying capacitor, while in the prior art, the conduction loss is reduced through reducing the resistance value of the inductance and the conduction loss, the capacitor in the power circuit 100 has smaller volume, so that the power circuit 100
The volume is almost unchanged, so that the power density is almost unchanged, but in the prior art, the reduction of the resistance value of the inductance L of 0 leads to the increase of the volume of the inductance L, and the power density is greatly reduced, therefore, the invention
The power circuit 100 of the present application improves power density while reducing conduction losses.
The power circuit reduces the inductance current, reduces the conduction loss, improves the power density on the basis of reducing the conduction loss, realizes high efficiency and high power density, and can
To solve the technical problem of power density reduction while reducing conduction loss of current in the converter. 5 based on the power circuit shown in FIG. 1, another embodiment of the present application further provides
A power circuit. Optionally, fig. 2 is a schematic structural diagram of another power circuit according to an embodiment of the present application, as shown in fig. 2, the first switch unit S1 includes: a first power switch 11, a first driving buffer 12, and a first level shift circuit 13.
The drain electrode of the first power switch tube 11 is electrically connected to the power input end VIN, the source electrode of the first power switch tube 110 is electrically connected to the first end of the first flying capacitor C1, and illustratively, the source electrode of the first power switch tube 11 and the first end of the first flying capacitor C1 are both connected to the circuit node V T1, the gate electrode of the first power switch tube 11 is electrically connected to the output end of the first driving buffer 12, and the input end of the first driving buffer 12 is electrically connected to the output end of the first level shift circuit 13.
Since the voltage of the source of the first power switch 11 is not fixed and changes with the operation of the power circuit 5, it is necessary to change the voltage of the source of the first power switch 11
Since the clock signal input to the first level shift circuit 13 is level-shifted, the first level shift circuit 13 needs to be connected to the driving circuit of the first power switching transistor 11.
The voltage at the source of the first power switch 11 is the same as the voltage at the circuit node V T1, and according to the two states of the corresponding switch in the operation of the power circuit 100, it can be calculated that the voltage at the circuit node V T1 changes according to the different operation states, so that the first level shift circuit 13 is a floating level shift circuit (Junction Isolation LEVEL SHIFTER, JILS).
The positive power supply end of the first driving buffer 12 is electrically connected to the first preset dc power supply 14, and the negative power supply end of the first driving buffer 12 is electrically connected to the source electrode of the first power switch tube, so that the voltage difference between the two ends of the power supply of the first driving buffer 12 is a preset fixed value.
The first level shift circuit 13 may receive the transmitted clock signal, after level shifting the clock signal, send the clock signal after level shifting to the first driving buffer 12, where the first driving buffer 12 may perform driving capability improvement on the clock signal after level shifting, so as to ensure that the clock signal has enough driving current in the driving process to drive the first power switch 11 to be turned on or turned off, and meanwhile, the first driving buffer 12 may further improve the anti-interference capability of the clock signal after level shifting.
The third switching unit S3 includes: the drain of the third power switch tube 31 is electrically connected to the first end of the first flying capacitor C1, illustratively, the drain of the third power switch tube 31 is electrically connected to the circuit node V T1, the source of the third power switch tube 31 is electrically connected to the first end of the second flying capacitor C2, the gate of the third power switch tube 31 is electrically connected to the output end of the third driving buffer 32, and the input end of the third driving buffer 32 is electrically connected to the output end of the third level shift circuit 33.
Since the voltage at the source of the third power switching transistor 31 is not zero, the clock signal input to the third level shift circuit 33 needs to be level-shifted according to the voltage change at the source of the third power switching transistor 31, and therefore the third level shift circuit 33 needs to be connected to the driving circuit of the third power switching transistor 31. The voltage at the source of the third power switching transistor 31 changes according to the two states of the corresponding switch in which the power circuit 100 operates, and therefore the third level shift circuit 33 is a floating level shift circuit.
The positive power supply end of the third driving buffer 32 is electrically connected to a third preset dc power supply 34, and the negative power supply end of the third driving buffer 32 is electrically connected to the source of the third power switch tube 31. The third level shift circuit 33 may receive the transmitted clock signal, level shift the clock signal, send the level-shifted clock signal to the third driving buffer 32, and the third driving buffer 32 may boost the driving capability of the level-shifted clock signal to drive the first power switch 11 to be turned on or turned off.
The sixth switching unit S6 includes: the drain electrode of the sixth power switch tube 61 is electrically connected to the power output terminal VOUT, the source electrode of the sixth power switch tube 61 is electrically connected to the second end of the second flying capacitor C2, for example, the source electrode of the sixth power switch tube 61 and the second end of the second flying capacitor C2 are both connected to the circuit node V B2, the gate electrode of the sixth power switch tube 61 is electrically connected to the output terminal of the sixth driving buffer 62, and the input terminal of the sixth driving buffer 62 is connected to the output terminal of the sixth level shift circuit 63.
Since the voltage of the source of the sixth power switching transistor 61 is not zero, the clock signal input to the sixth level shift circuit 63 needs to be level-shifted according to the voltage change of the source of the sixth power switching transistor 61, and therefore the sixth level shift circuit 63 needs to be connected to the driving circuit of the sixth power switching transistor 61. The voltage at the source of the sixth power switching transistor 61 changes according to the two states of the corresponding switch in which the power circuit 100 operates, and therefore the sixth level shift circuit 63 is a floating level shift circuit.
The positive power supply end of the sixth driving buffer 62 is electrically connected to a sixth preset dc power supply 64, and the negative power supply end of the sixth driving buffer 62 is electrically connected to the source of the sixth power switching tube 61. The sixth level shift circuit 63 may receive the transmitted clock signal, level shift the clock signal, send the level-shifted clock signal to the sixth driving buffer 62, and the sixth driving buffer 62 may boost the driving capability of the level-shifted clock signal to drive the sixth power switching tube 61 to be turned on or turned off.
The driving circuits of the first power switch 11, the third power switch 31 and the sixth power switch 61 all need to construct a floating voltage domain. For example, the sixth power switch 61 is specifically explained as an example, when the first switch unit S1, the fourth switch unit S4 and the fifth switch unit S5 are all closed, when the second switch unit S2, the third switch unit S3 and the sixth switch unit S6 are all opened, the voltage of the source of the sixth power switch 61 is 0, when the second switch unit S2, the third switch unit S3 and the sixth switch unit S6 are all closed, and when the first switch unit S1, the fourth switch unit S4 and the fifth switch unit S5 are all opened, the voltage of the source of the sixth power switch 61 is the output voltage Vout, and therefore, the voltages of the clock signals driving the closing and opening of the sixth power switch 61 are VDD5+vout and 0, respectively, which requires to establish a floating voltage domain capable of following the voltage change of the source thereof, that is, by the floating level shift circuit, it is satisfied that the voltage of the sixth power switch 61 can be driven by outputting the voltage of VDD5+vout when the clock signal is logic high (the sixth power switch unit 61 is closed/on).
In the embodiment of the present application, the voltages of the clock signals driving the first power switch 11 to be turned on and off are VDD5+vin and 2Vout, respectively, and the voltages of the clock signals driving the third power switch 31 to be turned on and off are VDD5+2vout and Vout, respectively.
In the embodiment of the present application, the first, third and sixth driving buffers 12, 32 and 62 have the same function in driving the switching tubes, and the first, third and sixth level shift circuits 13, 33 and 63 have the same function in driving the switching tubes.
According to the power circuit provided by the embodiment of the application, the floating level shifting circuit is arranged according to the voltage change conditions of the sources of the first power switching tube, the third power switching tube and the sixth power switching tube, so that the clock signals input to the three floating level shifting circuits are level shifted, and meanwhile, the driving control of the three power switching tubes is realized through the first driving buffer, the three driving buffers and the sixth driving buffer.
On the basis of the power circuit shown in fig. 2, the embodiment of the application also provides another power circuit. Optionally, fig. 3 is a schematic structural diagram of another power circuit according to an embodiment of the present application, as shown in fig. 3, a fourth switching unit S4 includes: a fourth power switching transistor 41, a fourth driving buffer 42, and a fourth level shift circuit 43.
The drain electrode of the fourth power switch tube 41 is electrically connected to the first end of the second flying capacitor C2, the source electrode of the fourth power switch tube 41 is electrically connected to the power output terminal VOUT, the gate electrode of the fourth power switch tube 41 is electrically connected to the output terminal of the fourth driving buffer 42, and the input terminal of the fourth driving buffer 42 is electrically connected to the output terminal of the fourth level shift circuit 43.
Since the voltage at the source of the fourth power switching transistor 41 is not zero, the clock signal input to the fourth level shift circuit 43 needs to be level-shifted according to the voltage change at the source of the fourth power switching transistor 41, and therefore the fourth level shift circuit 43 needs to be connected to the driving circuit of the fourth power switching transistor 41.
Since the voltage at the source of the fourth power switching transistor 41 is the same as the output voltage VOUT of the power supply output terminal VOUT, the voltage at the source of the fourth power switching transistor 41 is unchanged according to the two states of the corresponding switch in which the power circuit 100 operates, and therefore the fourth level shift circuit 43 is a fixed level shift circuit (Charge Pump-based LEVEL SHIFTERS, CPLS).
The positive power supply terminal of the fourth driving buffer 42 is electrically connected to the fourth preset dc power supply 44, and the negative power supply terminal of the fourth driving buffer 42 is electrically connected to the power output terminal VOUT, so that the voltage difference between the two terminals of the power supply of the fourth driving buffer 42 is always the output voltage VDD5.
The fourth level shift circuit 43 may receive the transmitted clock signal, after level shifting the clock signal, send the level shifted clock signal to the fourth driving buffer 42, where the fourth driving buffer 42 may boost the driving capability of the level shifted clock signal, so as to ensure that the clock signal has enough driving current in the driving process to drive the fourth power switch 41 to be turned on or turned off, and meanwhile, the fourth driving buffer 42 may perform a middle-stage stabilization on the level shifted clock signal, so as to improve the anti-interference capability of the signal.
In the embodiment of the application, the power switch tube with the source voltage of a fixed value is easier to drive than a power switch tube with a non-fixed value. The power switching transistor having a fixed source voltage is the fourth power switching transistor 41, and the voltage of the source of the fourth power switching transistor 41 is always a fixed output voltage Vout. Therefore, the clock signal received by the fourth level shift circuit 43 needs to be superimposed with one output voltage by level shift, and thus the voltages of the clock signals driving the fourth power switching transistor 41 to be turned on and off are VDD5+vout and Vout, respectively.
According to the power circuit provided by the embodiment of the application, the fixed level shift circuit is arranged according to the fact that the voltage of the source electrode of the fourth power switch tube is the fixed voltage, so that the clock signal input to the fourth level shift circuit is level shifted, and meanwhile, the driving control of the fourth power switch tube is realized through the fourth driving buffer.
On the basis of the power circuit shown in fig. 3, the embodiment of the application also provides another power circuit. Optionally, fig. 4 is a schematic structural diagram of another power circuit according to an embodiment of the present application, as shown in fig. 4, the second switch unit S2 includes: a second power switching tube 21, and a second driving buffer 22.
The drain electrode of the second power switch tube 21 is electrically connected to the second end of the first flying capacitor C1, the source electrode of the second power switch tube 21 is grounded, and the gate electrode of the second power switch tube 21 is electrically connected to the output end of the second driving buffer 22.
Since the source electrode of the second power switch tube 21 is grounded, the fan-out capability of the driving circuit corresponding to the gate electrode of the second power switch tube 21 is only needed to be considered for driving the second power switch tube 21, and the level shift of the clock signal is not needed, so that the level shift circuit is not needed to be arranged in the driving circuit of the second power switch tube 21.
The positive power supply terminal of the second driving buffer 22 is electrically connected to the second preset dc power supply 24, and the negative power supply terminal of the second driving buffer 22 is grounded. The second driving buffer 22 can receive the transmitted clock signal, so as to improve the driving capability, ensure that the clock signal has enough driving current in the driving process, drive the second power switch tube 21 to be closed or opened according to the clock signal, and meanwhile, the second driving buffer 22 can perform a middle-stage stabilization on the clock signal, so that the anti-interference capability of the signal is improved.
The fifth switching unit S5 includes: the drain of the fifth power switch tube 51 is electrically connected to the second end of the second flying capacitor C2, for example, the drain of the fifth power switch tube 51 is electrically connected to the circuit node V B2, the source of the fifth power switch tube 51 is grounded, and the gate of the fifth power switch tube 51 is electrically connected to the output end of the fifth drive buffer 52.
Since the source electrode of the fifth power switch tube 51 is grounded, the driving of the fifth power switch tube 51 only needs to consider the fanout capability of the driving circuit corresponding to the gate electrode of the fifth power switch tube 51, and no level shift is needed for the clock signal, so that no level shift circuit is needed in the driving circuit of the fifth power switch tube 51.
The positive power supply terminal of the fifth driving buffer 52 is electrically connected to a fifth preset dc power supply 54, and the negative power supply terminal of the fifth driving buffer 52 is grounded. The fifth driving buffer 52 can receive the transmitted clock signal, so as to improve the driving capability, ensure that the clock signal has enough driving current in the driving process, drive the fifth power switch tube 51 to be closed or opened according to the clock signal, and meanwhile, the fifth driving buffer 52 can perform a middle-stage stabilization on the clock signal, so as to improve the anti-interference capability of the signal.
In the embodiment of the present application, the voltages of the clock signals driving the second power switch tube 21 to be turned on and off are VDD5 and 0, respectively, and the voltages of the clock signals driving the fifth power switch tube 51 to be turned on and off are VDD5 and 0, respectively.
According to the power circuit provided by the embodiment of the application, the sources of the second power switch tube and the fifth power switch tube are grounded, and the driving control of the second power switch tube and the fifth power switch tube can be realized by only arranging the second driving buffer and the fifth driving buffer.
On the basis of the power circuit shown in fig. 1, the embodiment of the application also provides another power circuit. Optionally, fig. 5 is a schematic structural diagram of another power circuit according to an embodiment of the present application, as shown in fig. 5, the power circuit 100 further includes: and outputting a capacitor COUT.
The first end of the output capacitor COUT is electrically connected with the power supply output end VOUT, and the second end of the output capacitor COUT is grounded.
In the embodiment of the application, the output capacitor COUT can play roles of filtering and voltage stabilization.
In the embodiment of the application, the power bus voltage is 12V or 24V.
Fig. 6 is a schematic structural diagram of a power circuit switch state according to an embodiment of the present application, as shown in fig. 6, when the first switch unit S1, the fourth switch unit S4 and the fifth switch unit S5 are all closed, and when the second switch unit S2, the third switch unit S3 and the sixth switch unit S6 are all opened, the input voltage VIN provided by the power input terminal VIN may be the first flying capacitor C1 and the inductor L, the second flying capacitor C2 is in a discharging state, and in the switching state, the first flying capacitor C1 may be charged to 2Vout, the voltage on the second flying capacitor C2 is Vout, at this time, the voltage at the left end of the inductor L is VIN-2Vout, and the voltage at the right end of the inductor L is Vout, so the voltage difference across the inductor L is VIN-3Vout.
Fig. 7 is a schematic diagram of another power circuit switching state according to an embodiment of the present application, as shown in fig. 7, when the second switch unit S2, the third switch unit S3 and the sixth switch unit S6 are all closed, and when the first switch unit S1, the fourth switch unit S4 and the fifth switch unit S5 are all open, the first flying capacitor C1 is in a discharging state, the second flying capacitor C2 is in a charging state, and in the switching state, the voltage difference between two ends of the inductor L is-2 Vout.
The voltage difference between two ends of an inductor L in two switching states of a power circuit is substituted into a volt-second balance formula based on inductance-voltage, a transformation ratio expression M=Vout/vin=D/(2+D) can be obtained through calculation, wherein D is the duty ratio of a clock signal, the range of D is between 0 and 1, and the range of the transformation ratio M is between 0 and 1/3 through calculation.
In the embodiment of the application, the ideal range of the transformation ratio is 0-1/3, and the actual range of the output voltage of the power circuit is set to be 1.8-3.3V/5V in consideration of the influence of the actual application scene, parasitic capacitance, resistance and other reasons. When the power bus voltage is 12V, the actual range of the output voltage of the power circuit may be 1.8V-3.3V, and when the power bus voltage is 24V, the actual range of the output voltage of the power circuit may be 1.8V-5V.
In the embodiment of the present application, the steady-state capacitance voltage of the first flying capacitor C1 is 2Vout, and the steady-state capacitance of the second flying capacitor C2 is Vout.
According to the power circuit, the direct current of the inductor L can be calculated to be I L,DC＝M/(DIOUT)＝IOUT/(2+D) by using the expression of energy conservation and transformation ratio, wherein D ranges from 0 to 1, and I OUT is output current.
According to the power circuit provided by the embodiment of the application, the first end of the output capacitor is electrically connected with the power output end, the second end of the output capacitor is grounded, the voltage of the power bus is 12V or 24V, the inductance current which is equal to the output current in the traditional structure can be maximally reduced to 1/3 of the output current through the capacitor branch connected with the inductance in parallel, and the inductance of a large direct current resistor with smaller volume can be selected to improve the power density of the power circuit on the basis of ensuring that the direct current loss of the inductance is unchanged.
Meanwhile, in the switch capacitor-inductor hybrid structure in the power circuit provided by the application, the inductor has the function of voltage isolation, so that in the power circuit, a switch directly connected with the left end of the inductor or through the capacitor is a high-voltage switch, a switch directly connected with the right end of the inductor or through the capacitor is a low-voltage switch, and fig. 8 is a schematic diagram of the distribution of the conduction loss of the switch, which is provided by the embodiment of the application, as shown in fig. 8, the high-voltage switch flows through a small current, and the low-voltage switch flows through a large current, so that the separation of withstand voltage and current problems is realized, the loss of the switch is reduced, and the power density and the efficiency are further improved. Meanwhile, compared with a high-voltage switch, the low-voltage switch has superior performance (smaller Qg Ron), the application fully utilizes the performance advantage of the low-voltage switch compared with the high-voltage switch, relieves the challenges brought by high-voltage and high-current, can ensure high output current, and simultaneously selects and uses the inductor with small volume and large direct current resistance, thereby improving the power density of a converter system and ensuring the efficiency of the converter.
On the basis of the power circuits shown in fig. 1 to 8, the embodiment of the application further provides a direct current converter. Optionally, fig. 9 is a schematic structural diagram of a dc converter according to an embodiment of the present application, and as shown in fig. 9, a dc converter 1000 includes: a power circuit 100, a voltage sampling module 200, and an output voltage control module 300.
The power output end of the power circuit 100 is electrically connected to the input end of the voltage sampling module 200, the output end of the voltage sampling module 200 is electrically connected to the input end of the output voltage control module 300, and the output end of the output voltage control module 300 is electrically connected to the control end of each switch unit in the power circuit 100.
The power output end of the power circuit 100 is electrically connected with an electric load, and when the functions in the same electric load are changed, the current will change correspondingly, and the output voltage will be directly affected. Illustratively, taking a load current jump as an example, when the load current jumps from 0.5A to 1A, the transient output charge can only be provided by the output capacitance, which can result in an output voltage dip, and the voltage sampled by the voltage sampling module 200 can become low.
In order to ensure that the voltage is always stable when the power load function is changed, i.e. the output voltage is always maintained at a fixed voltage, the output voltage control module 300 is required to perform real-time linear adjustment and load adjustment on the output voltage of the power output terminal. For example, if the output voltage is lower than the fixed voltage, the power circuit 100 is regulated by the output voltage control module 300 such that the output voltage rises to the fixed voltage, and if the output voltage is higher than the fixed voltage, the power circuit 100 is regulated by the output voltage control module 300 such that the output voltage drops to the fixed voltage.
In the embodiment of the present application, the output voltage control module 300 may adjust the clock signal in time according to the variation condition of the output voltage acquired by the voltage sampling module 200, and further send the adjusted clock signal to the control end of each switch unit in the power circuit 100, so as to adjust the output voltage of the power circuit 100.
The embodiment of the application provides a direct current converter, which comprises: the power circuit, voltage sampling module, output voltage control module, the input of voltage sampling module is still connected to power circuit's power output end electricity, output voltage control module's input is still connected to voltage sampling module's output electricity, output voltage control module's output electricity is connected the control end of each switch unit in the power circuit, output voltage control module can in time adjust clock signal according to the output voltage that voltage sampling module gathered, power circuit 100 adjusts output voltage according to the clock signal after the adjustment, the voltage stability of power consumption load has been guaranteed.
On the basis of the direct current converter shown in fig. 9, another direct current converter is further provided in the embodiment of the application. Optionally, fig. 10 is a schematic structural diagram of another dc converter according to an embodiment of the present application, as shown in fig. 10, an output voltage control module 300 includes: error amplifier 310, triangular wave signal generator 320, comparator 330, clock signal generator 340.
The output end of the voltage sampling module 200 is electrically connected to the negative input end of the error amplifier 310, the voltage sampling module 200 can divide the collected output voltage, and the voltage after the voltage division is the voltage that the output voltage control module 300 can bear, so that the output voltage control module 300 analyzes the output voltage. In the embodiment of the present application, the voltage sampling module 200 includes a first voltage dividing resistor Rf1 and a second voltage dividing resistor Rf2, wherein a first end of the first voltage dividing resistor Rf1 is electrically connected to the power output terminal VOUT, a second end of the first voltage dividing resistor Rf1 is grounded through the second voltage dividing resistor Rf2, and a negative input end of the error amplifier 310 is electrically connected to an intermediate connection point of the first voltage dividing resistor Rf1 and the second voltage dividing resistor Rf 2.
The positive input of the error amplifier 310 is electrically connected to a preset reference power supply 350, which provides a reference voltage signal, so that the error amplifier 310 can compare the output voltage signal with the reference voltage signal to obtain an error voltage signal, and the error voltage signal is an analog signal.
The output end of the error amplifier 310 is electrically connected to the positive input end of the comparator 330, and the output end of the triangular wave signal generator 320 is electrically connected to the negative input end of the comparator 330. The input end of the triangular wave signal generator can input the maximum value and the minimum value of the generated triangular wave signal, and the triangular wave signal generator can generate a corresponding triangular wave signal according to the maximum value and the minimum value. The error amplifier 310 may compare the error voltage signal with the generated triangular wave signal to obtain a reference clock signal of the dc converter 1000, wherein the reference clock signal is a periodic signal having a specific duty cycle.
The output terminal of the comparator 330 is electrically connected to the input terminal of the clock signal generator 340, and the output terminal of the clock signal generator 340 is electrically connected to the control terminal of each switching unit in the power circuit 100. In an embodiment of the present application, to avoid shorting, the clock signal generator 340 is a non-overlapping clock signal generator, which may generate non-overlapping clock signals.
When the current of the power load changes, the output voltage can be directly influenced, the sampled voltage signal can change along with the change of the output voltage, the change is compared with the reference voltage signal to obtain an error voltage signal, the error voltage signal can change the duty ratio of the clock signal, and the power circuit is regulated in a negative feedback mode. Illustratively, taking the load current jump as an example, when the load current jumps from 0.5A to 1A, the output voltage suddenly drops, the sampled voltage becomes lower, which in turn causes the error voltage signal to rise. The increased error voltage signal, after being compared with the triangular wave signal, generates a reference clock signal with a higher duty ratio, and further more charges are injected into the power circuit to supplement the charges lost by the output capacitor, so that the output voltage can be restored to a fixed voltage.
In the embodiment of the present application, the output end of the clock signal generator 340 is electrically connected to the first level shift circuit 13, the second driving buffer 22, the third level shift circuit 33, the fourth level shift circuit 43, the fifth driving buffer 52, and the sixth level shift circuit 63, so as to send the non-overlapping clock signals to each switch unit respectively.
In the embodiment of the present application, the power circuit 100 in the dc converter 1000 has two operation states in one operation period according to the non-overlapping clock signals generated by the clock signal generator 340.
In the first state (Φ1:dt), the first switch unit S1, the fourth switch unit S4, and the fifth switch unit S5 are all in an on state, and the second switch unit S2, the third switch unit S3, and the sixth switch unit S6 are all in an off state. In the first state (Φ2 (1-D)) T, the second switching unit S2, the third switching unit S3, and the sixth switching unit S6 are all in the closed state, and the first switching unit S1, the fourth switching unit S4, and the fifth switching unit S5 are all in the open state.
Based on modeling analysis of conduction loss of a circuit by theoretical calculation, fig. 11 is a schematic diagram of modeling data analysis provided by the embodiment of the application, and as shown in fig. 11, a solid line is a simulation result corresponding to the technical scheme of the application, and a dotted line is a simulation result of the prior art, it can be seen that the technical scheme of the application realizes high efficiency.
According to the direct current converter provided by the embodiment of the application, the output end of the voltage sampling module is electrically connected with the negative input end of the error amplifier, the positive input end of the error amplifier is electrically connected with the preset reference power supply, the output end of the error amplifier is electrically connected with the positive input end of the comparator, the output end of the triangular wave signal generator is electrically connected with the negative input end of the comparator, the output end of the comparator is electrically connected with the input end of the non-overlapping clock signal generator, the output end of the clock signal generator is electrically connected with the control end of each switch unit in the power circuit, the output voltage can be regulated, meanwhile, the high-voltage direct current-direct current converter with low conduction loss characteristics is designed for a 12V/24V bus voltage architecture, the high-voltage direct current converter can output low voltage and large current with high efficiency so as to meet the development of increasingly-growing industry and automatic electronic technology, the direct current converter fully utilizes the superior performance (smaller Qg×Ron) of the low-voltage switch compared with the high-voltage switch, the high-voltage switch is decomposed, the high-voltage large-current problem of the direct current converter is borne by the low-voltage switch, the high-voltage switch bears larger current, the high-voltage switch is guaranteed, the high-voltage loss of the high-voltage switch is guaranteed, and the high-voltage switching loss of the whole switch is guaranteed, and the high-voltage loss is guaranteed. Compared with the traditional scheme of utilizing multi-stage flying capacitor voltage reduction for high voltage and large current, the method can achieve higher integration level and reduce the number of on-chip switching tubes and off-chip capacitors.
On the basis of the direct current converter shown in fig. 9, the embodiment of the application also provides a power management system. Optionally, fig. 12 is a schematic structural diagram of a power management system according to an embodiment of the present application, and as shown in fig. 12, the power management system 1 includes: a power bus 2000, and a dc converter 1000.
The power bus 2000 is electrically connected to a power input terminal of the dc converter 1000, and a power output terminal of the dc converter 1000 is electrically connected to the electrical load 2.
The DC converter 1000 provided by the application is suitable for a 12V/24V power bus voltage architecture, and is a high-efficiency high-conversion-ratio switch capacitor-inductor hybrid DC-DC converter topological structure.
The power management system provided by the application can realize high-efficiency high-power-density direct current-direct current conversion of an electric load under heavy load in the face of high input voltage.
In an embodiment of the present application, the power management system 1 may be referred to as an HV-MPSCI (High Voltage Multi-PATH SWITCHED-Capacitor Inductor) system.
Fig. 13 is a schematic structural diagram of an electrical device according to an embodiment of the present application, as shown in fig. 13, where the electrical device includes: a power management system 1 and an electrical load 2.
In the embodiment of the application, the electrical equipment can be electrical equipment of a data center, an electric automobile or an industrial robot, and the like.
The electrical equipment provided by the application can meet the requirements of rapid increase of functions and complexity of data centers, electric automobiles and industrial robots, and further improve the development of industrial and automatic electronic technologies.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but many modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A power circuit, comprising: the first flying capacitor, the second flying capacitor, the inductor, the first switching unit, the second switching unit, the third switching unit, the fourth switching unit, the fifth switching unit, the sixth switching unit, the power input end and the power output end;
the power input end is electrically connected with a power bus, and the power output end is electrically connected with an electric load; the power input end is electrically connected with the first end of the first flying capacitor through the first switch unit;
The first end of the first flying capacitor is electrically connected with the power output end through the third switch unit and the fourth switch unit in sequence, the second end of the first flying capacitor is electrically connected with the first end of the second flying capacitor through the inductor, the second end of the first flying capacitor is also grounded through the second switch unit, the first end of the second flying capacitor is also electrically connected with the first end of the fourth switch unit, the second end of the second flying capacitor is grounded through the fifth switch unit, and the second end of the second flying capacitor is also electrically connected with the power output end through the sixth switch unit.
2. The power circuit of claim 1, wherein the first switching unit comprises: a first power switch tube, a first driving buffer and a first level shift circuit; the drain electrode of the first power switch tube is electrically connected with the power input end, the source electrode of the first power switch tube is electrically connected with the first end of the first flying capacitor, the grid electrode of the first power switch tube is electrically connected with the output end of the first driving buffer, and the input end of the first driving buffer is electrically connected with the output end of the first level shift circuit; the positive power end of the first driving buffer is electrically connected with a first preset direct current power supply, and the negative power end of the first driving buffer is electrically connected with the source electrode of the first power switch tube;
The third switching unit includes: the third power switch tube, the third driving buffer and the third level shift circuit, wherein the drain electrode of the third power switch tube is electrically connected with the first end of the first flying capacitor, the source electrode of the third power switch tube is electrically connected with the first end of the second flying capacitor, the grid electrode of the third power switch tube is electrically connected with the output end of the third driving buffer, and the input end of the third driving buffer is electrically connected with the output end of the third level shift circuit; the positive power end of the third driving buffer is electrically connected with a third preset direct current power supply, and the negative power end of the third driving buffer is electrically connected with the source electrode of the third power switch tube;
The sixth switching unit includes: the power supply circuit comprises a sixth power switch tube, a sixth driving buffer and a sixth level shift circuit, wherein the drain electrode of the sixth power switch tube is electrically connected with the power supply output end, the source electrode of the sixth power switch tube is electrically connected with the second end of the second flying capacitor, the grid electrode of the sixth power switch tube is electrically connected with the output end of the sixth driving buffer, and the input end of the sixth driving buffer is connected with the output end of the sixth level shift circuit; the positive power end of the sixth driving buffer is electrically connected with a sixth preset direct current power supply, and the negative power end of the sixth driving buffer is electrically connected with the source electrode of the sixth power switch tube;
wherein the first level shift circuit, the third level shift circuit, and the sixth level shift circuit are floating level shift circuits.
3. The power circuit of claim 2, wherein the fourth switching unit comprises: the drain electrode of the fourth power switch tube is electrically connected with the first end of the second flying capacitor, the source electrode of the fourth power switch tube is electrically connected with the power output end, the grid electrode of the fourth power switch tube is electrically connected with the output end of the fourth drive buffer, and the input end of the fourth drive buffer is electrically connected with the output end of the fourth level shift circuit; the positive power end of the fourth driving buffer is electrically connected with a fourth preset direct current power supply, and the negative power end of the fourth driving buffer is electrically connected with the power output end;
wherein the fourth level shift circuit is a fixed level shift circuit.
4. A power circuit according to claim 3, wherein the second switching unit comprises: the drain electrode of the second power switch tube is electrically connected with the second end of the first flying capacitor, the source electrode of the second power switch tube is grounded, and the grid electrode of the second power switch tube is electrically connected with the output end of the second drive buffer; the positive power supply end of the second driving buffer is electrically connected with a second preset direct current power supply, and the negative power supply end of the second driving buffer is grounded;
The fifth switching unit includes: the drain electrode of the fifth power switch tube is electrically connected with the second end of the second flying capacitor, the source electrode of the fifth power switch tube is grounded, and the grid electrode of the fifth power switch tube is electrically connected with the output end of the fifth drive buffer; the positive power supply end of the fifth driving buffer is electrically connected with a fifth preset direct current power supply, and the negative power supply end of the fifth driving buffer is grounded.
5. The power circuit of claim 1, wherein the power circuit further comprises: an output capacitance;
the first end of the output capacitor is electrically connected with the power supply output end, and the second end of the output capacitor is grounded.
6. The power circuit of claim 1, wherein the voltage of the power bus is 12V or 24V.
7. A dc converter, comprising: a power circuit, a voltage sampling module and an output voltage control module, wherein the power circuit is the power circuit of any one of the claims 1-6;
The power supply output end of the power circuit is electrically connected with the input end of the voltage sampling module, the output end of the voltage sampling module is also electrically connected with the input end of the output voltage control module, and the output end of the output voltage control module is electrically connected with the control end of each switch unit in the power circuit.
8. The dc converter of claim 7, wherein the output voltage control module comprises: an error amplifier, a triangular wave signal generator, a comparator and a clock signal generator;
The output end of the voltage sampling module is electrically connected with the negative input end of the error amplifier, and the positive input end of the error amplifier is electrically connected with a preset reference power supply; the output end of the error amplifier is electrically connected with the positive input end of the comparator, the output end of the triangular wave signal generator is electrically connected with the negative input end of the comparator, the output end of the comparator is electrically connected with the input end of the clock signal generator, and the output end of the clock signal generator is electrically connected with the control end of each switch unit in the power circuit.
9. The dc converter of claim 7, wherein when the power circuit is in a first state, the first switch unit, the fourth switch unit, and the fifth switch unit are all in a closed state, and the second switch unit, the third switch unit, and the sixth switch unit are all in an open state;
when the power circuit is in a second state, the second switch unit, the third switch unit and the sixth switch unit are all in a closed state, and the first switch unit, the fourth switch unit and the fifth switch unit are all in an open state.
10. A power management system, comprising: a power bus, a dc converter as claimed in any one of claims 7 to 9; the power bus is electrically connected with the power input end of the direct current converter, and the power output end of the direct current converter is electrically connected with an electric load.
CN202211535943.5A 2022-12-01 2022-12-01 Power circuit, direct current converter and power management system Pending CN118137781A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211535943.5A CN118137781A (en) 2022-12-01 2022-12-01 Power circuit, direct current converter and power management system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211535943.5A CN118137781A (en) 2022-12-01 2022-12-01 Power circuit, direct current converter and power management system

Publications (1)

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CN118137781A true CN118137781A (en) 2024-06-04

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