CN111697820B

CN111697820B - Multi-output booster circuit

Info

Publication number: CN111697820B
Application number: CN201910193772.4A
Authority: CN
Inventors: 白文瑞
Original assignee: Shanghai Li Ke Semiconductor Technology Co ltd
Current assignee: Shanghai Li Ke Semiconductor Technology Co ltd
Priority date: 2019-03-14
Filing date: 2019-03-14
Publication date: 2021-12-03
Anticipated expiration: 2039-03-14
Also published as: CN111697820A

Abstract

The invention relates to a multi-output boosting circuit which comprises a plurality of voltage comparators, a duty ratio signal generator, a control logic circuit and an output circuit. The first input end of the voltage comparator inputs reference voltage, the second input end of the voltage comparator inputs feedback voltage, and the output end of the voltage comparator outputs comparison signals. The duty cycle signal generator generates a duty cycle signal. The control logic circuit inputs the comparison signal and the duty ratio signal and determines the form of the driving signal according to the comparison signal. The driving signal includes a charging signal and a plurality of freewheel signals, wherein the charging signal and the plurality of freewheel signals are generated according to the duty cycle signal. The output circuit includes an inductor, a charging switch, a plurality of freewheeling switches, and a plurality of capacitors. The inductor and the charging switch are connected between a power supply and a ground, each follow current switch is connected with the inductor and a corresponding capacitor, the charging switch inputs a charging signal, the follow current switch inputs a corresponding follow current signal, and the voltage on each capacitor is used as a feedback voltage.

Description

Multi-output booster circuit

Technical Field

The present invention relates to a boost circuit, and more particularly, to a multi-output boost circuit capable of outputting a plurality of voltages.

Background

In a system needing a plurality of paths of boosting power supplies, a single-inductor multi-output boosting structure is used, so that the number of inductor elements can be effectively reduced, and the system cost is reduced. But the control system inside the single-inductor multiple-output structure becomes more complicated while obtaining the benefit of saving the number of external components.

Fig. 1 is a schematic diagram of a multi-output boost circuit of the prior art. Referring to fig. 1, the error amplifier 101 and the error amplifier 102 perform error amplification on the multiplexed voltage feedback signals V1 and V2 and the reference voltage, respectively, to generate VC voltages VC1 and VC2, and are used for the voltage feedback loop. The inductor current sampling and slope compensation circuit 103 samples the information of the amplitude slope of the current of the inductor L during charging. Meanwhile, in order to meet the requirement of stability, the current amplitude slope information acquisition result is overlapped with a triangular wave with a fixed slope generated by a slope compensation circuit in the inductive current sampling and slope compensation circuit 103 to generate a sawtooth wave VRAMP carrying current amplitude and slope information. The voltage feedback loop frequency compensation circuit (acomp) 104 and the voltage feedback loop frequency compensation circuit (acomp) 105 use a large capacitance resistor to generate a low frequency zero pole for voltage feedback loop compensation, so as to improve the stability of the voltage feedback loop. The VC voltage in the voltage feedback loop and the sawtooth VRAMP in the current feedback loop are input to PWM comparator 106 and PWM comparator 107. The

PWM comparators

106 and 107 compare the outputs of the

error amplifiers

101 and 102 with the sawtooth wave VRAMP generated by the current sampling circuit to generate PWM trigger signals VPWM1 and VPWM 2. RS logic 108 generates an output switch drive signal with an appropriate duty cycle from the PWM signal. The freewheel switch control logic 109 controls the on and off of the freewheel switch according to the driving signal output by the RS logic 108. The anti-reverse-flow detection circuit 110 detects whether the inductor current is 0.

The process of voltage sampling and current sampling and generating PWM duty cycle information is also applicable to single-inductor single-output structures. Because the multiplexed output structure is to sample multiplexed output voltages, it is more complex than a single output structure.

In addition, the PWM trigger signal VPWM of the single-path output structure only needs to generate a signal with fixed duty ratio and period for controlling the single-path output charging and discharging through RS logic. The different multi-output structure requires the inductor current to be discharged to multiple paths. One way of charging and discharging is single-way follow current of single charging in each period, namely, only one way of output is followed current after the inductor charging in each period is completed, then the other way of output is followed current in the next period, and the follow current is carried out alternately in sequence. The method has good anti-crosstalk capability among the channels, but has poor reaction speed. Another charging and discharging mode is to supply multiple paths of follow current after the inductor is charged in each period, namely, all paths are sequentially opened in one follow current period. This approach has better response speed than the former approach, but has poor inter-path crosstalk prevention capability.

According to different control modes, the internal logics of the RS logic circuit 108 and the freewheel switch control logic circuit 109 are correspondingly different, and need to be selected and designed according to performance requirements.

When the load of the inductor current is small, the current of the freewheeling stage is reduced to 0, and at this time, the reverse-flow prevention detection circuit 110 needs to determine whether the inductor current is 0. If yes, the follow current tube is closed, and the charge backflow on the output capacitor is prevented to cause efficiency performance deterioration.

The above-described structure of the multi-output boost circuit of the prior art has the following disadvantages when applied to a low power consumption and low load system: 1. in order to take the stability of a voltage feedback loop and a current feedback loop into consideration, the circuit structure is complex, and the design difficulty is high; 2. the circuit modules are more, and a large compensation resistor and capacitor are needed, so that the chip area is occupied; 3. the loop structure is complex, and more functional module circuits are used, so that the circuit power consumption is higher, and the loop structure is not suitable for a low-power-consumption load system.

Disclosure of Invention

The invention aims to provide a multi-output booster circuit which has a simplified structure and lower power consumption.

The present invention provides a multi-output boost circuit, which solves the above technical problems, and comprises: the voltage comparator comprises a plurality of voltage comparators, wherein a first input end of each voltage comparator inputs reference voltage, a second input end of each voltage comparator inputs feedback voltage, and an output end of each voltage comparator outputs a comparison signal; a duty ratio signal generator generating a duty ratio signal; a control logic circuit for inputting the comparison signal and the duty ratio signal and determining the form of a driving signal according to the comparison signal, wherein the driving signal comprises a charging signal and a plurality of free-wheeling signals, and the charging signal and the plurality of free-wheeling signals are generated according to the duty ratio signal; and an output circuit including an inductor, a charging switch, a plurality of freewheel switches, and a plurality of capacitors, the inductor and the charging switch being connected between a power supply and ground, each freewheel switch connecting the inductor and a corresponding capacitor, the charging switch inputting the charging signal, the freewheel switch inputting a corresponding freewheel signal, a voltage on each capacitor being the feedback voltage.

In an embodiment of the present invention, the form of the charging signal includes charging and non-charging, in the charging form, the level of the charging signal varies according to a predetermined duty ratio; the form of the follow current signal comprises follow current and non-follow current, and the level of the follow current signal changes according to a preset duty ratio in the follow current form; wherein the freewheel signal of the freewheel configuration and the charge signal of the charge configuration are in anti-phase.

In an embodiment of the present invention, when any feedback voltage is lower than a reference voltage, the charging signal is in the charging state, and a freewheel signal corresponding to the feedback voltage is in the freewheel state.

In an embodiment of the present invention, the control logic circuit includes: the master control logic circuit inputs the comparison signal and the duty ratio signal and determines the form of a control signal according to the comparison signal, wherein the control signal is generated according to the duty ratio signal; and the follow current switch control logic circuit inputs the comparison signals and the control signals, determines the charging signals according to the control signals, and determines corresponding follow current signals according to the comparison signals and the control signals.

In an embodiment of the invention, the duty ratio signal generator further generates a clock synchronization signal, and the control logic circuit inputs the clock synchronization signal.

In an embodiment of the invention, at least one of the plurality of freewheel signals has a higher priority than the other freewheel signals.

In an embodiment of the present invention, the inductor further includes an anti-series flow switch connected between at least one freewheeling switch and the inductor, the anti-series flow switch inputs an anti-series flow signal of a control logic circuit, and the anti-series flow signal turns off the anti-series flow switch when the charging signal is in a charging state.

In an embodiment of the invention, the anti-series flow switch is an isolating switch with reverse substrate.

In an embodiment of the present invention, the duty ratio D of the duty ratio signal satisfies:

d ═ [ (V1+ V2+ … … + Vn-n VIN + L × (I1+ I2+ … … + In) ]/[ V1+ V2+ … … + Vn- (n-1) × VIN ], where V1, V2, …, Vn is a feedback voltage, I1, I2, …, In is an output current, VIN is a voltage of a power supply, L is an inductance of an inductor, and n is a positive integer.

In an embodiment of the present invention, the present invention further includes a reverse-filling prevention detection circuit, which is connected to the control logic circuit, and the reverse-filling prevention detection circuit provides a detection signal indicating whether the current of the inductor is zero.

Due to the adoption of the technical scheme, compared with the prior art, the invention has the following remarkable advantages:

1. the invention can complete the whole switch control only by collecting the output voltage signal and adopting the fixed duty ratio, has simple structure, is easy to design and realize, and saves the design cost and the circuit area cost;

2. the invention uses the master-slave mode during the follow current, and avoids the crosstalk of two or more paths of output voltage;

3. the anti-series flow switch design ensures normal follow current of high voltage and low voltage.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

fig. 1 is a schematic diagram of a multi-output boost circuit of the prior art.

Fig. 2 is a schematic structural diagram of a multi-output boost circuit according to an embodiment of the present invention.

Fig. 3 is a schematic structural diagram of a multi-output boost circuit according to another embodiment of the present invention.

Fig. 4 is a timing diagram of a multi-output boost circuit according to an embodiment of the invention.

Element numbering in the figures:

100: multi-output booster circuit

101. 102: error Amplifier (Error Amplifier, EA)

103: inductive current sampling and slope compensation circuit

104. 105: voltage feedback loop frequency compensation circuit

106. 107: pulse Width Modulation (PWM) comparator

108: Reset-Set (RS) logic circuit

109: follow current switch control logic circuit

110: anti-reverse-filling detection circuit

111: single-inductor multi-output structure power switch circuit

200: multi-output booster circuit

201. 202: voltage comparator

203: control logic circuit

203': master control logic circuit

204: duty ratio signal generator

205: follow current switch control logic circuit

206: anti-reverse-filling detection circuit

207: output circuit

300: multi-output booster circuit

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.

The following embodiments of the present invention describe a multi-output boost circuit. The multi-output booster circuit can be suitable for a light-load system, is simple in design structure, low in cost and free of occupying too much chip area. And, the circuit has lower power consumption due to the simple structure.

Fig. 2 is a schematic structural diagram of a multi-output boost circuit according to an embodiment of the present invention. The multi-output boost circuit 200 includes a plurality of voltage comparators (e.g., voltage comparator 201 and voltage comparator 202), a duty cycle signal generator 204, a control logic circuit 203, and an output circuit 207. Each voltage comparator has a first input terminal for inputting a reference voltage, a second input terminal for inputting a feedback voltage (e.g., feedback voltage V1 or feedback voltage V2), and an output terminal for outputting a comparison signal (e.g., comparison signal OVP1 and comparison signal OVP 2). The duty cycle signal generator 204 generates a duty cycle signal D. The duty ratio signal D may be a signal having a predetermined period and a predetermined duty ratio. In some embodiments, the period of the duty cycle signal D is fixed. In some embodiments, the period of the duty cycle signal D is adjustable. In some embodiments, the duty cycle of the duty cycle signal D is fixed. In some embodiments, the period of the duty cycle signal D is adjustable. The control logic circuit 203 receives the comparison signal and the duty ratio signal D, and determines the form of the driving signal according to the comparison signal. The drive signals include a charge signal DRV _ N and a plurality of freewheel signals (e.g., freewheel signal DRV _ P1 and freewheel signal DRV _ P2), and the charge signal DRV _ N and the plurality of freewheel signals are generated based on the duty cycle signal D. The output circuit 207 includes an inductor L, a charging switch NMOS, a plurality of freewheel switches (e.g., a freewheel switch PMOS1 and a freewheel switch PMOS2), and a plurality of capacitors (e.g., a capacitor C1 and a capacitor C2). The inductor L and the charging switch NMOS are connected between the power source VIN and the ground. It is understood that elements other than the inductor L and the charging switch NMOS may be connected in series between the power source VIN and the ground. Each freewheeling switch connects an inductor L and a corresponding capacitor. The charge switch NMOS inputs the charge signal DRV _ N. When the charge switch NMOS is turned on, the inductor L is charged by a current flowing from the power source VIN to the ground. The freewheeling switch inputs a corresponding freewheeling signal. When a certain freewheeling switch is turned on, the current flowing from the inductor L charges the corresponding capacitor through the freewheeling switch. The voltage across each capacitor is the output voltage (e.g., V1 and V2) as well as the feedback voltage described above. Although NMOS is used as an example of the charge switch and PMOS is used as an example of the freewheel switch in the present embodiment, it is understood that other devices known to those skilled in the art may be used for the charge switch and the freewheel switch. When the MOS tube is used, a driving signal is transmitted to the grid electrode of the MOS tube so as to enable the MOS tube to be switched on or switched off.

Fig. 4 is a timing diagram of a multi-output boost circuit according to an embodiment of the invention. The boost control process of the boost circuit with only two outputs will be described with reference to fig. 2 and 4.

The voltage comparator 201 has a first input terminal receiving the reference voltage, a second input terminal receiving the feedback voltage V1, and an output terminal outputting the comparison signal OVP 1. The voltage comparator 202 has a first input terminal for inputting the reference voltage, a second input terminal for inputting the feedback voltage V2, and an output terminal for outputting the comparison signal OVP 2.

The comparison signal OVP1, the comparison signal OVP2 and the duty ratio signal D generated by the duty ratio signal generator 204 are input to the control logic circuit 203 in common. The control logic 203 determines the form of the driving signal according to the comparison signal OVP1 and the comparison signal OVP 2. The driving signals generated according to the duty ratio signal D include a charging signal DRV _ N and a freewheel signal DRV _ P1, a freewheel signal DRV _ P2. In an embodiment of the present invention, the duty ratio signal generator 204 further generates a clock synchronization signal SCLK, which is input to the control logic circuit 203.

The output circuit 207 includes an inductor L, a charging switch NMOS, a freewheeling switch PMOS1 and a freewheeling switch PMOS2, and a capacitor C1 and a capacitor C2. The inductor L and the charging switch NMOS are connected between the power source VIN and the ground, the freewheel switch PMOS1 connects the inductor L and the capacitor C1, and the freewheel switch PMOS2 connects the inductor L and the capacitor C2. The charge switch NMOS inputs the charge signal DRV _ N. The freewheel switch PMOS1 inputs the freewheel signal DRV _ P1, and the freewheel switch PMOS2 inputs the freewheel signal DRV _ P2. The voltage V1 across the capacitor C1 is the feedback voltage V1, and the voltage V2 across the capacitor C2 is the feedback voltage V2.

In an embodiment of the present invention, the charging signal DRV _ N has a form including charging and non-charging, and in the charging form, the level of the charging signal DRV _ N varies according to a predetermined duty ratio. The forms of the freewheel signals (e.g., the freewheel signal DRV _ P1 and the freewheel signal DRV _ P2 in fig. 2) include freewheel and no freewheel, and in the freewheel form, the level of the freewheel signal changes at a predetermined duty cycle. The freewheel signal in the freewheel state and the charge signal DRV _ N in the charge state are inverted.

In an embodiment of the invention, when any one of the feedback voltages (e.g., the feedback voltage V1 or the feedback voltage V2) is lower than the reference voltage, the charging signal DRV _ N is in a charging state, and the freewheel signal corresponding to any one of the feedback voltages (e.g., the freewheel signal DRV _ P1 or the freewheel signal DRV _ P2) is in a freewheel state. The reference voltage is the desired output voltage value.

In one example, the comparison signal OVP1 is a logical value "0" when the feedback voltage V1 is lower than the reference voltage, and is "1" otherwise. Similarly, the comparison signal OVP2 is logic value "0" when the feedback voltage V2 is lower than the reference voltage, and is "1" otherwise.

Whether the inductor L of the output circuit 207 needs to be charged is determined according to a state whether the logic values of the comparison signal OVP1 and the comparison signal OVP2 are "0". If it is determined that the inductor L needs to be charged, the logic value of the charging signal DRV _ N generated by the control logic circuit 203 according to the duty signal D is "1". If it is determined that the inductor L does not need to be charged, the control logic circuit 203 generates a charge signal DRV _ N having a logic value of "0" according to the duty signal D. Since the charge switch NMOS is controlled by the charge signal DRV _ N, the charge switch NMOS is turned on when the logic value of the charge signal DRV _ N is "1", and the charge switch NMOS is turned off when the logic value of the charge signal DRV _ N is "0".

Similarly, when the logic value of the freewheel signal DRV _ P1 is "1", the freewheel switch PMOS1 is opened, the inductor L freewheels to the feedback voltage V1, and when the logic value of the freewheel signal DRV _ P1 is "0", the freewheel switch PMOS1 is closed. When the logic value of the freewheel signal DRV _ P2 is "1", the freewheel switch PMOS2 is turned on, the inductor L freewheels to the feedback voltage V2, and when the logic value of the freewheel signal DRV _ P2 is "0", the freewheel switch PMOS2 is turned off.

For example, in the boost control process of the boost circuit shown in fig. 2, a master-slave control mode is adopted, and the priority of the freewheel signal DRV _ P1 is higher than that of the freewheel signal DRV _ P2, so that the crosstalk of the two-way output can be effectively avoided.

When both the feedback voltage V1 and the feedback voltage V2 need to freewheel, the feedback voltage V1 is preferentially freewheeled. When the logic value of the comparison signal OVP1 is "0", it is indicated that the voltage of the feedback voltage V1 is lower than the reference voltage, the inductor L needs to be charged, the logic value of the freewheel signal DRV _ P1 is "1", and the freewheel switch PMOS1 opens to freewheel the feedback voltage V1 in the freewheel phase. When the feedback voltage V1 reaches the reference voltage and the logic value of the comparison signal OVP1 is "1", it is determined whether the feedback voltage V2 needs to freewheel. If the logic value of the comparison signal OVP2 is "0", which indicates that the voltage of the feedback voltage V2 is lower than the reference voltage, the inductor L needs to be charged, the logic value of the freewheel signal DRV _ P2 is "1", and the freewheel switch PMOS2 opens to freewheel the feedback voltage V2 in the freewheel phase. The above process is ended until the logic values of the comparison signal OVP1 and the comparison signal OVP2 are both "1".

When the number of output voltages exceeds 2, more priority may be set. In some embodiments, the priority is consistent with the number of output voltages. The output voltages of each path determine the free-wheeling sequence according to the set priority.

In an embodiment of the invention, the multi-output boost circuit 200 further includes an anti-series flow switch RCSW. The anti-series flow switch RCSW is connected between at least one freewheeling switch and the inductor L, and the anti-series flow switch RCSW inputs an anti-series flow signal RCSW of the control logic circuit 203, and turns off the anti-series flow switch RCSW when the charging signal DRV _ N is in a charging state. In one preferred embodiment of the present invention, the anti-series flow switch RCSW is a substrate-reversed isolation switch.

In an embodiment of the present invention, the duty ratio signal D generated by the duty ratio signal generator 204 of the multi-output boost circuit 200 satisfies the following relationship:

D＝[(V1+V2+……+Vn-n*VIN+L*(I1+I2+……+In)]/[V1+V2+……+Vn-(n-1)*VIN]

where V1, V2, …, Vn is the feedback voltage, I1, I2, …, In is the output current, VIN is the voltage of the power supply, L is the inductance of the inductor (as shown In fig. 2), and n is a positive integer.

For example, in the configuration of the boost circuit with only two outputs shown in fig. 2, the duty ratio signal D satisfies the following relationship:

D＝[(V1+V2-2*VIN+L*(I1+I2)]/(V1+V2-VIN)

where V1, V2 are feedback voltages, I1, I2 are output currents, VIN is the voltage of the power supply, and L is the inductance of the inductor.

In an embodiment of the invention, the multi-output boost circuit 200 further includes a reverse-flow prevention detection circuit 206. The reverse-flow prevention detection circuit 206 is connected to the control logic circuit 203, and the reverse-flow prevention detection circuit 206 provides a detection signal RCP indicating whether the current of the inductor L is zero.

For example, when the current of the inductor L is found to be zero, the logic value of the detection signal RCP signal is "0", the detection signal RCP sets the logic values of the freewheel signal DRV _ P1 and the freewheel signal DRV _ P2 to "0" through the control logic circuit 203, and the entire freewheel process is ended.

Unlike the conventional structure in which the detection signal RCP is used only for preventing the reverse flow of the inductor current, the detection signal RCP in the structure of the multi-output boost circuit 200 of the present invention is an important participant of the control logic circuit 203, and after each charge and discharge is completed (the feedback voltage reaches the reference voltage), each freewheeling switch must be turned off until the logic value of the detection signal RCP is "0", that is, the energy of the inductor L must be completely released.

Fig. 3 is a schematic structural diagram of a multi-output boost circuit according to another embodiment of the present invention. Referring to fig. 3, in another embodiment of the present invention, the control logic 203 may include a master control logic 203' and a freewheel switch control logic 205. The master logic circuit 203' inputs the comparison signal (e.g., the comparison signal OVP1 and the comparison signal OVP2) and the duty ratio signal D, and determines the form of the control signal DRV _ RST according to the comparison signal. The control signal DRV _ RST is generated according to the duty ratio signal D. When the comparison signal OVP1 and the comparison signal OVP2 are both logic 1, the control signal DRV _ RST is kept at a low level; when the comparison signal OVP1 or the comparison signal OVP2 is logic 0, the control signal DRV _ RST varies with the duty ratio signal D. The freewheel switch control logic circuit 205 inputs the comparison signal and the control signal DRV _ RST. The freewheel switch control logic circuit 205 determines the charge signal DRV _ N based on the control signal DRV _ RST and determines the corresponding freewheel signals (e.g., freewheel signal DRV _ P1 and freewheel signal DRV _ P2) based on the respective comparison signals and the control signal DRV _ RST. The waveform of the charging signal DRV _ N may be similar to the waveform of the control signal DRV _ RST. When a certain comparison signal is logic 0, the waveform of the corresponding free-wheeling signal is similar to that of the control signal DRV _ RST, otherwise, the corresponding free-wheeling signal is in low level.

The boost control process of the boost circuit with only two outputs will be described with reference to fig. 3 and 4.

The comparison signal OVP1, the comparison signal OVP2 and the duty ratio signal D generated by the duty ratio signal generator 204 are input to the main control logic circuit 203'. The master logic 203' determines the type of the control signal DRV _ RST according to the comparison signal OVP1 and the comparison signal OVP 2. The control signal DRV _ RST is generated according to the duty signal D, similar to the waveform of an NMOS. The freewheel switch control logic circuit 205 inputs the comparison signal OVP1, the comparison signal OVP2, and the control signal DRV _ RST. The freewheel switch control logic circuit 205 determines the charge signal DRV _ N according to the control signal DRV _ RST, determines the freewheel signal DRV _ P1 according to the comparison signal OVP1 and the control signal DRV _ RST, and determines the freewheel signal DRV _ P2 according to the comparison signal OVP2 and the control signal DRV _ RST.

The master logic circuit 203' determines the logic value of the control signal DRV _ RST according to whether the logic values of the comparison signal OVP1 and the comparison signal OVP2 are "0". When at least one of the logic values of the comparison signal OVP1 and the comparison signal OVP2 is "0", the logic value of the control signal DRV _ RST is "1", and when both the logic values of the comparison signal OVP1 and the comparison signal OVP2 are "1", the logic value of the control signal DRV _ RST is "0".

The freewheel switch control logic circuit 205 inputs the comparison signal OVP1, the comparison signal OVP2, and the control signal DRV _ RST. The freewheel switch control logic 205 determines the charging signal DRV _ N according to the control signal DRV _ RST to determine whether the inductor L of the output circuit 207 needs to be charged. When the logic value of the control signal DRV _ RST is "1", the logic value of the charge signal DRV _ N generated by the freewheel switch control logic circuit 205 is "1", and conversely is "0".

The freewheel switch control logic circuit 205 determines the freewheel signal DRV _ P1 based on the comparison signal OVP1 and the control signal DRV _ RST, and determines the freewheel signal DRV _ P2 based on the comparison signal OVP2 and the control signal DRV _ RST.

The logic value of the charging signal DRV _ N generated by the freewheel switch control logic 205 is "1" if it is determined that the inductor L needs to be charged. The logic value of the charging signal DRV _ N generated by the freewheel switch control logic circuit 205 is "0" if it is determined that charging of the inductor L is not required. Since the charge switch NMOS is controlled by the charge signal DRV _ N, the charge switch NMOS is turned on when the logic value of the charge signal DRV _ N is "1", and the charge switch NMOS is turned off when the logic value of the charge signal DRV _ N is "0".

It is understood that the logical values are merely examples, and the logical values may take opposite values.

The invention provides a multi-output booster circuit. The multi-output booster circuit can complete the whole switch control only by collecting feedback voltage information and a preset duty ratio. The invention uses a master-slave control mode to avoid crosstalk of multiple output voltages. And the invention adopts the design of the series flow prevention switch to ensure the normal follow current of high and low voltages. The multi-output booster circuit is suitable for a light-load low-power-consumption system, and has the advantages of simple design structure, low cost and no occupation of excessive chip area.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims

1. A multi-output boost circuit comprising:

the voltage comparator comprises a plurality of voltage comparators, wherein a first input end of each voltage comparator inputs reference voltage, a second input end of each voltage comparator inputs feedback voltage, and an output end of each voltage comparator outputs a comparison signal;

a duty cycle signal generator generating a duty cycle signal, wherein a duty cycle D of the duty cycle signal satisfies:

D＝[(V1+V2+……+Vn-n*VIN+L*(I1+I2+……+In)]/[V1+V2+……+Vn-(n-1)*VIN]，

wherein V1, V2, …, Vn is the feedback voltage, I1, I2, …, In is the output current, VIN is the voltage of the power supply, L is the inductance of the inductor, n is a positive integer;

a control logic circuit for inputting the comparison signal and the duty ratio signal and determining the form of a driving signal according to the comparison signal, wherein the driving signal comprises a charging signal and a plurality of free-wheeling signals, and the charging signal and the plurality of free-wheeling signals are generated according to the duty ratio signal; and

an output circuit comprising an inductor, a charging switch, a plurality of freewheeling switches and a plurality of capacitors, the inductor and the charging switch being connected between a power supply and ground, each freewheeling switch connecting the inductor and a corresponding capacitor, the charging switch inputting the charging signal, the freewheeling switches inputting a corresponding freewheeling signal, the voltage on each capacitor being the feedback voltage.

2. The multi-output boost circuit of claim 1,

the charging signal forms include a charging form and a non-charging form, and in the charging form, the level of the charging signal changes according to a preset duty ratio;

the form of the follow current signal comprises a follow current form and a non-follow current form, and the level of the follow current signal changes according to a preset duty ratio in the follow current form;

wherein the freewheel signal in the freewheel configuration and the charge signal in the charge configuration are in anti-phase.

3. A multi-output boost circuit according to claim 2, in which when any feedback voltage is lower than a reference voltage, the charge signal is in the charge configuration and a freewheel signal corresponding to said any feedback voltage is in the freewheel configuration.

4. The multi-output boost circuit of claim 1, wherein the control logic circuit comprises:

the master control logic circuit inputs the comparison signal and the duty ratio signal and determines the form of a control signal according to the comparison signal, wherein the control signal is generated according to the duty ratio signal;

and the follow current switch control logic circuit inputs the comparison signals and the control signals, determines the charging signals according to the control signals, and determines corresponding follow current signals according to the comparison signals and the control signals.

5. The multi-output boost circuit of claim 1, wherein the duty cycle signal generator further generates a clock synchronization signal, the control logic circuit inputting the clock synchronization signal.

6. The multi-output boost circuit of claim 1, wherein at least one of the plurality of freewheel signals has a higher priority than the other freewheel signals.

7. The multi-output boost circuit of claim 2, further comprising an anti-series flow switch connected between at least one freewheeling switch and the inductor, the anti-series flow switch inputting an anti-series flow signal of a control logic circuit, the anti-series flow signal causing the anti-series flow switch to be turned off when the charging signal is in a charging state.

8. The multi-output boost circuit of claim 7, wherein the anti-series flow switch is a substrate-reversal isolation switch.

9. The multi-output boost circuit of claim 1, further comprising a back-sink prevention detection circuit connected to the control logic circuit, the back-sink prevention detection circuit providing a detection signal indicating whether the current of the inductor is zero.