CN118136510A - Preparation method of trench type power device with shielding gate - Google Patents

Abstract

The invention provides a preparation method of a trench type power device with a shielding gate, which comprises the following steps: providing a substrate, and forming a first doping type epitaxial layer on the substrate; forming a gate trench in the cell region and a terminal trench in the terminal region by extending from the surface of the epitaxial layer to the inside; forming a field oxide layer and first polysilicon in the gate trench and the terminal trench in sequence, wherein the first polysilicon fills the gate trench and the terminal trench respectively; forming a hard mask layer on the epitaxial layer, patterning the hard mask layer to expose the surface of the epitaxial layer in the cell region, wherein the thickness of the hard mask layer is larger than that of the epitaxial layerSelectively removing the field oxide layer and the first polysilicon which are positioned at the upper part of the gate trench by taking the patterned hard mask layer as a mask, and forming the first polysilicon which is reserved in the gate trench into a shielding gate electrode; forming a control gate structure at the upper part of the gate trench; and performing ion implantation of the second doping type by utilizing a window defined by the patterned hard mask layer to form a body region.

Description

Preparation method of trench type power device with shielding gate

Technical Field

The invention belongs to the field of semiconductors, and particularly relates to a preparation method of a trench type power device with a shielding gate.

Background

A trench type power device (SHIELDING GATE TRENCH MOSFET) with a shielding gate is used as an advanced power MOSFET device technology, the shielding gate electrode is introduced to reduce the overlapping area of the gate and the drain of the device, so that the gate-drain capacitance is reduced, the purposes of improving the switching speed and reducing the dynamic loss of the device are achieved, and the use efficiency of a system is improved.

In consideration of device performance, the terminal design of the deep trench device adopts a deep trench structure as a base to combine with a field plate structure to improve the breakdown voltage of the terminal region, so as to realize the protection effect on the active region. Referring to fig. 1, a typical cross-sectional view of an SGT-MOSFET device cell region transitioning to a termination region is shown. As shown in fig. 1, a shielding Gate structure with an upper-lower structure is arranged in a trench of a cellular region, polysilicon at an upper layer is used as a control Gate electrode (Gate Poly, labeled as "G"), polysilicon at a lower layer is used as a shielding Gate electrode (Source Poly, labeled as "S"), and the shielding Gate electrode S is short-circuited with a Source; in the termination region indicated by the dashed box in fig. 1, the trench is filled with only the polysilicon field plate and the field oxide layer interposed between the polysilicon field plate and the epitaxial layer. In the conventional process flow of the SGT-MOSFET device, the etching definition of the shielding gate polysilicon electrode in the trench of the cell area is achieved by means of a photoetching process executed by a photomask, namely, the shielding gate polysilicon of the cell area is etched to a certain height, and the polysilicon field plate of the trench of the terminal area is protected from etching by photoresist; in addition, the field oxide layer on the side wall of the control gate region trench needs to be removed by introducing a photolithography process. Therefore, SGT-MOSFET devices are relatively expensive, and it is necessary to provide a manufacturing process that reduces the number of photolithography steps, thereby saving process costs.

It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a trench power device with a shield gate, which is used for solving the problem of high process cost of the trench power device with the shield gate in the prior art.

To achieve the above and other related objects, the present invention provides a method for manufacturing a trench type power device with a shield gate, including:

providing a substrate, forming a first doping type epitaxial layer on the substrate, wherein the epitaxial layer comprises a cell region and a terminal region positioned at the periphery of the cell region;

Forming a gate trench in the cell region and a terminal trench in the terminal region by extending from the surface of the epitaxial layer to the inside;

forming a field oxide layer and first polysilicon in the gate trench and the terminal trench in sequence, wherein the first polysilicon fills the gate trench and the terminal trench respectively;

forming a hard mask layer on the epitaxial layer, patterning the hard mask layer to expose the surface of the epitaxial layer in the cell region, wherein the thickness of the hard mask layer is larger than that of the epitaxial layer

Selectively removing the field oxide layer and the first polysilicon which are positioned at the upper part of the gate trench by taking the patterned hard mask layer as a mask, and forming the first polysilicon which is reserved in the gate trench into a shielding gate electrode;

forming a control gate structure at the upper part of the gate trench;

Performing ion implantation of a second doping type by utilizing a window defined by the patterned hard mask layer to form a body region;

And forming a first doping type source region extending from the surface to the inside of the body region at the side part of the gate trench.

Optionally, the step of selectively removing the first polysilicon includes; etching the first polysilicon back by taking the patterned hard mask layer as a mask, so that the first polysilicon remained in the gate trench has a set depth from the top surface of the epitaxial layer; and/or the number of the groups of groups,

A step of selectively removing the field oxide layer, comprising: and selectively removing the field oxide layer covered on the side wall of the upper part of the gate trench by using the patterned hard mask layer as a mask through a wet etching process, wherein the top surface of the field oxide layer obtained by etching is slightly lower than the top surface of the first polysilicon obtained by etching.

Optionally, the step of forming the patterned hard mask layer includes: forming a hard mask layer covering the surface of the epitaxial layer, wherein the hard mask layer comprises one of a lamination layer formed by silicon nitride layer, silicon nitride and silicon oxide; defining an etching window through a photoetching process to expose the hard mask layer positioned on the cellular region; and etching the hard mask layer by using the photoresist layer covered on the terminal area as a mask.

Optionally, a silicon nitride hard mask layer is formed by covering the surface of the epitaxial layer by chemical vapor deposition process, wherein the thickness of the silicon nitride hard mask layer is as followsThe above.

Optionally, before the step of forming the hard mask layer, the method includes: oxidizing the exposed first polysilicon by a thermal oxidation process to form a buffer layer, wherein the thickness of the buffer layer is

Optionally, the step of forming the control gate structure includes: growing a gate oxide layer on the upper side wall of the gate trench, and growing an inter-polysilicon oxide layer on the exposed first polysilicon; and forming second polysilicon which is coated on the first polysilicon and fills the gate trench.

Optionally, after the step of forming the second polysilicon, the method includes: removing the second polysilicon on the upper surface of the gate oxide layer; and/or performing a thermal annealing process to form a masking oxide layer on the exposed surfaces of the second polysilicon and the epitaxial layer.

Optionally, the step of forming the body region includes: and carrying out ion implantation by using a window defined by the patterned hard mask layer, and then forming the body region by pushing the well through a thermal annealing process.

Optionally, after the step of forming the source region, the method includes:

forming an interlayer dielectric layer covering the epitaxial layer;

forming a contact hole in the interlayer dielectric layer;

And covering the interlayer dielectric layer to form a front metal layer.

Optionally, the step of forming the front side metal layer includes separating the front side metal layer into a source metal layer and a gate metal layer, wherein the contact hole includes a source contact hole located above the source region, and the source metal layer is in contact with the source region through the source contact hole.

As described above, in the method for manufacturing a trench type power device with a shield gate of the present invention, after the field oxide layer and the first polysilicon are formed, the hard mask layer covering the epitaxial layer is formed and patterned, and the patterned hard mask layer remaining in the termination region is used to sequentially serve as a mask to achieve partial removal of the first polysilicon and the field oxide layer and to achieve ion implantation in the body region, two to three photolithography steps can be saved compared with the conventional device structure and the conventional process thereof, and the manufacturing cost can be effectively reduced on the premise of ensuring the electrical performance of the power device.

Drawings

Fig. 1 is a schematic diagram showing the structure of a trench MOSFET device with a shield gate according to a comparative example of the present invention.

Fig. 2 a-2 c are schematic diagrams showing the structures obtained in various stages of fabricating a trench MOSFET device with a shield gate in accordance with a comparative example of the present invention.

Fig. 3 is a process flow diagram of a method of fabricating a trench MOSFET device with a shield gate in accordance with an embodiment of the present invention.

Fig. 4 a-4 k are schematic diagrams showing the structures obtained at various stages in the fabrication of a trench MOSFET device with a shield gate in accordance with an embodiment of the present invention.

Description of element reference numerals

20. Epitaxial layer

21C gate trench

21G terminal trench

210. Field oxide layer

212. Buffer layer

31. 31A, 31b photoresist layer

220. First polysilicon of

230. Gate oxide layer

240. Second polysilicon

32. Patterned hard mask layer

23. Body region

24. Source region

30. Interlayer dielectric layer

310. Contact hole

40. Source electrode metal layer

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.

In the context of the present application, unless otherwise specified and defined, the structural terminology "above" a first feature described is to be understood in a broad sense, and may include, for example, embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Fig. 2 a-2 c are schematic views showing the structure of a trench power device with a shield gate according to a comparative example of the present invention at various stages.

Referring to fig. 2a, which shows a schematic structure obtained after sequentially forming a field oxide layer and a first polysilicon in a gate trench and a termination trench, gate trench 21c and termination trench 21g are respectively formed to extend inward from the surface of epitaxial layer 20, and first polysilicon 220 fills gate trench 21c and termination trench 21g, respectively;

referring to fig. 2b, a schematic diagram of the structure after etching back the first polysilicon is shown. As shown in fig. 2 a-2 b, the etching back step is performed herein, in which the cell region is defined by a photolithography process by means of a photomask, and the photoresist layer 31a overlying the terminal region is used to etch back the first polysilicon in the cell region, i.e. the first polysilicon in the cell region is etched to a certain height, and the polysilicon field plate in the terminal trench 21g of the terminal region is not etched due to the protection of the photoresist;

Referring to fig. 2c, a schematic structure is shown after selective removal of the field oxide layer at the upper part of the gate trench. The selective removal step performed here also requires a photolithography process to etch the field oxide layer in the cell region with photoresist layer 31b overlying the termination region.

In addition, after the process of forming the control gate structure, body implantation of the device is conventionally performed in a common injection manner, but in order to achieve design requirements of the device in terms of short circuit capability or other electrical properties, it is necessary to perform a photolithography process to define the extent of the body implantation, and the extent of the boundary defined by the photolithography process is substantially identical to the boundary defined by the photoresist layer shown in fig. 2b and 2 c.

In view of the above, the inventor of the present application improves the method for manufacturing a trench-type power device with a shield gate, and reduces the three photolithography processes before and after manufacturing the shield gate structure to one photolithography, thereby realizing the design requirements of the device on short circuit capability or other electrical properties, improving the breakdown voltage of the device, and greatly reducing the production cost of the chip.

Please refer to fig. 3-4 a-4 k. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

The term "semiconductor" used herein is a technical term commonly used by those skilled in the art, for example, for P-type and N-type impurities, p+ type represents P type with heavy doping concentration, P type with medium doping concentration, P-type represents P type with light doping concentration, n+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents N type with light doping concentration.

The invention provides a preparation method of a trench type power device with a shielding gate, wherein the trench type power device with the shielding gate can be an N type device or a P type device, and a person skilled in the art can directly and unambiguously understand that the P type device can be obtained by correspondingly exchanging the doping type in the N type device. The preparation method of the trench type power device with the shielding gate is suitable for manufacturing a trench type MOSFET device with the shielding gate, an IGBT device with the shielding gate or similar structures integrated with other elements.

Hereinafter, a method for manufacturing a trench type power device with a shield gate in an embodiment of the present invention will be specifically described with reference to fig. 3 and fig. 4a to 4k, taking a trench type MOSFET device with a shield gate as an example, where one of the first doping type and the second doping type is N type, and the other is P type. In this embodiment, the first doping type is N-type, and the second doping type is P-type, that is, a trench MOSFET device with a shield gate is taken as an example for describing an N-type device.

It should be noted that the above sequence does not strictly represent the preparation sequence of the method for manufacturing the trench MOSFET device with the shield gate, which is protected by the present invention, and those skilled in the art can vary according to actual process steps.

First, step S1 is performed to provide a substrate (not shown) and form a first doping type epitaxial layer 20 on the substrate.

As an example, the substrate may be made of silicon, silicon germanium, silicon carbide, or other suitable substrate materials, and the epitaxial layer 20 may be made of the same material as the substrate, or may be made of a different material. Preferably, the substrate is an n+ type silicon substrate, and the epitaxial layer 11 is an N-type silicon epitaxial layer. As shown in fig. 4a, the epitaxial layer 20 includes a cell region and a termination region located at the periphery of the cell region.

Then, step S2 is performed, see fig. 4a, of forming a gate trench 21c located in the cell region and a termination trench 21g located in the termination region extending from the surface of the epitaxial layer to the inside.

Specifically, the gate trench 21c and the termination trench 21g may be formed simultaneously by: forming a hard mask layer (not shown), such as a silicon dioxide-silicon nitride-silicon dioxide (ONO) stack, on the surface of the epitaxial layer 20; forming a patterned hard mask layer through a photoetching process and an etching process; etching is performed based on the patterned hard mask layer to form a plurality of trenches in the epitaxial layer 20, wherein the trenches located in the cell region serve as gate trenches 21c forming a shield gate structure, and the trenches located in the termination region serve as termination trenches 21g. No undue limitations are made herein with respect to the distribution, size, and morphology of the trenches.

It should be noted that although the gate trenches and the termination trenches shown in fig. 4a are illustrated as examples, the trench profile well known to those skilled in the art may also include, but not limited to, U-shape, quadrilateral shape, or the like.

Then, step S3 is performed, referring to fig. 4b, a field oxide layer 210 and a first polysilicon 220 are sequentially formed in the gate trench 21c and the termination trench 21 g. As shown in fig. 4b, the gate trench 21c and the termination trench 21g are filled with a first polysilicon 220.

At step S3, comprising: forming a field oxide layer 210 in the gate trench 21c and the termination trench 21g by a thermal oxidation method and/or a Chemical Vapor Deposition (CVD) process; first polysilicon is deposited in the gate trench 21c and the termination trench 21g until the deposited first polysilicon completely fills the gate trench 21c and the termination trench 21g. In a specific example, the field oxide layer 210 is formed by: a compact oxide film can be formed by a thermal oxidation method, and then a CVD process is adopted to deposit an oxide film, such as a high density plasma chemical vapor deposition (HDP CVD) process or a sub-atmospheric chemical vapor deposition (SACVD) process, so that good pore-filling characteristics can be ensured.

By way of example, methods of forming the first polysilicon 220 include, but are not limited to, chemical vapor deposition, physical vapor deposition, or other suitable method processes.

Then, step S4 is performed, see fig. 4c to 4e, to form a hard mask layer overlying the epitaxial layer 20, and patterning the hard mask layer to expose the top surface of the epitaxial layer in the cell region.

As an example, the hard mask layer may be made of a common material having an etching selectivity with respect to the silicon material, including but not limited to a stack of silicon nitride, silicon nitride and silicon oxide or the like, and has a sufficient thickness to serve as an etching mask for the first polysilicon and the field oxide layer in the cell region C; preferably, the hard mask layer has a thickness ofAbove is, for example/>In a specific example, the hard mask layer has a sufficient thickness to ensure that the hard mask layer can be used to define an implantation window of a subsequent body region after undergoing a patterning process, a back-etching process of polysilicon, and a wet etching process of a field oxide layer, without requiring an additional process or material layer for defining the implantation window; preferably, the hard mask layer is selected from silicon nitride hard mask layers having a thickness of at least/>The blocking effect on the high-energy particle injection is achieved.

As shown in fig. 4c, the step of forming the hard mask layer is preceded by covering the epitaxial layer and the first polysilicon growth buffer layer 212 by, for example, a thermal oxidation process. In one specific example, a buffer layer is formed on the silicon epitaxial layer prior to depositing the silicon nitride, the buffer layer acting to buffer the isolation silicon material from subsequently deposited silicon nitride, thereby reducing stress. Preferably, the thickness of the buffer layer 212 is

As shown in fig. 4d to 4e, the step of patterning the hard mask layer includes: defining an etching window through a photoetching process to expose the hard mask layer positioned on the cellular region; and etching the hard mask layer by using the photoresist layer covered on the terminal area as a mask.

Then, step S5 is performed, referring to fig. 4f to 4h, using the patterned hard mask layer 32 as a mask, to selectively remove the field oxide layer and the first polysilicon at the upper portion of the gate trench, and the first polysilicon remaining in the gate trench is used as a shielding gate electrode.

As an example, as shown in fig. 4g, the patterned hard mask layer is used as an etching mask, and the first polysilicon is etched back by a dry etching process, and since the terminal area is covered with the patterned hard mask layer, only the first polysilicon in the cell area is partially removed, and the first polysilicon remaining in the gate trench has a set depth from the top surface of the epitaxial layer 20. In a specific example, as shown in fig. 4f, before the step of etching back the first polysilicon 220, it includes: and removing the oxide layer on the upper surface of the epitaxial layer by taking the patterned hard mask layer as a mask and adopting a grinding or etching mode to expose the first polysilicon. In the example where the buffer layer is formed, the oxide layer mentioned here includes the buffer layer and a part of the field oxide layer.

Further, as shown in fig. 4h, the patterned hard mask layer is used as a mask, and an etchant with etching selectivity relative to the substrate material is used to remove the field oxide layer on the upper side wall of the trench through a wet etching process. For example, the wet etching process is performed by using a BOE etching solution, the field oxide layer on the upper side wall of the groove is removed, and the top surface of the etched field oxide layer is lower than the top surface of the etched first polysilicon.

Then, step S6 is performed, see fig. 4i, to form a control gate structure.

Specifically, the step of forming the control gate structure includes: a gate oxide layer 230 is grown on the upper sidewall of the gate trench, and an inter-polysilicon oxide layer (not shown) is grown on the exposed first polysilicon, the first polysilicon remaining in the gate trench serving as a shield gate electrode; and forming second polysilicon which is coated on the first polysilicon and fills the gate trench and is used as a control gate electrode, wherein the inter-polysilicon oxide layer is used for shielding isolation between the gate electrode and the control gate electrode.

As an example, the gate oxide layer 230 is formed on the upper sidewall of the gate trench by a thermal oxidation process and/or a chemical vapor deposition process, and an inter-polysilicon oxide layer is formed on the exposed first polysilicon.

As shown in fig. 4i, when the gate electrode is a polysilicon electrode, the gate trench 21c may be filled with a second polysilicon 240, the second polysilicon 240 serving as a control gate electrode, wherein the method of forming the second polysilicon includes, but is not limited to, chemical vapor deposition, physical vapor deposition, or other suitable method process.

Further, after the step of forming the second polysilicon 240, it includes: and performing a thermal annealing process for repairing the etching damage, and forming a masking oxide layer (not shown) on the exposed surfaces of the second polysilicon and the epitaxial layer. In a specific example, the second polysilicon 240 is further formed on the upper surface of the gate oxide layer on the epitaxial layer 20, and the step of forming the masking oxide layer is preceded by removing the second polysilicon 240 on the upper surface of the gate oxide layer, where the method of removing the second polysilicon includes chemical mechanical polishing, dry etching, wet etching, or other suitable method.

Then, step S7 is performed, see fig. 4j, to perform ion implantation of the second doping type using the window defined by the patterned hard mask layer 32, thereby forming the body region 23.

By way of example, the method of forming the body region 23 includes ion implantation using a window defined by a patterned hard mask layer remaining in the termination region, the ion implantation being performed, followed by a thermal annealing process to push the well to form a body region of the second doping type. In a specific example, a buffer layer is formed between the first polysilicon layer and the hard mask layer, so that damage caused by the ion implantation process can be reduced. Compared with the conventional common injection mode, the body region injection is carried out, the range of the body region injection is limited by forming the mask pattern, the short circuit capability and other electrical properties of the device can be considered, and the three photoetching processes required for forming the shielding gate structure to the body region 23 in the original manufacturing process are reduced to one photoetching process by utilizing the window limited by the patterned hard mask layer reserved in the terminal region through the process flow, so that the production cost of the chip is greatly reduced.

In this embodiment, the ion implantation described in step S7 is performed by using, for example, boron ions (Boron) as dopants, and the P-type body region is formed by a thermal annealing process.

Then, step S8 is performed to form a source region 24 extending from the surface of the body region to the inside at the trench side of the cell region.

Prior to the step of forming source regions 24, it includes: removing the patterned hard mask layer and a part of the oxide layer which are covered on the terminal area; defining an implantation mask pattern corresponding to the window for source region implantation by a photoetching process, performing ion implantation by using the window defined in the implantation mask pattern to form an implantation region heavily doped with the first doping type, and then forming a source region by pushing a well by a thermal annealing process. The oxide layer referred to herein includes a portion of the buffer layer and the masking oxide layer.

As an example, the ion implantation described in step S8 is performed using, for example, phosphorus ions (Phosphorus) as dopants.

Prior to the step of forming source regions 24, it includes: the oxide layer on the upper surface of the epitaxial layer is planarized using, for example, a Chemical Mechanical Polishing (CMP) process that rests on the oxide layer to remove only the damaged oxide layer located on the surface layer, i.e., a portion of the buffer layer remains within termination trench 21 g.

After the step of forming source regions 24, it includes:

Forming an interlayer dielectric layer 30 covering the epitaxial layer;

forming a contact hole 310 in the interlayer dielectric layer 30;

The capping interlayer dielectric layer 30 forms a front side metal layer.

As an example, the specific steps of forming the contact hole 310 are: defining a contact hole area in the developed photoresist layer by executing a series of processes such as spin coating, exposure, development and the like of the photoresist; contact holes are formed through the interlayer dielectric layer 130 by a dry etching process. As shown in fig. 4k, a source contact hole is located on top of source region 24, penetrating interlayer dielectric layer 30 to expose body region 23.

As an example, the step of forming the front side metal layer includes separating the front side metal layer into a source metal layer and a gate metal layer, wherein the source metal layer 40 is in contact with the source region 24 through a source contact hole and the control gate electrode is in contact with the gate metal layer, thereby completing the front side process of the device.

After the front side process of the trench power device with the shield gate, the method further comprises thinning the back side of the substrate and depositing a back side metal layer. Regarding the back side thinning and the deposition process of the back side metal layer, conventional processes and materials in the art may be used, and will not be described herein.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. The preparation method of the trench type power device with the shielding gate is characterized by comprising the following steps of:

providing a substrate, forming a first doping type epitaxial layer on the substrate, wherein the epitaxial layer comprises a cell region and a terminal region positioned at the periphery of the cell region;

Forming a gate trench in the cell region and a terminal trench in the terminal region by extending from the surface of the epitaxial layer to the inside;

forming a field oxide layer and first polysilicon in the gate trench and the terminal trench in sequence, wherein the first polysilicon fills the gate trench and the terminal trench respectively;

forming a hard mask layer on the epitaxial layer, patterning the hard mask layer to expose the surface of the epitaxial layer in the cell region, wherein the thickness of the hard mask layer is larger than that of the epitaxial layer

Selectively removing the field oxide layer and the first polysilicon which are positioned at the upper part of the gate trench by taking the patterned hard mask layer as a mask, and forming the first polysilicon which is reserved in the gate trench into a shielding gate electrode;

forming a control gate structure at the upper part of the gate trench;

Performing ion implantation of a second doping type by utilizing a window defined by the patterned hard mask layer to form a body region;

And forming a first doping type source region extending from the surface to the inside of the body region at the side part of the gate trench.

2. The method of manufacturing according to claim 1, characterized in that: a step of selectively removing the first polysilicon, comprising; etching the first polysilicon back by taking the patterned hard mask layer as a mask, so that the first polysilicon remained in the gate trench has a set depth from the top surface of the epitaxial layer; and/or, selectively removing the field oxide layer, including:

And selectively removing the field oxide layer covered on the side wall of the upper part of the gate trench by using the patterned hard mask layer as a mask through a wet etching process, wherein the top surface of the field oxide layer obtained by etching is slightly lower than the top surface of the first polysilicon obtained by etching.

3. The method of manufacturing of claim 1, wherein the step of forming the patterned hard mask layer comprises:

Forming a hard mask layer covering the surface of the epitaxial layer, wherein the hard mask layer comprises one of a lamination layer formed by silicon nitride layer, silicon nitride and silicon oxide; defining an etching window through a photoetching process to expose the hard mask layer positioned on the cellular region;

And etching the hard mask layer by using the photoresist layer covered on the terminal area as a mask.

4. A method of preparation according to claim 3, characterized in that: forming a silicon nitride hard mask layer by covering the surface of the epitaxial layer by a chemical vapor deposition process, wherein the thickness of the silicon nitride hard mask layer is as followsThe above.

5. The method of manufacturing according to claim 4, wherein: before the step of forming the hard mask layer, the method comprises the following steps: oxidizing the exposed first polysilicon by a thermal oxidation process to form a buffer layer, wherein the thickness of the buffer layer is

6. The method of manufacturing of claim 5, wherein the step of forming the control gate structure comprises: growing a gate oxide layer on the upper side wall of the gate trench, and growing an inter-polysilicon oxide layer on the exposed first polysilicon; and forming second polysilicon which is coated on the first polysilicon and fills the gate trench.

7. The method of preparing as claimed in claim 6, wherein after the step of forming the second polysilicon, comprising:

Removing the second polysilicon on the upper surface of the gate oxide layer; and/or performing a thermal annealing process to form a masking oxide layer on the exposed surfaces of the second polysilicon and the epitaxial layer.

8. The method of manufacturing according to claim 7, wherein the step of forming the body region comprises: and carrying out ion implantation by using a window defined by the patterned hard mask layer, and then forming the body region by pushing the well through a thermal annealing process.

9. The method of manufacturing of claim 1, wherein after the step of forming the source region, comprising:

forming an interlayer dielectric layer covering the epitaxial layer;

forming a contact hole in the interlayer dielectric layer;

And covering the interlayer dielectric layer to form a front metal layer.

10. The method of manufacturing according to claim 9, wherein: forming the front metal layer, including separating the front metal layer into a source metal layer and a gate metal layer; the contact hole comprises a source contact hole positioned above the source region, and the source metal layer is in contact with the source region through the source contact hole.