CN118119265A - Mixed resistance change mechanism memristor based on perovskite and perovskite heterojunction and preparation method thereof - Google Patents
Mixed resistance change mechanism memristor based on perovskite and perovskite heterojunction and preparation method thereof Download PDFInfo
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Abstract
The application discloses a mixed resistance change mechanism memristor based on a perovskite heterojunction and a preparation method thereof. In the application, a heterojunction structure of perovskite/perovskite is applied to a resistive layer of a memristor device for the first time. The memristor adopts a resistive switching effect which is formed by the combined action of an oxygen vacancy channel existing in the perovskite crystal structure and a perpendicular anisotropic magnetic effect generated by the interface of the perovskite and the perovskite. The memristor has the characteristics of stable multi-resistance state and simulated synaptic plasticity while improving the switching ratio, and supports a memory integrated chip and pulse neural network hardware.
Description
Technical Field
The invention belongs to the field of information material devices, and particularly relates to a mixed resistance change mechanism memristor based on a perovskite heterojunction and a preparation method thereof. The memristor adopts a resistance change effect formed by a perovskite oxygen vacancy channel and a perpendicular anisotropic magnetic effect generated by a perovskite/perovskite interface, can achieve a large switching ratio and stable multi-resistance state, and supports synaptic plasticity required by synaptic simulation in pulse neural network hardware.
Background
Brain heuristic computation accomplishes many important computational tasks, ranging from artificial intelligence to deep learning. However, the traditional von neumann computing architecture used by computers today physically separates the memory module from the computing module, creating bottlenecks in computer computing speed and efficiency, and fast, efficient, low-power computation of artificial intelligence and large data demands is difficult to achieve. The human brain can process a large amount of information with ultra-low power consumption, which benefits from the plasticity of the synapse in the human brain, and the inspired chip similar to the human brain computing architecture, namely the brain-like chip, is becoming an important branch in the fields of artificial intelligence and neuromorphism, and is gaining wide attention.
Information transfer and processing in the human brain is accomplished by charge pulse transfer in a neural network. In the brain-like chip, the calculation mode imitating the human brain is called third generation neural network-impulse neural network calculation. Therefore, the core of the brain-like chip is a brain-like device that mimics the function of neurons and synapses. According to the neuroscience theory basis of the impulse neural network algorithm, namely the Hubby theory, the key to realizing brain-like calculation is a device capable of simulating the plasticity of the nerve synapses.
The memristor is a novel nano device and has a sandwich structure formed by an upper electrode, a lower electrode and a middle resistance change layer. The simple device structure enables high density integration. And the resistance variable layer material enables the resistance value of the memristor to be related to the charge flowing through the memristor and to be nonvolatile, and low power consumption and continuously adjustable resistance value are realized. These characteristics make memristors the most advantageous device for analog computation, enable a very small number of devices to complete the simulation of a nerve synapse, and become the first-choice core device in impulse neural network hardware. The pulse neural network hardware application based on the memristor covers various directions of information storage, chaotic circuits, artificial intelligence, various perceptions and the like, is a core device of the artificial intelligence hardware in the future, and is a necessary way for obtaining a low-cost brain-like chip.
The main concern of the current memristor research is the stability and uniformity of each resistance state, and the stability directly affects the reliability of the brain-like chip as a core device of the brain-like chip.
In the invention, a heterojunction structure of the perovskite/perovskite is introduced into the field of brain-like devices for the first time and is used as a resistance variable layer of the memristor. The single crystal huntite has anisotropic oxygen vacancy channels and can stably form conductive filaments under the action of an electric field. The interface between lanthanum strontium ferrite and the calcium ferrite layer forms a vertical anisotropic magnetic effect with controllable electric field, and the vertical anisotropic magnetic effect is matched with the formation of the oxygen vacancy conductive filaments, so that the resistance change performance of the whole memristor under the regulation and control of the electric field is affected, the on-off ratio is increased, and the structure further realizes more stable multi-resistance state adjustable performance.
Disclosure of Invention
The invention aims at: a mixed resistance change mechanism memristor based on a heterojunction structure of perovskite/perovskite and a preparation method thereof are provided. The manufactured memristor can realize larger switching ratio and stable multi-resistance state adjustable performance at the same time. The preparation method mostly adopts the same deposition process, pulse laser deposition epitaxial growth is adopted from the bottom electrode to the resistance change layer, and the film forming uniformity of the material is high and the surface is flat. The lattice mismatch degree of the materials used from the substrate to the whole resistance change layer is small, and the film stress is small. The top electrode employs an inert metal layer with high stability and conductivity. The whole structure enables the device to form a conducting channel with small randomness, realizes stable multi-resistance state, further solves the problems that the stability of the traditional memristor is insufficient, the reliability of the device serving as a core device of a brain-like chip is low, and the brain-like chip and a pulse neural network algorithm cannot be well supported.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
the mixed resistance-changing memristor based on the heterojunction structure of the perovskite/perovskite comprises a top electrode, a resistance-changing layer, a bottom electrode and a substrate from top to bottom in sequence;
The top electrode and the bottom electrode have asymmetry, metal is used as the top electrode, a heterojunction of perovskite/perovskite is used as a resistive layer, perovskite is used as the bottom electrode, and strontium titanate is used as a substrate.
Further, the substrate is strontium titanate (SrTiO 3) with the thickness of 0.1-1 mm.
Further, the bottom electrode material adopts strontium ruthenate (SrRuO 3) with the thickness of 10-50 nm.
Further, the resistive layer adopts a multi-layer heterojunction structure of perovskite/perovskite as the resistive layer. The perovskite layer may be one of a perovskite type strontium ferrite (SrFeO 2.5, BM-SFO), a perovskite type strontium cobaltate (SrCoO 2.5, BM-SCO), and a perovskite type lanthanum cobaltate (LaCoO 2.5, BM-LCO), which is lanthanum strontium manganese oxide (La 2/3Sr1/3MnO3, LSMO) film in the present invention.
Further, the resistive layer multilayer heterojunction structure has only one layer of perovskite layer, the upper layer and the lower layer of the resistive layer are both made of the perovskite, and the resistive layer is composed of three layers of materials in total. The thickness of each layer can be of various designs, wherein the thickness of the perovskite monolayer is 5-50 nm and the thickness of the perovskite monolayer is 5-40 nm.
Further, the top electrode material is made of a relatively stable inert metal material, including one of gold (Au), platinum (Pt), tungsten (W) and titanium nitride (TiN), and the thickness of the top electrode material is 10-50 nm.
On the other hand, the invention also discloses a preparation method of the memristor, which comprises the following steps:
(a) Preparing and cleaning a strontium titanate substrate;
(b) Preparing a bottom electrode: epitaxially growing strontium ruthenate serving as a bottom electrode on a substrate by adopting pulse laser deposition, wherein the thickness is 10-50 nm;
(c) Preparing a first layer of a resistance change layer: epitaxially growing single-layer geite on the substrate obtained in the step (b) by adopting pulse laser deposition, wherein the thickness is 5-50 nm;
(d) Preparing a second layer of the resistive layer: epitaxially growing a single-layer perovskite La 2/3Sr1/3MnO3 on the sample obtained in the step (c) by adopting pulse laser deposition, wherein the thickness is 5-40 nm;
(e) Preparing a third layer of the resistance change layer: epitaxially growing single-layer geite on the sample obtained in the step (d) by adopting pulse laser deposition, wherein the thickness is 5-50 nm;
(f) Preparing a top electrode: coating the sample obtained in the step (e) with a mask plate, further depositing a top electrode on the resistive layer by using a magnetron sputtering method or electron beam evaporation, wherein the electrode material is one of gold (Au), platinum (Pt), tungsten (W) or titanium nitride (TiN), and the thickness of the electrode is 10-50 nm, so as to obtain a final device;
compared with the prior art, the technical scheme provided by the invention has the following technical effects:
(1) The invention provides a mixed mechanism resistance-changing memristor with a perovskite/perovskite heterojunction structure and a preparation method thereof, and the variety of the resistance-changing device is enriched.
(2) Compared with the traditional single-resistance-change-mechanism memristor, the invention adopts a mixed-action resistance change mechanism.
(3) The memristor structure prepared by the invention reduces the randomness of the formation of the conducting channel, realizes stable multi-resistance state, solves the problems that the stability of the existing memristor is insufficient, the reliability of the existing memristor as a core device of a brain-like chip is low, and the brain-like chip and a pulse neural network algorithm cannot be well supported.
Drawings
The invention will be further described with reference to the drawings and examples.
Fig. 1 is a block diagram of the device after the top electrode is prepared.
Legend description: 1-top electrode; 2-calcium iron layer; 3-perovskite layer; a 4-calcium iron layer; 5-a bottom electrode; 6-substrate.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention.
Those of skill in the art will appreciate hardware devices that may be one or more of the steps, acts, and schemes of the related manufacturing processes described herein. The hardware devices may be specially designed and constructed for the required purposes.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The technical scheme of the invention is further described in detail below with reference to the accompanying drawings:
(a) And cleaning the strontium titanate substrate. And respectively placing the strontium titanate substrate with the thickness of 0.5mm in acetone, absolute ethyl alcohol and deionized water, ultrasonically cleaning for 10 minutes, and then drying by using nitrogen for standby.
(B) A bottom electrode is prepared. And (c) preparing a layer of strontium ruthenate (SrRuO 3) with the thickness of 40nm on the substrate obtained in the step (a) by adopting pulse laser deposition, and taking the whole layer as a bottom electrode. The specific preparation conditions are as follows: and (3) target material: strontium ruthenate; pulse wavelength: 248nm; substrate temperature: 750 ℃; deposition oxygen pressure: 12Pa; frequency: 4Hz; energy: 300mJ; annealing temperature: 750 ℃; annealing oxygen pressure: 12Pa.
(C) Preparing the calcium-iron stone film. Placing the sample obtained in the step (b) in a pulse laser deposition device for growth, wherein the calcium ferrite is strontium ferrite (SrFeO 2.5) and the thickness is 30nm. The specific preparation conditions are as follows: and (3) target material: ferrierite-strontium ferrite; pulse wavelength: 248nm; substrate temperature: 750 ℃; deposition oxygen pressure: 1.3Pa; frequency: 2Hz; energy: 300mJ; annealing temperature: 750 ℃; annealing oxygen pressure: 0.013Pa.
(D) And preparing a perovskite film. And (3) placing the sample obtained in the step (c) in a pulse laser deposition device for growth, wherein perovskite is (La 2/3Sr1/3MnO3) and the thickness is 10nm. The specific preparation conditions are as follows: pulse wavelength: 248nm; substrate temperature: 700 ℃; deposition oxygen pressure: 30Pa; frequency: 2Hz; energy: 300mJ; annealing temperature: 700 ℃; annealing oxygen pressure: 50Pa.
(E) Preparing the calcium-iron stone film. Placing the sample obtained in the step (d) in a pulse laser deposition device for growth, wherein the calcium ferrite is strontium ferrite (SrFeO 2.5) and the thickness is 30nm. The specific preparation conditions are as follows: ferrierite-strontium ferrite; and (3) target material: pulse wavelength: 248nm; substrate temperature: 750 ℃; deposition oxygen pressure: 1.3Pa; frequency: 2Hz; energy: 300mJ; annealing temperature: 750 ℃; annealing oxygen pressure: 0.013Pa.
(F) And (c) defining a top electrode pattern by using a mask plate, and preparing a metal top electrode on the sample obtained in the step (c) by adopting a direct current reaction magnetron sputtering method, wherein the top electrode material is titanium nitride (TiN), the thickness of the top electrode is 20nm, and the size of the top electrode is 40 multiplied by 40 mu m square. The specific preparation conditions are as follows: and (3) target material: a titanium metal target; target material pre-sputtering treatment: 5kW-2 minutes-argon atmosphere; deposition air pressure: 0.0066mbar to 0.0133 mbar.
(G) Each small square electrode is separated, and the whole device structure is schematically shown in fig. 1.
Thus far, the preparation of the mixed resistance variable memristor based on the perovskite/the perovskite is finished, and the obtained overall memristor is shown in fig. 1. The memristor adopts a novel resistance-change layer structure material, can be opened under smaller voltage stimulation, has the characteristics of homoplasmic substrate epitaxy, no stress of a film, stable multi-resistance state, continuous and adjustable resistance value and the like, and solves the problems of insufficient stability and low reliability of the existing memristor.
Claims (6)
1. A memristor based on a mixed resistance change mechanism of perovskite and perovskite heterojunction belongs to the technical field of microelectronics. The invention is characterized in that: the bottom electrode to the resistance change layer are of a multilayer epitaxial growth structure, the resistance change layer adopts a heterojunction structure of perovskite/perovskite, and the top electrode is a traditional metal electrode. The resistance change mechanism of the memristor is mixed with two resistance change mechanisms of a perpendicular anisotropic magnetic effect generated by a perovskite oxygen vacancy channel and a perovskite/perovskite interface. The memristor comprises a top electrode, a resistance change layer, a bottom electrode and a substrate from top to bottom.
2. The memristor of claim 1, wherein the substrate is strontium titanate (SrTiO 3) having a thickness of between 0.1 and 1 mm.
3. The memristor of claim 1, wherein the bottom electrode material is strontium ruthenate (SrRuO 3) with a thickness of 10-50 nm.
4. The memristor of claim 1, wherein the resistive layer employs a multi-layer heterojunction structure of perovskite/perovskite as the resistive layer. The perovskite layer may be a perovskite type strontium ferrite (SrFeO 2.5, BM-SFO), a perovskite type strontium cobaltate (SrCoO 2.5, BM-SCO), or a perovskite type lanthanum cobaltate (LaCoO 2.5, BM-LCO), which in this invention is a lanthanum strontium manganese oxide (La 2/3Sr1/3MnO3, LSMO) film. Wherein the thickness of the single-layer perovskite is 5-50 nm, and the thickness of the perovskite single-layer is 5-40 nm.
5. The memristor of claim 1, wherein the top electrode material is a relatively stable metallic material, including gold (Au), platinum (Pt), or titanium nitride (TiN), having a thickness of 10-50 nm.
6. A preparation method of a memristor based on a perovskite and perovskite multilayer epitaxial heterojunction with a mixed resistance change mechanism comprises the following steps:
(a) Preparing and cleaning a strontium titanate substrate;
(b) Preparing a bottom electrode: epitaxially growing strontium ruthenate serving as a bottom electrode on a substrate by adopting pulse laser deposition, wherein the thickness is 10-50 nm;
(c) Preparing a first layer of a resistance change layer: coating the mask on the substrate obtained in the step (b), and epitaxially growing single-layer ferrierite on the sample obtained in the step (b) by adopting pulse laser deposition, wherein the thickness is 5-50 nm;
(d) Preparing a second layer of the resistive layer: epitaxially growing a single-layer perovskite (La 2/3Sr1/3MnO3) on the sample obtained in the step (c) by pulse laser deposition without removing the mask plate used in the step (c), wherein the thickness is 5-40 nm;
(e) Preparing a third layer of the resistance change layer: epitaxially growing a single-layer geite on the sample obtained in the step (d) by adopting pulse laser deposition without removing the mask plate used in the step (d), wherein the thickness is 5-50 nm;
(f) Preparing a top electrode: and (3) removing the mask used in the step (e), replacing the mask, covering the sample obtained in the step (e), and further depositing a top electrode on the resistive layer by adopting a magnetron sputtering method or electron beam evaporation, wherein the electrode material adopts one of gold (Au), platinum (Pt) or titanium nitride (TiN), and the thickness of the electrode is 10-50 nm, so that the final device is obtained.
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