CN111081875A - Ferroelectric polarization regulated artificial synapse device and preparation method thereof - Google Patents
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Abstract
The invention relates to an artificial synapse device for ferroelectric polarization regulation and control and a preparation method thereof, which is characterized in that a two-dimensional semiconductor layer, a source/drain electrode, a ferroelectric functional layer and a gate electrode are sequentially prepared on a substrate to form an artificial synapse structure for ferroelectric polarization regulation and control, wherein the two-dimensional semiconductor is MoS2Or WSe2A transition metal chalcogenide coating; the ferroelectric functional layer is a polyvinylidene fluoride base ferroelectric polymer film; the preparation of the synapse device comprises: SiO 22Preparing a/Si layer, a transition metal chalcogenide, a back gate structure, a polyvinylidene fluoride layer and a metal top gate electrode. Compared with the prior art, the invention has the advantages of ultra-low power consumption, long service life and the like, and the characteristics make the synapse of the organic ferroelectric transistor have very prospect, can promote a large-scale neural structure network to simulate the human brain,and inspires massive parallelism and low-power-consumption operation in human brain algorithm networks.
Description
Technical Field
The invention relates to the field of field effect transistor electronic technology, in particular to an artificial synapse device based on organic iron polarization regulation and a preparation method thereof.
Background
The traditional digital computer has the defects in the fields of automatic control, mode recognition, associative memory, signal processing and the like, so that a hardware which breaks through the technology of the original system and realizes rapidness, light weight and low power consumption is urgently needed to be found, the human brain is simulated, and the development of a nerve form computer is the direction for scientists to seek breakthrough. Each neuron of the human brain is connected with thousands of neurons through synapses, and signals are conducted in a distributed and concurrent mode, so that the defect of processing speed of a single neuron is overcome. The connection strength between synapses of neurons can be modulated by the relative pulse time of pre-and post-synaptic neurons, which is the biological basis for the human brain to perform calculations, learning, and memory.
At present, the neural morphology calculation is mainly realized by software and hardware-based methods, and the software-based methods, such as AlphaGo which recently defeats the human Weiqi champion, are programs based on a deep learning algorithm and work on a traditional digital computer, so the method is also high in energy consumption and is not an ideal scheme for realizing the neural morphology calculation in the long run; and a hardware-based method constructs an electronic device which can simulate synapse and neuron functions from the bottom layer and is used for constructing a neuromorphic computing system. One of the keys of such methods is the realization of artificial synapse solid-state electronics that can function by continuously varying the weights of simulated biological synapses.
In recent years, an artificial synapse device developed on the basis of a memristor attracts extensive attention of researchers of various countries, the memristor is a nonlinear resistor with a memory function, the resistance value of the nonlinear resistor can be controlled to be continuously changed through an external electric field, and the memristor effect can effectively simulate the plasticity behavior of biological synapse connection weight. The memristor is applied to a neuromorphic system as an electronic synapse, and a brain-simulated chip of the high-integration neuromorphic system close to the human brain is expected to be constructed.
The research of the memristor in the prior art is mainly focused on inorganic insulating materials, and the memristive mechanism of the inorganic insulating materials is mainly based on the movement of anions and cations in the materials. The non-uniformity of the electric field is further increased by the movement of ions under the drive of the non-uniform electric field, resulting in very poor repeatability of the performance of such memristors and poor uniformity between different devices. This greatly limits the development of memristors in circuit integration, and it is therefore very important to explore new memristor devices with high speed, high stability and high repeatability.
Disclosure of Invention
The invention aims to design a ferroelectric polarization regulated artificial synapse device and a preparation method thereof aiming at the defects of the prior art, polyvinylidene fluoride base ferroelectric polymer material is adopted as gate dielectric material, a two-dimensional semiconductor is adopted as a conducting channel to prepare a three-terminal field effect transistor, ferroelectric material is introduced into the traditional field effect transistor structure to form the ferroelectric polarization regulated artificial synapse structure, and the ferroelectric synapse device with ultralow power consumption, high stability, high repeatability and complete electric signal control of the device is realized based on the response of ferroelectric polarization dynamics under an electric field. The ferroelectric polarization state of the polyvinylidene fluoride base ferroelectric polymer material can be continuously regulated and controlled by an external electric field, the polarization electric fields in different polarization states change the carrier concentration of the two-dimensional semiconductor channel, thereby causing continuous change of the conductivity of the two-dimensional semiconductor channel, the conductivity of the polyvinylidene fluoride ferroelectric polymer can be regulated and controlled by five orders of magnitude by a polarization field, the polarization state of the polyvinylidene fluoride ferroelectric polymer material is non-volatile, highly controllable, excellent in retentivity and fatigue property, low in power consumption of polarization reversal, the polyvinylidene fluoride-based ferroelectric polymer material film and the ferroelectric transistor of the two-dimensional semiconductor can realize a novel artificial synapse device, have better repeatability and stability and lower energy consumption, and realize the wide application of the two-dimensional semiconductor ferroelectric field effect structure in the field of artificial electronic synapses.
The specific technical scheme of the invention is as follows: an artificial synapse device regulated and controlled by ferroelectric polarization is characterized by consisting of an oxide layer, a two-dimensional semiconductor layer, a source/drain electrode, a ferroelectric functional layer and a gate electrode which are sequentially prepared on a substrate, wherein the substrate is prepared from a heavily doped p-Si material, single side of the substrate is polished, and the thickness of the substrate is 0.5 mm; the oxide layer is SiO2A layer having a thickness of 270 to 300 nm; the two-dimensional semiconductor is MoS2Or WSe2A transition metal chalcogenide coating layer with a thickness of 2-10 molecular layers; the source/drain electrodes are Cr/Au plating layers, the thickness of the Cr plating layer is 5-10 nm, and the thickness of the Au plating layer is 30-50 nm; the ferroelectric functional layer is a polyvinylidene fluoride base ferroelectric polymer film, and the thickness of the ferroelectric functional layer is 100-300 nm; the gate electrode is an Al coating, and the thickness of the gate electrode is 15-30 nm.
A preparation method of a synapse device based on organic ferroelectrics is characterized in that the preparation of the synapse device comprises the following steps:
preparation of the (mono) oxide layer
The silicon dioxide layer prepared on the substrate of the heavily doped p-Si material by a thermal oxidation method is an oxide layer, and the thickness of the silicon dioxide layer is 285 +/-15 nm.
Preparation of two-dimensional semiconductor layer
SiO using mechanical lift-off transfer method to transfer transition metal chalcogenide to oxide layer2The surface is a two-dimensional semiconductor layer with a thickness of 270-300 nm.
Preparation of (III) Source/Drain electrodes
And preparing a source electrode and a drain electrode by adopting an ultraviolet lithography technology or an electron beam exposure technology and combining a thermal evaporation and lift-off process to form a back gate structure transition metal chalcogenide two-dimensional semiconductor field effect structure device, wherein the electrodes are chromium and gold, and the thicknesses of the electrodes are respectively 5-10 nm and 30-50 nm.
Preparation of (IV) ferroelectric functional layer
And preparing the polyvinylidene fluoride base ferroelectric functional layer on the prepared back gate device by using a spin coating method, and annealing at the temperature of 135 ℃ for 2-4 hours to ensure the crystallization characteristic of the functional layer, wherein the thickness of the polyvinylidene fluoride base ferroelectric functional layer is 100-300 nm.
(V) preparation of metal top gate electrode
And obtaining a specific pattern electrode structure on the ferroelectric function layer by photoetching and etching methods, and preparing a semitransparent or transparent aluminum layer as a metal top gate electrode, wherein the thickness of the aluminum layer is 15-20 nm.
Compared with the prior art, the invention has the following advantages:
1) different local electric fields generated by different polarizations of a P (VDF-TrFE) ferroelectric polymer material are utilized to regulate and control current carriers in a channel, so that a synapse device based on complete electric signal regulation and control is realized, and the stability and the repeatability of an electronic synapse device are improved;
2) the adoption of the extremely small grid leakage current occupies most of energy consumption, so that the synapse device has the characteristic of ultralow power consumption (less than 1 fJ);
3) the synapse device has good fatigue property, can work for ten years at the frequency of 10Hz, and has the advantage of long service life.
Drawings
FIG. 1 is a schematic diagram of a synapse device structure in accordance with the present invention;
FIG. 2 is the PVDF-MoS of example 12Transferring the graph;
FIG. 3 is PVDF-WSe of example 22Transferring the graph;
FIG. 4 shows the fatigue characteristics of the synapse device prepared in example 1.
Detailed Description
Referring to the attached figure 1, the invention sequentially comprises a substrate 1, an oxide layer 2, a two-dimensional semiconductor layer 3, a source/drain electrode 4, a ferroelectric functional layer 5 and a gate electrode 6 from bottom to top, wherein the substrate 1 is prepared from a heavily doped p-Si material, the single surface of the substrate is polished, and the thickness of the substrate is 0.5 mm; the oxide layer 2 is SiO formed on a heavily doped p-Si substrate 12A layer having a thickness of 270 to 300 nm; the two-dimensional semiconductor 3 is SiO2MoS spin-coated on layer2Or WSe2A transition metal chalcogenide coating layer with a thickness of 2-10 molecular layers; the source/drain electrode 4 is a transitionThe Cr/Au coating is deposited on the metal chalcogenide coating, the thickness of the Cr coating is 5-10 nm, and the thickness of the Au coating is 30-50 nm; the ferroelectric functional layer 5 is a polyvinylidene fluoride film which is spin-coated on the Cr/Au coating, and the thickness of the polyvinylidene fluoride film is 100-300 nm; the gate electrode 6 is a transparent or semitransparent Al coating, and the thickness of the Al coating is 15-30 nm.
The invention is prepared by forming SiO on a substrate 12Preparing a two-dimensional semiconductor layer 3 of transition metal chalcogenide, preparing a metal electrode as a source/drain electrode 4 of a semiconductor channel by combining an ultraviolet lithography method or an electron beam lithography method with a stripping process, preparing an organic ferroelectric film of polyvinylidene fluoride on the structure as a ferroelectric functional layer 5, and preparing a semi-transparent or transparent gate electrode 6 on the organic ferroelectric film to form an artificial synapse structure for ferroelectric polarization regulation. The device firstly polarizes the organic ferroelectric material by applying a continuously-changed electric signal to the grid electrode, further regulates and controls a background carrier of a two-dimensional semiconductor channel, then applies a tiny voltage between the source electrode and the drain electrode, and realizes the continuous updating rule of the synaptic weight by measuring the change of source leakage current under different grid voltages, namely the continuous change of the synaptic weight. The artificial synapse is regulated and controlled by a pure electrical signal, so that the controllability and the consistency are very good. Meanwhile, the artificial brain has the outstanding advantages of ultralow power consumption (less than 1fJ), long service life (about 10 years of operation under the working frequency of 10Hz biological brain), and the like. These characteristics make the organic ferroelectric transistor synapse very promising, can prompt large-scale neural structure networks to simulate the human brain, and inspire large-scale parallelism and low-power-consumption operation in human brain algorithm networks.
The present invention is further illustrated by the following specific examples.
Example 1
Preparing an artificial synapse device based on organic ferroelectricity according to the following steps:
1) substrate selection: selecting heavily doped p-type silicon with the thickness of 0.5mm as a substrate 1, and performing single-side polishing
And (4) carrying out light treatment.
2) Preparing an oxide dielectric layer: silicon dioxide to SiO with 285nm thickness on p-type silicon surface by thermal oxidation2Oxide layer 2 of/Si.
3) Two-dimensional semiconductor transfer preparation: MoS of transition metal chalcogenide with adhesive tape2The crystals are mechanically exfoliated and transferred to SiO2On the oxide layer 2 of/Si, its MoS2Three molecular layers thick.
4) Preparing a metal source drain electrode: an electrode pattern is prepared by adopting an ultraviolet photoetching method, then a metal electrode with 5nm of chromium and 30nm of gold is prepared by utilizing a thermal evaporation technology and is used as a source/drain electrode 4, and the metal film is stripped to form the source/drain electrode 4 by combining a lift-off method, so that a back gate device with the channel width of 5um is obtained.
5) Preparing a ferroelectric functional layer: and preparing a P (VDF-TrFE) film on the prepared back gate device by adopting a spin coating method, wherein the thickness of the P (VDF-TrFE) film is 300nm, and then annealing the P (VDF-TrFE) film for 4 hours at the temperature of 135 ℃ to prepare the ferroelectric functional layer 5 with the crystallization characteristic.
6) Preparing a semi-permeable metal top gate electrode: a specific electrode pattern structure is obtained on the ferroelectric function layer 5 through photoetching and etching methods, then a semitransparent Al layer is prepared through a thermal evaporation method, and an Al electrode with the thickness of 15nm is a gate electrode 6.
The artificial synapse device prepared above applies a continuously changing electrical signal between the drain and the gate, so that the ferroelectric functional layer 5 of P (VDF-TrFE) is in different polarization states, and the background carriers of the two-dimensional semiconductor channel are regulated. When the synapse device works, a tiny constant voltage of 0.5V is introduced between a source electrode and a drain electrode, currents at two ends of the electrodes are detected, the electrical response characteristics of the two-dimensional semiconductor channel under different grid voltages are measured, different current changes are equivalent to different synapse weight values, and therefore continuous updating of the weight of the ferroelectric synapse is achieved.
Referring to FIG. 2, the transfer characteristic of the artificial synapse device prepared above is tested, and the curve shows the unipolar two-dimensional semiconductor MoS excited by different gate voltages2The electrical response characteristic of the channel, the channel conductance, can be continuously regulated by the gate voltage, which is equivalent to the continuous update of the synaptic weights. The invention removes unipolar molybdenum disulfide (MoS)2) Besides materials, bipolar WSe can also be adopted2Or MoTe2Of equal material for gate electrodes of different polaritiesAnd meanwhile, different grid voltages are used for regulating and controlling the concentration of the channel carriers.
Referring to FIG. 4a, the artificial synapse device prepared above is stimulated by different gate voltages to be a unipolar two-dimensional semiconductor MoS2The electric response characteristic of the channel, the channel conductance, can be regulated and controlled by four orders of magnitude by the grid voltage.
Referring to FIG. 4b, an artificial synapse device fabricated as described above is shown generally at 107After secondary polarization complete inversion circulation, under the excitation of different grid voltages, the single-polarity two-dimensional semiconductor MoS2The electric response characteristic of the channel, the channel conductance, can be regulated and controlled by four orders of magnitude by the grid voltage.
Referring to FIG. 4c, the artificial synapse device fabricated as described above is excited by a unipolar two-dimensional semiconductor MoS under 100 gate voltage pulses2The electrical response characteristic of the channel, the channel conductance, can be continuously regulated.
Referring to FIG. 4d, an artificial synapse device as prepared above is shown generally at 107After the second polarization complete inversion cycle, the unipolar two-dimensional semiconductor MoS is excited by 100 gate voltage pulses2The electrical response characteristic of the channel, the channel conductance, can be continuously regulated. The device still maintains good performance, which is equivalent to ten years of operation at 10 Hz.
Example 2
Preparing an artificial synapse device based on organic ferroelectricity according to the following steps:
1) substrate selection: heavily doped p-type silicon with the thickness of 0.5mm is selected as a substrate 1, and single-side polishing treatment is carried out.
2) Preparing an oxide dielectric layer: silicon dioxide to SiO with 285nm thickness on p-type silicon surface by thermal oxidation2Oxide layer 2 of/Si.
3) Two-dimensional semiconductor transfer preparation: WSe of transition metal chalcogenides by adhesive tape2The crystals are mechanically exfoliated and transferred to SiO2On the oxide layer 2 of/Si, its MoS2Five molecular layers in thickness.
4) Preparing a metal source drain electrode: an electrode pattern is prepared by adopting an ultraviolet photoetching method, then a metal electrode with 5nm of chromium and 30nm of gold is prepared by utilizing a thermal evaporation technology, and a source/drain electrode 4 is obtained after a metal film is stripped by combining a lift-off method, so that a back gate device with the channel width of 5um is obtained.
5) Preparing a ferroelectric functional layer: and preparing a P (VDF-TrFE) film on the prepared back gate device by adopting a spin coating method, wherein the thickness of the P (VDF-TrFE) film is 300nm, and then annealing the P (VDF-TrFE) film for 4 hours at the temperature of 135 ℃ to prepare the ferroelectric functional layer 5 with the crystallization characteristic.
6) Preparing a semi-permeable metal top gate electrode: a specific electrode pattern structure is obtained on the ferroelectric function layer 5 through photoetching and etching methods, then a semitransparent Al layer is prepared through a thermal evaporation method, and an Al electrode with the thickness of 20nm is a gate electrode 6.
The synapse device prepared above applies a continuously varying electrical signal between the drain and the gate, so that the ferroelectric functional layer 5 of P (VDF-TrFE) is in different polarization states, regulating and controlling the background carriers of the two-dimensional semiconductor channel. When the synapse device works, a tiny constant voltage of 0.5V is introduced between the source electrode and the drain electrode, and the current at two ends of the electrode is detected. The electric response characteristics of the two-dimensional semiconductor channel under different gate voltages are measured, and different current changes are equivalent to different synapse weight values, so that the weight of the ferroelectric synapse is continuously updated.
Referring to FIG. 3, the synapse device prepared above is tested for transfer characteristics, and the curves show bipolar two-dimensional semiconductor WSe under different gate voltage excitations2The electrical response characteristic of the channel, the channel conductance, can be continuously regulated by the gate voltage, which is equivalent to the continuous update of the synaptic weights. While different gate voltage polarities can be in WSe2Different types of carriers are excited in the channel, which is equivalent to adding one dimension of regulation to synapses.
The above description is only a preferred example of the present invention and is not intended to limit the scope of the present invention, and it will be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention.
Claims (4)
1. An artificial synapse device regulated by ferroelectric polarization, characterized in that the artificial synapse deviceThe device consists of an oxide layer, a two-dimensional semiconductor layer, a source/drain electrode, a ferroelectric functional layer and a gate electrode which are sequentially prepared on a substrate, wherein the substrate is prepared from a heavily doped p-Si material, is polished on one side and has the thickness of 0.5 mm; the oxide layer is SiO2A layer having a thickness of 270 to 300 nm; the two-dimensional semiconductor is MoS2Or WSe2A transition metal chalcogenide coating layer with a thickness of 2-10 molecular layers; the source/drain electrodes are Cr/Au plating layers, the thickness of the Cr plating layer is 5-10 nm, and the thickness of the Au plating layer is 30-50 nm; the ferroelectric functional layer is a polyvinylidene fluoride base ferroelectric polymer film, and the thickness of the ferroelectric functional layer is 100-300 nm; the gate electrode is an Al coating, and the thickness of the gate electrode is 15-30 nm.
2. A method for fabricating the ferroelectric polarization modulated artificial synapse device as claimed in claim 1, wherein the fabrication comprises:
a. spin coating SiO on heavily doped p-Si substrate2Is an oxide layer with the thickness of 270-300 nm and is polished on one side;
b. MoS is peeled off mechanically2Or WSe2Transition metal chalcogenide transfer to SiO2The two-dimensional semiconductor layer is arranged on the layer, and the thickness of the two-dimensional semiconductor layer is 2-10 molecular layers;
c. adopting ultraviolet lithography or electron beam exposure and combining thermal evaporation and lift-off processes to manufacture a Cr/Au electrode with a back gate structure on the two-dimensional semiconductor layer as a source/drain electrode of a semiconductor channel, wherein the thickness of the Cr electrode is 5-10 nm, and the thickness of Au is 30-50 nm;
d. spin-coating a P (VDF-TrFE) film on a back gate device, wherein the thickness of the film is 100-300 nm, and crystallizing the spin-coated polymer film at the temperature of 100-150 ℃ for 1-5 h to prepare a crystalline layer which is a ferroelectric functional layer;
e. and plating a semitransparent or transparent Al layer on the ferroelectric functional layer by adopting an electron beam evaporation process, wherein the thickness of the Al layer is 15-30 nm, and obtaining a gate electrode with a graphic structure by a photoetching and etching method to form the artificial synapse structure regulated and controlled by ferroelectric polarization.
3. Iron-based according to claim 2The preparation method of the artificial synapse device regulated by electric polarization is characterized in that the mechanical stripping adopts a transition metal chalcogenide material sheet, the transition metal chalcogenide material sheet is adhered to an adhesive tape and repeatedly folded to be continuously thinned, and then the sheet material is transferred to SiO by PMMA2The thickness of the prepared two-dimensional semiconductor layer is 2-10 molecular layers.
4. The method of claim 2, wherein the spin coating is performed by a diethyl carbonate solution at 500-600 rpm/sec for 5s and then at 3000-4000 rpm/sec for 25 s.
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| CN112542515A (en) * | 2020-12-14 | 2021-03-23 | 中国科学院微电子研究所 | Photoelectric regulation nerve synapse transistor and preparation method thereof |
| CN113113535A (en) * | 2021-03-30 | 2021-07-13 | 天津理工大学 | Based on MoS2All-solid-state electrolyte memristor and preparation method thereof |
| CN113161494A (en) * | 2021-04-23 | 2021-07-23 | 光华临港工程应用技术研发(上海)有限公司 | Photoelectric artificial synapse and preparation method thereof |
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| CN112542515A (en) * | 2020-12-14 | 2021-03-23 | 中国科学院微电子研究所 | Photoelectric regulation nerve synapse transistor and preparation method thereof |
| CN113113535A (en) * | 2021-03-30 | 2021-07-13 | 天津理工大学 | Based on MoS2All-solid-state electrolyte memristor and preparation method thereof |
| CN113161494A (en) * | 2021-04-23 | 2021-07-23 | 光华临港工程应用技术研发(上海)有限公司 | Photoelectric artificial synapse and preparation method thereof |
| CN113161494B (en) * | 2021-04-23 | 2023-12-26 | 光华临港工程应用技术研发(上海)有限公司 | Preparation method of photoelectric artificial synapse and photoelectric artificial synapse |
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