CN113113535A - Based on MoS2All-solid-state electrolyte memristor and preparation method thereof - Google Patents

Based on MoS2All-solid-state electrolyte memristor and preparation method thereof Download PDF

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CN113113535A
CN113113535A CN202110338872.9A CN202110338872A CN113113535A CN 113113535 A CN113113535 A CN 113113535A CN 202110338872 A CN202110338872 A CN 202110338872A CN 113113535 A CN113113535 A CN 113113535A
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CN113113535B (en
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王芳
梁安阁
张楷亮
张力方
单欣
林欣
胡凯
袁育杰
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Tianjin University of Technology
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20Multistable switching devices, e.g. memristors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/881Switching materials
    • H10N70/882Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8822Sulfides, e.g. CuS

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Abstract

Based on MoS2The all-solid-state electrolyte memristor and the preparation method thereof belong to the field of electronic preparation technology and brain-like calculation, and MoS is selected firstly2As a channel material, MoS2The preparation method is characterized by combining ALD and CVD, selecting lithium salt as a solid electrolyte, preparing a solid electrolyte layer by using a magnetron sputtering method, and preparing an electrode by using methods such as electron beam evaporation and magnetron sputtering. The band structure of molybdenum disulfide is changed by modulating the embedding and the separating of lithium ions through a grid end electric field, and reading voltage is applied to the source and the drain ends to obtain the change of channel conductance, so that the memristor device has good conductance updating linearity and lower operation power consumption, and can be applied to the calculation of new-generation nerve morphology. The corresponding all-solid-state electrolyte memristor is prepared by utilizing the device structure, good conductivity update symmetry and nearly 98% conductivity linearity are realized under pulse excitation, and meanwhile, the device has the conductivity of 105The above durability.

Description

Based on MoS2All-solid-state electrolyte memristor and preparation method thereof
Technical Field
The invention belongs to the field of electronic preparation process and brain-like calculation, and because the Moore's law is gradually invalid with the improvement of semiconductor process, the performance can not be continuously improved by improving the integration level; also because of the bottleneck of ' storage walls ' in the traditional von neumann computing architecture, the further improvement of the computing efficiency is limited, the neuromorphic computing of the memristor based on the two-dimensional material becomes a very promising direction for surpassing the moore's law and realizing the non-von architecture, and the invention relates to a molybdenum sulfide-based memristor device which is used for neuromorphic computing and is compatible with a CMOS (complementary metal oxide semiconductor) process.
Technical Field
With the rapid development of big data and artificial intelligence, the size and growth speed of data are also rapidly expanding, and how to calculate and store data at high speed becomes the first problem facing current technological development. The traditional method for improving the computational power and the memory density of the chip is realized by continuously reducing the size of the transistors and increasing the number of the transistors to improve the integration level of the chip according to moore's law, in recent years, along with the continuous improvement of the process, the integration level of the chip is higher and higher, the performance of the chip is also improved at a rapid pace, but the problem of a memory wall caused by the limitation of the bus speed between a CPU and a memory in the traditional von Neumann architecture is more obvious. In order to solve the problem, the memory-resistor synapse device is designed to realize the memory-computation integrated capability of the human brain.
The resistive type memristor has the advantages of simple structure, compatibility with a CMOS (complementary metal oxide semiconductor) process and the like, and is widely concerned in the aspect of nerve morphology calculation; however, because the formation and breakage of oxygen vacancies or metal ion conductive filaments in the resistive device unit are uncontrollable, the problem of optimization of simulation characteristics caused by conductance mutation behaviors exists. The phase change memory type synapse device has the advantages of high speed, multi-state storage and the like, and is widely applied to the aspect of developing a nonvolatile memoryAttention is paid broadly; however, the device changes the resistance state by utilizing the mutual conversion between the crystalline state and the amorphous state of the joule heat control phase change material generated by current, and higher current (I) is required during the operation process of the device>106A cm-2) The nucleation barrier (2-4 eV) of the crystalline state is overcome, so that the power consumption of the device is relatively large. In addition, the above two types of synapse devices belong to a double-ended structure, which cannot parallel information transfer and learning functions in time and space, and when a synapse dynamic function is simulated, the number of devices needs to be increased to complete more complex functions.
Most of the current electrolyte memristors adopt ionic gel, and the working principle is as follows: the ionized lithium ions in the gel are pushed to the channel under the action of an electric field, the potential barrier of the molybdenum sulfide is changed along with the insertion and the adsorption of the lithium ions, and the resistance of the device is in a low-resistance state; under the action of reverse electric field, the metal particles are originally embedded and adsorbed in MoS2The lithium ions in the lithium ion battery will be extracted back to the gel, and the device returns to the high-resistance state. The two resistance states can be switched with each other under the action of an applied electric field.
(1.Dual-gated MoS2 neuristor for neuromorphic computing[J].ACS applied materials&interfaces,2019,11(44):41482-41489.
2.Programmable Synapse-Like MoS2 Field-Effect Transistors Phase-Engineered by Dynamic Lithium-Ion Modulation[J].Advanced Electronic Materials,2020,6(5):1901410.
3. MoS 2-based memristor based on coexistence of analog type and digital type and preparation method [ P ]. Beijing City: CN111933794A,2020.11.13.)
But the use of ionic gels and the like is not compatible with standard CMOS processes. Meanwhile, the stability of the gel is poor, the existence of other impurity ions in the gel influences the stability of the resistance state of the device, the data retention capability and the linearity of conductance updating of the device are weakened, and the controllability of the conductance of the device is influenced. The invention provides an all-solid-state electrolyte memristor, which utilizes lithium cobaltate as a solid electrolyte, can firstly overcome the problem that the existing liquid electrolytes such as ionic gel and the like are incompatible with a CMOS (complementary metal oxide semiconductor) process, secondly improves the stability of the resistance state of the device, improves the data retention capacity, can conveniently control the movement direction and quantity of lithium ions through a grid electric field, and further improves the controllability of the device.
Disclosure of Invention
The invention aims to solve the technical problem of structural construction of an all-solid-state electrolyte memristor compatible with a CMOS (complementary metal oxide semiconductor) process. Firstly, MoS is selected2As a channel material, MoS2Prepared by a method using Atomic Layer Deposition (ALD) in combination with Chemical Vapor Deposition (CVD). Lithium salt is selected as a solid electrolyte, and a magnetron sputtering method is used for preparing the solid electrolyte layer. The pattern is manufactured through an ultraviolet lithography technology, the electrodes are prepared through methods such as electron beam evaporation and magnetron sputtering, good synapse simulation characteristics are achieved through optimized excitation, and a device basis is provided for neural morphology calculation based on the memristor.
The technical scheme of the invention is as follows:
based on MoS2The basic mechanism of the all-solid-state electrolyte memristor sequentially comprises a gate electrode, a gate dielectric layer, a molybdenum sulfide layer, a solid-state electrolyte layer and a source electrode and a drain electrode from bottom to top; molybdenum disulfide is selected as a channel material, and the channel material can be in a single crystal state or a polycrystalline state. The solid electrolyte layer provides lithium ions for regulating and controlling channel conductance, and the gate drain source electrode adopts an inert electrode for applying an electric field;
the device substrate of the invention is a silicon dioxide \ silicon substrate or a sapphire substrate. The solid electrolyte layer adopts a medium layer which is easy to generate alkali metal ions under the action of a grid electric field, and is any one of lithium manganate, lithium cobaltate, lithium nickel cobalt manganate or lithium iron phosphate. The source and drain electrodes are metal electrodes with stable properties. The gate dielectric layer is made of conventional metal oxide, including silicon dioxide, aluminum oxide or hafnium oxide metal oxide.
The gate dielectric layer is made of silicon dioxide or any one of other dielectrics, a thermal oxide silicon dioxide substrate is adopted, or the gate dielectric layer is prepared through ALD (atomic layer deposition), for example, trimethylaluminum and deionized water are utilized to perform self-limiting reaction, the substrate temperature is 200 ℃, nitrogen is selected as gas, and aluminum oxide with the required thickness is sputtered.
The invention is based on MoS2The preparation steps of the all-solid-state electrolyte memristor are as follows:
1) MoO deposition using ALD3
2) MoO by CVD process3Annealing, sulfurizing and annealing to obtain polycrystalline MoS with good crystallinity2
3) Ti/Au electrodes are prepared by conventional ultraviolet lithography and electron beam evaporation processes, with thicknesses of-10 nm and-80 nm, respectively.
4) And preparing a lithium cobaltate solid electrolyte layer with the thickness of 20nm by using a radio frequency magnetron sputtering process.
5) And exposing the source, drain and gate electrodes by using ultraviolet lithography and plasma etching processes.
The molybdenum disulfide is prepared by adopting a two-step method, namely an ALD (atomic layer deposition) combined CVD (chemical vapor deposition) method, and the controllable preparation of the layer number of the molybdenum sulfide can be realized, wherein the annealing temperature of the molybdenum oxide is 200-; the vulcanization temperature is 500 ℃ and 800 ℃, and the preferred vulcanization temperature is 550 ℃; the annealing temperature of the molybdenum sulfide is 800-.
The thickness of the gate-drain source electrode is 5 nm-200 nm, and the inert metal electrode is prepared by adopting direct current magnetron sputtering or electron beam evaporation.
The thickness of the solid electrolyte layer is 5 nm-5 mu m, the solid electrolyte layer is prepared by adopting radio frequency magnetron sputtering, a high-purity ceramic target is selected, argon is used as sputtering atmosphere, the power is 100-200W, preferably 120W, and the sputtering time is 5-60min, preferably 20 min.
The working mechanism of the invention is as follows:
in a common electrolyte memristor, ionic gel is usually adopted as a liquid electrolyte, and a layer of electrolyte is covered on the surface of a channel material in a dropping coating or soaking mode, but a device prepared in the mode is incompatible with the traditional CMOS process, and meanwhile, impurity ions in the gel or the solution can influence the stability of the device, weaken the data retention capacity and the linearity of conductivity updating of the device, and influence the conductivity controllability of the device. Applying voltage to the back gate electrode, under the action of a gate electric field, enabling alkali metal ions in the solid electrolyte layer to be separated from the electrolyte and continuously pushed into a molybdenum sulfide channel, and gradually reducing a channel potential barrier along with the adsorption and embedding of the alkali metal ions so that the device is continuously changed from a high-resistance state to a low-resistance state; and meanwhile, due to the layered structure of molybdenum sulfide, larger gaps are formed between layers, and the crystal structure of the molybdenum sulfide channel material cannot be changed due to the embedding and the extracting of the alkali metal ions with relatively small volume. The two resistance states can be conveniently regulated and controlled by an external electric field of the grid electrode, and meanwhile, the device has good data retention characteristics and durability.
The invention has the beneficial effects that:
based on the above consideration, the lithium salt is used as the solid electrolyte material, so that the preparation process of the device is compatible with the traditional CMOS (complementary metal oxide semiconductor) process, and the conductivity adjustability and the data retention capability of the device are improved. Molybdenum sulfide has a typical layered structure, bonded between layers by van der waals forces, and can be easily removed from MoS due to the extremely small volume of lithium ions2In-and out-of-insertion without changing MoS2The structure of (1). Along with the embedding of lithium ions, the channel potential barrier is continuously reduced, and the resistance of the device is in a low resistance state; under the action of a reverse electric field, lithium ions are extracted and returned to the electrolyte layer, the device is recovered to a high-resistance state, and the transformation of the high-resistance state is controlled only by the insertion and extraction of the lithium ions. Therefore, the concentration and the direction of lithium ion embedding can be easily controlled through the size and the direction of a grid electric field, so that the channel conductance of the device is effectively controlled, and the adjustability of the conductance is improved. On the other hand, the gate voltage application is stopped, and the metal ions are bound to the MoS2In addition, the original resistance state of the device can be effectively maintained, the long-term plasticity of the memristor is improved, a novel ultra-large-scale memristor array with reliable performance is finally manufactured, and functions such as image recognition are achieved through a corresponding neural network.
Drawings
Fig. 1 is a schematic structural diagram of the all-solid-state electrolyte memristor, where a diagram (a) is a high-resistance state and a diagram (b) is a low-resistance state.
In the figure: 1 grid electrode, 2 grid dielectric layers, 3 molybdenum sulfide layers, 4 solid dielectric layers, 5 source electrodes and 6 drain electrodes.
Figure 2 is an XPS plot of the device showing the channel material as molybdenum sulfide and demonstrating lithium ion intercalation.
Figure 3 is a pulse test result of the device showing good conductance update linearity.
Fig. 4 is a high and low impedance detection graph of the device, indicating good endurance of the device.
Detailed Description
The essential features and the significant advances of the invention are further clarified by the following examples. The invention is in no way limited to the examples
Example 1:
the preparation steps of the all-solid-state electrolyte memristor are as follows:
1) 2.7nm MoO deposition by ALD (atomic layer deposition)3
2) Using CVD (chemical vapor deposition) process to MoO3Annealing at 400 deg.C, sulfurizing at 550 deg.C, and annealing at 900 deg.C to obtain polycrystalline MoS with good crystallinity2
3) Ti/Au electrodes are prepared by conventional ultraviolet lithography and electron beam evaporation processes, with thicknesses of-10 nm and-80 nm, respectively.
4) And preparing a lithium cobaltate solid electrolyte layer with the thickness of 20nm by using a radio frequency magnetron sputtering process.
5) And exposing the source, drain and gate electrodes by using ultraviolet lithography and plasma etching processes.
In the embodiment, heavily doped silicon is adopted for the grid electrode, the thickness of the grid medium layer is 270nm, three layers of polycrystalline molybdenum disulfide are selected to be 2.1nm, 10nm Ti is adopted for the source electrode and the drain electrode as an adhesion layer, 80nm Au is adopted for an inert electrode, and 20nm lithium cobalt oxide is adopted for the solid electrolyte layer.
Example 2:
different from the embodiment 1, in the embodiment, heavily doped silicon is adopted for the gate, the gate dielectric layer is a silicon dioxide layer with the thickness of 270nm, two layers of polycrystalline molybdenum disulfide with the thickness of 1.4nm are adopted, 10nm Ti is adopted for the source electrode and the drain electrode as an adhesion layer, 80nm of Ti is adopted for the inert electrode, and 20nm of lithium cobalt oxide is adopted for the solid electrolyte layer.
Example 3:
different from the embodiment 1 and the embodiment 2, the gate electrode in the embodiment adopts Pt, the gate dielectric layer is an alumina layer with the thickness of 100nm, three layers of polycrystalline molybdenum disulfide with the thickness of 2.1nm are selected, the source electrode and the drain electrode adopt 10nm Ti as an adhesion layer, 80nmAu as an inert electrode, and the solid electrolyte layer adopts lithium cobaltate with the thickness of 20 nm. Fig. 1 is a schematic structural diagram of an all-solid-state electrolyte memristor according to the present invention, in which a diagram (a) is a high resistance state and a diagram (b) is a low resistance state.
Fig. 2 is an XPS plot of an all-solid-state electrolyte memristor of the present invention, showing that the channel material is molybdenum sulfide and demonstrating intercalation of lithium ions.
FIG. 3 is a pulse test result of the solid electrolyte memristor of the present invention, showing good conductance update linearity.
FIG. 4 is a high-low impedance detection graph of the solid electrolyte memristor of the present invention, demonstrating the good endurance of the device.
The all-solid-state electrolyte memristor fully utilizes the stability and band gap adjustable characteristics of the electrolyte material and the channel material. In addition to the memristors of the above-described embodiments, other device structures may also be constructed with the materials of the above-described characteristics. The above description is only exemplary of the invention and should not be taken as limiting, and any modifications, equivalents, improvements and the like that are within the spirit and principle of the invention should be included in the scope of the invention.

Claims (10)

1. Based on MoS2The all-solid-state electrolyte memristor is characterized in that:
comprises a gate drain source electrode, a gate dielectric layer and MoS2A layer and a solid electrolyte layer;
the solid electrolyte layer adopts a dielectric layer which is easy to generate alkali metal ions under the action of a grid electric field;
the source electrode and the drain electrode adopt metal electrodes with stable properties; the gate dielectric layer is made of conventional metal oxide.
2. MoS-based according to claim 12The all-solid-state electrolyte memristor is characterized in that: the gate dielectric layer is made of silicon dioxide, aluminum oxide or hafnium oxide metal oxide.
3. MoS-based according to claim 12The all-solid-state electrolyte memristor is characterized in that: and depositing a solid electrolyte layer on the surface of the molybdenum disulfide channel by using a magnetron sputtering method, wherein the solid electrolyte layer is any one of lithium manganate, lithium cobaltate, lithium nickel cobalt manganese oxide or lithium iron phosphate.
4. MoS-based according to claim 12The all-solid-state electrolyte memristor is characterized in that: the metal electrode is any one of gold, platinum, iridium or ruthenium.
5. MoS-based according to claim 12The all-solid-state electrolyte memristor is characterized in that:
the thickness of the molybdenum disulfide layer is 0.6 nm-20 nm;
the thickness of the gate-drain source electrode is 5 nm-200 nm;
the thickness of the solid electrolyte layer is 5 nm-5 mu m;
the thickness of the gate dielectric layer is 10 nm-300 mu m.
6. MoS-based according to claim 52The all-solid-state electrolyte memristor is characterized in that:
the thickness of the molybdenum disulfide layer is 0.6 nm-3.5 nm;
the thickness of the gate dielectric layer is 10 nm-100 mu m.
7. MoS-based according to any of claims 1 to 62The preparation method of the all-solid-state electrolyte memristor is characterized in thatThe method comprises the following steps:
1) MoO deposition using ALD3
2) MoO by CVD process3Annealing, sulfurizing and annealing to obtain polycrystalline MoS with good crystallinity2
3) Preparing a Ti/Au electrode by a conventional ultraviolet photoetching and electron beam evaporation process;
4) preparing a lithium cobaltate solid electrolyte layer by utilizing a radio frequency magnetron sputtering process;
5) exposing the source, drain and gate electrodes by using ultraviolet lithography and plasma etching processes;
the thickness of the solid electrolyte layer is 5 nm-5 mu m, the solid electrolyte layer is prepared by adopting radio frequency magnetron sputtering, a high-purity ceramic target is selected, and the sputtering time is 5-60min under the inert gas sputtering atmosphere with the power of 100-;
the preparation of molybdenum disulfide was carried out in a two-step process, first by depositing MoO by Atomic Layer Deposition (ALD)3Precursor, sulfur source and MoO3The membrane is placed into a tubular furnace, and the MoO is treated by the tubular furnace according to the preset temperature of 400-3Annealing, vulcanizing and annealing to obtain large-area MoS with controllable layer number2
8. MoS-based according to claim 72The preparation method of the all-solid-state electrolyte memristor is characterized by comprising the following steps:
the inert gas is nitrogen, argon or other inert mixed gas;
the sulfur source is gaseous H2S or solid sulfur powder, sulfur blocks or a mixture of any two of the solid sulfur powder and the sulfur blocks;
the molybdenum source is molybdenum hexacarbonyl and C12H30N4Mo molybdenum metal organic compound.
9. MoS-based according to claim 72The preparation method of the all-solid-state electrolyte memristor is characterized by comprising the following steps: the molybdenum disulfide is in a single crystal or polycrystalline state.
10. MoS-based according to claim 72OfThe preparation method of the solid electrolyte memristor is characterized by comprising the following steps: transferring the electrode pattern by electron beam exposure or ultraviolet lithography; the deposition of the metal electrode adopts electron beam evaporation or magnetron sputtering.
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